WO2021057221A1

WO2021057221A1 - Method and apparatus for realizing state update based on fpga

Info

Publication number: WO2021057221A1
Application number: PCT/CN2020/103589
Authority: WO
Inventors: 潘国振; 魏长征; 闫莺
Original assignee: 支付宝(杭州)信息技术有限公司
Priority date: 2019-09-25
Filing date: 2020-07-22
Publication date: 2021-04-01
Also published as: CN110688651A

Abstract

One or more embodiments of the present invention provide a method and apparatus for realizing state update based on an FPGA. The method comprises: an FPGA structure loads a deployed circuit logic configuration file to an FPGA chip contained therein, so that an on-chip processor used for achieving virtual machine logic is formed on the FPGA chip; the FPGA structure reads a code program of an intelligent contract and a contract state related to the code program into the on-chip processor, so that the on-chip processor runs the code program to update the value of the contract state, the intelligent contract being related to a transaction received by a blockchain node to which the FPGA structure belongs; and the FPGA structure caches the updated value of the contract state in a local space to further synchronize the updated value of the contract state from the local space to the blockchain node.

Description

Method and device for realizing status update based on FPGA

Technical field

One or more embodiments of this specification relate to the field of blockchain technology, and in particular, to a method and device for implementing status updates based on FPGA.

Background technique

Blockchain technology is built on a transmission network (such as a peer-to-peer network). The network nodes in the transmission network use chained data structures to verify and store data, and use distributed node consensus algorithms to generate and update data.

At present, the two biggest challenges in enterprise-level blockchain platform technology are privacy and performance. It is often difficult to solve these two challenges at the same time. Most of the solutions are to lose performance in exchange for privacy, or do not consider privacy to pursue performance. Common encryption technologies that solve privacy problems, such as Homomorphic encryption and Zero-knowledge proof, are highly complex, have poor versatility, and may also cause serious performance losses.

Trusted Execution Environment (TEE) is another way to solve privacy issues. TEE can play the role of a black box in the hardware. Neither the code executed in the TEE nor the data operating system layer can be peeped, and only the pre-defined interface in the code can operate on it. In terms of efficiency, due to the black box nature of TEE, plaintext data is calculated in TEE instead of complex cryptographic operations in homomorphic encryption. There is no loss of efficiency in the calculation process. Therefore, the combination with TEE can achieve less performance loss. Under the premise, the security and privacy of the blockchain are greatly improved. At present, the industry is very concerned about the TEE solution. Almost all mainstream chip and software alliances have their own TEE solutions, including TPM (Trusted Platform Module) in software and Intel SGX (Software Guard Extensions) in hardware. , Software Protection Extension), ARM Trustzone (trust zone) and AMD PSP (Platform Security Processor, platform security processor).

Summary of the invention

In view of this, one or more embodiments of this specification provide a method and device for implementing status update based on FPGA.

To achieve the foregoing objectives, one or more embodiments of the present specification provide technical solutions as follows.

According to the first aspect of one or more embodiments of this specification, a method for implementing state update based on FPGA is proposed, which includes: the FPGA structure loads the deployed circuit logic configuration file to the FPGA chip contained in the FPGA structure, so that the An on-chip processor for realizing virtual machine logic is formed on the chip; the FPGA structure reads the code program of the smart contract and the contract state related to the code program into the on-chip processor, so that the on-chip processor runs all The code program is used to update the value of the contract state, the smart contract is related to the transaction received by the blockchain node to which the FPGA structure belongs; the FPGA structure caches the updated value of the contract state in Local space to further synchronize from the local space to the blockchain node.

According to the second aspect of one or more embodiments of the present specification, an apparatus for implementing state update based on FPGA is proposed, which includes: a loading unit, which enables the FPGA structure to load the deployed circuit logic configuration file to the FPGA chip contained in itself, so as to An on-chip processor for realizing virtual machine logic is formed on the FPGA chip; a reading unit enables the FPGA structure to read the code program of the smart contract and the contract state involved in the code program into the on-chip processor , Enabling the on-chip processor to run the code program to update the value of the contract state, the smart contract is related to the transaction received by the blockchain node to which the FPGA structure belongs; a cache unit, enabling the FPGA The structure caches the updated value of the contract state in the local space, so as to further synchronize from the local space to the blockchain node.

According to a third aspect of one or more embodiments of this specification, an electronic device is proposed, including: a processor; a memory for storing executable instructions of the processor; wherein the processor runs the executable instructions In order to realize the method as described in the first aspect.

According to the fourth aspect of one or more embodiments of the present specification, a computer-readable storage medium is provided, on which computer instructions are stored, and when the instructions are executed by a processor, the steps of the method described in the first aspect are implemented.

Description of the drawings

Fig. 1 is a flowchart of a method for implementing status update based on FPGA provided by an exemplary embodiment.

Fig. 2 is a schematic structural diagram of a blockchain node provided by an exemplary embodiment.

Fig. 3 is a schematic diagram of forming a functional module on an FPGA chip provided by an exemplary embodiment.

Fig. 4 is a schematic structural diagram of another blockchain node provided by an exemplary embodiment.

Fig. 5 is a block diagram of a device for implementing status update based on FPGA provided by an exemplary embodiment.

detailed description

The exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings indicate the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with one or more embodiments of this specification. Rather, they are merely examples of devices and methods consistent with some aspects of one or more embodiments of this specification as detailed in the appended claims.

It should be noted that in other embodiments, the steps of the corresponding method are not necessarily executed in the order shown and described in this specification. In some other embodiments, the method may include more or fewer steps than described in this specification. In addition, a single step described in this specification may be decomposed into multiple steps for description in other embodiments; and multiple steps described in this specification may also be combined into a single step in other embodiments. description.

Block chains are generally divided into three types: Public Blockchain, Private Blockchain and Consortium Blockchain. In addition, there are many types of combinations, such as private chain + alliance chain, alliance chain + public chain and other different combinations. Among them, the most decentralized one is the public chain. The public chain is represented by Bitcoin and Ethereum. Participants who join the public chain can read the data records on the chain, participate in transactions, and compete for the accounting rights of new blocks. Moreover, each participant (ie, node) can freely join and exit the network, and perform related operations. The private chain is the opposite. The write permission of the network is controlled by an organization or institution, and the data read permission is regulated by the organization. In simple terms, the private chain can be a weakly centralized system with strict restrictions and few participating nodes. This type of blockchain is more suitable for internal use by specific institutions. Consortium chain is a block chain between public chain and private chain, which can realize "partial decentralization". Each node in the alliance chain usually has a corresponding entity or organization; participants are authorized to join the network and form a stakeholder alliance to jointly maintain the operation of the blockchain.

Regardless of whether it is a public chain, a private chain or a consortium chain, for the purpose of privacy protection, the nodes in the blockchain network may use a solution that combines the blockchain and the TEE (Trusted Execution Environment). Execute received transactions within TEE. TEE is a secure extension based on CPU hardware and a trusted execution environment that is completely isolated from the outside. TEE was first proposed by Global Platform to solve the security isolation of resources on mobile devices, and parallel to the operating system to provide a trusted and secure execution environment for applications. ARM's Trust Zone technology is the first to realize the real commercial TEE technology. With the rapid development of the Internet, security requirements are getting higher and higher. Not only mobile devices, cloud devices, and data centers have put forward more demands on TEE. The concept of TEE has also been rapidly developed and expanded. Compared with the originally proposed concept, the TEE referred to now is a more generalized TEE. For example, server chip manufacturers Intel and AMD have successively introduced hardware-assisted TEE and enriched the concepts and features of TEE, which has been widely recognized in the industry. The TEE mentioned now usually refers more to this kind of hardware-assisted TEE technology.

Taking Intel SGX technology as an example, SGX provides an enclave (also known as an enclave), which is an encrypted trusted execution area in the memory, and the CPU protects data from being stolen. Taking the first blockchain node using a CPU that supports SGX as an example, using the newly added processor instructions, a part of the area EPC (Enclave Page Cache, enclave page cache or enclave page cache) can be allocated in the memory, and through the CPU The encryption engine MEE (Memory Encryption Engine) encrypts the data in it. The encrypted content in EPC will be decrypted into plain text only after entering the CPU. Therefore, in SGX, users can distrust the operating system, VMM (Virtual Machine Monitor), and even BIOS (Basic Input Output System). They only need to trust the CPU to ensure that private data will not leakage. Therefore, the enclosure is equivalent to the TEE produced under SGX technology.

Different from the mobile terminal, cloud access requires remote access, and the end user is invisible to the hardware platform. Therefore, the first step in using TEE is to confirm the authenticity of TEE. For example, the related technology provides a remote certification mechanism for the above-mentioned SGX technology to prove that the SGX platform on the target device and the challenger have deployed the same configuration file. However, because the TEE technology in the related technology is implemented by software or a combination of software and hardware, even if the remote attestation method can indicate to a certain extent that the configuration file deployed in the TEE has not been tampered with, the TEE itself depends on the operation The environment cannot be verified. For example, on a blockchain node that needs to implement privacy functions, a virtual machine for executing smart contracts needs to be configured in the TEE. The instructions executed by the virtual machine are not directly executed, but actually executed corresponding X86 instructions (Assuming that the target device adopts the X86 architecture), which poses a certain degree of security risk.

To this end, this specification proposes a hardware TEE technology based on FPGA implementation. FPGA implements hardware TEE by loading circuit logic configuration files. Because the content of the circuit logic configuration file can be checked and verified in advance, and the FPGA is configured and operated completely based on the logic recorded in the circuit logic configuration file, it can be ensured that the hardware TEE implemented by the FPGA has relatively higher security. However, FPGA needs to frequently synchronize the state of the contract with the blockchain node, which consumes a lot of resources.

The following describes a method for implementing status updates based on FPGA provided in this specification in conjunction with embodiments, so as to reduce the number of data interactions.

Fig. 1 is a flowchart of a method for implementing status update based on FPGA provided by an exemplary embodiment. As shown in Figure 1, the method is applied to the FPGA structure and may include steps 102-106.

Step 102: The FPGA structure loads the deployed circuit logic configuration file to the FPGA chip contained in the FPGA structure to form an on-chip processor for realizing virtual machine logic on the FPGA chip.

The FPGA chip contains a number of editable hardware logic units. After these hardware logic units are configured via a circuit logic configuration file, they can be implemented as corresponding functional modules to implement corresponding logic functions. Specifically, the circuit logic configuration file can be burned to the FPGA structure based on the form of a bit stream. For example, the above-mentioned on-chip processor is formed by the deployed circuit logic configuration file, and by further deploying other related functional modules, the FPGA structure can be configured as a hardware TEE on the blockchain node. Since these functional modules are completely configured by the circuit logic configuration file, it is possible to determine the logic and other aspects of the information realized by the functional module configured by checking the circuit logic configuration file to ensure that the functional module can be configured according to the complete user’s requirements. Needs to be formed and run.

After the user generates the circuit logic configuration file, if it is located at the location of the FPGA structure, the circuit logic configuration file can be deployed locally to the FPGA structure. For example, the deployment operation can be implemented in an offline environment to ensure safety. Or, when the FPGA structure is in an online environment, the user can remotely deploy the circuit logic configuration file to the FPGA structure.

Step 104: The FPGA structure reads the code program of the smart contract and the state of the contract involved in the code program into the on-chip processor, and makes the on-chip processor run the code program to update the contract status. Value, the smart contract is related to the transaction received by the blockchain node to which the FPGA structure belongs.

After the blockchain node receives the transaction initiated by the transaction initiator, it can transmit the transaction to the FPGA structure to obtain the code program of the smart contract involved in the transaction from the FPGA structure. For example, when the transaction is used to deploy a smart contract, the FPGA structure can obtain the code program from the data field of the transaction; when the transaction is used to call a smart contract, the FPGA structure can obtain the called smart contract from the to field of the transaction And obtain the deployed code program based on the contract address, where the code program can be deployed at the blockchain node or in the local space of the FPGA structure.

A node private key can be deployed on the FPGA structure, and the node public key corresponding to the node private key is in a public state. The above transaction can be encrypted and generated by the transaction initiator based on the symmetric key and node public key maintained by itself (for example, randomly generated for each transaction) using a digital envelope method: the transaction initiator encrypts the plaintext transaction content through the symmetric key to obtain The ciphertext transaction content, and the above-mentioned symmetric key is encrypted by the node public key to obtain the ciphertext symmetric key, and the above-mentioned transaction includes the ciphertext transaction content and the ciphertext symmetric key. Correspondingly, the FPGA structure can form a decryption module on the FPGA chip through the deployed circuit logic configuration file, and decrypt the above-mentioned transaction through the decryption module. Among them, the decryption module first decrypts the ciphertext symmetric key based on the node's private key to obtain the above-mentioned symmetric key, and then the decryption module decrypts the ciphertext transaction content based on the symmetric key to obtain the above-mentioned plaintext transaction content, and then based on The data field or to field of the plaintext transaction content obtains the above-mentioned code program.

The contract state involved in the code program can be stored at the blockchain node or in the local space of the FPGA structure. The FPGA structure can access the local space first. If it is found in the local space, it can avoid the relatively higher overhead caused by accessing the blockchain node, and it can also improve the efficiency of obtaining the contract state; of course, the above code program is not included in the local space. In the case of contract status, the FPGA structure needs to request the blockchain node to obtain the contract status involved in the code program.

Step 106: The FPGA structure caches the updated value of the contract state in a local space, so as to further synchronize from the local space to the blockchain node.

By caching the updated value of the contract state in the local space of the FPGA structure, for the frequently used contract state, the FPGA structure can directly read the value of the contract state from the local space, avoiding access to the blockchain node This causes relatively higher overhead and improves the efficiency of reading the value of the contract state. At the same time, the updated value of the contract state cached in the local space is synchronized to the blockchain node by periodically or triggering to ensure that the blockchain node can update the world state maintained in a timely manner.

The local space of the FPGA structure may include: on-chip storage space of the FPGA chip, or external storage space of the FPGA chip (for example, external DDR, etc.), or both. Since the inside of the FPGA chip is considered to be in the security range and the outside of the FPGA chip is considered to be a security risk, when the value of the contract state is updated and cached in the on-chip storage space, it can be directly stored in plaintext form, and when the contract state is updated When the value is cached in the external storage space, the updated value of the contract state needs to be encrypted by the encryption module on the FPGA chip to realize the cache. The encryption module is formed by loading the aforementioned deployed circuit logic configuration file by the FPGA chip. Therefore, in the aforementioned process of obtaining the contract state involved in the code program from the local space, if the value of the contract state is cached in the on-chip cache space, the value of the contract state can be directly read from the on-chip cache space and read in On-chip processor, if the value of the contract state is cached in the external storage space, the decryption module on the FPGA chip needs to decrypt the encrypted contract state read from the external storage space, and the decrypted contract state The value is read into the on-chip processor.

Correspondingly, when the FPGA structure needs to synchronize the data in the on-chip storage space to the blockchain node, since the data in the on-chip storage space is in plaintext state, it is necessary to encrypt the data in the on-chip storage space through the aforementioned encryption module After that, it is synchronized to the blockchain node. When the FPGA structure needs to synchronize the data in the external storage space to the blockchain node, since the data in the external storage space is encrypted, the data in the external storage space can be directly synchronized to the blockchain node.

As mentioned earlier, the FPGA structure synchronizes the updated value of the contract state cached in the local space to the blockchain node, so that the blockchain node can update the world state. In one case, the FPGA structure caches the updated value of the contract state in the local space before the code program is executed, and after the code program is executed, the updated value of the contract state cached in the local space is synchronized in batches To the blockchain node. Since the value of the contract state may be in an intermediate state before the code execution is completed, and there is a possibility of change, the implementation of batch synchronization after the execution of the code program can reduce the data interaction between the local space and the blockchain node. In order to reduce the corresponding resource consumption. In another case, the FPGA structure can take the updated value of the contract state cached in the local space, and the updated value of the contract state involved in other smart contracts cached in the local space, and synchronize them to the blockchain. Node; among them, the cumulative number of smart contracts and other smart contracts is not less than the preset value. Compared with the former case, synchronization is implemented after each smart contract is executed. In the latter case, batch synchronization can be implemented for the execution results of multiple smart contracts, so there is no dependency between these smart contracts. This can not only ensure the correct execution of the code program, but also further reduce the data interaction between the local space and the blockchain node, so as to reduce the corresponding resource consumption.

In addition to caching the value of the contract state, the local space of the FPGA structure can also cache world state data. When the world state data is cached in the local space, the FPGA structure can update the world state data based on the updated value of the contract state obtained above, and then synchronize the latest world state data in the local space to the blockchain node. Since the world state data is in the local space of the FPGA structure, when the value of the contract state is updated in the FPGA structure, compared to the aforementioned update of the contract state, the value is synchronized to the blockchain node and the blockchain node Actively update the world state, which can update the world state data in the local space relatively earlier or even in real time (or quasi real time),

The above-mentioned world state data cached in the local space may include the full amount of world state data, that is, both the local space and the blockchain node maintain the full amount of world state data. Alternatively, the world state data cached in the above-mentioned local space may include hot world state data, that is, only a part of the world state data is cached in the local space, which is different from the full amount of world state data maintained by the blockchain node. Hot world state data refers to world state data with a relatively higher update frequency or update probability, that is, hot data in world state data, which is different from cold data in world state data that is not updated for a long time and has a relatively lower update frequency. In most cases, it satisfies the need to update the world state in the local space, and can reduce the occupation of the local space. The hotspot world state data may include, for example, the world state data related to the most recent one or more blocks, or the world state data corresponding to the hotspot account, etc. This specification does not limit this.

Fig. 2 is a schematic structural diagram of a blockchain node provided by an exemplary embodiment. Based on the technical solution in this specification, an FPGA structure can be added to the blockchain node to implement hardware TEE. For example, the FPGA structure can be an FPGA board as shown in FIG. 2. The FPGA board can be connected to the blockchain node through the PCIE interface to realize the data interaction between the FPGA board and the blockchain node. FPGA boards can include FPGA chips, Flash (flash memory) chips, and dense tube chips; of course, in addition to FPGA chips in some embodiments, they may only include parts of the remaining Flash chips and dense tube chips. , Or may contain more structures, here are just examples.

In the initial stage, no user-defined logic is programmed on the FPGA chip, which is equivalent to the FPGA chip in a blank state. Users can burn circuit logic configuration files on the FPGA chip to form corresponding functions or logic on the FPGA chip. When programming the circuit logic configuration file for the first time, the FPGA board does not have the capability of security protection, so it usually needs to provide an external security environment. For example, users can implement the programming of the circuit logic configuration file in an offline environment to achieve physical security isolation. Instead of implementing remote programming online.

For the function or logic that the user needs to implement, the corresponding logic code can be formed through FPGA hardware language, and then the logic code can be mirrored to obtain the above-mentioned circuit logic configuration file. Before programming to the FPGA board, the user can check the above-mentioned logic code. Especially, when multiple users are involved at the same time, multiple users can check the above logic code separately to ensure that the FPGA board can finally meet the needs of all users and prevent security risks, logic errors, fraud and other abnormalities. problem.

After confirming that the code is correct, the user can burn the circuit logic configuration file to the FPGA board in the above-mentioned offline environment. Specifically, the circuit logic configuration file is transferred from the blockchain node to the FPGA board, and then deployed to the Flash chip as shown in Figure 2, so that even if the FPGA board is powered off, the Flash chip can still save the above-mentioned circuit logic. Configuration file.

Fig. 3 is a schematic diagram of forming a functional module on an FPGA chip provided by an exemplary embodiment. By loading the circuit logic configuration file deployed in the Flash chip to the FPGA chip, the hardware logic unit contained in the FPGA chip can be configured to form corresponding functional modules on the FPGA chip. For example, the formed functional modules can include such Figure 3 shows the on-chip cache module, plaintext calculation module, key agreement module, decryption verification module, encryption and decryption module, etc. At the same time, the circuit logic configuration file can also be used to transmit the information that needs to be stored to the FPGA board. For example, the preset certificate can be stored on the FPGA chip, and the authentication root key can be stored in the secret tube chip (the authentication root key can also be Stored on the FPGA chip) and so on.

Based on the key agreement module formed on the FPGA chip and the authentication root key deployed on the FPGA board, the FPGA board can realize remote key agreement with the user. The key agreement process can use related technologies. Any algorithm or standard can be implemented, and this specification does not limit it. For example, the key agreement process can include: the user can generate a key Ka-1 at the local client, the key agreement module can generate a key Kb-1 locally, and the client can generate a key Kb-1 based on the key Ka- 1 Calculate the key agreement information Ka-2, the key agreement module can calculate the key agreement information Kb-2 based on the key Kb-1, and then the client sends the key agreement information Ka-2 to the key agreement module, The key agreement module sends the key agreement information Kb-2 to the client, so that the client can generate a secret value based on the key Ka-1 and the key agreement information Kb-2, and the key agreement module can be based on the key Kb -1 generates the same secret value as the key agreement information Ka-2, and finally the client and the key agreement module respectively derive the same configuration file deployment key from the same secret value based on the key derivation function, and the configuration file deployment The key can be stored in the FPGA chip or the secret management chip. In the above process, although the key agreement information Ka-2 and key agreement information Kb-2 are transmitted between the client and the key agreement module via the blockchain node, the key Ka-1 is controlled by the client , The key Kb-1 is controlled by the key agreement module, so it can ensure that the blockchain node cannot know the final secret value and the configuration file deployment key, so as to avoid possible security risks.

In addition to the configuration file deployment key, the secret value is also used to derive the business secret deployment key; for example, the secret value can be derived as a 32-bit value, the first 16 bits can be used as the configuration file deployment key, and the last 16 bits can be used as the business secret deployment Key. The user can deploy the service key to the FPGA board through the service secret deployment key. For example, the service key may include the node private key and the service root key. For example, the user can use the business secret deployment key on the client to sign, encrypt the node private key or the business root key, and send it to the FPGA board, so that after the FPGA board is decrypted and verified through the decryption verification module, Deploy the obtained node private key or service root key.

Based on the deployed node key, service root key, encryption and decryption module and plaintext calculation module on the FPGA chip, the FPGA board can be implemented as a TEE on the blockchain node to meet privacy requirements. For example, when a blockchain node receives a transaction, if the transaction is a plaintext transaction, the blockchain node can directly process the plaintext transaction, if the transaction is a private transaction, the blockchain node transmits the private transaction to the FPGA The board is processed.

The transaction content of a plaintext transaction is in plaintext form, and the contract status generated after the transaction is executed is also stored in plaintext form. The transaction content of a private transaction is in the form of cipher text, which is obtained by encrypting the content of the transaction in plain text by the transaction initiator, and the contract state generated after the transaction is executed needs to be stored in the form of cipher text to ensure the protection of transaction privacy. For example, the transaction initiator can generate a symmetric key randomly or based on other methods. Similarly, the business public key corresponding to the above-mentioned business private key is disclosed, then the transaction initiator can perform transaction content in plaintext based on the symmetric key and the business public key. Digital Envelope Encryption: The transaction initiator encrypts the plaintext transaction content with a symmetric key, and encrypts the symmetric key with the business public key. The two parts obtained are included in the above-mentioned private transaction; in other words, the private transaction includes Two parts of content: the content of the transaction in plaintext encrypted with a symmetric key, and the symmetric key encrypted with the business public key.

Therefore, after the FPGA board receives the private transaction from the blockchain node, the encryption and decryption module can use the business private key to decrypt the symmetric key encrypted with the business public key to obtain the symmetric key, and then the encryption and decryption module The symmetric key is used to decrypt the plaintext transaction content encrypted with the symmetric key to obtain the plaintext transaction content. Private transactions can be used to deploy smart contracts, then the data field of the plaintext transaction content can contain the contract code of the smart contract to be deployed; or, the privacy transaction can be used to call the smart contract, then the to field of the plaintext transaction content can contain the called The contract address of the smart contract, and the FPGA board can retrieve the corresponding contract code based on the contract address.

The plaintext calculation module formed on the FPGA chip is used to implement virtual machine logic in related technologies, that is, the plaintext calculation module is equivalent to the "hardware virtual machine" on the FPGA board. Therefore, after the contract code is determined based on the foregoing plaintext transaction content, the contract code can be passed into the plaintext calculation module, so that the plaintext calculation module executes the contract code. The plaintext calculation module is equivalent to the on-chip processor formed on the FPGA chip in this specification.

The contract code involves one or more contract states. The on-chip processor needs to read the historical value (recent value) of these contract states during the execution of the contract code, and the execution of the contract code may cause at least part of the contract state The value of has changed. During the previous execution of the contract code, the on-chip processor can store the value of the contract state involved in the on-chip cache module on the FPGA chip; accordingly, the on-chip processor executes the contract code of each smart contract. , Will first look up the value of the contract state involved in the contract code from the on-chip cache module. If the value of the required contract state is stored in the on-chip cache module, the on-chip processor directly reads the value from the on-chip cache module; if the value of the required contract state is not stored in the on-chip cache module, it is processed on-chip The device then obtains the value of the required contract state from the blockchain node. But obviously, compared to obtaining the value of the contract state from the blockchain node, the on-chip processor consumes less resources and the reading speed is relatively faster to read the value of the contract state from the on-chip cache module.

At the same time, because the inside of the FPGA chip is considered to be within the security range and the outside of the FPGA chip is considered to be outside the security range, the value of the contract state stored in the on-chip cache module is in the clear text state, and the contract state maintained at the blockchain node The value of is in the ciphertext state, so the value of the contract state read by the on-chip processor from the on-chip cache module can directly participate in the execution of the corresponding contract code, while the on-chip processor fetches the contract state obtained from the blockchain node The value needs to be decrypted by the encryption and decryption module before it can participate in the execution of the contract code by the on-chip processor. Therefore, compared to the value obtained from the blockchain node for the contract state, the on-chip processor obtains the value from the on-chip cache module. Reading the value of the contract state consumes less resources and the reading speed is relatively faster.

Based on the above description, when the on-chip processor executes the contract code, if the value of the contract state involved is updated, the updated value can be stored in the on-chip cache module for subsequent direct access from the on-chip cache module Read these values. And, after the contract code is executed, the updated value of the contract state stored in the on-chip cache module can be synchronized to the blockchain node for the blockchain node to update the world state maintained. Of course, the synchronized data needs to be encrypted by the encryption and decryption module, so that the blockchain node can only receive the ciphertext data.

The on-chip cache module can also be used to maintain the state of the world. For example, the on-chip cache module can maintain full world state data or hotspot world state data. Then, when the on-chip processor executes the contract code, the updated value of the contract state can be stored in the on-chip cache module in real time, so that the on-chip cache module can update the maintained world state in real time; of course, after the contract state is updated The value needs to be encrypted by the encryption and decryption module before participating in the update process for the world state. And, the on-chip cache module synchronizes the maintained world state to the blockchain node, so that the blockchain node updates the world state maintained by itself.

It can be seen that by configuring the on-chip cache module on the FPGA chip, the value of the cached contract state can be directly synchronized to the blockchain node, so that the blockchain node can synchronize the world state, and it can also be used in the on-chip cache module. The world state is updated, and the updated world state is synchronized to the blockchain node.

In addition to configuring the on-chip cache module on the FPGA chip, you can also configure an external storage space for the FPGA chip. For example, FIG. 4 is a schematic structural diagram of a blockchain node provided by an exemplary embodiment. As shown in FIG. 4, based on the embodiment shown in FIG. 2, the FPGA board may further include an external DDR, and the external DDR can implement data interaction with the FPGA chip. Then, the external DDR can implement the above-mentioned related functions of the on-chip cache module, such as caching the value of the contract state, or caching the world state. However, because the external DDR is not on the FPGA chip, the data on the FPGA chip needs to be encrypted by the encryption and decryption module before being transmitted to the external DDR to ensure that only ciphertext data exists on the external DDR, and the data on the external DDR also needs After the decryption process of the encryption and decryption module, the obtained plaintext data can be applied to processing operations such as on-chip processors. Although compared with the on-chip cache module, the external DDR involves data encryption and decryption and the data transmission efficiency is relatively lower, but it is relatively better than the data transmission efficiency between the FPGA board and the blockchain node.

In contrast, the storage space of the external DDR is often larger or even much larger than the storage space of the on-chip cache module, so the external DDR can help to achieve more data cache. Of course, the FPGA board can include an on-chip cache module and an external DDR at the same time. For example, the value of the contract state can be cached in the on-chip cache module, and the world state can be maintained in the external DDR.

For some reasons, the user may want to update the version of the circuit logic configuration file deployed on the FPGA board. For example, the authentication root key contained in the circuit logic configuration file may be known by risky users, or the user wants to update the version on the FPGA board. The deployed functional modules are upgraded, etc. This manual does not limit this. In order to facilitate the distinction, the circuit logic configuration file that has been deployed in the above process can be referred to as the old version of the circuit logic configuration file, and the circuit logic configuration file that needs to be deployed is referred to as the new version of the circuit logic configuration file.

Similar to the old version of the circuit logic configuration file, the user can generate a new version of the circuit logic configuration file through the process of writing code and mirroring. Further, the user can sign the new version of the circuit logic configuration file with his own private key, and then encrypt the signed new version of the circuit logic configuration file with the configuration file deployment key negotiated above to obtain the encrypted new version of the circuit Logical configuration file. In some cases, there may be multiple users at the same time, so the old version of the circuit logic configuration file needs to deploy the preset certificates corresponding to these users to the FPGA board, and these users need to use their own private keys to pair the new version of the circuit. Sign the logical configuration file.

The user can remotely send the encrypted new version of the circuit logic configuration file to the blockchain node through the client, and the blockchain node will further transfer it to the FPGA board. The decryption verification module formed on the FPGA chip in the foregoing process is located on the transmission path between the PCIE interface and the Flash chip, so that the encrypted new version of the circuit logic configuration file must first be successfully processed by the decryption verification module before it can be The Flash chip is passed in to achieve a credible update, and the Flash chip cannot be updated directly without bypassing the process of decryption and verification.

After the decryption verification module receives the encrypted new version of the circuit logic configuration file, it first decrypts it with the configuration file deployment key deployed on the FPGA board. If the decryption is successful, the decryption verification module is further based on the preset certificate deployed on the FPGA chip , To perform signature verification on the decrypted new version of the circuit logic configuration file. If the decryption fails or the signature verification fails, it means that the received file is not from the above-mentioned user or has been tampered with, and the decryption and signature verification module will trigger the termination of the update operation; and if the decryption is successful and the signature verification is passed, you can It is determined that the obtained new version of the circuit logic configuration file is from the aforementioned user and has not been tampered with during the transmission process. The new version of the circuit logic configuration file can be further transmitted to the Flash chip to update and deploy the old version of the circuit logic configuration file in the Flash chip.

After the new version of the circuit logic configuration file is loaded into the FPGA chip, the above-mentioned plaintext calculation module, on-chip cache module, key agreement module, encryption and decryption module, decryption verification module, and storage in the FPGA chip can also be formed on the FPGA chip. Enter the preset certificate, and store the authentication root key to the secret management chip and other information. Among them, the formed plaintext calculation module, on-chip cache module, key agreement module, encryption/decryption module, decryption and signature verification module, etc., the implemented functional logic can be changed and upgraded, and stored in the deployed preset certificate, authentication root Information such as keys may also be different from the information before the update. Then, the FPGA board can remotely negotiate with the user to obtain a new configuration file deployment key based on the updated key agreement module, authentication root key, etc., and the configuration file deployment key can be used for the next renewal Update process. Similarly, a reliable update operation for FPGA boards can be continuously implemented accordingly.

After completing the update deployment, the FPGA board can generate certification results for the new version of the circuit logic configuration file. For example, the above-mentioned key agreement module can calculate the hash value of the new version of the circuit logic configuration file and the hash value of the configuration file deployment key negotiated based on the new version of the circuit logic configuration file through an algorithm such as sm3 or other algorithms. The calculation result can be used as the above-mentioned authentication result, and the key agreement module sends the authentication result to the user. Correspondingly, the user can verify the authentication result on the client based on the maintained new version of the circuit logic configuration file and the configuration file deployment key negotiated accordingly. If the verification is successful, it indicates that the new version of the circuit logic configuration file is successful on the FPGA board. Deployed, and the user and the FPGA board successfully negotiated accordingly to obtain a consistent configuration file deployment key, thereby confirming the successful completion of the circuit logic configuration file update deployment.

Fig. 5 is a schematic structural diagram of a device for implementing status update based on FPGA provided by an exemplary embodiment. Please refer to FIG. 5, in the software implementation, the device for implementing status update based on FPGA may include: a loading unit 501, which causes the FPGA structure to load the deployed circuit logic configuration file to the FPGA chip contained in the FPGA chip, so as to load the deployed circuit logic configuration file on the FPGA chip. An on-chip processor used to implement the logic of the virtual machine is formed on the above; the reading unit 502 enables the FPGA structure to read the code program of the smart contract and the contract state involved in the code program into the on-chip processor, so that the The on-chip processor runs the code program to update the value of the contract state, and the smart contract is related to the transaction received by the blockchain node to which the FPGA structure belongs; the cache unit 503 makes the FPGA structure store all The updated value of the contract state is cached in the local space to further synchronize from the local space to the blockchain node.

Optionally, the reading unit 502 is specifically configured to: enable the FPGA structure to preferentially access the local space;

In the case that the local space does not contain the contract state involved in the code program, the FPGA structure is made to request the blockchain node to obtain the contract state involved in the code program.

Optionally, it further includes: a contract state synchronization unit 504, which enables the FPGA structure to synchronize the updated value of the contract state cached in the local space to the blockchain node so that the block The chain node updates the world state.

Optionally, the contract state synchronization unit 504 is specifically configured to: enable the FPGA structure to cache the updated value of the contract state in the local space before the execution of the code program is completed; After the execution of the code program is completed, the updated value of the contract state cached in the local space is synchronized to the blockchain node in batches.

Optionally, the contract state synchronization unit 504 is specifically configured to: enable the FPGA structure to obtain the updated value of the contract state cached in the local space, and other smart contract locations cached in the local space The updated value of the involved contract status is synchronized to the blockchain node together; wherein, the cumulative number of contracts of the smart contract and the other smart contracts is not less than a preset value.

Optionally, it further includes: a world state synchronization unit 505, which enables the FPGA structure to perform data on the world state data based on the updated value of the contract state when the world state data is cached in the local space. Update; enable the FPGA structure to synchronize the latest world state data in the local space to the blockchain node.

Optionally, the world state data cached in the local space includes: full world state data or hotspot world state data.

Optionally, the hotspot world state data includes: world state data related to one or more recent blocks, or world state data corresponding to a hotspot account.

Optionally, the local space includes: on-chip storage space of the FPGA chip, and/or external storage space of the FPGA chip.

The caching unit 503 is specifically configured to: enable the FPGA structure to cache the updated value of the contract state in the on-chip storage space in plain text; enable the FPGA structure to pair with the encryption module on the FPGA chip The updated value of the contract state is encrypted and then cached in the external storage space; wherein the encryption module is formed by loading the deployed circuit logic configuration file by the FPGA chip.

Optionally, it further includes: an encryption unit 506, which enables the FPGA structure to encrypt data in the on-chip storage space through the encryption module, and then synchronizes the data to the blockchain node; a data synchronization unit 507 enables all The FPGA structure synchronizes the data in the external storage space to the blockchain node.

The systems, devices, modules, or units explained in the above embodiments may be implemented by computer chips or entities, or implemented by products with certain functions. A typical implementation device is a computer. The specific form of the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email receiving and sending device, and a game control A console, a tablet computer, a wearable device, or a combination of any of these devices.

In a typical configuration, the computer includes one or more processors (CPU), input/output interfaces, network interfaces, and memory.

The memory may include non-permanent memory in a computer readable medium, random access memory (RAM) and/or non-volatile memory, such as read-only memory (ROM) or flash memory (flash RAM). Memory is an example of computer readable media.

Computer-readable media include permanent and non-permanent, removable and non-removable media, and information storage can be realized by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disc (DVD) or other optical storage, Magnetic cassettes, disk storage, quantum memory, graphene-based storage media or other magnetic storage devices or any other non-transmission media can be used to store information that can be accessed by computing devices. According to the definition in this article, computer-readable media does not include transitory media, such as modulated data signals and carrier waves.

It should also be noted that the terms "include", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or equipment including a series of elements not only includes those elements, but also includes Other elements that are not explicitly listed, or they also include elements inherent to such processes, methods, commodities, or equipment. If there are no more restrictions, the element defined by the sentence "including a..." does not exclude the existence of other identical elements in the process, method, commodity, or equipment that includes the element.

The foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims may be performed in a different order than in the embodiments and still achieve desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown in order to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

The terms used in one or more embodiments of this specification are only for the purpose of describing specific embodiments, and are not intended to limit one or more embodiments of this specification. The singular forms "a", "said" and "the" used in one or more embodiments of this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and/or" as used herein refers to and includes any or all possible combinations of one or more associated listed items.

It should be understood that, although the terms first, second, third, etc. may be used to describe various information in one or more embodiments of this specification, the information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of one or more embodiments of this specification, the first information may also be referred to as second information, and similarly, the second information may also be referred to as first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "when" or "in response to determination".

The foregoing descriptions are only preferred embodiments of one or more embodiments of this specification, and are not intended to limit one or more embodiments of this specification. All within the spirit and principle of one or more embodiments of this specification, Any modification, equivalent replacement, improvement, etc. made should be included in the protection scope of one or more embodiments of this specification.

Claims

A method for implementing status update based on FPGA, including:

The FPGA structure loads the deployed circuit logic configuration file to the FPGA chip contained in itself, so as to form an on-chip processor for realizing virtual machine logic on the FPGA chip;

The FPGA structure reads the code program of the smart contract and the contract state involved in the code program into the on-chip processor, and causes the on-chip processor to run the code program to update the value of the contract state, so The smart contract is related to the transaction received by the blockchain node to which the FPGA structure belongs;

The FPGA structure caches the updated value of the contract state in a local space, so as to further synchronize from the local space to the blockchain node.
The method according to claim 1, wherein the FPGA structure reading the contract state involved in the code program into the on-chip processor, comprising:

The FPGA structure preferentially accesses the local space;

In the case that the local space does not contain the contract state involved in the code program, the FPGA structure requests the blockchain node to obtain the contract state involved in the code program.
The method according to claim 1, further comprising:

The FPGA structure synchronizes the updated value of the contract state cached in the local space to the blockchain node, so that the blockchain node updates the world state.
The method according to claim 3, wherein the FPGA structure synchronizing the updated value of the contract state cached in the local space to the blockchain node includes:

The FPGA structure caches the updated value of the contract state in the local space before the execution of the code program is completed;

After the execution of the code program is completed, the FPGA structure synchronizes the updated value of the contract state cached in the local space to the blockchain node in batches.
The method according to claim 3, wherein the FPGA structure synchronizing the updated value of the contract state cached in the local space to the blockchain node includes:

The FPGA structure synchronizes the updated value of the contract state cached in the local space and the updated value of the contract state involved in other smart contracts cached in the local space to the Blockchain node;

Wherein, the cumulative contract quantity of the smart contract and the other smart contracts is not less than a preset value.
The method according to claim 1, further comprising:

In the case where world state data is cached in the local space, the FPGA structure updates the world state data based on the updated value of the contract state;

The FPGA structure synchronizes the latest world state data in the local space to the blockchain node.
The method according to claim 6, wherein the world state data cached in the local space includes: full world state data or hotspot world state data.
The method according to claim 7, wherein the hotspot world state data includes: world state data related to the most recent one or more blocks, or world state data corresponding to a hotspot account.
The method according to claim 1, wherein the local space comprises: on-chip storage space of the FPGA chip, and/or external storage space of the FPGA chip.
The method according to claim 9, wherein the FPGA structure caches the updated value of the contract state in a local space, comprising:

The FPGA structure caches the updated value of the contract state in the on-chip storage space in plain text;

After the FPGA structure encrypts the updated value of the contract state through the encryption module on the FPGA chip, it is cached in the external storage space; wherein the encryption module is loaded by the FPGA chip The deployed circuit logic configuration file is formed.
The method according to claim 10, further comprising:

After the FPGA structure encrypts the data in the on-chip storage space through the encryption module, it is synchronized to the blockchain node;

The FPGA structure synchronizes the data in the external storage space to the blockchain node.
A device for realizing status update based on FPGA, including:

The loading unit causes the FPGA structure to load the deployed circuit logic configuration file to the FPGA chip contained therein, so as to form an on-chip processor for realizing virtual machine logic on the FPGA chip;

The reading unit causes the FPGA structure to read the code program of the smart contract and the contract state involved in the code program into the on-chip processor, and causes the on-chip processor to run the code program to update the contract state The value of, the smart contract is related to the transaction received by the blockchain node to which the FPGA structure belongs;

The cache unit enables the FPGA structure to cache the updated value of the contract state in a local space, so as to further synchronize from the local space to the blockchain node.
An electronic device including:

processor;

A memory for storing processor executable instructions;

Wherein, the processor implements the method according to any one of claims 1-11 by running the executable instruction.
A computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implements the steps of the method according to any one of claims 1-11.