WO2021012846A1 - Data deserialization device, time delay unit, and data processing method - Google Patents

Abstract

A data deserialization device (100) comprises multiple deserialization data processing modules (101) and multiple FIFO clock buffer modules (102), where each of the deserialization data processing modules (101) is connected to one of the FIFO clock buffer modules (102). The data deserialization device (100) further comprises multiple data input channels, and each of the deserialization data processing modules (101) processes data in one of the data input channels. When the the multiple data input channels input data into the data deserialization device (100) at the same time, each of the data input channels corresponds to one of the deserialization data processing modules (101) and one of the FIFO clock buffer modules (102), which means that a data volume processed by one single deserialization data processing module (101) is the data volume of one of the data input channels, thereby preventing the issue of data congestion due to an excessive data volume input into the deserialization data processing modules (101).

Description

Data serial-parallel conversion device, delay device and data processing method

This disclosure is based on a Chinese patent application with an application number of 201910655477.6 and an application date of July 19, 2019, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated by reference into this application.

Technical field

The invention relates to the field of data serial-to-parallel conversion processing, and more specifically, to a data serial-to-parallel conversion device, a delay device and a data processing method.

Background technique

The current video and audio delayer is designed for the input of 4 channels of 3G-SDI signal. With the advancement of technology, the ultra-high-definition era has come. When the video and audio signal input in the video and audio delayer is When 4 channels of 12G-SDI video and audio signals are used, since each channel is a 4K 2160p 12G bandwidth large channel data, when 4 channels of 12G-SDI signals are simultaneously input to the data serial-to-parallel conversion device, because of entering the data string The data volume of the parallel conversion device is too large. The data serial-to-parallel conversion device in the video and audio delayer cannot process 4×12G-SDI signals at the same time, making the 4-channel 12G-SDI signal unable to pass or fail to pass the data serial-to-parallel conversion normally Device, and because the amount of signal data transmitted by each channel is too large, the frequency, clock, and jitter of the signal data transmitted in each channel will be more unstable, which affects the quality of signal transmission.

Summary of the invention

Based on the above problems, the present invention provides a data serial-to-parallel conversion device. The data serial-to-parallel conversion device in the present invention includes:

Multiple serial-parallel data processing modules, multiple FIFO clock buffer modules, each serial-parallel data processing module is connected to a FIFO clock buffer module; the data serial-parallel conversion device also includes multiple data input channels, each serial-parallel data processing module processes One of the data input channels is the data; the serial-parallel data processing module is configured to convert serial data into parallel data and send the parallel data to the FIFO clock buffer module; the FIFO clock buffer module is configured to receive data from the serial-parallel data processing module The parallel data is buffered and sent to the lower-level processing module.

The data serial-parallel conversion device provided by the present invention is provided with multiple serial-parallel data processing modules, multiple FIFO clock buffer modules, and multiple data input channels. Each serial-parallel data processing module is connected to a FIFO clock buffer module. The parallel data processing module and the FIFO clock buffer module connected to it process the data in one of the data input channels. When the data in multiple data input channels are simultaneously input to the data serial-parallel conversion device, the data in each data input channel Each corresponds to a serial-parallel data processing module and a FIFO clock buffer module, that is, the amount of data processed by a single serial-parallel data processing module is only the amount of data in one data input channel, which means that not all data in the data input channel is A serial and parallel data processing module performs processing, so as to avoid the phenomenon that the data cannot be passed or cannot be passed normally due to the excessive amount of input data in the serial and parallel data processing module. In the data serial-to-parallel conversion device provided by the present invention, each serial-to-parallel data processing module is also correspondingly connected to a FIFO clock buffer module for temporary storage of input valid data and additional information data, and for additional information data Perform separation, registration, and reorganization to solve the problem of unstable data frequency, clock, and jitter when the data volume of each data input channel is too large.

Further, the FIFO clock buffer module includes multiple data buffer spaces, and the multiple data buffer spaces are configured to simultaneously perform independent data processing according to predefined instructions.

Setting multiple data buffer spaces in the FIFO clock buffer module, multiple data buffer spaces, and multiple data buffer spaces simultaneously perform independent data processing, which greatly increases the data transmission rate and improves the work efficiency of the data serial-to-parallel conversion device.

Further, the data buffer space includes a data status registration register and a local clock generator. The data status registration register is connected to the local clock generator for two-way communication. The data status registration register is configured to read, write, and append valid data according to instructions. Information data, and separate and register additional information data; the local clock generator is configured to send the local clock information generated in the local clock generator to the data status registration register, and the local clock generator is also configured to receive the data status registration register The output effective data and additional information data are reformed to the effective data and additional information data, and the reformed effective data and additional information data are sent to the lower-level processing module.

A local clock generator is added to each data buffer space. The local clock generator provides accurate local clock information for the data, which further improves the stability of the data clock and ensures the transmission quality of the data during the data transmission process.

The present invention also provides a data processing method based on the above data serial-to-parallel conversion device, wherein the data processing method of the serial-to-parallel data processing module includes the following steps:

Perform data matching and detection, detect and extract data format and data transmission rate;

Perform data descrambling;

Perform data parallel conversion, convert serial data into multiple parallel data;

Demultiplex each parallel data, extract valid data and additional information data;

Remove the sync bit information in valid data and additional information data;

Detect data format and generate format information;

Data multiplexing, the parallel data processed by the serial and parallel data processing module is integrated on a bus for parallel output.

Further, the data processing method in the FIFO clock buffer module includes:

Multiple data buffer spaces read and write data according to the status, and write valid data and additional information data to the data status registration register in the data buffer space;

The data status registration register separates and registers the additional information data, and adds the local clock information generated by the local clock generator to the valid data while separating and registering;

The data status registration register sends the valid data and the separated and registered additional information data to the local clock generator;

The local clock generator reformulates the valid data and the additional information data after separation and registration;

The local clock generator selects the lower-level data transmission target according to the state of the lower-level processing module, and outputs additional information data and valid data.

Further, reading and writing data in the multiple data buffer spaces according to the status includes:

Determine the status of multiple data buffer spaces;

If one or more of the data buffer spaces are empty, almost empty, or almost full, according to the order in which the multiple parallel data stacks output by the serial-parallel data processing module arrive first, the first one or more parallel data Write to the data status registration register of one or more data buffer spaces whose status is empty, empty or nearly full respectively.

Further, the local clock generator performs the lower-level data transmission target selection according to the status of the lower-level processing module including:

When the processor in the lower-level processing module is in a full state, the local clock generator chooses to transmit data to the FIFO memory in the lower-level processing module, and the FIFO memory is configured to temporarily store data;

Otherwise, the local clock generator selects the processor that transmits the data to the subordinate processing module.

The present invention also provides a delay device, including a data serial-to-parallel conversion device, a data quantization processing device connected to the data serial-to-parallel conversion device, a delay processing device connected to the data quantization processing device, and a synthesis device connected to the delay processing device The output device and the data serial-to-parallel conversion device are the aforementioned data serial-to-parallel conversion device.

Further, the data serial-to-parallel conversion device included in the delay device provided by the present invention uses the above-mentioned data processing method.

The present invention also provides a signal conversion processor. The signal conversion processor includes the aforementioned data serial-to-parallel conversion device, and the data serial-to-parallel conversion device applies the aforementioned data processing method.

Description of the drawings

Fig. 1 shows a schematic structural diagram of a data serial-to-parallel conversion device according to an embodiment of the present invention;

Fig. 2 shows a schematic diagram of a data buffer space structure according to an embodiment of the present invention;

Figure 3 shows a flow chart of a data processing method for a serial-to-parallel conversion module according to an embodiment of the present invention;

4 shows a flowchart of a data processing method of a FIFO clock buffer module according to an embodiment of the present invention;

Figure 5 shows a schematic diagram of a data input channel data processing circuit in the data serial-to-parallel conversion device according to the present invention;

Fig. 6 shows a schematic structural diagram of a delay device according to an embodiment of the present invention.

Detailed ways

Hereinafter, various aspects of the present invention will be described in detail in conjunction with the accompanying drawings and specific embodiments. Among them, the well-known modules and units and their mutual connections, links, communications or operations are not shown or detailed. And, the described features or functions can be combined in any manner in one or more embodiments. Those skilled in the art should understand that the following various embodiments are only used for illustration, and are not used to limit the protection scope of the present invention. It can also be easily understood that the modules or units or processing modes in the various embodiments described herein and shown in the drawings can be combined and designed in various configurations.

Referring to FIG. 1, FIG. 1 shows a schematic structural diagram of a data serial-to-parallel conversion device 100 according to an embodiment of the present invention. The data serial-parallel conversion device 100 includes a plurality of serial-parallel data processing modules 101 and a plurality of FIFO clock buffer modules 102, wherein the number of serial-parallel data processing modules 101 is equal to the number of FIFO clock buffer modules 102, and each serial In addition, the data processing modules 101 are respectively connected to one of the FIFO clock buffer modules 102. The data serial-to-parallel conversion device 100 also includes a plurality of data input channels, and each serial-to-parallel data processing module 101 and the FIFO clock buffer module 102 connected thereto process data in one of the multiple data input channels. Each serial-parallel data processing module 101 is configured to convert serial data into multiple parallel data, extract information from each parallel data, extract valid data and additional information data, and delete synchronization bits in valid data and additional information data According to the instruction, the effective data after the synchronization bit information is deleted and the additional information data are output to the FIFO clock buffer module 102 connected to the serial and parallel data processing module 101; the FIFO clock buffer module 102 is configured to buffer the data, Store valid data and additional information data, and separate, register, and reorganize additional information data. Among them, the effective data refers to the actual information to be transmitted in the data transmission, which is usually called actual data or data body, and the additional information data refers to the data that assists the transmission of the effective data. There are specific instructions in the following, and it will not be too much. Repeat.

Since the data processing process performed on the data in each data input channel is the same, the following describes the data processing process in one of the data input channels.

In an implementation manner provided by the present invention, for ease of understanding, a specific embodiment in which each data input channel transmits 12G-SDI video and audio signals is described. SDI (serial digital interface) is a digital component serial interface. The line interface is the interface that transmits each bit of the data word and the corresponding data sequentially through a single channel. The data transmission rate of the 12G-SDI video and audio signal is 12Gb/s.

When the data serial and parallel processing device processes the 12G-SDI video and audio signals in multiple data input channels, take 4 data input channels as an example, if each of the 4 data input channels inputs 12G-SDI For SDI video and audio signals, each input channel of 12G-SDI signals corresponds to a serial-parallel data processing module 101 and a FIFO clock buffer module 102 connected to the serial-parallel data processing module 101. Compared with the previous 4-channel 12G-SDI video and audio data are all input to a serial and parallel data processing module for processing, the serial and parallel data processing module 101 in the present invention only processes one channel of 12G-SDI video and audio data , Which reduces the amount of data that the serial-parallel data processing module 101 needs to process at the same time, so there will be no problems that data cannot pass or cannot pass normally due to excessive data volume, and it ensures that the 4 channels of 12G-SDI signals are at the same time Data stability during input; after the data is converted from serial to parallel, it is buffered by the FIFO clock buffer module 102 to demultiplex and separate the input data packets (in the data input channel, the data is the data packet In the form of transmission), separated into multiple valid data packets and separate additional information data packets, eliminating invalid information and original clock information in the original input data, replacing and inserting stable local clock information, redefining the data The packet read and write status is defined according to the flag bits of each valid data packet, and then sent to the subsequent data processing module, which effectively solves the problem of unstable frequency, clock, and jitter of the input data, and further ensures the quality of data transmission.

It can be understood that the data serial-to-parallel conversion device 100 of the present invention can also process other signals, including pure data signals, high-frequency waveform oscillation signals, microwave load transmission signals, etc. The video and audio signals are only proposed to facilitate the understanding of the present invention. An example cannot be regarded as a limitation on the protection scope of the present invention. In the process of multi-channel data transmission, when the amount of data to be processed by each channel is too large, the data serial-to-parallel conversion device provided by the present invention can be used, so that each channel is equipped with a serial-parallel data processing module and a serial-parallel data processing module. The FIFO clock buffer module connected to the data processing module ensures the stability of the input data and improves the quality of data transmission. Of course, when the amount of data is not large, such as when each channel transmits 3G-SDI input signals, the data serial-to-parallel conversion device provided by the present invention is also applicable, and the data serial-to-parallel conversion device provided by the present invention can be applied to more quickly Data is transmitted to improve the efficiency of data transmission. Specifically, the data processing method of the present invention is described in detail below.

In another embodiment, the FIFO clock buffer module 102 includes multiple data buffer spaces 1021. It is assumed that the number of data buffer spaces 1021 is equal to the number of multiple parallel data channels output by the serial-parallel data processing module 101. The data processing module 101 converts the 12G-SDI video and audio signal into 4 channels of parallel data, and the number of data buffer spaces 1021 is also 4. The multiple data buffer spaces 1021 are configured to perform independent data buffer processing at the same time according to predefined instructions without interfering with each other. After the current-stage serial-parallel data processing module 101 converts serial data into parallel data, the FIFO clock buffer module 102 follows the instructions Perform read and write operations. Specifically, different instructions will be issued according to the status of each data buffer space 1021, and each path of parallel data will be written into different empty data buffer spaces 1021 or waiting to be written to the data buffer. Space 1021, each data buffer space 1021 can simultaneously and independently perform data buffer processing, improving the speed of data buffering. For ease of understanding, taking the number of data buffer spaces 1021 in this embodiment as an example, taking a 12G-SDI video and audio signal as an example, the 12G-SDI video and audio signal data is converted to by the serial-parallel data processing module 101. 4 channels of 3G-SDI parallel data are written into the FIFO clock buffer module 102. Specifically, each channel of parallel data is written into each data buffer space 1021 according to the state of each data buffer space 1021. The status of each data buffer space 1021 includes empty, full, almost empty, almost full, and so on. When the state of the data buffer space 1021 is empty, it means that the current data buffer space 1021 can only be used for writing, but not for reading. If the reading is performed, it will overflow and invalid data will be read. When the state of the space 1021 is full, it means that the current data buffer space 1021 can only be read and cannot be written. If the write operation is performed, overflow will occur; the state of the data buffer 1021 is other than full or empty In other states (for example, almost empty or almost full), it means that the current data buffer space 1021 can perform both a write operation and a read operation. The data buffer space 1021 issues different commands according to different states to control the writing of the parallel data output by the previous-stage serial-parallel data processing module 101.

It should be noted that there is no one-to-one correspondence between multiple data buffer spaces 1021 and multiple parallel data. Specifically, for ease of understanding, the following is an example: the multiple parallel data is numbered 1, 2, 3, and 4. Similarly, the data buffer space 1021 is numbered A, B, C, and D. Assuming that A in the four data buffer spaces 1021 of A, B, C, and D is in an empty state, and the remaining three data buffer spaces B, C, and D are all in a full state, then the four parallel data channels are based on the stack first arrival order , The first parallel data will be written to the data buffer space 1021 of A, until the state of A changes from empty to full, and the remaining 3 parallel data will need to wait for the state of each data buffer space 1021 to be other than full. Then write according to the stack order; if in the 4 data buffer spaces 1021 of A, B, C, and D, the status of A and B is empty, the 4 parallel data will be sent and written to according to the order of the first arrival of the stack. A and B data buffer space 1021, the data sent by the serial-parallel data processing module 101 is distinguished in sequence (the sequence of data sent by the serial-parallel data processing module 101 is controlled at 220 video scanning pixels, or 250 clocks, or 1us Within), usually the states of the four data buffer spaces 1021 of A, B, C, and D are not empty or full at the same time, but when any two or more data buffer spaces 1021 are empty at the same time Or when it is full, the data is sequentially written into the data buffer space 1021 according to the sequence of data sent by the serial-parallel data processing module 101. In this embodiment, by setting the FIFO clock buffer module 102 to include multiple data buffer spaces 1021, The buffer space 1021 can read, process, and output data at the same time, which improves the data processing speed of the FIFO clock buffer module 102. Even if the amount of data to be processed is large, it can be completed in a shorter time, improving data serial-to-parallel conversion The working efficiency of the device.

In another embodiment, as shown in FIG. 2, the data buffer space 1021 includes a data state registration register 10211 and a local clock generator 10212, and the data state registration register 10211 is configured to read the data output by the serial and parallel data processing module 101 , Write, where the written data includes valid data, marked as ism(n)_set_pkttoobig; additional information data, marked as pkt_rdy_slot(n); and video format, frame rate, and original clock information corresponding to the video frame rate , Marked as FF_AF. The data status registration register 10211 temporarily stores the written valid data, additional information data, video format, frame rate, and the original clock information corresponding to the video frame rate, and separates and registers the written additional information data; The clock generator 10212 is used to generate local clock information. The local clock information is a stable 270MHz data reference clock. It uses the local reference clock to perform stable data receiving, sending, reading, and reading of all valid data packets in all data processing links. For writing and related processing, the data status registration register 10211 communicates with the local clock generator 10212. The data status registration register 10211 separates and registers the read additional information data and reads the local clock generator 10212 in real time. Add the local clock information to the additional information data, separate and register the additional information data packets in the data state registration register 10211, and add all valid data packets to the local clock information, the data state registration register 10211 The valid data and additional information data will be transmitted to the local clock generator 10212. The local clock generator 10212 will generate local clock information in real time and update the clock information in all valid data packets to resolve the clock of the source input signal data itself. The phenomenon of clock instability in the data transmission process caused by deviation, to ensure the stable transmission of data. The data processing process in each data buffer space 1021 is the same, which will be described in detail later, and will not be repeated here.

As shown in Figure 3, the present invention also provides a data processing method based on a data serial-to-parallel conversion device. The 12G-SDI video and audio signal is still taken as an example for description, because the data processing method of each data input channel is the same. , Here we only introduce the data processing method in one of the data input channels in detail to facilitate understanding. Among them, the processing method of the serial-parallel data processing module in a data input channel includes the following steps:

S301: Perform data matching and detection, and detect the data format and transmission rate;

Specifically, for 12G-SDI video and audio signals, first detect the data format and transmission rate of the signal of the input channel, that is, detect the video format, frame rate, audio format, and transmission rate of the 12G-SDI video and audio signal, and detect and determine Later, you need to save the relevant information such as video format, frame rate, audio format, and transmission rate first. The relevant information is necessary additional information in the processing links of each data sending, sending, reading, and writing, and cannot be changed. Even if the video data is reformed and the audio data is resampled, it is necessary to add back the original video and audio format, frame rate, transmission rate and other related information in the final output module.

S302: Perform data descrambling;

Specifically, because the data rate of the serial digital signal is very high, it must be processed before transmission. The original data stream is transmitted and scrambled and encoded with NRZI to ensure reliable recovery of the original data at the receiving end. Therefore, the serial-to-parallel conversion is performed After the device receives the signal, it needs to descramble the signal and perform NRZI non-return-to-zero decoding to restore the original data.

S303: Perform parallel conversion on the data, and convert the serial data into multiple parallel data;

Specifically, serially input data can be converted in parallel based on one data bus, and one data bus can be separated into multiple sub-data buses, and each sub-data bus can process part of the data simultaneously. For example, in this embodiment, the serially input 12Gbps data is converted in parallel based on an 80Bits data bus, and an 80Bits data bus is separated into four 20Bits sub-data buses, and each sub-data bus simultaneously processes 3Gbps data. For data, of course, a data bus can also be separated into 3, 5, etc. sub-data buses as required, and the present invention has no limitation on this.

S304: Demultiplex the data transmitted by each sub-data bus;

Since the data processing performed on multiple sub-data buses is the same, take the data processing process on one of the sub-data buses as an example. Specifically, demultiplexing is: extracting valid data and additional information data; among them, valid data Refers to video data and audio data. Additional information data refers to line information, check digits, interface type, sampling structure, components, bit depth, image update rate, video blanking information, video auxiliary data, video format information, audio channels and audio Format information and other information. It is understandable that data is transmitted in the form of data packets during the transmission process. In this step, the data transmitted in a single packet is transformed into data transmitted in multiple packets for parallel transmission, that is, the single packet data is divided into multiple valid data packets and separate data packets. The additional information packet is transmitted backward at the same time. The additional information data packet will be sent to the final data output stage through each module, and will be appended to the valid video and audio data packets again for the final signal transmission output.

S305: Remove the sync bit information data in the valid data and the additional information data;

The synchronization bit information includes clock information. Since new clock information is generated in the FIFO clock buffer module 102, the synchronization bits in the valid data packet and the additional information data packet in the serial-parallel data processing module 101 are redundant, and the valid data The synchronization bit information data in the packet and the additional information data packet is removed, which reduces the processing of invalid data and improves the processing efficiency.

S306: Detect the data format, and generate data format information;

The data format here includes the structure format after data reorganization. After the data processing of the above steps S301-S305, the structure format of the data will change. Therefore, the data format needs to be checked again before output, and the format information is extracted separately and released to the later The additional information data packet after the data clock reforming process of the level FIFO clock buffer module 102 will be sent to the final data output stage through each module, and will be attached to the valid data packet again for final signal transmission output.

S307: Data multiplexing.

Multiple sub-data processing buses are multiplexed into one data bus, and data is transmitted in parallel on one data bus. Specifically, in this embodiment, four 20Bits sub-data processing buses are multiplexed into an 80Bits parallel data processing bus, and the 4 parallel data processed by the serial and parallel data processing module 101 are transmitted in parallel through the 80Bits data processing bus. It is sent to the FIFO clock buffer module 102, and the FIFO clock buffer module 102 performs subsequent data processing. After the above process, the serial-parallel data processing module 101 converts the 12Gbps serial data into 4 channels of 3Gbps parallel data and outputs it to the FIFO clock buffer module 102. It should be noted that the data processed by the serial-parallel data processing module 101 is effective data and additional information data separated and removed from the original signal synchronization bit information.

Through the above method, the serial-parallel data processing module 101 converts 12G bps data into multiple parallel 3G bps data, and through the demultiplexing step, separates the transmitted data packet into multiple valid data packets and separate additional information Data packets, additional information data packets contain all additional information data, separate the valid data packets and the synchronization bit information in the additional information data packets, remove invalid information and invalid data, further improve data transmission efficiency, and reduce unnecessary data transmission.

The FIFO clock buffer module 102 processes data in accordance with pre-defined instructions. Specifically, the FIFO clock buffer module 102 includes multiple data buffer spaces 1021, because the number of data buffer spaces corresponds to the number of parallel data transmitted in each channel. The numbers are the same. Therefore, in this embodiment, there are 4 data buffer spaces 1021, and the data processing process in each data buffer space 1021 is the same. The following takes one of the data buffer spaces 1021 as an example for illustration. During data transmission Each data is transmitted in the form of data packets. As shown in FIG. 4, the data processing method of the data buffer space 1021 includes the following steps:

S401: Read data output by the serial-parallel data processing module according to the state of the data buffer space.

Specifically, when the state of the data buffer space 1021 is in a state other than full, data can be read from the serial-parallel data processing module 101. The states other than full include empty, almost full, and almost empty states, that is, the data buffer space 1021 is from the serial Before the data processing module 101 reads the data, it needs to determine the state of the data buffer space 1021. When the state of the data buffer space 1021 is not full, perform a data reading operation until the state of the data buffer space 1021 becomes full, then stop data reading Operation: After the data buffer space 1021 processes the data and sends the data to the lower-level processing module, the data buffer space 1021 becomes a state other than full, and the data reading operation is repeated. The data buffer space 1021 includes a data state registration register 10211 and a local clock generator 10212. Specifically, the data state registration register 10211 reads information such as valid data packets and additional information data packets processed by the serial-parallel data processing module 101. The above process is the specific data reading and writing process in a data buffer space. Multiple data buffer spaces simultaneously read and write data according to their respective states. The process of reading and writing data is described in detail above, so I will not go too much here. Repeat.

S402: The data state registration register separates and registers the information carried in the additional information data packet;

Specifically, the information carried in the additional information data packet includes data information such as interface type, sampling structure, components, bit depth and image update rate, video blanking information, video auxiliary data, video format information, audio channel and audio format information, etc. The above-mentioned information is registered and reserved in the data state registration register 10211 according to predefined instructions. The process of registering each information is to add a flag bit to each information. The flag bit corresponds each information to the valid data, which facilitates the subsequent restoration of the video and audio signal to accurately restore the video and audio signal.

S403: The data status registration register reads the local clock information generated by the local clock generator, and adds the local clock information to the valid data packet;

Specifically, as mentioned above, the data state registration register 10211 and the local clock generator 10212 are in a two-way communication connection, that is, the data state registration register 10211 can transmit data to the local clock generator 10212, and the local clock generator 10212 can also transmit data to the data state. The register 10211 transmits data. Therefore, the data status registration register 10211 can read the local clock information generated by the local clock generator 10212. While separately registering the data in the additional information packet, local clock information is added to all valid data packets. The local clock information is a stable 270MHz data reference clock, which uses the local reference clock for all valid data packets. Perform stable data receiving, sending, reading, writing and related processing in all data processing links, so that each video and audio effective data receiving, sending, reading, and writing processing module can have a stable reference clock to prevent system The original built-in clock offset or error accumulation caused by the signal after the signal is transmitted through multiple nodes, resulting in video frame sampling and audio popping problems.

S404: The local clock generator reads the valid data packet and the additional information data packet in the data state registration register, generates local clock information, and adds the local clock information to the valid data packet;

Specifically, the local clock generator 10212 rearranges valid data packets and additional information data packets, adding data information such as clock information, transmission destination, and transmission length. The local clock generator 10212 is a 270MHz local clock generator that can generate Stable and accurate local clock information. Here, adding the local clock information to the valid data packet again means to update the clock information in the valid data packet to further ensure the stability of the data clock.

S405: The local clock generator selects the data transmission target according to the state of the post-processing module.

Specifically, according to the status of the post-processing module, there are two data transmission targets to choose from: (1) Send data directly to the post-processing module processor for processing; (2) Temporarily store the data in the FIFO of the post-processing module In the memory. When the post-processing module is in a state other than full, the data is sent directly to the post-processing module processor. When the post-processing module status is full, the data is temporarily stored in the FIFO memory of the post-processing module, and waiting When the state of the first-level processing module becomes empty, the data is sent to the post-processing module processor for processing. FIFO (First-in-First-out) first-in first-out memory is used to temporarily store data and play a data buffer effect.

Through the above method, the FIFO clock buffer module 102 reformates the valid data and additional information data, and adds locally stable clock information to prevent the clock deviation of the input signal itself. (The input source signal itself has a certain clock deviation, and after multi-node transmission processing, there will be accumulated and amplified error clock information). The SMPTE international standards followed in video SDI data processing are:

(1) SMPTE ST 2082; (2) SMPTE ST 2081; (3) SMPTE ST 2048; (4) SMPTE ST 2036; (5) SMPTE ST 424; (6) SMPTE ST 292; (7) SMPTE ST 259.

The data status registration register 10211 in the data buffer space 1021 reads the valid data, additional information data, video frame rate and clock information in the serial-parallel data processing module 101; separates and registers the information in the additional information packet, and reads Obtaining local clock information, etc. are all performed in accordance with pre-defined instructions.

Specifically, various instructions can refer to the following table:

(1) Instructions for data transfer

Bits	Def	Command indication
22:16	Data compensation	Various flag information for each data packet
13:0	Data length	Indicate the data length of each data packet

(2) Instructions for reading and registration

(3) Instructions for data output

(4) Instructions for reporting data information

For ease of understanding, as shown in Figure 5, the present invention provides a schematic diagram of a data processing circuit of a data input channel in a data serial-to-parallel conversion device, where the SDI signal is input from the pin SDI_IO+, and the pins VDD_CDR and VDD_LDO are used Used to send/receive demultiplexed data, pins OUT0+, OUT0-, _OUT-, _OUT+ are high-speed interfaces, used to send data to the lower-level processing module, pin CLOCK is connected to the local clock generation circuit, and access to external stable The clock signal, the peripheral circuit connected to each pin has been specifically given in Figure 5, and will not be described again.

The present invention also provides a delayer. As shown in FIG. 6, the delayer 600 includes the aforementioned data serial-to-parallel conversion device 100, a data quantization processing device connected to the data serial-to-parallel conversion device, and a data quantization processing device. The connected delay processing device, the synthesis output device connected with the delay processing device.

Since the data serial-parallel conversion device can support 4 channels of 12G-SDI signal input at the same time, it solves the problem that the signal data cannot pass when 4 channels are input at the same time and the data volume of each channel is too large. Each serial-parallel conversion processing module in the conversion device corresponds to a FIFO clock buffer module, which solves the problems of unstable data frequency, clock, and jitter. Further, add a local clock to the clock buffer module and add local stable clock information to the data to prevent the clock deviation of the input signal itself (the input signal itself has a certain clock deviation, and after multi-node transmission processing, it will be more effective Accumulated and enlarged error clock information appears). The use of the above-mentioned data serial-to-parallel conversion device in the delayer ensures the stability of data transmission in the data input stage of the delayer, and ensures the quality of data transmission.

Further, while the above-mentioned data serial-to-parallel conversion device is used in the delay 600, the above-mentioned data processing method is also used for data processing. As there are detailed introductions above, it will not be described here.

The present invention also provides a signal conversion processor. The signal conversion processor includes the aforementioned data serial-to-parallel conversion device, and the data serial-to-parallel conversion device applies the aforementioned data processing method. As there is a detailed introduction above, I will not go into more details here.

In order to facilitate understanding, each embodiment of the present invention uses 12G-SDI as an audio signal as an example. However, it should be noted that this should not be regarded as a limitation of the present invention. The present invention can also be applied to other large-data signals. Transmission, processing.

The terms and expressions used in the specification of the present invention are for illustrative purposes only, and are not meant to constitute limitations. Those skilled in the art should understand that various changes can be made to the details of the above-mentioned embodiments without departing from the basic principles of the disclosed embodiments. Therefore, the scope of the present invention is only determined by the claims. In the claims, unless otherwise specified, all terms should be understood in the broadest and reasonable sense.

Claims (10)

1. A data serial-to-parallel conversion device, characterized in that it comprises a plurality of serial-parallel data processing modules and a plurality of FIFO clock buffer modules, each of the serial-parallel data processing modules is connected to one of the FIFO clock buffer modules;

   The data serial-to-parallel conversion device further includes a plurality of data input channels, and each of the serial-to-parallel data processing modules processes data in one of the data input channels;

   The serial-parallel data processing module is configured to convert serial data into parallel data, and send the parallel data to the FIFO clock buffer module;

   The FIFO clock buffer module is configured to buffer the parallel data received from the serial-parallel data processing module and send the parallel data to a lower-level processing module.
2. The data serial-to-parallel conversion device according to claim 1, wherein the FIFO clock buffer module comprises a plurality of data buffer spaces, and the plurality of data buffer spaces are configured to simultaneously perform independent data processing according to predefined instructions .
3. The data serial-to-parallel conversion device according to claim 2, wherein the data buffer space includes a data state registration register and a local clock generator, and the data state registration register and the local clock generator perform bidirectional Communication connection

   The data status registration register is configured to read and write valid data and additional information data according to instructions, and to separate and register the additional information data;

   The local clock generator is configured to send the local clock information generated in the local clock generator to the data status registration register, and the local clock generator is also configured to receive all output from the data status registration register. The effective data and the additional information data are reformed, the effective data and the additional information data are reformed, and the reformed effective data and the additional information data are sent to a lower-level processing module.
4. A data processing method based on the data serial-parallel conversion device of claim 3, wherein the data processing method of the serial-parallel data processing module includes the following steps:

   Perform data matching and detection, detect and extract data format and data transmission rate;

   Perform data descrambling;

   Perform data parallel conversion, convert serial data into multiple parallel data;

   Demultiplex each parallel data, extract valid data and additional information data;

   Remove the sync bit information in valid data and additional information data;

   Detect data format and generate format information;

   For data multiplexing, the parallel data processed by the serial-parallel data processing module is integrated on a bus and output in parallel.
5. The data processing method according to claim 4, wherein the data processing method in the FIFO clock buffer module comprises the following steps:

   A plurality of the data buffer spaces read and write data according to the state, and write the valid data and the additional information data to the data state registration register in the data buffer space;

   The data state registration register separates and registers the additional information data, and adds the local clock information generated by the local clock generator to the valid data while separating and registering;

   The data state registration register sends the valid data and the separated and registered additional information data to the local clock generator;

   The local clock generator reorganizes the valid data and the separated and registered additional information data;

   The local clock generator selects a lower-level data transmission target according to the state of the lower-level processing module, and outputs the additional information data and the valid data.
6. The data processing method according to claim 5, wherein the reading and writing of data in a plurality of the data buffer spaces according to the state comprises:

   Judging multiple states of the data buffer space;

   If one or more of the data buffer spaces are empty, almost empty, or almost full, according to the first arrival order of the multiple parallel data stacks output by the serial-parallel data processing module, the first one or more Parallel data are respectively written into the data state registration registers of one or more of the data buffer spaces whose states are empty, about to be empty, or about to be full.
7. The data processing method according to claim 5, wherein the local clock generator selecting the lower-level data transmission target according to the state of the lower-level processing module comprises:

   When the processor in the lower-level processing module is in a full state, the local clock generator selects to transmit data to the FIFO memory in the lower-level processing module, and the FIFO memory is configured to temporarily store data;

   Otherwise, the local clock generator selects the processor that transmits the data to the lower-level processing module.
8. A delay device comprising a data serial-to-parallel conversion device, a data quantization processing device connected to the data serial-to-parallel conversion device, a delay processing device connected to the data quantization processing device, and a delay processing device connected to the delay processing device The composite output device is characterized in that:

   The data serial-to-parallel conversion device is the data serial-to-parallel conversion device according to any one of claims 1-3.
9. The delay device according to claim 8, wherein the data serial-to-parallel conversion device uses the data processing method according to any one of claims 4-7.
10. A signal conversion processor, wherein the signal conversion processor comprises the data serial-to-parallel conversion device according to any one of claims 1-3, and the data serial-to-parallel conversion device applies any one of claims 4-7 The data processing method described in item.

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