WO2021008552A1

WO2021008552A1 - Data reading method and apparatus, and computer-readable storage medium

Info

Publication number: WO2021008552A1
Application number: PCT/CN2020/102123
Authority: WO
Inventors: 董礼玲
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2019-07-15
Filing date: 2020-07-15
Publication date: 2021-01-21
Also published as: CN112231241A; CN112231241B

Abstract

Disclosed in the present application are a data reading method and apparatus, and a computer-readable storage medium. The method comprises: receiving a read data request carrying a target storage address in a target memory, and converting the target storage address into a first cache address; reading first data corresponding to the first cache address from a first cache, the first data comprising a second cache address; reading second data corresponding to the second cache address from a second cache, comparing the second data with the read data request, and determining whether the read data request hits the second data, wherein the entry width W1 of the first cache is less than the entry width W2 of the second cache, the number of entries K1 of the first cache is greater than the number of entries K2 of the second cache, and K1*W1+K2*W2<K1*W2; in response to a determination result that the read data request hits the second data, outputting the second data; and in response to a determination result that the read data request does not hit the second data, reading data in the target memory according to the target storage address and outputting the read data in the target memory.

Description

Data reading method and device, computer readable storage medium

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office with an application number of 201910637085.7 on July 15, 2019. The entire content of this application is incorporated into this application by reference.

Technical field

The embodiments of the present application relate to, but are not limited to, the field of network communication technology, such as a data reading method and device, and a computer-readable storage medium.

Background technique

With the increase of table item capacity in network equipment (routers, switches, etc.), the static random access memory (SRAM) inside the network processor (Network Processor, NP) chip cannot meet the capacity requirements of table items. Large-capacity dynamic random access memory (Dynamic Random Access Memory, DRAM), that is, DRAM, etc. will be used to store table entry information. However, the DRAM access time is relatively long, and it cannot meet the bandwidth requirement of NP for table lookup. Therefore, a small-capacity cache (Cache) is usually set inside the NP to absorb part of the traffic for accessing DRAM.

As shown in Figure 1, in the network processor application scenario, the central processing unit (CPU) or the packet processor (PP) initiates a table lookup operation. This operation will first go through the Cache management module. If the Cache If it hits, it will directly return the table lookup result. If the Cache misses, then send a table lookup request to the DRAM.

Due to the huge difference in capacity between DRAM and Cache, it is impossible for all data in DRAM to be written into Cache, so there must be a situation where multiple entries in DRAM are mapped to the same address in Cache. The mapping methods include:

(1) Direct mapping: As shown in Figure 2a, the position of each entry in the DRAM in the Cache is unique;

(2) Fully associative mapping: As shown in Figure 2b, each entry in the DRAM can be mapped to any location in the Cache;

(3) Group associative mapping: As shown in Figure 2c, between full associative mapping and direct mapping, each entry in the DRAM can be mapped to a part of the Cache.

In direct mapping, because the location of the DRAM entry in the Cache is uniquely determined, there is generally no need to replace the algorithm, but there are situations where multiple commonly used DRAM data is mapped to the same address in the Cache. When this occurs, there will be frequent Cache replacement operations. Causes the Cache performance to degrade.

In full associative and group associative mapping, since each entry in the DRAM can be mapped to multiple locations in the Cache, the possibility of frequent replacement is reduced. Fully associative Cache can often get the best performance, but it needs to compare all items in the Cache, which is too complex to implement. Therefore, group-associated Cache is commonly used. Usually, the address range of DRAM is divided into K groups in implementation, and each group can be mapped to n entries in the Cache. Because the Cache space between groups cannot be shared, the required The depth of the Cache (that is, the number of entries) is K*n.

There is very little research on how to save the storage space of the cache and reduce the overhead of the cache. Most studies only focus on the impact of replacement strategies on Cache performance, and most applications are still based on the principle of "locality" (that is, if a storage unit is being accessed, it is likely to be accessed again in the near future), which does not conform to the network The flow characteristics of the processor. Other solutions use multi-level Cache and hybrid replacement strategies, which cannot meet the high bandwidth requirements of network processors.

Summary of the invention

The embodiments of the present application provide a data reading method and device, and a computer-readable storage medium, which can save the total storage space of the cache and reduce the overhead of the cache.

The embodiment of the application provides a data reading method, including:

Receiving a read data request, where the read data request carries a target storage address in the target memory; converting the target storage address into a first cache address;

Reading first data corresponding to the first cache address from the first cache, where the first data includes a second cache address;

Read the second data corresponding to the second cache address from the second cache, compare the second data with the read data request, and determine whether the read data request hits the second data, wherein the first The entry width W1 of a cache is smaller than the entry width W2 of the second cache, the number of entries K1 of the first cache is greater than the number of entries K2 of the second cache, and K1*W1+K2*W2<K1*W2, Among them, W1, W2, K1, K2 are all natural numbers greater than 1;

In response to the judgment result that the read data request hits the second data, the second data is output; in response to the judgment result that the read data request misses the second data, the target memory is read according to the target storage address. Data and output the read data in the target memory.

The embodiments of the present application also provide a computer-readable storage medium, the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to realize The data reading method described in any of the above.

An embodiment of the present application also provides a data reading device, including a processor and a memory, wherein the processor is configured to execute a program stored in the memory to implement the data reading method described in any one of the above.

The embodiment of the present application also provides a data reading device, including an address conversion module, a first cache, a second cache, and a data search module, wherein:

An address conversion module, configured to receive a read data request, where the read data request carries a target storage address in the target memory; convert the target storage address into a first cache address;

The first cache is set to cache the second cache address;

The second cache is set to cache data in the target memory;

A data search module, configured to read first data corresponding to the first cache address from a first cache, the first data including a second cache address; read from the second cache corresponding to the second cache address Compare the second data with the read data request to determine whether the read data request hits the second data, wherein the entry width W1 of the first cache is smaller than the entry of the second cache Width W2, the number of entries K1 in the first cache is greater than the number K2 of entries in the second cache, and K1*W1+K2*W2<K1*W2, where W1, W2, K1, and K2 are all greater than 1. Natural number; in response to the judgment result that the read data request hits the second data, output second data; in response to the judgment result that the read data request misses the second data, read the target memory according to the target storage address And output the read data in the target memory.

Description of the drawings

The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application, and do not constitute a limitation to the technical solution of the present application.

Figure 1 is a schematic diagram of the data flow of a network processor accessing DRAM in related technologies;

Figure 2a is a schematic diagram of the principle of direct mapping between cache and DRAM in related technologies;

Figure 2b is a schematic diagram of the principle of a fully associative mapping method between cache and DRAM in related technologies;

Figure 2c is a schematic diagram of the principle of the group associative mapping method between the cache and the DRAM in the related technology;

FIG. 3 is a first exemplary flowchart of a data reading method according to an embodiment of the present application;

4 is a schematic diagram of a first exemplary structure of a data reading device according to an embodiment of the application;

5 is a schematic diagram of a second exemplary structure of a data reading device according to an embodiment of the application;

6 is a schematic diagram of a third exemplary structure of a data reading device according to an embodiment of the application;

7 is a schematic diagram of a fourth exemplary structure of a data reading device according to an embodiment of the application;

FIG. 8 is a schematic diagram of a cache lookup and cache update process according to an embodiment of the application;

FIG. 9 is a schematic diagram of an aging and keep-alive process according to an embodiment of the application.

Detailed ways

Hereinafter, the embodiments of the present application will be described with reference to the drawings.

The steps shown in the flowchart of the drawings may be executed in a computer system such as a set of computer-executable instructions. Also, although a logical sequence is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than here.

As shown in FIG. 3, an embodiment of the present application provides a data reading method, including:

Step 310: Receive a read data request, where the read data request carries a target storage address in the target memory; convert the target storage address into a first cache address.

The method of converting the target storage address into the first cache address can use the address conversion method in the related art, which is not limited in this application.

Step 320: Read the first data corresponding to the first cache address from the first cache, where the first data includes the second cache address.

In an exemplary embodiment, the mapping method between the first cache and the target memory is group associative mapping, and the address range of the target memory is divided into K groups, and each group can be indirectly mapped to all groups. There are n entries in the first cache, that is, the number of entries in the first cache K1=K*n, and both K and n are natural numbers greater than 1.

Step 330: Read the second data corresponding to the second cache address from the second cache, compare the second data with the read data request, and determine whether the read data request hits the second data, where the entry width of the first cache W1 is smaller than the entry width W2 of the second cache, the number of entries in the first cache K1 is greater than the number of entries in the second cache K2, and K1*W1+K2*W2<K1*W2, W1, W2, K1, and K2 are all greater than 1. The natural number, * is the multiplication sign.

When using the group associative mapping method in the related technology, the number of Cache entries required is K1, and the required Cache entry width is W2, that is, the total cache space required is K1*W2; when using the indirect mapping method of this application When, the total buffer space required is K1*W1+K2*W2. Since the entry in the first cache of the present application stores the second cache address, and the entry in the second cache stores data in the target memory, the entry width W1 of the first cache is significantly smaller than the entry width W2 of the second cache Therefore, by using the indirect mapping method of this application, K1*W1+K2*W2<K1*W2 can be easily satisfied, which saves the total storage space of the cache and reduces the overhead of the cache.

In an exemplary embodiment, the number of entries in the second cache is K2=K.

Step 340: If the read data request hits the second data, output the second data.

In an exemplary embodiment, after the output of the second data, the method further includes: increasing the keep-alive weight of the second data by 1.

Step 350: If the read data request misses the second data, read and output the data in the target memory according to the target memory address.

Compared with the related technology, the data reading method provided by the embodiment of the present application sets two caches: the first cache and the second cache, and indirectly maps and reads the data in the target memory. Because the entries in the first cache are stored Is the second cache address, the entry in the second cache stores the data in the target memory, the entry width of the first cache is obviously smaller than the entry width of the second cache, by setting: K1*W1+K2*W2<K1* W2 effectively saves the total storage space of the cache, reduces the overhead of the cache, and compared with the direct mapping using a cache (the number of entries is K2, the entry width is W2), only a small amount of storage space is added (because W1 is far away). Less than W2, K1*W1 is also much smaller than K2*W2), but it effectively improves the hit rate of the Cache and meets the high bandwidth requirements of the network processor.

In an exemplary embodiment, after the reading of the data in the target memory according to the target storage address, the method further includes: detecting whether there is a usable second cache address in the second cache; if there is a usable second cache address in the second cache, The second cache address stores the read data in the target memory to the available second cache address, and stores the available second cache address to the first cache address.

In the Cache solution in the related technology, as long as the DRAM has data returned, the Cache is updated and a replacement operation occurs. Common replacement strategies include:

(1) Least Recently Used (LRU): Replace the least frequently used items. This method usually needs to be implemented through a complex doubly linked list. After each visit, the accessed entry is taken out of the linked list and inserted into the head of the linked list, and the logic implementation is more complicated.

(2) First Input First Output (FIFO): Replace the earliest entry into the Cache. The logic of this method is simple to implement, but it is not necessarily suitable for the actual business model.

(3) Random: randomly select one for replacement, that is, completely ignore the historical usage of items in the Cache.

(4) Least Frequently Used (LFU): Record the most recently used frequency of each item, and select the least frequently used item when replacement occurs.

However, in the network processor, the performance is often better when the Cache is not updated for small bandwidth traffic. Therefore, in the embodiment of the present application, the Cache update operation is performed only when the Cache has available space, which reduces the possibility of replacing a large-traffic entry with a small-traffic entry from the Cache.

Unlike ordinary processors, the flow of network processors accessing DRAM does not have the feature of "locality", that is, accessing an item does not mean that the item will be frequently accessed in a short time. The replacement strategies of LRU including pseudo Least Recently Used (pLRU), FIFO, Random, etc. may have the possibility of "squeezing out" the contents of high-traffic entries into the Cache after small-flow entries are written into the Cache. Therefore, only LFU is most suitable for the application scenario of the network processor, but in order to select the item with the lowest frequency of use, sorting is required in most implementations, and the logic implementation is more complicated.

In an exemplary embodiment, the detecting whether there is an available second cache address in the second cache includes: when there is second data with a keep-alive weight of 0 in the second cache, then there is Available second cache address; when there is no second data with a keep-alive weight of 0 in the second cache, there is no available second cache address in the second cache.

In the embodiment of the present application, by setting the keep-alive weight and simulating the LFU operation, the large-traffic entries are kept in the cache, which reduces the possibility of replacing the large-traffic entries out of the cache by small-traffic entries, and improves the cache hit rate.

In an exemplary embodiment, after detecting whether there is a second cache address available in the second cache, the method further includes: if there is no available second cache address, determining the second cache address of the current aging location Whether the keep-alive weight of the data is 0; if the keep-alive weight of the second data at the current aging location is 0, record the current aging location as an available second cache address; if the keep-alive weight of the second data at the current aging location is not If the value is 0, the keep-alive weight of the second data at the current aging position is reduced by 1, and the current aging position is pointed to the next second cache address, and the cycle is executed to determine whether the keep-alive weight of the second data at the current aging position is 0 Until the keep-alive weight of the second data at the current aging position is 0.

The embodiment of the application realizes the selection of available cache space through simple aging and keep-alive operations, avoiding complicated sorting or comparison logic.

In the embodiment of the present application, the cache access operation includes two parts: a table lookup operation and an update operation. The steps of the table lookup operation include: after a read data request arrives, after address conversion processing, an address for accessing the first cache is generated; Read the address of the second cache in the corresponding position in the middle, read the data (second data) of the second cache in the second cache according to the address, and compare it with the read data request to determine whether the read data request hits the read According to whether the read data request hits the read second cache data, it is determined whether a read request needs to be sent to the DRAM. When the read data request hits the read data in the second cache, there is no need to send a read request to the DRAM, just return the read data in the second cache directly to the CPU/PP, and perform the corresponding entry in the second cache. Keep-alive operation (the keep-alive weight of the data in the second cache that is about to be read increases by 1); when the read data request does not hit the read second cache data, a read request needs to be sent to the DRAM, and the DRAM responds The result is returned to the CPU/PP. After the DRAM response is returned, if the second cache has an available address, the cache update operation is performed, and if there is no available address in the second cache, only the table lookup result is returned without cache update.

When the DRAM response returns, if the second cache has an available address, the cache update operation is performed. The steps are as follows: calculate the address of the entry in the first cache in the address conversion module; write the available address in the second cache to the first cache A corresponding position calculated in the cache; the data returned by the DRAM response is written into the position corresponding to the available address in the second cache.

In order to simplify the implementation, when the read data request hits the second data, the corresponding entry in the second cache is kept alive, that is, the keep-alive weight of the second data is incremented by 1; when the read data request does not hit the second data, the The process of aging and finding free space is as follows:

Determine whether the current second cache has an available address. If there is an available address, the aging process ends; if the current second cache does not have an available address, then determine whether the keep-alive weight of the second data pointed to by the current aging location is 0, if the current aging The keep-alive weight of the second data pointed to by the location is 0, then the second cache address of the current aging location is set as an available address, and the aging process ends, and the address can be used for subsequent cache updates; if the current aging location points to the second data If the keep-alive weight is not 0, the keep-alive weight of the second data at the current aging position is decremented by 1, and the current aging position is pointed to the next address in the second cache, and the second data pointed to by the current aging position is determined circularly The operation of whether the keep-alive weight of is 0 until the keep-alive weight of the second data pointed to by the current aging position is 0 occurs.

The embodiments of the present application also provide a computer-readable storage medium, the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to realize Any of the data reading methods described above.

An embodiment of the present application also provides a data reading device, including a processor and a memory, and the processor is configured to execute a program stored in the memory to implement the data reading method as described above.

As shown in FIG. 4, an embodiment of the present application also provides a data reading device, including an address conversion module 401, a first cache 402, a second cache 403, and a data search module 404. The address conversion module 401 is configured to receive reading A data request, the read data request carries the target storage address in the target memory; the target storage address is converted to a first cache address; the first cache 402 is set to cache the second cache address; the second cache 403 is set to cache Data in the target memory; the data search module 404 is configured to read the first data corresponding to the first cache address from the first cache 402, the first data includes the second cache address; read from the second cache 403 The second data corresponding to the second cache address is compared with the read data request to determine whether the read data request hits the second data. The entry width W1 of the first cache 402 is smaller than the entry width of the second cache 403 W2, the number of entries K1 of the first cache 402 is greater than the number of entries K2 of the second cache 403, and K1*W1+K2*W2<K1*W2, where W1, W2, K1, and K2 are all natural numbers greater than 1; if If it hits, output the second data; if it misses, read the data in the target memory according to the target storage address and output it.

The method for the address conversion module 401 to convert the target storage address into the first cache address can use an address conversion method in the related art, which is not limited in this application.

In an exemplary embodiment, the mapping method between the first cache 402 and the target memory is group associative mapping, and the address range of the target memory is divided into K groups, and each group can be indirectly mapped to For the n entries in the first cache 402, the number of entries in the first cache 402 is K1=K*n, where K and n are both natural numbers greater than 1.

When using the group associative mapping method in the related technology, the number of Cache entries required is K1, and the required Cache entry width is W2, that is, the total cache space required is K1*W2; when using the indirect mapping method of this application When, the total buffer space required is K1*W1+K2*W2. Since the entry in the first cache 402 of the present application stores the second cache address, and the entry in the second cache 403 stores data in the target memory, the entry width W1 of the first cache 402 is significantly smaller than the second cache 403 Therefore, by using the indirect mapping method of this application, K1*W1+K2*W2<K1*W2 can be easily satisfied, which saves the total storage space of the cache and reduces the overhead of the cache.

In an exemplary embodiment, the number of entries in the second cache 403 is K2=K.

In an exemplary embodiment, as shown in FIG. 5, the data reading device further includes a cache update module 405. The data search module 404 notifies the cache after reading the data in the target memory according to the target storage address. Update module 405; The cache update module 405 is configured to receive a notification from the data search module 404 to detect whether there is a second cache address available in the second cache 403; if there is a second cache address available, it will The read data in the target memory is stored in the available second cache address, and the available second cache address is stored in the first cache address.

In an exemplary embodiment, the cache update module 405 detects whether there is a usable second cache address in the second cache 403, including: when there is a keep-alive weight of 0 in the second cache 403, For the second data, the second cache address is available in the second cache 403; when the second data with a keep-alive weight of 0 does not exist in the second cache 403, the second cache There is no second cache address available in 403.

In the Cache solution in the related technology, as long as the DRAM has data returned, the Cache is updated and a replacement operation occurs. But in the network processor, the performance is often better when the Cache is not updated for small bandwidth traffic. Therefore, in the embodiment of the present application, the Cache update operation is performed only when the Cache has available space, which reduces the possibility of replacing a large-traffic entry with a small-traffic entry from the Cache.

In an exemplary embodiment, as shown in FIG. 6, the data reading device further includes an aging keep-alive module 406, and the cache update module 405 is further configured to notify if there is no available second cache address The aging keep-alive module 406; the aging keep-alive module 406 is configured to receive the notification from the cache update module 405 to determine whether the keep-alive weight of the second data at the current aging position is 0; if it is 0, record the current The aging position is the available second cache address; if the keep-alive weight of the second data at the current aging position is not 0, the keep-alive weight of the second data at the current aging position is reduced by 1, and the current aging position is pointed to the next first Second, cache the address, and cyclically execute the step of judging whether the keep-alive weight of the second data at the current aging position is 0, until the keep-alive weight of the second data at the current aging position is 0 appears. The embodiment of the application realizes the selection of available cache space through simple aging and keep-alive operations, avoiding complicated sorting or comparison logic.

In an exemplary embodiment, after the data search module 404 outputs the second data, it is further configured to: notify the aging keep-alive module 406; the aging keep-alive module 406 is further configured to receive the The notification from the data search module 404 increases the keep-alive weight of the second data by 1.

In another exemplary embodiment, as shown in FIG. 7, a data reading device according to an embodiment of the present application includes:

(1) Address conversion module: set to convert the request to the address of the access pointer Ram, and when the DRAM response returns, the same operation is also required to obtain the address of the write-back pointer Ram. For example, it can be implemented by using truncation or cyclic redundancy check (Cyclic Redundancy Check, CRC) calculation.

(2) Pointer Ram (that is, the first cache): Set to store the address of the corresponding entry in the Cache ram to achieve indirect access to the Cache Ram. The Ram depth of the pointer is usually an integer multiple of Cache Ram. Under the same Cache depth, the probability of collision can be effectively reduced.

(3) Cache Ram (that is, the second cache): set to store actual entry data and address information.

(4) Data search module: It is set to search the corresponding data in the cache (including the pointer Ram and Cache Ram) or DRAM according to the address of the pointer Ram.

(5) Aging keep-alive module: It is set to record the keep-alive weight corresponding to each entry in the Cache, and it is also set to determine whether keep-alive and aging operations are required according to whether there is an item hit at that time and the available Cache space.

(6) Cache update module: When the DRAM response is returned, if the aging keep-alive module returns available Cache space, the Cache update operation is performed.

(7) Output arbitration module: Arbitrate between Cache Ram return (Cache hit) and DRAM return (Cache miss), and select the final result returned to the CPU/PP.

In this solution, the Cache access operation can be divided into two parts, the table lookup operation and the update operation, and the aging operation is performed independently of the table lookup process. As shown in Figure 8, the steps of the table lookup operation are:

(1) After the request address arrives, it is processed by the address conversion module to generate the address of the access pointer Ram.

(2) Read the address to access the Cache Ram from the corresponding position in the pointer Ram, read the Cache data in the Cache Ram according to the address, and compare it with the request to determine whether it is a hit.

(3) Determine whether a read request needs to be sent to the DRAM according to whether the Cache is hit. When the Cache hits, there is no need to send a read request to the DRAM, just return the data in the Cache to the CPU/PP directly through the output arbitration module, and the aging keep-alive module will keep alive the corresponding entries in the Cache (that is, the Cache ram The keep-alive weight of the address increases 1); when the Cache misses, it needs to send a read request to the DRAM, and the DRAM response result is returned to the CPU/PP through the output arbitration module. After the DRAM response is returned, the aging keep-alive module returns When there is an available address, the Cache update operation is performed. When the aging keep-alive module does not return an available address, only the table lookup result is returned without Cache update.

In the Cache update module, when the DRAM response is returned, if the aging keep-alive module returns available Cache space, the Cache update operation is performed, as shown in Figure 8. The update operation steps are as follows:

(1) Calculate the address of the entry in the pointer Ram through the address calculation module.

(2) Write the available address of the Cache Ram into the corresponding position of the address in the calculated pointer Ram.

(3) Write the read DRAM data into the corresponding location of the Cache Ram available address.

In order to simplify the implementation, in the aging keep-alive module, when the Cache hits, the corresponding entry of the Cache is kept alive, that is, the keep-alive weight of the Cache ram address is incremented by 1; when the Cache does not hit, it performs aging and searches for available space. Operation. As shown in Figure 9, the process of the aging operation is as follows:

(1) Determine whether there is available Cache space at that time. If there is an available address, the aging process ends, and the address can be used for subsequent Cache updates.

(2) When there is no available Cache space, first determine whether the keep-alive weight of the current location is 0. If the keep-alive weight is 0, the aging process ends, and the location is saved as a usable address. If the keep-alive weight is not If it is 0, the keep-alive weight of the current position is reduced by 1, and the current aging position is pointed to the next address, and the above judgment process is executed in a loop until the keep-alive weight is 0.

Adopting the data reading method and device and computer-readable storage medium provided by the embodiments of the present application has the following advantages: through indirect mapping, a group-associated cache is realized with lower overhead, and the probability of cache conflict is reduced; Simulates the LFU operation, keeps large traffic entries in the Cache, improves the Cache hit rate, and meets the high bandwidth requirements of the network processor; through simple aging and keep-alive operations, the choice of available Cache space is realized, avoiding complexity The sorting or comparison logic effectively reduces the logic complexity and saves the resource overhead of Cache.

Claims

A data reading method includes:

Receiving a read data request, where the read data request carries a target storage address in the target memory;

Converting the target storage address into the first cache address;

Reading first data corresponding to the first cache address from the first cache, where the first data includes a second cache address;

Read the second data corresponding to the second cache address from the second cache, compare the second data with the read data request, and determine whether the read data request hits the second data, wherein the first The entry width W1 of a cache is smaller than the entry width W2 of the second cache, the number of entries K1 of the first cache is greater than the number of entries K2 of the second cache, and K1*W1+K2*W2<K1*W2, Among them, W1, W2, K1, K2 are all natural numbers greater than 1;

In response to the judgment result that the read data request hits the second data, the second data is output; in response to the judgment result that the read data request misses the second data, the target memory is read according to the target storage address. Data and output the read data in the target memory.
The method according to claim 1, after the reading data in the target memory according to the target storage address, further comprising:

Detecting whether there is a usable second cache address in the second cache;

In response to the detection result that there is an available second cache address in the second cache, store the read data in the target memory to the available second cache address, and store the available second cache address The cache address is stored in the first cache address.
The method according to claim 2, wherein the detecting whether there is a second cache address available in the second cache comprises:

In the case where the second data with a keep-alive weight of 0 exists in the second cache, the second cache address is available in the second cache; there is no keep-alive weight in the second cache In the case of the second data of 0, there is no available second cache address in the second cache.
The method according to claim 3, after the output of the second data, further comprising: increasing the keep-alive weight of the second data by 1.
The method according to claim 3, after said detecting whether there is an available second cache address in the second cache, further comprising:

In response to the detection result that the second cache address is not available in the second cache, determining whether the keep-alive weight of the second data currently aging the second cache address is 0;

In response to the judgment result that the keep-alive weight of the second data of the currently aged second cache address is 0, recording the currently aged second cache address as the available second cache address;

In response to the judgment result that the keep-alive weight of the second data of the currently aging second cache address is not 0, the keep-alive weight of the second data of the currently aging second cache address is reduced by 1, and the current The aging second cache address points to the next aging second cache address, and the step of determining whether the keep-alive weight of the second data of the currently aging second cache address is 0 is performed cyclically until the current aging second cache address appears The keep-alive weight of the second data is 0.
The method according to any one of claims 1 to 5, wherein the mapping mode between the first cache and the target memory is group associative mapping, and the address range of the target memory is divided into K groups , Each group can be indirectly mapped to n entries in the first cache, and the number of entries in the first cache is K1=K*n, where K and n are both natural numbers greater than 1.
The method according to claim 6, wherein the number of entries in the second cache is K2=K.
A computer-readable storage medium stores at least one program, and the at least one program can be executed by at least one processor to implement the data reading method according to any one of claims 1 to 7.
A data reading device includes a processor and a memory, wherein the processor is configured to execute a program stored in the memory to implement the data reading method according to any one of claims 1 to 7.
A data reading device includes an address conversion module, a first cache, a second cache, and a data search module, wherein:

An address conversion module, configured to receive a read data request, where the read data request carries a target storage address in the target memory; convert the target storage address into a first cache address;

The first cache is set to cache the second cache address;

The second cache is set to cache data in the target memory;

The data search module is configured to read the first data corresponding to the first cache address from the first cache, the first data including the second cache address; read the second cache address from the second cache Compare the second data with the read data request to determine whether the read data request hits the second data, wherein the entry width W1 of the first cache is smaller than the entry of the second cache Width W2, the number of entries K1 in the first cache is greater than the number K2 of entries in the second cache, and K1*W1+K2*W2<K1*W2, where W1, W2, K1, and K2 are all greater than 1. Natural number; in response to the judgment result that the read data request hits the second data, output second data; in response to the judgment result that the read data request misses the second data, read the target memory according to the target storage address And output the read data in the target memory.