WO2020261276A1

WO2020261276A1 - Single photon detector based on thyristor working principle

Info

Publication number: WO2020261276A1
Application number: PCT/IL2020/050712
Authority: WO
Inventors: Aharon Roni EL-BAHAR
Original assignee: 5D Sensing Ltd.
Priority date: 2019-06-25
Filing date: 2020-06-25
Publication date: 2020-12-30

Abstract

A photon detector comprises a semiconductor device comprising a plurality of P-type and N-type layers, a cathode, and an anode. A quenching resistor electrically connects between the anode and a drain voltage. At least two gates connect between adjacent layers of the P-type and N-type layers. Absorption of a photon causes the gates to switch between an open state, in which the semiconductor device is in a forward blocking mode, and in which a voltage across the device is the drain voltage, and a closed state, in which the semiconductor device is in a forward conducting mode, and in which the voltage across the device is discharged. The quenching resistor is configured to restore the voltage to the drain voltage. A sensitivity of the detector is adjustable, to permit switching between the forward blocking mode and the forward conducting mode through absorption of an adjustable number of photons.

Description

SINGLE PHOTON DETECTOR BASED ON THYRISTOR WORKING PRINCIPLE

RELATED APPLICATIONS

This Application claims priority to U.S. Provisional Patent Application No. 62/866,188, filed June 25, 2019, entitled “LOW OPERATION VOLTAGE CONFIGURABLE SINGLE PHOTON DETECTOR DEVICE IN CMOS TECHNOLOGY,” the contents of which are incorporated by reference as if fully set forth herein.

BACKGROUND

The present invention, in some embodiments, relates to a photon detection device, and more specifically, but not exclusively, to a CMOS compatible photon sensor based on a thyristor working principle, in which the gate current pulse for triggering the device is replaced by photons that generate the needed charge.

Single photon detectors are critical components in many applications, such as ultra-low light detection and measurement of photon arrival times. Ultra-low light detection is used for night vision, low light photography, and star detection in space. Single photon detectors are also commonly used in LIDAR applications, in which a laser pulse is transmitted, reflected off of a target object, and subsequently received. The LIDAR device measures the time taken for the light pulse to return, also known as the“time of flight.” This time of flight measurement is then converted, using the speed of light, to distance or depth of the target object.

The most common single photon detector is a Single Photon Avalanche Diodes (SPAD). A SPAD is a semiconductor diode that is reverse biased well above its breakdown voltage. Due to this reverse bias, any absorption of radiation results in an avalanche effect and complete breakdown of the reverse bias potential. This breakdown results in a pulse of discharge, which occurs very quickly. Even a single photon may cause this avalanche effect. The mechanism of operation of a SPAD is explicated, among other places, in International Patent Application, co filed on herewith date, attorney docket number 83033, by inventor Aharon El-Bahar, entitled DIGITAL READOUT ENABLING 2D AND 3D ANALYSIS FOR SILICON PHOTO MULTIPLIER, which claims priority to U.S. Provisional Patent Application No. 62/866,135, filed June 25, 2019, entitled MULTI OUTPUT READOUT TECHNIQUE ENABLING 2D AND 3D READOUT CONCURRENTLY OF CMOS BASED SENSORS, and U.S. Provisional Patent Application No. 62/866,173, filed June 25, 2019, entitled NOVEL DIGITAL CONTROLLED READOUT TECHNIQUE FOR SINGLE PHOTON AVALANCHE DIODE ARRAY AND SILICON PHOTO MULTIPLIER, the contents of which are incorporated by reference as if fully set forth herein.

A thyristor, also known as a silicon controlled rectifier, is a four-layered, three-terminal semiconductor device, with each layer consisting of alternately N-type or P-type material, typically P-N-P-N. The anode and cathode terminals are across all four layers. The control terminal, called the gate, is typically attached to p-type material near the cathode. The operation of a thyristor can be understood in terms of a pair of tightly coupled bipolar junction transistors, arranged to cause a self-latching action. Thyristors have three states. The first state is a reverse blocking mode, in which voltage is applied in a direction that would be blocked by a diode. The second state is a forward blocking mode, in which voltage is applied in a direction that would cause a diode to conduct, but the thyristor has not been triggered into conduction. The third state is a forward-conducting mode, in which the thyristor has been triggered into conduction and will remain conducting until the forward current drops below a threshold value known as a“holding current.”

A schematic depiction of a prior art thyristor 10 is shown in FIG. 1. When the anode is at a positive potential with respect to the cathode, junctions J1 and J3 are forward biased, while junction J2 is reverse biased. As J2 is reverse biased, no conduction takes place. If the voltage at the anode is increased beyond the breakdown voltage of the thyristor, an avalanche breakdown of J2 takes place, and the thyristor starts conducting. If a positive potential is applied at the gate terminal with respect to the cathode, the breakdown voltage of junction J2 is lowered. When the voltage at the anode is at or above this lower value, the thyristor begins conducting. The gate thus functions as a switch for converting the thyristor into forward-conducting mode.

SUMMARY

SPAD typically operate at a reverse bias voltage of approximately 25 V. This comparatively high voltage is required in order to create an electric field of a suitable magnitude (typically higher than 3 x 10⁵ V/cm) so that a single charge carrier injected into the depletion layer can trigger a self-sustaining avalanche. SPADs are not suited for operation at lower voltages, such as a voltage of 5V or 3.3V which are standard voltages for semiconductor materials. Integrating a SPAD with a digital circuit thus typically requires a voltage transformation.

In addition, the high voltage requirement for a SPAD results in a relatively large depletion layer. Generally, the thickness of a depletion layer is proportional to the square root of the applied voltage. Thus, a SPAD that operates on 25 Volts typically has a diameter of around 25 pm. While smaller SPADs have been developed, the active area in such SPADs is very small. In addition to the comparatively large size requirements for a semiconductor device, the physical implementation of an array of SPADs on a semiconductor substrate poses challenges. SPADs are typically implemented as either having an n-type layer on a p-type substrate, or a p- type layer within a deep n-well layer. In the former case, the SPAD requires an additional AC coupling layer, and also experiences a strong cross -coupling effect between neighboring SPAD devices. The cross-coupling is addressed either through distancing between neighboring SPAD devices and/or including trench isolations. The n-well layer architecture typically enables stronger isolation between neighboring SPAD devices and allows lower output voltage from the SPAD device. However, forming an effective SPAD with this architecture requires a very deep N-well layer, which is hard to implement.

In addition, SPADs have a fixed configuration and triggered through absorption of a single photon. It is not possible to adjust SPADs to be triggered with a different quantity of photons. Triggering with more than one photon is desirable, however, in a case of a high noise environment, when lesser sensitivity is required in order to minimize cases of false detection.

Accordingly, there is a need for a single photon detector which is capable of being implemented at low voltage, and consequently in smaller dimensions. There is also a need for a single-photon detector which is capable of being implemented effectively on a CMOS (complementary metal oxide semiconductor) topology without incurring the challenges present in current SPAD devices. There is also a need for a single photon detector that may be triggered by an adjustable quantity of photons. There is also a need for a device that can recover from detection very quickly, so it will be able to detect subsequent photon transmission events.

The present disclosure presents embodiments of a novel opto-electronic device for detecting a single photon, in which the gate of a thyristor is replaced by a light-detecting architecture that is responsive to a single photon pulse. The device sensitivity may be set to trigger at absorbance of a single photon, or at a lower sensitivity, such that it will pulse only when more photons are absorbed by the active area of the device. A quenching resistor enables the device to recharge quickly and thus operate as an ultra-fast single photon detector. The device is implementable using a standard CMOS implementation process, and may be easily integrated using analog or digital designs. The device also operates on low voltage, such as 5 volts or lower, for compatibility with voltage domains of CMOS circuits, and may have a diameter of as low as 2 pm.

According to a first aspect, a photon detector comprises a multilayered semiconductor device comprising a plurality of P-type and N-type layers, a cathode, and an anode. A quenching resistor electrically connects between the anode and a drain voltage. At least two gates connect between adjacent layers of the plurality of P-type and N-type layers. Absorption of at least one photon causes the gates to switch between an open state, in which the semiconductor device is in a forward blocking mode, and in which a voltage across the semiconductor device is the drain voltage, and a closed state, in which the semiconductor device is in a forward conducting mode, and in which the voltage across the semiconductor device is discharged. Following the discharge, the quenching resistor is configured to restore the voltage across the semiconductor device to the drain voltage. A sensitivity of the detector is adjustable, to permit switching between the forward blocking mode and the forward conducting mode through absorption of an adjustable number of photons.

Advantageously, the photon detector is capable of being operated with a comparatively low drain voltage, such as 5V or lower. Due to the low voltage used, the diameter of the photon detector may be as small as 2 pm. The photon detector may be constructed using a standard CMOS topology. In addition, the adjustable sensitivity of the photon detector allows it to be used for detecting different quantities of photons.

In another implementation according to the first aspect, the plurality of P-type and N-type layers comprise alternating P-type and N-type layers. Adjacent sets of alternating P-type and N- type layers respectively form a PNP bipolar transistor and a NPN bipolar transistor. The alternating layers thus function in the same manner as a thyristor, to block flow of current until one or more photons are absorbed, and to permit continuous flow of current after a photon is absorbed.

In another implementation according to the first aspect, the alternating p-type and n-type layers are arranged in a stack of layers defining outer layers and inner layers, the anode is an outer P-type layer, and the cathode is an outer N-type layer. Current flows across the entire photon detector, from cathode to anode, following triggering of the device with the at least one photon.

In another implementation according to the first aspect, each of the gates is connected to a gate voltage, and a sensitivity of the detector is controllable by adjusting at least one of the gate voltages. For example, lowering the gate voltages may cause the device to trigger only with absorbance of a larger number of photons, and vice versa. The gate voltages may be adjusted even after the photon detector is assembled.

In another implementation according to the first aspect, each of the gates is connected to at least one gate resistor, and a sensitivity of the detector is controllable by controlling the resistance of at least one of the gate resistors. Optionally, each gate resistor is implemented as a MOS transistor. The gate resistors stabilize the photon detector, and make it possible for the photon detector to remain in a forward blocking mode at the edge of transition to a conducting mode, so that absorption of only a single photon would trigger a transition to the conducting mode. The desired gate voltage for each gate may be controlled by a single resistor, or by more than one resistor, for example, two or three resistors per gate. A larger number of resistors at each gate allows the control of each gate voltage and leakage current to be more flexible. The MOS transistors may be more easily implemented in a CMOS topology compared to polysilicon or diffused resistors with equivalent resistance. In alternative embodiments, the resistors may be replaced with a current bias. The resistors may be installed when the photon detector is assembled, and additionally, in certain embodiments, may be removed and replaced following assembly.

In another implementation according to the first aspect, a sensitivity of the detector is adjustable by controlling the resistance of the quenching resistor. As the resistance of the quenching resistor is increased, the sensitivity of the detector is increased. The quenching resistor thus provides another, parallel, control for the sensitivity of the detector. The resistance of the quenching resistor is typically set when the device is assembled.

In another implementation according to the first aspect, an active quenching circuit electrically connects between the anode and the drain voltage. The active quenching circuit is additionally configured to maintain the voltage across semiconductor device at drain voltage when the semiconductor device is in the forward blocking mode, and to restore the voltage across the semiconductor device to the drain voltage following the discharge. The active quenching circuit works in parallel with the quenching resistor to restore the semiconductor device to a forward blocking state following absorption of one or more photons.

In another implementation according to the first aspect, the semiconductor device is formed within a complementary metal oxide semiconductor (CMOS) topology. CMOS topologies are a standard fabrication process for semiconductor devices, and exhibit advantages such as high noise immunity and low static power consumption.

In another implementation according to the first aspect, the photon detector further comprises an analog output for measuring the voltage across the semiconductor device, and a digital logic gate comprising an inverter configured to transform the analog output into a digital output. Transforming the analog output to a digital output enables various forms of further analysis, such as combining the digital output with digital outputs of other devices, and correlating the digital outputs with a clock.

Optionally, the photon detector further comprises processing circuitry for temporally correlating output pulses of the digital output with a time value. Optionally, processing circuitry is configured to conduct time-of-flight analysis for each temporally correlated output pulse, and to thereby convert the temporally correlated digital output pulses into a 3D depth map. Advantageously, the temporally correlated output pulses may be used in LIDAR applications in order to determine location or depth contours of target objects.

In another implementation according to the first aspect, the photon detector further comprises a photon counter for measuring 2D light intensity of photons absorbed by the photon detector and processing circuitry for converting output of the photon counter into a 2D intensity image. The 2D intensity image may be used to determine the amount of ambient or environmental light present at the location of the photon detector.

According to a second aspect, a method is disclosed. The method comprises detecting at least one photon with a photon detector. The photon detector comprises a multilayered semiconductor device comprising a plurality of P-type and N-type layers, a cathode, and an anode. A quenching resistor electrically connects between the anode and a drain voltage. At least two gates connect between adjacent layers of the plurality of P-type and N-type layers. Absorption of at least one photon causes the gates to switch between an open state, in which the semiconductor device is in a forward blocking mode, and in which a voltage across the semiconductor device is the drain voltage, and a closed state, in which the semiconductor device is in a forward conducting mode, and in which the voltage across the semiconductor device is discharged. Following the discharge, the quenching resistor is configured to restore the voltage across the semiconductor device to the drain voltage. A sensitivity of the detector is adjustable, to permit switching between the forward-blocking mode and the forward-conducting mode through absorption of an adjustable number of photons. The detecting step comprises absorbing at least one photon, thereby switching the gates to the closed state, and thereby discharging the voltage across the semiconductor device.

Advantageously, the absorption of at least one photon may be performed while the photon detector is operated with a comparatively low drain voltage, such as 5V or lower. The photon detector may be constructed using a standard CMOS topology. Due to the low voltage used, the diameter of the photon detector may be as small as 2 pm. In addition, the adjustable sensitivity of the photon detector allows it to be used for detecting different quantities of photons.

In another implementation according to the second aspect, the plurality of P-type and N- type layers comprise alternating P-type and N-type layers, and the adjacent sets of alternating P- type and N-type layers respectively form a PNP bipolar transistor and a NPN bipolar transistor. The alternating layers thus function in the same manner as a thyristor, to block flow of current until one or more photons are absorbed, and to permit continuous flow of current after a photon is absorbed.

Optionally, the adjacent sets of alternating P-type and N-type layers are arranged in a stack of layers defining outer layers and inner layers, the anode is an outer P-type layer, and the cathode is an outer N-type layer. Current thus flows across the entire photon detector, from cathode to anode, following triggering of the device with the at least one photon.

In another implementation according to the second aspect, each of the gates is connected to a gate voltage, and the method further comprises adjusting the sensitivity of the detector by adjusting at least one of the gate voltages. For example, lowering the gate voltages may cause the device to trigger only with absorbance of a larger number of photons, and vice versa. The gate voltages may be adjusted even after the photon detector is assembled.

In another implementation according to the second aspect, each of the gates is connected to at least one gate resistor, and the method further comprises adjusting the sensitivity of the detector by controlling the resistance of at least one of the gate resistors. Optionally, each gate resistor is implemented as a MOS transistor. The gate resistors stabilize the photon detector, and make it possible for the photon detector to remain in a forward blocking mode at the edge of transition to a conducting mode, so that absorption of only a single photon would trigger a transition to the conducting mode. The desired gate voltage for each gate may be controlled by a single resistor, or by more than one resistor, for example, two or three resistors per gate. A larger number of resistors at each gate allows the control of each gate voltage to be more flexible. The MOS transistors may be more easily implemented in a CMOS topology compared to polysilicon or diffused resistors with equivalent resistance. In alternative embodiments, the resistors may be replaced with a current bias. The resistors may be installed when the photon detector is assembled, and additionally, in certain embodiments, may be removed and replaced following assembly.

In another implementation according to the second aspect, a sensitivity of the detector is adjustable by controlling the resistance of the quenching resistor, wherein as the resistance of the quenching resistor is increased, the sensitivity of the detector is increased, and the method further comprises adjusting the sensitivity of the detector by adjusting the resistance of the quenching resistor. The quenching resistor thus provides another, parallel, control for the sensitivity of the detector. The resistance of the quenching resistor is typically set when the device is assembled.

In another implementation according to the second aspect, the detector further comprises an active quenching circuit electrically connecting between the anode and the drain voltage, and additionally configured to maintain the voltage across the semiconductor device at drain voltage when the semiconductor device is in the forward blocking mode, and to restore the voltage across the semiconductor device to the drain voltage following the discharge. The active quenching circuit works in parallel with the quenching resistor to restore the voltage, allowing for a quicker recovery time following absorption of a photon. In another implementation according to the second aspect, the method further comprises forming the semiconductor device within a complementary metal oxide semiconductor (CMOS) topology. CMOS topologies are a standard fabrication process for semiconductor devices, and exhibit advantages such as high noise immunity and low static power consumption.

In another implementation according to the second aspect, the method further comprises measuring an analog output of the voltage across the semiconductor device, and transforming the analog output into a digital output with a digital logic gate comprising an inverter. Advantageously, transforming the analog output to a digital output enables various forms of further analysis, such as combining the digital output with digital outputs of other devices, and correlating the digital outputs with a clock.

Optionally, the method further comprises temporally correlating output pulses of the digital output pulse with a time value. Optionally, the method further comprises conducting time-of-flight analysis for each temporally correlated output pulse, and thereby converting the temporally correlated digital output pulse into a 3D depth map. Advantageously, the temporally correlated output pulses may be used in LIDAR applications in order to determine location or depth contours of target objects.

In another implementation according to the second aspect, the photon detector further comprises a photon counter for measuring 2D light intensity received by the photon detector, and the method further comprises converting output of the photon counter into a 2D intensity image. The 2D intensity image may be used to determine the amount of ambient or environmental light present at the location of the photon detector.

Other systems, methods, features, and advantages of the present disclosure will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure, and be protected by the accompanying claims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Some embodiments of the invention are herein described, by way of example only, with reference to the accompanying drawings. With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of embodiments of the invention. In this regard, the description taken with the drawings makes apparent to those skilled in the art how embodiments of the invention may be practiced. In the drawings:

FIG 1 depicts a block diagram of a prior art thyristor;

FIG. 2A depicts a block diagram of a semiconductor device with alternating P and N layers, an anode, a cathode, and two gates, according to embodiments of the invention;

FIG. 2B depicts an electrical symbol for the semiconductor device of FIG. 4A, according to embodiments of the invention;

FIG. 2C depicts layers of a PNP bipolar transistor and an NPN bipolar transistor that are components of the semiconductor device of FIG.2A, according to embodiments of the invention;

FIG. 2D depicts the layers as shown in FIG. 2C combined into a single device having alternating P and N layers, according to embodiments of the invention;

FIG. 3A depicts a photon detector including the semiconductor device of FIG. 2A, a quenching resistor, and an output capacitor, according to embodiments of the invention;

FIG. 3B depicts an analog voltage output of the photon detector of FIG. 3A, according to embodiments of the invention;

FIG. 3C depicts the photon detector of FIG. 3A with an inverter for converting analog voltage output into a digital output, according to embodiments of the invention;

FIG. 3D depicts a digital voltage output of the photon detector of FIG. 3C, according to embodiments of the invention;

FIG. 4A depicts the photon detector of FIG. 3A including gate resistors electrically connected to each of the gates, according to embodiments of the invention;

FIG. 4B is an alternative illustration of the photon detector of FIG. 4A using the electrical symbol of FIG. 2B, according to embodiments of the invention;

FIG. 5A depicts a cross-section view of the photon detector of FIG. 3A implemented in a CMOS topology, according to embodiments of the invention; and

FIG. 5B depicts a top view of the photon detector of FIG. 5A, according to embodiments of the invention.

DETAILED DESCRIPTION

Before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not necessarily limited in its application to the details of construction and the arrangement of the components and/or methods set forth in the following description and/or illustrated in the drawings and/or the Examples. The invention is capable of other embodiments or of being practiced or carried out in various ways.

Elements of the present disclosure include processing circuitry. The processing circuitry may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention. The computer readable storage medium may be a tangible device that may retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.

Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network.

The computer readable program instructions may execute entirely on the processing circuitry, partly on the processing circuitry, as a stand-alone software package, partly on the processing circuitry and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the processing circuitry through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.

Referring to FIGS. 2A-2D, multilayered semiconductor device 20 includes anode 22, cathode 24, and a plurality of P-type and N-type layers configured therebetween. The P-type and N-type layers are arranged in alternating layers. P-type layer 801 is at the anode 22, followed by n-type layer N802, and p-type layer P803, and N-type layer N804 is at the cathode 24. The four layers form two bipolar junction transistors Q1 and Q2, as shown schematically in FIG. 2C. Transistor Q1 is a PNP transistor having layer P801 as an emitter, layer N802 as a base, and layer P803 as a collector. Transistor Q2 is an NPN transistor having layer N802 as an emitter, layer P803 as a base, and layer N804 as a collector. The electrical symbol indicated in FIG. 2B and marked with reference numeral TD100 will be used in electrical block diagrams throughout the remaining Figures in place of the four layers P801, N802, P803, N804.

Two gates G1 and G2 are electrically connected to multilayered semiconductor device 20. Gate G1 is connected to layer P803, and Gate G2 is connected to layer N802. Each of gates G1 and G2 includes a window and/or optical fiber connection to permit photons to be transmitted onto either layer P803, in the case of Gl, or layer N802, in the case of G2. Gates G1 and G2 may also be connected to other electronic circuitry and/or semiconductor devices, as will be discussed further herein.

Referring now to FIG. 3A, photon detector 30 includes semiconductor device 20 having layers TD100 and gates Gl and G2, quenching resistor R102 connected to drain voltage VDD, and output capacitor Cl 02. Photon detector 30 may also be referred to herein as a“Single Photon Thyristor Device,” or SPTD, and an output voltage of photon detector 30 may be referred to in the Figures as a“SPTD Output Voltage.”

Quenching resistor serves to pull the voltage of photon detector 30 up to VDD. Typical values for VDD may be approximately 5V, approximately 3.3 V, or even approximately IV, or any other voltage suitable for performing the functions described herein. Advantageously, this voltage is significantly lower than a voltage for a SPAD, which is typically around 25V. Correspondingly the size of photon detector 30 may be significantly smaller than that of a SPAD. For example, a diameter of the semiconductor device 20 may be as small as 2 pm, and the entire semiconductor device may have dimensions of 2 pm x 2 pm. In addition, the photon detector 30 is more readily integrated with other electronic devices running on a standard voltage of 5V.

Output capacitor C 102 is used to isolate the voltage between semiconductor device 20 and an analog output voltage readout. This isolated voltage output may be measured and analyzed, as will be discussed further below.

In operation, photon detector 30 begins a cycle in forward blocking mode, due to the reverse bias at the junction between layers N802 and P803. The voltage at the anode may be tuned by adjusting the resistance of R102. For example, lowering the resistance at R102 causes the voltage to increase, and vice versa.

The voltage at the anode may be set precisely so that absorption of a photon at either gate Gl or G2 produces an electron-hole pair at the N802-P803 junction, which is sufficient to overcome the reverse bias at that junction and cause the photon detector to latch into a forward conducting state. Absorption of the photon in either the N802 or the P803 layer causes this effect. The absorption of a photon has a similar effect compared to application of a gate voltage at gate G1 or G2, in that it allows the voltage applied at the anode to cause the semiconductor device 20 to latch into the forward conducting mode. Stated differently, absorption of the photon causes at least one of gates G1 and G2 to switch between an open state, in which the semiconductor device is in a forward blocking mode and in which a voltage across the semiconductor device is a drain mode, and a closed state, in which the semiconductor device is in a forward conducting mode, and in which the voltage across the semiconductor device is discharged.

Photon detector 30 is tunable precisely to respond to absorption of only a single photon. Photon detector 30 may also be adjusted to respond to absorption of a larger number of photons.

Following latching of the device into a forward conducting mode, current is discharged from the anode to the cathode, and the voltage across capacitor C102 decreases. The voltage is then gradually restored to its initial level as the voltage is recharged through quenching resistor R102.

In addition to quenching resistor R102, an active quenching circuit (AQC) 40 may electrically connect between the anode and the drain voltage. Active quenching circuit 40 is an active circuit or transistor that may be controlled by detection of circuit output change. The active quenching circuit 40 is additionally configured to maintain the voltage across the semiconductor device 20 at drain voltage when the semiconductor device 20 is in the forward blocking mode, and to restore the voltage across the semiconductor device to the drain voltage following the discharge. The active quenching circuit 40 works in parallel with the quenching resistor R 102 to restore the voltage, allowing for a quicker recovery time following absorption of a photon. Optionally, active quenching circuit 40 takes the place of quenching resistor R102.

FIG. 3B illustrates an analog voltage output of photon detector 30 as measured over time across capacitor Cl 02. The voltage is initially at VDD. Light arrives to the photon detector at time Tl, at which point the voltage output dramatically drops. The voltage output then gradually increases as the quenching resistor R102 charges the photon detector 30 back to VDD.

In the embodiment of FIG. 3C, photon detector 30 is coupled to a digital readout domain 35. The digital readout domain 35 includes a digital logic gate. In the illustrated embodiment, the digital logic gate includes an inverter INV101. INV101 is connected to VCC power supply. INV101 has high gain and yields a digital output voltage on VCC power supply. VCC may be the same voltage as VDD or may be a lower voltage. For example, VDD may be 3.3V or 5 V, and VCC may be IV. In alternative embodiments, the digital logic gate may include other digital logic functions, such as NAND or NOR. The digital logic gate is configured to output either a low or high state depending on whether the voltage across the capacitor C102 is above or below a threshold value. Optionally, the digital readout domain 35 further includes a separate resistor R105 connected to VCC. The resistor R105 and capacitor C 102 function as a filter. The filter keeps the input level of the voltage at the digital readout domain high, to ensure that the measured voltage does not drop below the threshold value due to random fluctuations.

FIG. 3D depicts a digital output of photon detector 30 when coupled to a digital readout domain 35. Due to the inverter INV101, in combination with the filter, when present, the output rises when the voltage decreases, and vice versa. The digital signal starts in a“low” state, when the voltage across output capacitor C102 is high. At T2, shortly after a photon is absorbed, the digital output rises from a“low” value to a“high” value. T2 may be the same as Tl, or a very short time after Tl. The readout is maintained at“high” during the charging of photon detector 30 back to VDD, until the voltage increases to past the threshold of the digital logic gate, at which point the digital readout reverts back to“low.” As a result, a square wave is formed, with the digital readout changing from“low” to“high” immediately after each firing event, and reverting back to “low” after the photon detector 30 is charged.

The digital output of the photon detector 30 may be further processed and analyzed. For example, the digital output may be combined with digital outputs of other devices. The photon detector 30 may also include processing circuitry 42 for temporally correlating output pulses of the digital output with a time value. The processing circuitry 42 may be configured to conduct time-of-flight analysis for each temporally correlated output pulse, and to thereby convert the temporally correlated digital output pulses into a 3D depth map. Advantageously, the temporally correlated output pulses may be used in LIDAR applications in order to determine location or depth contours of target objects. The photon detector 30 may further comprise a photon counter 44 for measuring 2D light intensity of photons absorbed by the photon detector and processing circuitry for converting output of the photon counter into a 2D intensity image. The 2D intensity image may be used to determine the amount of ambient or environmental light present at the location of the photon detector 30.

Further applications of 2D and 3D digital outputs for photon detectors, which may be implemented with digital outputs of photon detector 30, are described in the above-mentioned co filed International Patent Application co-filed on herewith date, attorney docket number 83033.

FIGS. 4A and 4B depict further implementations of photon detector 30, and in particular include additional elements for controlling the sensitivity of gates G1 and G2. In FIGS. 4A and 4B, gate resistors R103 and R104 are connected in series with gates G1 and G2. Gate resistors R103 and R104 may be parasitic resistors, or may be polysilicon resistors that are added externally to the semiconductor device 20. Gate voltages VG1 and VG2 may be applied to the gates G1 and G2.

Gate resistors R103 and R104 and gate voltages VG1 and VG2 are adjustable to control the sensitivity of photon detector 30. Specifically, increasing the voltage applied to gates G1 or G2 reduces the energy required to latch the photon detector 30 from the forward blocking state to forward conducting state. Conversely, lowering the voltages at gates G1 or G2 may cause the device to trigger only with absorbance of a larger number of photons. The voltages at gates G1 and G2 may be controlled by adjusting the resistance of the resistors, or by modulating the applied voltage, or both. Advantageously, the gate voltages and resistances may be adjusted even after the photon detector is constructed.

The gate resistors R103, R104 stabilize the photon detector 30, and make it possible for the photon detector 30 to remain in a forward blocking mode at the edge of transition to a conducting mode, so that absorption of only a single photon would trigger a transition to the conducting mode.

Although it is theoretically possible to control the sensitivities of gates G1 and G2 with just the quenching resistor R102, or with the quenching resistor R102 and only one additional gate resistor, use of at least two gate resistors R103 and R104 provides distinct advantages. As discussed, the photon detector 30 is configured such that absorption of even a single photon causes conversion of the photon detector 30 to forward conducting mode. Thus, prior to absorption of the photon, gates G1 and G2 are on the edge of breakdown. Any current supplied to the gates G1 and G2 must be carefully calibrated to adjust the gain, and thereby maintain the desired voltage.

The use of multiple resistors provides a mechanism for carefully adjusting the gain. The network of resistors enables adjusting the voltages and current such that the breaking point of the photon detector 30 will be set to the desired level, so that absorption of a desired number of photons will cause the semiconductor device 20 to latch into the forward conducting position. Every resistor, by its nature, allows a leakage current, with the size of the leakage current being controllable by the degree of resistance. Thus, the use of three or more resistors divides the overall current supplied to the photon detector from one large current into many small currents. Each of these smaller currents may be separately controlled to calibrate the photon detector 30. Additional resistors, while making the photon detector 30 larger and more complex, would provide even finer control of the calibration of photon detector 30.

In some embodiments, the resistance of resistors R103 and R104 may be substantially identical. In other embodiments, resistors R103 and R104 have different resistances. In the illustrated embodiment, the voltage at each gate Gl, G2 is controlled by only one resistor R103, R104. In an alternative embodiment, a network of resistors could generate the needed gate voltage. For example, for each gate, two or three resistors may be connected from drain voltage to ground, and have serial resistance to the gate. In such topologies, more flexible control of the voltage and current through the gates is feasible.

Resistors R103, R104, as well as quenching resistor R102 and digital readout domain resistor R105, may be implemented as metal oxide semiconductor (MOS) transistors. In many CMOS technologies, it is difficult to fabricate resistors with tightly-controlled values or a reasonable physical size. Consequently, it is desirable to replace such resistance with a MOS transistor. A metal oxide semiconductor field effect transistor (MOSFET) may be implemented as a small-signal resistor if its gate and drain are shorted. The active resistor may be used in place of a polysilicon or diffused resistor to produce a DC voltage drop and /or provide small signal resistance that is linear over a small range. In addition, there are many cases in which the area required to obtain a small signal resistance is more important than the linearity. A small MOS or BJT device may simulate a resistor in much less die-area than is required with an equivalent polysilicon or diffused resistor.

Optionally, the resistors R103, R104 may be replaced with a voltage bias. The voltage bias may achieve the same function as the resistors, namely to reduce the gain delivered to the gates Gl and G2 from the respective gate voltages.

Resistors R103, R104 may be installed when the photon detector is assembled. Optionally, resistors R103, R104 may be removed and replaced following assembly.

Optionally, an additional mechanism for adjusting the sensitivity of the photon detector 30 is by controlling the bulk bias, also known as the body bias, of the semiconductor device 20.

Optionally, one or more of gates Gl or G2 includes an active voltage control (not shown). The active voltage control may accelerate quenching following discharge of voltage in the photon detector 30.

FIGS. 5 A and 5B depict an exemplary CMOS implementation of photon detector 30. In view of the low voltage on which photon detector 30 operates, the semiconductor device of photon detector 30 may be as small as 2 pm x 2 pm.

FIG. 5A depicts a cross-section view of the semiconductor device 20, and FIG. 5B depicts a top view of the same semiconductor device. The four layers P801, N802, P803, and N804 are arranged concentrically. P801 is arranged as a shallow implant in the center, and is a highly doped p++ region. Electrical contact P811 connects to layer P801, and may provide a connection to a PMOS source, to the drain voltage, and to the quenching resistor. Electrical contact P811 and the other electrical contacts shown in FIGS. 5 A and 5B may be metallic. N+ layer N802 is implemented deeper than P++ shallow implant P801. It is connected to electrical contact N812, which may provide a connection, for example, to gate G2 and resistor R103. P-type layer P803 is implemented using a P-well layer, and is connected to electrical contact P813, which may connect, for example, to gate G1 and resistor R104. Layer P803 is a deeper implant compared to P-type layer P801, and has a lower dose of doping. N layer N804 is a deep N-well, and is connected to electrical contact N814. Substrate P805 substrate is a p-type substrate. A highly doped p++ section P806 is placed at an edge of the substrate P805 that contacts electrical contact P815, in order to improve the electrical connection. Substrate P805 is used for electrical isolation and other parasitic effect control.

Light absorption area 820 is marked. Light absorption area 820 defines a device fill factor, which is a ratio between the active detection area and the semiconductor device 20 surface area. Optionally, backside illumination may be used in order to increase the fill factor of the semiconductor device 20.

Deep trench isolation 1840 is optionally included for mechanical and optical isolation from neighboring semiconductor devices 20. Electrical and optical coupling between neighboring devices results in degradation of performance due to false firing events; deep trench isolation 1840 prevents such coupling. While the trench isolation 1840 is useful for improving performance, a photon detector based on the architecture as shown in FIGS. 5 A and 5B will work also without it.

The foregoing example serves only to demonstrate that photon detector 30 is readily implementable using a standard CMOS implementation process. Other CMOS implementations are possible, and accordingly the example is not to be taken in a limiting sense.

It is expected that during the life of a patent maturing from this application many photon counters and many digital logic gates will be developed that are suitable for the functions described herein, and the scope of the terms photon counter and digital logic gate is intended to include all such new technologies a priori.

As used herein the term“about” refers to ± 10 %.

The terms "comprises", "comprising", "includes", "including", “having” and their conjugates mean "including but not limited to". This term encompasses the terms "consisting of" and "consisting essentially of".

The phrase "consisting essentially of" means that the composition or method may include additional ingredients and/or steps, but only if the additional ingredients and/or steps do not materially alter the basic and novel characteristics of the claimed composition or method. As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. For example, the term "a compound" or "at least one compound" may include a plurality of compounds, including mixtures thereof.

The word“exemplary” is used herein to mean“serving as an example, instance or illustration”. Any embodiment described as“exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and/or to exclude the incorporation of features from other embodiments.

The word“optionally” is used herein to mean“is provided in some embodiments and not provided in other embodiments”. Any particular embodiment of the invention may include a plurality of“optional” features unless such features conflict.

Throughout this application, various embodiments of this invention may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range.

Whenever a numerical range is indicated herein, it is meant to include any cited numeral (fractional or integral) within the indicated range. The phrases“ranging/ranges between” a first indicate number and a second indicate number and“ranging/ranges from” a first indicate number “to” a second indicate number are used herein interchangeably and are meant to include the first and second indicated numbers and all the fractional and integral numerals therebetween.

It is appreciated that certain features of the invention, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination or as suitable in any other described embodiment of the invention. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments, unless the embodiment is inoperative without those elements.

All publications, patents and patent applications mentioned in this specification are herein incorporated in their entirety by reference into the specification, to the same extent as if each individual publication, patent or patent application was specifically and individually indicated to be incorporated herein by reference. In addition, citation or identification of any reference in this application shall not be construed as an admission that such reference is available as prior art to the present invention. To the extent that section headings are used, they should not be construed as necessarily limiting.

In addition, any priority document(s) of this application is/are hereby incorporated herein by reference in its/their entirety.

Claims

WHAT IS CLAIMED IS:

1. A photon detector, comprising:

a multilayered semiconductor device comprising a plurality of P-type and N-type layers, a cathode, and an anode;

a quenching resistor electrically connecting between the anode and a drain voltage; and at least two gates connecting between adjacent layers of the plurality of P-type and N-type layers, wherein absorption of at least one photon causes the gates to switch between an open state, in which the semiconductor device is in a forward blocking mode, and in which a voltage across the semiconductor device is the drain voltage; and a closed state, in which the semiconductor device is in a forward conducting mode, and in which the voltage across the semiconductor device is discharged; wherein, following said discharge, the quenching resistor is configured to restore the voltage across the semiconductor device to the drain voltage;

wherein a sensitivity of the detector is adjustable, to permit switching between the forward blocking mode and the forward conducting mode through absorption of an adjustable number of photons.

2. The photon detector of claim 1, wherein the plurality of P-type and N-type layers comprise alternating P-type and N-type layers, wherein adjacent sets of alternating P-type and N- type layers respectively form a PNP bipolar transistor and a NPN bipolar transistor.

3. The photon detector of claim 2, wherein the alternating P-type and N-type layers are arranged in a stack of layers defining outer layers and inner layers, and wherein the anode is an outer P-type layer, and the cathode is an outer N-type layer.

4. The photon detector of claim 1, wherein each of the gates is connected to a gate voltage, and a sensitivity of the detector is controllable by adjusting at least one of the gate voltages.

5. The photon detector of claim 1, wherein each of the gates is connected to at least one gate resistor, and a sensitivity of the detector is adjustable by controlling the resistance of at least one of the gate resistors.

6. The photon detector of claim 5, wherein each of the at least one gate resistors is implemented as a MOS transistor.

7. The photon detector of claim 1, wherein a sensitivity of the detector is adjustable by controlling the resistance of the quenching resistor, wherein as the resistance of the quenching resistor is increased, the sensitivity of the detector is increased.

8. The photon detector of claim 1, further comprising an active quenching circuit electrically connecting between the anode and the drain voltage, and additionally configured to maintain the voltage across the semiconductor device at drain voltage when the semiconductor device is in the forward blocking mode, and to restore the voltage across the semiconductor device to the drain voltage following the discharge.

9. The photon detector of claim 1, wherein the semiconductor device is formed within a complementary metal oxide semiconductor (CMOS) topology.

10. The photon detector of claim 1, further comprising an analog output for measuring the voltage across the semiconductor device, and a digital logic gate comprising an inverter configured to transform the analog output into a digital output.

11. The photon detector of claim 10, further comprising processing circuitry for temporally correlating output pulses of the digital output with a time value.

12. The photon detector of claim 11, further comprising processing circuitry configured to conduct time-of-flight analysis for each temporally correlated output pulse, and to thereby convert the temporally correlated digital output pulses into a 3D depth map.

13. The photon detector of claim 1, further comprising a photon counter for measuring 2D light intensity of photons absorbed by the photon detector and processing circuitry for converting output of the photon counter into a 2D intensity image.

14. A method comprising detecting at least one photon with a photon detector, wherein the photon detector comprises:

wherein a sensitivity of the detector is adjustable, to permit switching between the forward blocking mode and the forward conducting mode through absorption of an adjustable number of photons;

and the detecting step comprises absorbing at least one photon, thereby switching the gates to the closed state, and thereby discharging the voltage across the semiconductor device.

15. The method of claim 14, wherein the plurality of P-type and N-type layers comprise alternating P-type and N-type layers, wherein adjacent sets of alternating P-type and N-type layers respectively form a PNP bipolar transistor and a NPN bipolar transistor.

16. The method of claim 15, wherein the alternating P-type and N-type layers are arranged in a stack of layers defining outer layers and inner layers, and wherein the anode is an outer P-type layer, and the cathode is an outer N-type layer.

17. The method of claim 14, wherein each of the gates is connected to a gate voltage, and the method further comprises adjusting the sensitivity of the detector by adjusting at least one of the gate voltages.

18. The method of claim 14, wherein each of the gates is connected to at least one gate resistor, and the method further comprises adjusting the sensitivity of the detector by controlling the resistance of at least one of the gate resistors.

19. The method of claim 18, wherein each of the at least one gate resistors is implemented as a MOS transistor.

20. The method of claim 14, wherein a sensitivity of the detector is adjustable by controlling the resistance of the quenching resistor, wherein as the resistance of the quenching resistor is increased, the sensitivity of the detector is increased, and the method further comprises adjusting the sensitivity of the detector by adjusting the resistance of the quenching resistor.

21. The method of claim 14, wherein the detector further comprises an active quenching circuit electrically connecting between the anode and the drain voltage, and additionally configured to maintain the voltage across the semiconductor device at drain voltage when the semiconductor device is in the forward blocking mode, and to restore the voltage across the semiconductor device to the drain voltage following the discharge.

22. The method of claim 14, further comprising forming the semiconductor device within a complementary metal oxide semiconductor (CMOS) topology.

23. The method of claim 14, further comprising measuring an analog output of the voltage across the semiconductor device, and transforming the analog output into a digital output with a digital logic gate comprising an inverter.

24. The method of claim 23, further comprising temporally correlating output pulses of the digital output with a time value.

25. The method of claim 24, further comprising conducting time-of-flight analysis for each temporally correlated output pulse, and thereby converting the temporally correlated digital output pulse into a 3D depth map.

26. The method of claim 14, wherein the photon detector further comprises a photon counter for measuring 2D light intensity received by the photon detector, and the method further comprises converting output of the photon counter into a 2D intensity image.