WO2020228017A1

WO2020228017A1 - Signal generation method, signal generation circuit, and display apparatus

Info

Publication number: WO2020228017A1
Application number: PCT/CN2019/087227
Authority: WO
Inventors: 黄耀; 周洋; 张跳梅; 李孟
Original assignee: 京东方科技集团股份有限公司; 成都京东方光电科技有限公司
Priority date: 2019-05-16
Filing date: 2019-05-16
Publication date: 2020-11-19
Also published as: CN110313028A; CN110313028B

Abstract

A signal generation method, a signal generation circuit, and a display apparatus. The signal generation method is used for a shift register, wherein the shift register comprises N cascaded shift register units. The signal generation method comprises: enabling N cascaded shift register units to respectively output N pre-output signals; respectively performing phase inversion on the N pre-output signals to obtain N pre-output phase-inverted signals; and combining an n-th pre-output phase-inverted signal of the N pre-output phase-inverted signals with an (n+1)th pre-output signal of the N pre-output signals to generate an n-th output signal, thereby obtaining N-1 output signals, wherein n is an integer meeting 1 ≤ n ≤ N-1, and N is an integer greater than or equal to two. An output signal generated by the signal generation method can be used for driving a pixel circuit.

Description

Signal generation method, signal generation circuit and display device

Technical field

The embodiments of the present disclosure relate to a signal generation method, a signal generation circuit, and a display device.

Background technique

In the field of display technology, in order to improve the quality of the display picture and the user experience, the realization of high PPI (Pixels Per Inch, the number of pixels per inch) and narrow borders has gradually become the research direction. In recent years, with the continuous improvement of the manufacturing process of amorphous silicon thin film transistors or oxide thin film transistors, the driving circuit can be directly integrated on the thin film transistor array substrate to form a GOA (Gate Driver On Array) to drive the display panel. GOA technology helps to realize the narrow frame design of the display panel, and can reduce the production cost of the display panel.

Summary of the invention

At least one embodiment of the present disclosure provides a signal generation method for a shift register. The shift register includes N cascaded shift register units. The signal generation method includes: shifting N cascades The register unit respectively outputs N pre-output signals; respectively inverts the N pre-output signals to obtain N pre-output inverted signals; and outputs the nth pre-output of the N pre-output inverted signals The inverted signal is combined with the n+1th pre-output signal among the N pre-output signals to generate the n-th output signal, thereby obtaining N-1 output signals; n is that 1≤n≤N-1 An integer of, N is an integer greater than or equal to 2.

For example, in the signal generation method provided by an embodiment of the present disclosure, the pre-output signals output by the shift register units of adjacent stages differ by one system clock cycle.

For example, in the signal generation method provided by an embodiment of the present disclosure, the difference between the nth pre-output inverted signal and the n+1th pre-output inverted signal in the N pre-output inverted signals is one system Clock cycle.

For example, in the signal generation method provided by an embodiment of the present disclosure, the 2k+1 stage shift register unit and the 2k-1 stage shift register unit in the shift register are connected to receive the N pre-outputs The 2k-1th pre-output signal in the signal, the 2k+2th stage shift register unit and the 2kth stage shift register unit in the shift register are connected to receive the 2kth stage of the N pre-output signals A pre-output signal; k is an integer satisfying 1≤k≤(N/2).

For example, the signal generation method provided by an embodiment of the present disclosure further includes: providing a first clock signal and a second clock signal to the odd-numbered shift register unit in the shift register; and providing the even number in the shift register The stage shift register unit provides a third clock signal and a fourth periodic signal.

For example, in the signal generation method provided by an embodiment of the present disclosure, the first clock signal and the third clock signal differ by one system clock period, and the second clock signal and the fourth clock signal The difference is one system clock cycle.

For example, in the signal generation method provided by an embodiment of the present disclosure, the duty cycle of at least one of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal is greater than 50%.

For example, in the signal generation method provided by an embodiment of the present disclosure, the duty ratios of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are all greater than 50% .

For example, in the signal generation method provided by an embodiment of the present disclosure, the n-th pre-output inverted signal among the N pre-output inverted signals and the n+1-th pre-output signal in the N pre-output signals The output signal is configured to control at least two transistors in the display area of the display panel to be turned on or off.

For example, in the signal generation method provided by an embodiment of the present disclosure, the at least two transistors include two different types of transistors.

At least one embodiment of the present disclosure further provides a signal generation circuit, including a shift register and an inverter circuit, the shift register includes N cascaded shift register units, and the N cascaded shift register units Are configured to respectively output N pre-output signals; the inverting circuit is configured to respectively invert the N pre-output signals to obtain N pre-output inverted signals; invert the N pre-outputs The n-th pre-output inverted signal in the signal and the n+1-th pre-output signal among the N pre-output signals are combined to generate the n-th output signal, thereby obtaining N-1 of the signal generating circuit Output signals; n is an integer satisfying 1≤n≤N-1, and N is an integer greater than or equal to 2.

For example, in the signal generation circuit provided by an embodiment of the present disclosure, the inverter circuit includes N inverter subcircuits, and the mth inverter subcircuit is connected to the mth stage shift register unit and is configured In order to invert the m-th pre-output signal among the N pre-output signals to obtain the m-th pre-output inverted signal among the N pre-output inverted signals, m is to satisfy 0≤m≤N The integer.

For example, in the signal generation circuit provided by an embodiment of the present disclosure, the 2k+1 stage shift register unit and the 2k-1 stage shift register unit in the shift register are connected to receive the N pre-outputs The 2k-1th pre-output signal in the signal, the 2k+2th stage shift register unit and the 2kth stage shift register unit in the shift register are connected to receive the 2kth stage of the N pre-output signals A pre-output signal; k is an integer satisfying 1≤k≤(N/2).

For example, in the signal generation circuit provided by an embodiment of the present disclosure, the pre-output signals output by the shift register units of adjacent stages differ by one system clock cycle.

For example, the signal generation circuit provided by an embodiment of the present disclosure further includes a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line. The first clock signal line and the shifter The odd-numbered shift register units in the register are connected to provide a first clock signal, and the second clock signal line is connected to the odd-numbered shift register units in the shift register to provide a second clock signal; The third clock signal line is connected to the even-numbered shift register unit in the shift register to provide a third clock signal, and the fourth clock signal line is connected to the even-numbered shift register unit in the shift register Connect to provide the fourth clock signal.

For example, in the signal generation circuit provided by an embodiment of the present disclosure, the first clock signal and the third clock signal are different by one system clock period, and the second clock signal is different from the fourth clock signal. The difference is one system clock cycle.

For example, in the signal generation circuit provided by an embodiment of the present disclosure, the duty cycle of at least one of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal More than 50%.

At least one embodiment of the present disclosure further provides a display device including any signal generation circuit provided in the embodiments of the present disclosure.

For example, the display device provided by an embodiment of the present disclosure further includes a display panel, the display panel includes a plurality of pixel circuits arranged in an array, the plurality of pixel circuits are connected to the signal generating circuit, and the pixel circuit in the nth row It is configured to receive the n-th output signal among the N-1 output signals of the signal generating circuit, where n is an integer satisfying 1≤n≤N-1, and N is an integer greater than or equal to 2.

For example, in the display device provided by an embodiment of the present disclosure, the pixel circuit includes a data writing sub-circuit, a driving sub-circuit, a compensation sub-circuit, a reset sub-circuit, a light-emitting control sub-circuit, and a light-emitting element, and the nth row The compensation sub-circuit and the data writing sub-circuit in the pixel circuit are configured to receive the nth output signal of the signal generating circuit.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present disclosure more clearly, the following will briefly introduce the drawings of the embodiments. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limit the present disclosure. .

Figure 1 is a circuit diagram of a pixel circuit;

FIG. 2 is a signal timing diagram corresponding to the operation of the pixel circuit shown in FIG. 1;

FIG. 3 is a schematic diagram of a signal generation method provided by at least one embodiment of the present disclosure;

4 is a circuit diagram of a shift register unit and an inverting sub-circuit provided by at least one embodiment of the present disclosure;

FIG. 5 is a signal timing diagram corresponding to the operation of the circuit shown in FIG. 4;

6 is a schematic diagram of a clock signal provided by at least one embodiment of the present disclosure;

FIG. 7 is a schematic diagram of charging time corresponding to FIG. 6;

FIG. 8 is a timing diagram of another signal corresponding to the operation of the circuit shown in FIG. 4;

FIG. 9 is a schematic diagram of another clock signal provided by at least one embodiment of the present disclosure;

FIG. 10 is a schematic diagram of charging time corresponding to FIG. 9;

FIG. 11 is a schematic diagram of a signal generating circuit provided by at least one embodiment of the present disclosure;

FIG. 12 is a schematic diagram of another signal generating circuit provided by at least one embodiment of the present disclosure;

FIG. 13 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure; and

FIG. 14 is a schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the protection scope of the present disclosure.

Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those with ordinary skills in the field to which this disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity, or importance, but are only used to distinguish different components. Similarly, similar words such as "a", "one" or "the" do not imply a quantity limit, but mean that there is at least one. "Include" or "include" and other similar words mean that the element or item appearing before the word encompasses the element or item listed after the word and its equivalents, but does not exclude other elements or items. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

With the continuous improvement of the resolution of the display device, the layout space for the pixel circuit in each pixel unit in the display device is getting smaller and smaller. For example, FIG. 1 shows a pixel circuit that includes 6 transistors and 1 storage capacitor, which can be referred to as a 6T1C pixel circuit for short. The 6T1C pixel circuit occupies a smaller layout space than the 7T1C pixel circuit (including 7 transistors and 1 storage capacitor), so it can meet the design requirements of the display device for higher resolution.

For example, as shown in Figure 1, the pixel circuit includes six transistors, which are a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a One transistor T1 is a driving transistor, and the other transistors are switching transistors. The pixel circuit also includes a storage capacitor CST. The pixel circuit is used to drive the light-emitting element to emit light. For example, as shown in FIG. 1, the light-emitting element may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED). The OLED or QLED can be of various types, such as top-emission, bottom-emission, etc., and can emit red light, green light, blue light, or white light, which is not limited in the embodiments of the present disclosure.

As shown in FIG. 1, the gate of the first transistor T1 is connected to the first node D1, the first electrode of the first transistor T1 is connected to the second node D2, and the second electrode of the first transistor T1 is connected to the third node D3. The gate of the second transistor T2 is configured to receive the first scan signal Gate1, the first pole of the second transistor T2 is configured to receive the data signal DATA, and the second pole of the second transistor T2 is connected to the second node D2. The gate of the third transistor T3 is configured to receive the second scan signal Gate2, the first electrode of the third transistor T3 is connected to the third node D3, and the second electrode of the third transistor T3 is connected to the first node D1. The gate of the fourth transistor T4 is configured to receive the second scan signal Gate2, the first pole of the fourth transistor T4 is configured to receive the reset voltage Vinit, and the second pole of the fourth transistor T4 is connected to the fourth node D4. The gate of the fifth transistor T5 is configured to receive the first light emission control signal EM1, the first electrode of the fifth transistor T5 is configured to receive the first power supply voltage VDD, and the second electrode of the fifth transistor T5 is connected to the second node D2 . The gate of the sixth transistor T6 is configured to receive the second light emission control signal EM2, the first electrode of the sixth transistor T6 is connected to the third node D3, and the second electrode of the sixth transistor T6 is connected to the fourth node D4. The anode of the light emitting element OLED is connected to the fourth node D4, and the cathode of the light emitting element OLED is configured to receive the second power supply voltage VSS.

It should be noted that in the pixel circuit shown in FIG. 1, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are P-type transistors, and the third transistor T3 and the fourth transistor T4 are For N-type transistors, the working principle of the pixel circuit shown in FIG. 1 will be described below in conjunction with the signal timing diagram shown in FIG. 2.

In the first phase P1, the third transistor T3 and the fourth transistor T4 are turned on under the control of the high-level second scan signal Gate2, and the sixth transistor T6 is controlled by the low-level second light-emitting control signal EM2 The bottom is turned on. The second transistor T2 is turned off under the control of the high-level first scan signal Gate1, and the fifth transistor T5 is turned off under the control of the high-level first light emission control signal EM1. In the first stage P1, the turned-on fourth transistor T4, sixth transistor T6, and third transistor T3 form a reset path, so that the storage capacitor CST can be discharged through the reset path, thereby discharging the first node D1, the third node The levels of the node D3 and the fourth node D4 are reset at the same time. The storage capacitor CST is reset, so that the charge stored in the storage capacitor CST is released, so that the data signal in the subsequent stage can be stored in the storage capacitor CST more quickly and reliably; at the same time, the fourth node D4 is also reset That is, the OLED is reset, so that the OLED can be displayed in a black state before emitting light, that is, not emitting light, which will improve the display effect such as the contrast of the display device using the above-mentioned pixel circuit.

In the second phase P2, the third transistor T3 and the fourth transistor T4 are turned on under the control of the high-level second scanning signal Gate2, and the second transistor T2 is under the control of the low-level first scanning signal Gate1. Is turned on. In addition, since the third transistor T3 is turned on and the first transistor T1 is in a diode connection mode, the first transistor T1 remains in the on state. The fifth transistor T5 is turned off under the control of the high-level first emission control signal EM1, and the sixth transistor T6 is turned off under the control of the high-level second emission control signal EM2.

In the second phase P2, the turned-on second transistor T2, the first transistor T1, and the third transistor T3 form a data writing path, so that the data signal DATA received by the second transistor T2 can be used to charge the storage capacitor CST. As a result, the level of the first node D1 gradually increases. It is easy to understand that the level of the second node D2 is the voltage Vdata corresponding to the data signal DATA, and according to the characteristics of the first transistor T1, when the level of the first node D1 increases to Vdata+Vth, the first transistor T1 is turned off , The above charging process ends. It should be noted that Vth represents the threshold voltage of the first transistor. Since the first transistor T1 is a P-type transistor as an example, the threshold voltage Vth here may be a negative value. After the second stage P2, the levels of the first node D1 and the third node D3 are both Vdata+Vth, that is to say, the voltage information with the data signal DATA and the threshold voltage Vth is stored in the storage capacitor CST for use When the subsequent OLED emits light, it provides gray scale display data and compensates the threshold voltage of the first transistor T1 itself.

In the third phase P3, the second transistor T2 is turned on under the control of the low-level first scan signal Gate1, and the remaining transistors are all turned off. The third stage P3 is a blank stage and no operation is performed.

In the fourth phase P4, the fifth transistor T5 is turned on under the control of the low-level first light-emitting control signal EM1, the second transistor T2 is turned off under the control of the high-level first scan signal Gate1, and the first The three transistors T3 and the fourth transistor T4 are turned off under the control of the second scan signal Gate2 of low level, and the sixth transistor T6 is turned off under the control of the second light emission control signal EM2 of high level. In the fourth phase P4, the turned-on fifth transistor T5 can provide the received first power supply voltage VDD to the second node D2, so that the level of the second node D2 becomes the first power supply voltage VDD. Due to the effect of the storage capacitor CST, the level of the gate (ie, the first node D1) of the first transistor T1 can continue to be Vdata+Vth, and the level of the first electrode (for example, the source) of the first transistor T1 Is the first power supply voltage VDD, so the absolute value of the difference between the level of the gate of the first transistor T1 and the level of the first pole is |Vgs|=|VDD-(Vdata+Vth)|>|Vth|, so that The first transistor T1 is turned on.

In the fifth stage P5, the fifth transistor T5 is turned on under the control of the low-level first emission control signal EM1, and the sixth transistor T6 is turned on under the control of the low-level second emission control signal EM2 , The first transistor T1 continues to maintain the on state. The second transistor T2 is turned off under the control of the high-level first scan signal Gate1, and the third transistor T3 and the fourth transistor T4 are turned off under the control of the low-level second scan signal Gate2.

In the fifth stage P5, the turned-on fifth transistor T5, the first transistor T1, and the sixth transistor T6 form a driving light emitting path. The anode and cathode of the light-emitting element OLED are respectively connected to the first power supply voltage VDD (for example, a high-level voltage) and the second power supply voltage VSS (for example, a low-level voltage), so that the light-emitting element OLED flows through the first transistor. Light is emitted by the driving current of T1. The level of the first node D1 may continue to be maintained at Vdata+Vth, and the levels of the second node D2 and the third node D3 are the first power supply voltage VDD.

Specifically, the value of the driving current I _OLED flowing through the light-emitting element OLED can be obtained according to the following formula:

I _OLED ＝K(Vgs-Vth) ²

＝K[(Vdata+Vth-VDD)-Vth] ²

＝K(Vdata-VDD) ²

In the above formula, Vth represents the threshold voltage of the first transistor T1, Vgs represents the voltage between the gate of the first transistor T1 and the first electrode such as the source, and K is a constant value. It can be seen from the above formula that the driving current I _OLED flowing through the light-emitting element OLED is no longer related to the threshold voltage Vth of the first transistor T1, but only related to the voltage Vdata corresponding to the data signal DATA that controls the light-emitting gray level of the pixel circuit. This can realize the compensation of the pixel circuit, solve the problem of the threshold voltage drift of the driving transistor (the first transistor T1) due to the process and long-term operation, eliminate its influence on the driving current I _OLED , thereby improving the display effect.

As shown in FIGS. 1 and 2, since the second transistor T2 uses a P transistor in the pixel circuit shown in FIG. 1, when the first scan signal Gate1 received by the gate of the second transistor T2 is low, The second transistor T2 is turned on, and when the first scan signal Gate1 is at a high level, the second transistor T2 is turned off. In addition, the third transistor T3 and the fourth transistor T4 are N-type transistors, so when the second scan signal Gate2 is high, the third transistor T3 and the fourth transistor T4 are turned on, and when the second scan signal Gate2 is low, Usually, the third transistor T3 and the fourth transistor T4 are turned off.

For example, as shown in FIG. 2, the duration of the first phase P1, the second phase P2, the third phase P3, the fourth phase P4, and the fifth phase P5 are all one system clock cycle H. It should be noted that, in the embodiment of the present disclosure, the system clock period H is, for example, the smallest reference unit generated in the display device for controlling the driving timing of the display device, and all other control signals or clock signals are based on this System clock cycle H. The following embodiments are the same and will not be repeated here.

As shown in Figure 2, in the first phase P1 and the second phase P2, the third transistor T3 and the fourth transistor T4 are turned on, and in the second phase P2 and the third phase P3, the second transistor T2 is turned on, only In the second phase P2, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on at the same time, so that the storage capacitor CST can be charged. In order to drive the pixel circuit in FIG. 1 to work normally, it is necessary to provide the pixel circuit with the first scan signal Gate1 and the second scan signal Gate2 as shown in FIG. 2. The first scan signal Gate1 and the second scan signal Gate2 are not mutually exclusive. They are mutually inverted signals. For example, the first scan signal Gate1 and the second scan signal Gate2 can be provided by shift registers respectively. For example, in display panel technology, in order to achieve low cost and narrow frame, GOA (Gate Driver On Array) technology can be used to integrate the shift register on the display panel through thin film transistor technology, so that narrow frame and cost reduction can be achieved. Advantage.

To sum up, in order to make the 6T1C pixel circuit in FIG. 1 work normally, it is necessary to provide the 6T1C pixel circuit with the first scan signal Gate1 and the second scan signal Gate2 as shown in FIG. 2. At least one embodiment of the present disclosure provides a signal generation method. The signal generation method is used in, for example, a shift register. The shift register includes N cascaded shift register units. The signal generation method includes: The connected shift register units respectively output N pre-output signals;

Invert the N pre-output signals respectively to obtain N pre-output inverted signals; and invert the n-th pre-output inverted signal among the N pre-output inverted signals and the n+th in the N pre-output signals One pre-output signal is combined to generate the nth output signal, thereby obtaining N-1 output signals; n is an integer satisfying 1≤n≤N-1, and N is an integer greater than or equal to 2.

At least one embodiment of the present disclosure also provides a signal generating circuit and a display device corresponding to the above-mentioned signal generating method.

The embodiments and examples of the present disclosure will be described in detail below with reference to the accompanying drawings.

At least one embodiment of the present disclosure provides a signal generation method. The signal generation method is used in a shift register. The shift register includes N cascaded shift register units. The signal generation method includes the following operation steps.

Step S100: Make the N cascaded shift register units respectively output N pre-output signals;

Step S200: Invert the N pre-output signals respectively to obtain N pre-output inverted signals;

Step S300: Combine the n-th pre-output inverted signal among the N pre-output inverted signals and the n+1-th pre-output signal among the N pre-output signals to generate the n-th output signal, thereby obtaining N -1 output signal.

Here, n is an integer satisfying 1≦n≦N-1, and N is an integer greater than or equal to 2.

For example, as shown in FIG. 3, a shift register used in, for example, a gate drive circuit is shown on the left side. The shift register includes N cascaded shift register units, for example, shift register units G, respectively. (0), G(1), G(2), G(3), G(4)...G(N-2), G(N-1), in step S100, the N cascaded The shift register unit outputs N pre-output signals, for example, POUT(0), POUT(1), POUT(2), POUT(3), POUT(4)...POUT(N-2), POUT( N-1). For example, the pre-output signals output by the shift register units of adjacent stages differ by one system clock cycle H.

In step S200, the N pre-output signals output by the shift register are respectively inverted to obtain N pre-output inverted signals, for example, NOUT(0), NOUT(1), NOUT(2), NOUT, respectively. (3), NOUT(4)...NOUT(N-2), NOUT(N-1). For example, adjacent pre-output inverted signals differ by one system clock cycle H.

In step S300, the n-th pre-output inverted signal NOUT(n-1) among the above-mentioned N pre-output inverted signals and the n+1-th pre-output signal POUT(n-1) among the above-mentioned N pre-output signals ) Is combined to generate the nth output signal, thereby obtaining N-1 output signals.

The N-1 output signals obtained by the above-mentioned signal generation method can be used, for example, in a pixel array using the pixel circuit shown in FIG. 1 (that is, an array of pixel units using the pixel circuit shown in FIG. 1), for example, The nth pre-output inverted signal NOUT(n-1) included in the nth output signal can be used as the second scan signal Gate2 to drive the third transistor T3 and the fourth transistor T4 in the pixel circuit, the nth The n+1th pre-output signal POUT(n) included in the output signal may be used as the first scan signal Gate1 to drive the second transistor T2 in the pixel circuit. For example, when a plurality of pixel circuits as shown in FIG. 1 are arranged in an array, for example, the array includes N-1 rows of pixel circuits, the nth output signal obtained by the above-mentioned signal generation method can be used for driving Pixel circuit in the nth row. n is an integer satisfying 1≤n≤N-1, and N is an integer greater than or equal to 2.

The output signal generated by the signal generation method provided by at least one embodiment of the present disclosure can be used to drive a 6T1C pixel circuit, for example, can be used to drive a 6T1C pixel circuit as shown in FIG. 1. It should be noted that in the embodiment of the present disclosure, the 6T1C pixel circuit shown in FIG. 1 is only used to illustrate the signal generation method provided by the embodiment of the present disclosure, but does not indicate the signal generation provided by the embodiment of the present disclosure. The method can only be used for the 6T1C pixel circuit shown in FIG. 1, as long as the pixel circuit is driven by the first scan signal Gate1 and the second scan signal Gate2 shown in FIG. 2 can be applied to this signal generation method.

For example, in some embodiments, each of the N cascaded shift register units in the aforementioned shift register may adopt an exemplary shift register unit G(n) as shown in FIG. 4. As shown in FIG. 4, the shift register unit G(n) includes eight transistors (first transistor M1 to eighth transistor M8) and two capacitors (first capacitor C1 and second capacitor C2).

As shown in FIG. 4, the gate of the first transistor M1 is configured to receive the first control signal CR1, the first pole of the first transistor M1 is configured to receive the input signal IN, the second pole of the first transistor T1 and the first node N1 connection. The gate of the second transistor M2 is connected to the first node N1, the first electrode of the second transistor M2 is configured to receive the first control signal CR1, and the second electrode of the second transistor M2 is connected to the second node N2. The gate of the third transistor M3 is configured to receive the first control signal CR1, the first pole of the third transistor M3 is configured to receive the second level voltage VL, and the second pole of the third transistor M3 is connected to the second node N2 . The gate of the fourth transistor M4 is connected to the second node N2, the first electrode of the fourth transistor M4 is configured to receive the first level voltage VH, and the second electrode of the fourth transistor M4 is connected to the first output terminal PT. The gate of the fifth transistor M5 is connected to the fourth node N4, the first electrode of the fifth transistor M5 is configured to receive the second control signal CR2, and the second electrode of the fifth transistor M5 is connected to the first output terminal PT. The gate of the sixth transistor M6 is connected to the second node N2, the first electrode of the sixth transistor M6 is configured to receive the first level voltage VH, and the second electrode of the sixth transistor M6 is connected to the third node N3. The gate of the seventh transistor M7 is configured to receive the second control signal CR2, the first electrode of the seventh transistor M7 is connected to the third node N3, and the second electrode of the seventh transistor M7 is connected to the first node N1. The gate of the eighth transistor M8 is configured to receive the second level voltage VL, the first pole of the eighth transistor M8 is connected to the first node N1, and the second pole of the eighth transistor M8 is connected to the fourth node N4. The first pole of the first capacitor C1 is connected to the fourth node N4, and the second pole of the first capacitor C1 is connected to the first output terminal PT. The first pole of the second capacitor C2 is connected to the second node N2, and the second pole of the second capacitor C2 is configured to receive the first level voltage VH. The first output terminal PT is configured to output the pre-output signal POUT(n).

For example, FIG. 4 also shows an exemplary inverting sub-circuit IP(n), which includes four transistors (ninth transistor M9 to twelfth transistor M12) and a first Three capacitors C3.

As shown in FIG. 4, the gate of the ninth transistor M9 is connected to the first output terminal PT, the first electrode of the ninth transistor M9 is configured to receive the first level voltage VH, and the second electrode of the ninth transistor M9 is connected to the first output terminal PT. Five-node N5 connection. The gate of the tenth transistor M10 is configured to receive the first control signal CR1, the first pole of the tenth transistor M10 is connected to the fifth node N5, and the second pole of the tenth transistor M10 is configured to receive the second level voltage VL . The gate of the eleventh transistor M11 is connected to the first output terminal PT, the first pole of the eleventh transistor M11 is configured to receive the first level voltage VH, and the second pole of the eleventh transistor M11 is connected to the second output terminal. NT connection. The gate of the twelfth transistor M12 is connected to the fifth node N5, the first pole of the twelfth transistor M12 is configured to receive the second level voltage VL, the second pole of the twelfth transistor M12 and the second output terminal NT connection. The first pole of the third capacitor C3 is connected to the fifth node N5, and the second pole of the third capacitor C3 is configured to receive the second control signal CR2. The second output terminal NT is configured to output the pre-output inverted signal NOUT(n).

It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor except for the gate, one pole is directly described as the first pole and the other pole is the second pole. Therefore, in the embodiments of the present disclosure, all or part of the transistors have the first pole. The pole and the second pole are interchangeable as needed. For example, in the embodiments of the present disclosure, the first electrode of the transistor may be a source and the second electrode may be a drain; or, the first electrode of the transistor may be a drain and the second electrode may be a source.

In addition, transistors can be divided into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages) ); When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable Voltage).

In addition, in the embodiments of the present disclosure, for example, the first power supply voltage VDD and the first level voltage VH are high-level voltages. For example, the high-level voltage can turn on the N-type transistor and turn off the P-type transistor. ; The second power supply voltage VSS and the second level voltage VL are low-level voltages, for example, the low-level voltage can make the P-type transistor turn on and make the N-type transistor turn off. The following embodiments are the same and will not be repeated here.

In the embodiment of the present disclosure, the high level and the low level are relative. The high level indicates a higher voltage range (for example, the high level can be 5V, 10V or other suitable voltages), and multiple high levels can be the same or different. Similarly, the low level represents a lower voltage range (for example, the low level may adopt 0V, -5V, -10V or other suitable voltages), and multiple low levels may be the same or different. For example, the minimum value of the high level is greater than the maximum value of the low level.

In addition, the transistors shown in FIG. 4 (the first transistor M1 to the twelfth transistor M12) are all P-type transistors as examples. The embodiments of the present disclosure include but are not limited to this. For example, some of the transistors in FIG. 4 may also Use N-type transistors.

The working principle of the shift register unit G(n) and the inverting sub-circuit IP(n) in FIG. 4 will be described below in conjunction with the signal timing shown in FIG. 5. It should be noted that, as shown in FIG. 5, the durations of the first phase Q1, the second phase Q2, the third phase Q3, and the fourth phase Q4 are all two system clock cycles, that is, 2H.

As shown in FIGS. 4 and 5, in the first stage Q1, the first control signal CR1 and the input signal IN are at a low level, and the second control signal CR2 is at a high level. The first transistor M1 is turned on under the control of the low-level first control signal CR1, and the eighth transistor M8 is turned on under the control of the low-level second-level voltage VL, thereby enabling a low-level input The signal IN is transmitted to the fourth node N4 through the turned-on first transistor M1 and the eighth transistor M8, thereby pulling down the level of the fourth node N4, and the fifth transistor M5 is turned on. The high-level second control signal CR2 is transmitted to the first output terminal PT through the fifth transistor M5.

The third transistor M3 is turned on under the control of the low-level first control signal CR1, and the low-level second-level voltage VL is transmitted to the second node N2 through the turned-on third transistor M3, and the fourth transistor M4 When turned on, the high-level first-level voltage VH is transmitted to the first output terminal PT through the turned-on fourth transistor M4.

Both the high-level first-level voltage VH and the high-level second control signal CR2 are transmitted to the first output terminal PT, so in the first stage Q1, the first output terminal PT outputs a high-level pre-output signal POUT(n).

Since the first output terminal PT is at a high level, the ninth transistor M9 and the eleventh transistor M11 are turned off. The tenth transistor M10 is turned on under the control of the low-level first control signal CR1, and the low-level second-level voltage VL is transmitted to the fifth node N5 through the turned-on tenth transistor M10, thereby pulling down the At the level of the node N5, the twelfth transistor M12 is turned on. The low-level second-level voltage VL is transmitted to the second output terminal NT through the turned-on twelfth transistor M12, so that the second output terminal NT outputs the low-level pre-output inverted signal NOUT(n).

In the second stage Q2, the input signal IN and the first control signal CR1 are at a high level, and the second control signal CR2 is at a low level. The eighth transistor M8 is kept on under the control of the low-level second-level voltage VL. Due to the function of the first capacitor C1, the fourth node N1 and the first node N1 can maintain the low level of the previous stage. The second transistor M2 is turned on, the high-level first control signal CR1 is transmitted to the second node N2 through the turned-on second transistor M2, thereby pulling up the level of the second node N2, the fourth transistor M4 and the sixth The transistor M6 is turned off.

Since the fourth node N4 is at the low level, the fifth transistor M5 remains on, and the low-level second control signal CR2 is transmitted to the first output terminal PT through the turned-on fifth transistor M5, so in the second stage Q2 The first output terminal PT outputs a low-level pre-output signal POUT(n).

Since the first output terminal PT is at a low level, the ninth transistor M9 and the eleventh transistor M11 are turned on. The high-level first-level voltage VH is transmitted to the fifth node N5 through the turned-on ninth transistor M9, and the twelfth transistor M12 is turned off. The high-level first-level voltage VH is transmitted to the second output terminal NT through the turned-on eleventh transistor M11, so in the second stage Q2, the second output terminal NT outputs a high-level pre-output inverted signal NOUT(n).

In the third stage Q3, the input signal IN and the second control signal CR2 are at a high level, and the first control signal CR1 is at a low level. The third transistor M3 is turned on under the control of the low-level first control signal CR1, and the low-level second-level voltage VL is transmitted to the second node N2 through the turned-on third transistor M3, so the fourth transistor M4 is turned on, the high-level first-level voltage VH is transmitted to the first output PT through the turned-on fourth transistor M4, so in the third stage Q3, the first output terminal PT outputs a high-level pre-output The signal POUT(n).

At the same time, in the third stage Q3, the first transistor M1 is turned on under the control of the low-level first control signal CR1, and the high-level input signal IN is transmitted to the first node N1 through the turned-on first transistor M1. And the fourth node N4, the fifth transistor M5 is turned off.

Since the first output terminal PT is at a high level, the ninth transistor M9 and the eleventh transistor M11 are turned off. The tenth transistor M10 is turned on under the control of the low-level first control signal CR1, and the low-level second-level voltage is transmitted to the fifth node N5 through the turned-on tenth transistor M10, and the twelfth transistor M12 Is turned on, the low-level second-level voltage VL is transmitted to the second output terminal NT through the turned-on twelfth transistor M12, so that in the third stage Q3, the second output terminal NT outputs a low-level preset The inverted signal NOUT(n) is output.

In the fourth stage Q4, the input signal IN and the first control signal CR1 are high, and the second control signal CR2 is low. Due to the effect of the second capacitor C2, the second node N2 can maintain the low level of the previous stage, so the fourth transistor M4 continues to be turned on, and the high-level first-level voltage VH is passed through the turned-on fourth transistor M4. Transmitted to the first output terminal PT. In addition, due to the function of the fourth capacitor C4, the fourth node N4 can maintain the high level of the previous stage, so the fifth transistor M5 remains off, so that the first output terminal PT continues to output the high level in the fourth stage Q4 The pre-output signal POUT(n).

Similar to the previous stage, in the fourth stage Q4, the second output terminal NT is made to output a low-level pre-output inverted signal NOUT(n).

As shown in FIG. 5, the pre-output signal POUT(n) output by the first output terminal PT and the pre-output inverse signal NOUT(n) output by the second output terminal NT are mutually inverted signals, as shown in FIG. 4 The inverting sub-circuit IP(n) is used to invert the pre-output signal POUT(n) output by the shift register unit G(n) shown in FIG. 4 to output the pre-output inverted signal NOUT(n).

It should be noted that the inverting sub-circuit IP(n) shown in FIG. 4 is only exemplary. The embodiment of the present disclosure does not limit the specific circuit structure of the inverting sub-circuit IP(n), as long as it can Invert POUT(n) to obtain the pre-output inverted signal NOUT(n).

In addition, the shift register unit G(n) shown in FIG. 4 is also exemplary. The embodiment of the present disclosure does not limit the specific circuit structure of the shift register unit G(n), as long as it is the first output terminal PT The signal shown in Figure 5 can be output. In addition, the inverting sub-circuit IP(n) shown in FIG. 4 can also be regarded as a part of the shift register unit G(n), which is not limited in the embodiment of the present disclosure.

As shown in Figure 3, when N shift register units are cascaded, the 2k+1 stage shift register unit G(2k+1) and the 2k-1 stage shift register unit G( 2k-1) is connected to receive the 2k-1th pre-output signal POUT(2k-1) among the N pre-output signals, for example, the 2k+1th stage shift register unit G(2k+1) and the 2k-th The first output terminal PT of the first stage shift register unit G (2k-1) is connected, so that the 2k-1th pre-output signal POUT (2k-1) is input as the output signal IN to the 2k+1 stage shift register unit G(2k+1).

The shift register unit G (2k+2) of the 2k+2 stage and the shift register unit G (2k) of the 2k stage are connected to receive the 2k pre-output signal POUT (2k) among the N pre-output signals. For example, the first output terminal PT of the 2k+2 stage shift register unit G(2k+2) and the 2k stage shift register unit G(2k) are connected, so that the 2kth pre-output signal POUT(2k) is The output signal IN is input to the shift register unit G (2k+2) of the 2k+2 stage. k is an integer satisfying 1≤k≤(N/2).

That is to say, the N shift register units in the shift register in FIG. 3 are cascaded according to odd-numbered stages and even-numbered stages, respectively.

The signal generation method provided by at least one embodiment of the present disclosure further includes the following operation steps.

Step S400: Provide the first clock signal CK1 and the second clock signal CK2 to the odd-numbered shift register units in the shift register;

Step S500: Provide the third clock signal CK3 and the fourth periodic signal CK4 to the even-numbered shift register units in the shift register.

For example, the first clock signal CK1 provided to the odd-numbered shift register unit may be used as the first control signal CR1, and the second clock signal CK2 provided to the odd-numbered shift register unit may be used as the second control signal CR2. The third clock signal CK3 provided to the even-numbered shift register unit can be used as the first control signal CR1, and the fourth clock signal CK4 provided to the even-numbered shift register unit can be used as the second control signal CR2.

As shown in FIG. 6, the first clock signal CK1 and the second clock signal CK2 are two system clock cycles H apart, the first clock signal CK1 and the third clock signal CK3 are one system clock cycle H apart, and the third clock signal CK3 is different from the first clock signal CK3. The four clock signal CK4 differs by two system clock periods 2H, and the second clock signal CK2 and the fourth clock signal CK4 differ by one system clock period H. The duty ratios of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are all 50%.

When the shift register formed by the cascade connection of N shift register units as shown in Fig. 4 adopts the clock signal shown in Fig. 6, the pre-output signal POUT( n-1) The timing relationship between the inverted pre-output inverted signal NOUT(n-1) and the pre-output signal POUT(n) output by the n+1th stage shift register unit G(n) is shown in Figure 7. For example, when a plurality of pixel circuits as shown in FIG. 1 are arranged in an array, for example, the array includes N-1 rows of pixel circuits, the pre-output inverted signal NOUT(n-1 ) And the pre-output signal POUT(n) can be used to drive pixel circuits in the nth row. n is an integer satisfying 1≤n≤N-1, and N is an integer greater than or equal to 2. As shown in FIG. 7, the charging time CT for charging the storage capacitor CST in the pixel circuit is one system clock period H.

In some other embodiments of the present disclosure, the circuit shown in FIG. 4 may also adopt the signal timing shown in FIG. 8. As shown in Figure 8, in the first stage W1, the input signal IN and the first control signal CR1 are at low level, the second control signal CR2 is at high level, and the first output terminal PT outputs a high level pre-output signal. POUT(n), the second output terminal NT outputs a low-level pre-output inverted signal NOUT(n). For the working principle of the first stage W1, please refer to the working principle of the first stage Q1 mentioned above, which will not be repeated here.

In the second stage W2, the second stage Q2 is similar, the first output terminal PT outputs a low-level pre-output signal POUT(n), and the second output terminal NT outputs a high-level pre-output inverted signal NOUT(n ).

In the third stage W3, the second control signal CR2 changes from low level to high level, the pre-output signal POUT(n) output by the first output terminal PT also changes from low level to high level, and the ninth transistor M9 and the eleventh transistor M11 are turned off. At this time, since the first control signal CR1 is still at a high level, the tenth transistor M10 is also turned off. Due to the effect of the third capacitor C3, the fifth node N5 is still at the high level of the previous stage, so the twelfth transistor M12 is also turned off, and the pre-output inverted signal NOUT(n) output by the second output terminal NT will not be The pull-down is still high.

For the working principle of the fourth stage W4, you can refer to the working principle of the third stage Q3, and the working principle of the fifth stage W5 can refer to the working principle of the fourth stage Q4, which will not be repeated here.

As shown in Figure 9, the first clock signal CK1 and the third clock signal CK3 differ by one system clock period H, the second clock signal CK2 and the fourth clock signal CK4 differ by one system clock period H, and the first clock signal CK1 and the The duty ratios of the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are all greater than 50%.

When the shift register formed by the cascade of N shift register units as shown in FIG. 4 adopts the clock signal shown in FIG. 9, the pre-output signal POUT( n-1) The timing relationship between the inverted pre-output inverted signal NOUT(n-1) and the pre-output signal POUT(n) output by the n+1th stage shift register unit G(n) is shown in Figure 10. For example, when a plurality of pixel circuits as shown in FIG. 1 are arranged in an array, for example, the array includes N-1 rows of pixel circuits, the pre-output inverted signal NOUT(n) and The pre-output signal POUT(n+1) can be used to drive the pixel circuit of the nth row. n is an integer satisfying 1≤n≤N-1, and N is an integer greater than or equal to 2. As shown in FIG. 10, the charging time CT for charging the storage capacitor CST in the pixel circuit is greater than one system clock period H.

In the signal generation method provided by the above-mentioned embodiments of the present disclosure, when the duty ratio of the adopted clock signal is greater than 50%, the charging time CT for charging the storage capacitor CST in the pixel circuit can be increased.

Furthermore, in order to further increase the charging time CT for charging the storage capacitor CST in the pixel circuit, the gate of the tenth transistor M10 in FIG. 4 may also be configured to receive other control signals different from the first control signal CR1. The tenth transistor M10 is turned on later, so that the pulse width of the pre-output inverted signal output by the second output terminal NT of the shift register unit shown in FIG. 4 is wider, so that the charging time CT can be increased.

For example, in the signal generation method provided by some embodiments of the present disclosure, the n-th pre-output inverted signal among the N pre-output inverted signals and the n+1-th pre-output signal among the N pre-output signals are At least two transistors in the display area of the display panel are configured to be turned on or off. For example, the nth pre-output inverted signal NOUT(n-1) can be used as the second scan signal Gate2 to drive the third transistor T3 and the fourth transistor T4 in the pixel circuit as shown in FIG. One pre-output signal POUT(n) can be used as the first scan signal Gate1 to drive the second transistor T2 in the pixel circuit shown in FIG. 1. For example, the second transistor T2 is a P-type transistor, and the third transistor T3 and the fourth transistor T4 are N-type transistors.

At least one embodiment of the present disclosure also provides a signal generating circuit 100. As shown in FIG. 11, the signal generating circuit 100 includes a shift register 110 and an inverter circuit 120.

For example, the shift register 110 includes N cascaded shift register units (such as G(0), G(1), G(2), G(3)...G(N-1) shown in FIG. )), N cascaded shift register units are configured to respectively output N pre-output signals, such as POUT(0), POUT(1)...POUT(n)...POUT(N-1). For example, the shift register unit may adopt the shift register unit G(n) shown in FIG. 4.

For example, the inverter circuit 120 is configured to invert the N pre-output signals to obtain N pre-output inverted signals, such as NOUT(0), NOUT(1)...NOUT(n)...NOUT(N -1).

Combine the nth pre-output inverted signal NOUT(n-1) among the N pre-output inverted signals and the n+1th pre-output signal POUT(n) among the N pre-output signals to generate the nth Output signals, thereby obtaining N-1 output signals of the signal generating circuit 100. n is an integer satisfying 1≤n≤N-1, and N is an integer greater than or equal to 2.

The output signal generated by the signal generating circuit 100 provided by at least one embodiment of the present disclosure can be used to drive a 6T1C pixel circuit, for example, can be used to drive a 6T1C pixel circuit as shown in FIG. 1.

For example, in the signal generating circuit 100 provided by some embodiments of the present disclosure, as shown in FIG. 12, the inverter circuit 120 includes N inverter sub-circuits, such as IP(0), IP(1), IP(2). ), IP(3)...IP(N-1), the m-th inverting sub-circuit IP(m) is connected to the m-th stage shift register unit G(m), and is configured to respond to the N pre-output signals The m-th pre-output signal POUT(m) is inverted to obtain the m-th pre-output inverted signal NOUT(m) among the N pre-output inverted signals, where m is an integer satisfying 0≤m≤N. For example, the inverting sub-circuit may adopt the inverting sub-circuit IP(n) shown in FIG. 4.

For example, as shown in FIG. 12, the 2k+1 stage shift register unit G (2k+1) and the 2k-1 stage shift register unit G (2k-1) in the shift register are connected to receive N presets. The 2k-1th pre-output signal POUT(2k-1) in the output signal, for example, the 2k+1th stage shift register unit G(2k+1) and the 2k-1th stage shift register unit G(2k- The first output terminal PT of 1) is connected, so that the 2k-1th pre-output signal POUT(2k-1) is input to the 2k+1th stage shift register unit G(2k+1) as the output signal IN.

The shift register unit G (2k+2) of the 2k+2 stage and the shift register unit G (2k) of the 2k stage are connected to receive the 2k pre-output signal POUT (2k) among the N pre-output signals. For example, the first output terminal PT of the 2k+2 stage shift register unit G(2k+2) and the 2k stage shift register unit G(2k) are connected, so that the 2kth pre-output signal POUT(2k) is used as The output signal IN is input to the shift register unit G (2k+2) of the 2k+2 stage. k is an integer satisfying 1≤k≤(N/2).

For example, as shown in FIG. 12, the shift register unit G(0) may receive the first frame signal STV0 as the input signal IN, and the shift register unit G(1) may receive the second frame signal STV1 as the input signal IN.

That is to say, the N shift register units in the shift register in FIG. 12 are cascaded according to odd-numbered stages and even-numbered stages, respectively.

For example, the pre-output signals output by the shift register units of adjacent stages differ by one system clock cycle H.

It should be noted that for the working principle of the shift register unit and the inverting sub-circuit in FIG. 12, reference may be made to the working principle of the circuit shown in FIG. 4, which will not be repeated here.

The signal generation circuit 100 provided by some embodiments of the present disclosure further includes a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line. The first clock signal line is connected to the odd-numbered shift register unit in the shift register to provide a first clock signal CK1, and the second clock signal line is connected to the odd-numbered shift register unit in the shift register to provide a second clock signal CK2; the third clock signal line is connected to the even-numbered shift register unit in the shift register to provide the third clock signal CK3, and the fourth clock signal line is connected to the even-numbered shift register unit in the shift register to provide the fourth Clock signal CK4.

For example, the first clock signal CK1 and the third clock signal CK3 differ by one system clock period H, and the second clock signal CK2 and the fourth clock signal CK4 differ by one system clock period H.

For example, in some embodiments, the duty ratios of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are all 50%.

For example, in some embodiments, the duty ratios of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are all greater than 50%.

For the detailed description of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4, reference may be made to the corresponding description in the foregoing embodiment of the signal generation method, which will not be repeated here.

At least one embodiment of the present disclosure further provides a display device 10. As shown in FIG. 13, the display device 10 includes a signal generating circuit 100. For example, the signal generating circuit 100 may use the signal generating circuit provided in the above-mentioned embodiments.

For example, in some embodiments, as shown in FIG. 13, the display device 10 further includes a display panel 200. The display panel 200 includes a plurality of pixel circuits 300 arranged in an array, and the plurality of pixel circuits 300 are connected to the signal generating circuit 100. For example, a plurality of pixel units PI arranged in an array may be provided in the display panel 200, and a pixel circuit 300 is provided in each pixel unit PI. For example, the display panel 200 includes N-1 rows of pixel circuits 300, and the nth row of pixel circuits is configured to receive the nth output signal among the N-1 output signals of the signal generating circuit 100.

For example, in some embodiments of the present disclosure, the pixel circuit 300 shown in FIG. 13 may adopt the pixel circuit shown in FIG. 14. As shown in FIG. 14, the pixel circuit 300 includes a data writing sub-circuit 320 and a driver The circuit 310, the compensation sub-circuit 330, the reset sub-circuit 340, the light-emission control sub-circuit, and the light-emitting element 360. For example, the light emission control circuit includes a first light emission control sub-circuit 351 and a second light emission control sub-circuit 352. For example, the pixel circuit shown in FIG. 14 may be implemented as the circuit structure shown in FIG. 1, but the embodiments of the present disclosure include but are not limited to this, and the pixel circuit shown in FIG. 14 may also be implemented as other circuit structures.

For example, as shown in FIG. 14, the compensation sub-circuit 330, the reset sub-circuit 340, and the data writing sub-circuit 320 in the pixel circuit of the n-th row are configured to receive the n-th output signal of the signal generating circuit 100. For example, the compensation sub-circuit 330 and the reset sub-circuit 340 are configured to receive the pre-output inverted signal NOUT(n) in the nth output signal, and the data writing sub-circuit is configured to receive the pre-output in the nth output signal. The signal POUT(n+1).

It should be noted that the display device 10 provided by at least one embodiment of the present disclosure may be: LCD panel, LCD TV, display, OLED panel, OLED TV, electronic paper, mobile phone, tablet computer, notebook computer, digital photo frame, navigator, etc. Any product or component with display function.

For the technical effects of the display device 10 provided by the embodiments of the present disclosure, reference may be made to the corresponding description of the signal generation method and the signal generation circuit 100 in the above-mentioned embodiments, which will not be repeated here.

The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

A signal generation method for a shift register, wherein the shift register includes N cascaded shift register units, and the signal generation method includes:

Make N cascaded shift register units output N pre-output signals respectively;

Inverting the N pre-output signals respectively to obtain N pre-output inverted signals; and

Combine the n-th pre-output inverted signal among the N pre-output inverted signals and the n+1-th pre-output signal among the N pre-output signals to generate the n-th output signal, thereby obtaining N-1 output signals;

Wherein, n is an integer satisfying 1≤n≤N-1, and N is an integer greater than or equal to 2.
4. The signal generating method according to claim 1, wherein the pre-output signals output by the shift register units of adjacent stages differ by one system clock cycle.
The signal generating method according to claim 1 or 2, wherein the difference between the nth pre-output inverted signal and the n+1th pre-output inverted signal in the N pre-output inverted signals is one system Clock cycle.
The signal generation method according to any one of claims 1 to 3, wherein the 2k+1 stage shift register unit and the 2k-1 stage shift register unit in the shift register are connected to receive the N The 2k-1th pre-output signal in the N pre-output signals, the 2k+2-stage shift register unit and the 2k-stage shift register unit in the shift register are connected to receive the N pre-output signals. The 2kth pre-output signal of;

Among them, k is an integer satisfying 1≤k≤(N/2).
The signal generation method according to any one of claims 1 to 4, further comprising:

Providing a first clock signal and a second clock signal to the odd-numbered stage shift register units in the shift register; and

The third clock signal and the fourth period signal are provided to the even-numbered shift register units in the shift register.
5. The signal generating method according to claim 5, wherein the first clock signal and the third clock signal differ by one system clock period, and the second clock signal and the fourth clock signal differ by one system clock cycle.
The signal generation method according to claim 5 or 6, wherein a duty cycle of at least one of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal is greater than 50%.
8. The signal generating method according to claim 7, wherein the duty ratios of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are all greater than 50%.
8. The signal generating method according to any one of claims 1-8, wherein the nth pre-output inverted signal in the N pre-output inverted signals and the n+th in the N pre-output signals One pre-output signal is configured to control at least two transistors in the display area of the display panel to be turned on or off.
The signal generating method according to claim 9, wherein the at least two transistors include two different types of transistors.
A signal generating circuit includes a shift register and an inverter circuit, wherein,

The shift register includes N cascaded shift register units,

The N cascaded shift register units are configured to output N pre-output signals respectively;

The inverting circuit is configured to invert the N pre-output signals to obtain N pre-output inverted signals;

Combine the n-th pre-output inverted signal among the N pre-output inverted signals and the n+1-th pre-output signal among the N pre-output signals to generate the n-th output signal, thereby obtaining N-1 output signals of the signal generating circuit;

Wherein, n is an integer satisfying 1≤n≤N-1, and N is an integer greater than or equal to 2.
The signal generating circuit according to claim 11, wherein the inverting circuit includes N inverting sub-circuits, and the m-th inverting sub-circuit is connected to the m-th stage shift register unit and is configured to pair Inverting the m-th pre-output signal among the N pre-output signals to obtain the m-th pre-output inverted signal among the N pre-output inverted signals,

Among them, m is an integer satisfying 0≤m≤N.
The signal generating circuit according to claim 11 or 12, wherein the 2k+1 stage shift register unit and the 2k-1 stage shift register unit in the shift register are connected to receive the N pre-outputs The 2k-1th pre-output signal in the signal, the 2k+2th stage shift register unit and the 2kth stage shift register unit in the shift register are connected to receive the 2kth stage of the N pre-output signals Pre-output signals;

Among them, k is an integer satisfying 1≤k≤(N/2).
The signal generating circuit according to any one of claims 11-13, wherein the pre-output signals output by the shift register units of adjacent stages differ by one system clock cycle.
The signal generation circuit according to any one of claims 11-14, further comprising a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line,

The first clock signal line is connected to the odd-stage shift register unit in the shift register to provide a first clock signal, and the second clock signal line is connected to the odd-stage shift register in the shift register. The register unit is connected to provide a second clock signal;

The third clock signal line is connected to the even-numbered stage shift register unit in the shift register to provide a third clock signal, and the fourth clock signal line is shifted with the even-numbered stage in the shift register The register unit is connected to provide the fourth clock signal.
15. The signal generating circuit according to claim 15, wherein the first clock signal and the third clock signal differ by one system clock period, and the second clock signal and the fourth clock signal differ by one System clock cycle.
The signal generating circuit according to claim 15 or 16, wherein a duty cycle of at least one of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal is greater than 50%.
A display device comprising the signal generating circuit according to any one of claims 11-17.
The display device according to claim 18, further comprising a display panel, wherein:

The display panel includes a plurality of pixel circuits arranged in an array in N-1 rows, and the plurality of pixel circuits are connected to the signal generating circuit,

The pixel circuit of the nth row is configured to receive the nth output signal among the N-1 output signals of the signal generating circuit,

Wherein, n is an integer satisfying 1≤n≤N-1, and N is an integer greater than or equal to 2.
The display device according to claim 19, wherein the pixel circuit includes a data writing sub-circuit, a driving sub-circuit, a compensation sub-circuit, a reset sub-circuit, a light-emission control sub-circuit, and a light-emitting element,

The compensation sub-circuit, the reset sub-circuit, and the data writing sub-circuit in the n-th row of pixel circuits are configured to receive the n-th output signal of the signal generating circuit.