WO2020220347A1 - Amplifier and amplification device - Google Patents

Abstract

Disclosed are an amplifier and an amplification device, which are used for reducing the gain and power consumption fluctuation of an amplifier while improving the linearity of the amplifier. The amplifier comprises: at least one first gain circuit for amplifying a first signal, each first gain circuit comprising a first transistor and a second transistor, wherein a channel of the first transistor is in a strong inversion state, and a channel of the second transistor is in a weak inversion state; and at least one second gain circuit for amplifying a second signal, each second gain circuit comprising a third transistor and a fourth transistor, wherein a channel of the third transistor is in a strong inversion state, and a channel of the fourth transistor is in a weak inversion state. The first signal and the second signal constitute a differential signal. A gate electrode bias voltage of the first transistor and the third transistor is a first voltage, and a gate electrode bias voltage of the second transistor and the fourth transistor is a second voltage.

Description

Amplifier and amplifying device Technical field

This application relates to the field of communication technology, and in particular to an amplifier and an amplifier device.

Background technique

With the development of broadband wireless communication, the performance index requirements of the amplifier in the radio frequency front end are becoming more and more stringent. The radio frequency front end amplifier must take into account the gain, noise, linearity, and power consumption indicators.

In the prior art, the schematic diagram of the structure of the amplifier of the radio frequency front end may be as shown in FIG. 1. In Figure 1, the signal input from the positive input terminal (Vip) is amplified by multiple metal-oxide semiconductor (MOS) tubes connected in parallel, and then transmitted to the negative output terminal (Von) after passing through a parallel resonant load; negative The signal input from the input terminal (Vin) is amplified by multiple parallel MOS transistors, and then transmitted to the positive output terminal (Vop) after passing through the parallel resonant load (ie, the resistance R, the capacitor C, and the inductance L in Figure 1) to achieve the pairing Amplification of differential input signals. That is to say, in this amplifier, multiple MOS tubes connected in parallel are used to realize the amplification function.

Generally, in order to improve the linearity of the amplifier, the intrinsic non-linear characteristics of the active transistors (such as MOS transistors) in the amplifier can be used to position the active transistors at the bias point of the n-th order (such as the third order) with the least non-linearity. For the amplifier shown in Figure 1, the MOS tube is set at the bias point with the smallest n-th order nonlinearity by adjusting the gate-source bias voltage Vgs. In specific implementation, the gate-source bias voltage Vgs can be determined by the feedback circuit shown in FIG. 2, and the output of the feedback circuit can be used as the gate-source bias voltage to be applied to the Vgs terminal in FIG. 1. It can be deduced from the voltage value of each node and the current value of each branch in FIG. 2 that using the output of FIG. 2 as the gate-source bias voltage can make the third-order nonlinearity of the amplifier shown in FIG. 1 be zero.

However, using the method shown in Figure 2 to improve the linearity of the amplifier will have the following problems: Since the feedback circuit shown in Figure 2 includes active transistors, current sources, operational amplifiers and other electronic devices, When the display circuit drives active transistors, it is affected by the process, temperature, model accuracy of these electronic devices, etc., which will cause the output of the circuit shown in Figure 2 to fluctuate greatly (that is, cause the Vgs to fluctuate greatly), and then cause the circuit shown in Figure 1. The gain of the amplifier fluctuates greatly with the process, temperature, and model accuracy of the electronic device in Figure 2. Therefore, adopting the scheme of improving linearity shown in Fig. 2, the consistency of mass production of amplifier gain and power consumption is poor, and the product yield rate is low.

In summary, there is an urgent need for a solution to improve the linearity of the amplifier, so as to reduce the gain and power consumption fluctuation of the amplifier while improving the linearity of the amplifier.

Summary of the invention

The embodiments of the present application provide an amplifier and an amplifying device, which are used to improve the linearity of the amplifier while reducing fluctuations in the gain and power consumption of the amplifier.

In a first aspect, an embodiment of the present application provides an amplifier, the amplifier includes: at least one first gain circuit for amplifying a first signal; each first gain circuit includes a first transistor and a second transistor; The channel is in a strong inversion state, and the channel of the second transistor is in a weak inversion state; at least one second gain circuit is used to amplify the second signal; each second gain circuit includes a third transistor and a fourth transistor; The channel of the three transistors is in a strong inversion state, and the channel of the fourth transistor is in a weak inversion state; the first signal and the second signal constitute a differential signal; wherein, the gate bias voltage of the first transistor and the third transistor is The first voltage, the gate bias voltage of the second transistor and the fourth transistor are the second voltage.

With the above solution, since the channels of the first transistor and the third transistor are in a strong inversion state, the first signal and the second signal can be amplified by the first transistor and the third transistor respectively. The channels of the four transistors are in a weak inversion state, so the output signal of the first transistor and the output signal of the third transistor can be non-linearly compensated by the second transistor and the fourth transistor respectively, thereby improving the linearity of the amplifier.

In addition, in the amplifier provided in the first aspect, the channels of the second transistor and the fourth transistor are in a weak inversion state, the gain is small, and the power consumption is small. Therefore, in the amplifier provided in the first aspect, the gain and power consumption are mainly determined by the first transistor and the third transistor; the second transistor and the fourth transistor are responsible for canceling the nonlinearity, and only contribute a very low proportion of power consumption and gain. Therefore, in the amplifier, the linearity of the amplifier can be improved by the second transistor and the fourth transistor, and the gain fluctuation and power consumption fluctuation of the amplifier can be reduced.

Specifically, since the channel of the first transistor is in a strong inversion state and the channel of the second transistor is in a weak inversion state, the first transistor can be used to amplify the first signal, and the second transistor can be used to output the first transistor. The signal is nonlinearly compensated; since the channel of the third transistor is in a strong inversion state and the channel of the fourth transistor is in a weak inversion state, the third transistor can be used to amplify the second signal, and the fourth transistor can be used to The output signal of the transistor performs nonlinear compensation.

In a possible design, the gate of the first transistor is used to receive the first signal, the source of the first transistor is coupled to ground, the drain of the first transistor is coupled to the load of the amplifier; the source of the second transistor is coupled to ground , The drain of the second transistor is coupled to the load of the amplifier; the gate of the third transistor is used to receive the second signal, the source of the third transistor is coupled to ground, and the drain of the third transistor is coupled to the load of the amplifier; the fourth transistor The source of the transistor is coupled to ground, and the drain of the fourth transistor is coupled to the load of the amplifier.

In a second aspect, an embodiment of the present application provides an amplifier, which includes: at least one first gain circuit, each first gain circuit includes a first transistor and a second transistor; the channel of the first transistor is in a strong inversion state , The channel of the second transistor is in a weak inversion state; at least one second gain circuit, each second gain circuit includes a third transistor and a fourth transistor; the channel of the third transistor is in a strong inversion state, the fourth transistor The channel is in a weak inversion state; where the first signal and the second signal constitute a differential signal; the gate bias voltage of the first transistor and the third transistor is the first voltage, and the gates of the second transistor and the fourth transistor The bias voltage is the second voltage.

With the above solution, since the channels of the first transistor and the third transistor are in a strong inversion state, the first signal and the second signal can be amplified by the first transistor and the third transistor respectively. The channels of the four transistors are in a weak inversion state, so the output signal of the first transistor and the output signal of the third transistor can be non-linearly compensated by the second transistor and the fourth transistor respectively, thereby improving the linearity of the amplifier.

In addition, in the amplifier provided by the second aspect, the channels of the second transistor and the fourth transistor are in a weak inversion state, the gain is small, and the power consumption is small. Therefore, in the amplifier provided by the second aspect, the gain and power consumption are mainly determined by the first transistor and the third transistor; the second transistor and the fourth transistor are responsible for canceling the nonlinearity, and only contribute a very low proportion of power consumption and gain. Therefore, in the amplifier, the linearity of the amplifier can be improved by the second transistor and the fourth transistor, and the gain fluctuation and power consumption fluctuation of the amplifier can be reduced.

Specifically, since the channel of the first transistor is in a strong inversion state and the channel of the second transistor is in a weak inversion state, the first transistor can be used to amplify the first signal, and the second transistor can be used to output the first transistor. The signal is nonlinearly compensated; since the channel of the third transistor is in a strong inversion state and the channel of the fourth transistor is in a weak inversion state, the third transistor can be used to amplify the second signal, and the fourth transistor can be used to The output signal of the transistor performs nonlinear compensation.

In a possible design, the gate of the first transistor is used to receive the first signal, the source of the first transistor is coupled to ground, the drain of the first transistor is coupled to the load of the amplifier; the source of the second transistor is coupled to ground , The drain of the second transistor is coupled to the load of the amplifier; the gate of the third transistor is used to receive the second signal, the source of the third transistor is coupled to ground, and the drain of the third transistor is coupled to the load of the amplifier; the fourth transistor The source of the transistor is coupled to ground, and the drain of the fourth transistor is coupled to the load of the amplifier.

In a third aspect, an embodiment of the present application provides an amplifying device, which includes an amplifier and a closed-loop feedback circuit. Wherein, the amplifier includes at least one first gain circuit for amplifying the first signal and at least one second gain circuit for amplifying the second signal. Each first gain circuit includes a first transistor and a second transistor; the channel of the first transistor is in a strong inversion state, and the channel of the second transistor is in a weak inversion state; each second gain circuit includes a third transistor and The fourth transistor; the channel of the third transistor is in a strong inversion state, and the channel of the fourth transistor is in a weak inversion state; the first signal and the second signal constitute a differential signal; wherein the gates of the first transistor and the third transistor The pole bias voltage is the first voltage generated by the first current source, and the gate bias voltages of the second transistor and the fourth transistor are the second voltage; the closed loop feedback circuit is used to generate the second voltage.

With the above solution, since the channels of the first transistor and the third transistor are in a strong inversion state, the first signal and the second signal can be amplified by the first transistor and the third transistor respectively; because the second transistor and the second transistor The channels of the four transistors are in a weak inversion state, so the output signal of the first transistor and the output signal of the third transistor can be non-linearly compensated by the second transistor and the fourth transistor respectively, thereby improving the linearity of the amplifier.

In addition, since the first transistor and the third transistor are biased by the first current source, the gain fluctuation and power consumption fluctuation of the first transistor and the third transistor are also small. When the second transistor and the fourth transistor are biased through the closed-loop feedback circuit, although the bias provided by the closed-loop feedback circuit will cause fluctuations in gain and power consumption, the channels of the second and fourth transistors are in a weak inversion state. The gain is small and the power consumption is small, so even if gain fluctuations and power consumption fluctuations occur, the value of the fluctuations will hardly have a large impact on the first gain circuit and the second gain circuit. Therefore, in the amplifying device provided by the third aspect, the gain fluctuation and power consumption fluctuation of the first gain circuit and the second gain circuit are small.

To sum up, in the amplifying device provided by the third aspect, the gain and power consumption are mainly determined by the first transistor and the third transistor; the second transistor and the fourth transistor are responsible for offsetting the nonlinearity, and only contribute a very low proportion of the power consumption and power consumption. Gain. Therefore, in the amplifying device provided by the third aspect, the linearity of the amplifier can be improved by the second transistor and the fourth transistor, and the gain fluctuation and power consumption fluctuation of the amplifier can be reduced.

Specifically, since the channel of the first transistor is in a strong inversion state and the channel of the second transistor is in a weak inversion state, the first transistor can be used to amplify the first signal, and the second transistor can be used to output the first transistor. The signal is nonlinearly compensated; since the channel of the third transistor is in a strong inversion state and the channel of the fourth transistor is in a weak inversion state, the third transistor can be used to amplify the second signal, and the fourth transistor can be used to The output signal of the transistor performs nonlinear compensation.

In a possible design, the closed-loop feedback circuit includes a first differential amplifier circuit, a second differential amplifier circuit, a third differential amplifier circuit, and a fourth differential amplifier circuit; among them, the first differential amplifier circuit and the third differential amplifier circuit The DC bias is generated by the second current source; the DC bias of the second differential amplifier circuit and the fourth differential amplifier circuit is the output voltage of the closed loop feedback circuit.

Further, the gain coefficient of the third differential amplifier circuit may be 1/m of the gain coefficient of the first differential amplifier circuit, and the AC input voltage of the third differential amplifier circuit may be m times the AC input voltage of the first differential amplifier circuit, m>1; the gain coefficient of the fourth differential amplifier circuit can be 1/m of the gain coefficient of the second differential amplifier circuit, and the AC input voltage of the fourth differential amplifier circuit can be m times the AC input voltage of the second differential amplifier circuit .

With the above solution, the first differential amplifier circuit and the second differential amplifier circuit can be constructed as a differential amplifier circuit with a small input signal and a large gain coefficient, and the third differential amplifier circuit and the fourth differential amplifier circuit can be constructed as a large input signal, small Differential amplifier circuit with gain coefficient.

In a possible design, the closed-loop feedback circuit further includes: an error amplifier for combining the output signal of the first differential amplifier circuit and the second differential amplifier circuit, and the third differential amplifier circuit and the fourth differential amplifier circuit. The error of the output signal after the circuit is compared, and the second voltage is output.

Using the above solution, the output signal of the differential amplifier circuit with small input signal and large gain coefficient can be compared with the output signal of the differential amplifier circuit with large input signal and small gain coefficient. When the two output signals are approximately the same, use The non-linear compensation transistor can compensate the non-linearity of the transistor that it compensates. Therefore, the gate bias voltage that meets the design requirements can be obtained through the above solution.

In a possible design, the closed loop feedback circuit further includes: a first transimpedance amplifier, the positive output terminal of the first differential amplifier circuit, and the positive output terminal of the second differential amplifier circuit are coupled to the negative input terminal of the first transimpedance amplifier , The negative output terminal of the first differential amplifier circuit and the negative output terminal of the second differential amplifier circuit are coupled to the positive input terminal of the first transimpedance amplifier; the second transimpedance amplifier, the positive output terminal of the third differential amplifier circuit and the fourth The positive output terminal of the differential amplifier circuit is coupled to the negative input terminal of the second transimpedance amplifier, and the negative output terminal of the third differential amplifier circuit and the negative output terminal of the fourth differential amplifier circuit are coupled to the positive input terminal of the second transimpedance amplifier; The amplification factor of the second transimpedance amplifier is the same as the amplification factor of the first transimpedance amplifier; by mistake, the positive output terminal of the first transimpedance amplifier and the positive output terminal of the second transimpedance amplifier are coupled to the negative input terminal of the error amplifier, The negative output terminal of the first transimpedance amplifier and the negative output terminal of the second transimpedance amplifier are coupled to the positive input terminal of the error amplifier.

With the above solution, the DC bias of the first differential amplifier circuit and the third differential amplifier circuit is provided by the second current source; the DC bias of the second differential amplifier circuit and the fourth differential amplifier circuit is the output voltage of the closed loop feedback circuit. Therefore, the second differential amplifier circuit can perform nonlinear compensation on the first differential amplifier circuit, and the fourth differential amplifier circuit can perform nonlinear compensation on the third differential amplifier circuit. The DC bias of the second differential amplifier circuit and the fourth differential amplifier circuit found through feedback can be used as the DC bias of the second transistor and the fourth transistor in the amplifier, so that the second transistor can perform the output signal of the first transistor. Non-linear compensation, and enables the fourth transistor to perform non-linear compensation on the output signal of the third transistor.

Further, the first differential amplifier circuit includes at least one fifth transistor and at least one sixth transistor, the gate of the fifth transistor is coupled to the positive input terminal of the first differential amplifier circuit, and the gate of the sixth transistor is coupled to the first differential amplifier. The negative input terminal of the circuit is coupled, the number of the fifth transistor is obtained by reducing the number of the first transistor in the amplifying device by the first ratio, and the number of the sixth transistor is obtained by reducing the number of the third transistor in the amplifying device by the first ratio The second differential amplifier circuit includes at least one seventh transistor and at least one eighth transistor. The gate of the seventh transistor is coupled to the positive input terminal of the second differential amplifier circuit, and the gate of the eighth transistor is coupled to the second differential amplifier. The negative input terminal of the circuit is coupled, the number of the seventh transistor is obtained by reducing the number of the second transistor in the amplifying device by the first ratio, and the number of the eighth transistor is obtained by reducing the number of the fourth transistor in the amplifying device by the first ratio The third differential amplifier circuit includes at least one ninth transistor and at least one tenth transistor. The gate of the ninth transistor is coupled to the positive input terminal of the third differential amplifier circuit, and the gate of the tenth transistor is coupled to the third differential amplifier. The negative input terminal of the circuit is coupled. The number of the ninth transistor is obtained by reducing the number of the first transistor in the amplifying device by the second ratio, and the number of the tenth transistor is obtained by reducing the number of the third transistor in the amplifying device by the second ratio. After obtaining; the fourth differential amplifier circuit includes at least one eleventh transistor and at least one twelfth transistor, the gate of the eleventh transistor is coupled to the positive input of the fourth differential amplifier circuit, and the gate of the twelfth transistor is coupled to The negative input of the fourth differential amplifier circuit is coupled, the number of the eleventh transistor is obtained by reducing the number of the second transistor in the amplifying device by the second ratio, and the number of the twelfth transistor is obtained by reducing the number of the fourth transistor in the amplifying device The quantity is obtained after the second scale is reduced.

With the above solution, the first differential amplifying circuit, the second differential amplifying circuit, the third differential amplifying circuit, and the fourth differential amplifying circuit are all formed by reducing the number of transistors in the amplifying device to a certain extent, which can reduce the power of the closed-loop feedback circuit. Therefore, the power consumption of the amplifier is mainly used to amplify the input signal, and only a small power consumption is used to determine the gate bias voltage of the second transistor and the fourth transistor to compensate for the nonlinearity of the output signal.

In addition, the closed-loop feedback circuit may further include: a second current source for providing a DC bias for the first differential amplifier circuit and the third differential amplifier circuit; a buffer for the second differential amplifier circuit and the fourth differential amplifier circuit Provides a DC bias, the input of the buffer is coupled to the output of the closed loop feedback circuit; the first resistor, the second resistor, the third resistor, and the fourth resistor are connected in series in sequence; the first resistor is coupled to the first power supply and the fourth resistor Coupled to ground, the second resistor and the third resistor are coupled to the second current source; the resistance ratio of the first resistance to the second resistance is m-1, and the resistance ratio of the fourth resistance to the third resistance is m-1 , The second resistor and the third resistor have the same resistance; where the connection between the first resistor and the first power supply is coupled to the positive input end of the third differential amplifier circuit, and the coupling ground end of the fourth resistor is coupled to the third differential amplifier circuit The connection of the first resistor and the second resistor is coupled to the positive input of the first differential amplifier circuit, and the connection of the third resistor and the fourth resistor is coupled to the negative input of the first differential amplifier circuit; The fifth resistor, the sixth resistor, the seventh resistor, and the eighth resistor are connected in series in sequence; the fifth resistor is coupled to the second power source, the eighth resistor is coupled to the ground, and the sixth resistor and the seventh resistor are coupled to the output terminal of the buffer; The resistance ratio of the fifth resistor to the sixth resistor is m-1, the resistance ratio of the eighth resistor to the seventh resistor is m-1, and the resistance of the sixth resistor and the seventh resistor are the same; among them, the fifth resistor The connection with the second power supply is coupled with the positive input end of the fourth differential amplifier circuit, the coupling ground end of the eighth resistor is coupled with the negative input end of the fourth differential amplifier circuit; the connection between the fifth resistor and the sixth resistor is coupled with the first The positive input ends of the two differential amplifier circuits are coupled, and the junction of the seventh resistor and the eighth resistor is coupled with the negative input end of the second differential amplifier circuit.

By adopting the above implementation scheme, the AC input and DC bias can be provided for the four differential amplifier circuits through the second current source, the buffer and the multiple resistors. The buffer can save and output the output voltage of the closed-loop feedback circuit, so that the DC bias of the second differential amplifier circuit and the fourth differential amplifier circuit is a stable voltage value, and will not fluctuate with current changes.

Wherein, the second current source can be obtained by mirror biasing of the first current source. For example, the second current source may include a first current source, an N-type MOS tube (i.e. NMOS) and a P-type MOS tube (i.e. PMOS). The first current source is output after passing through NMOS and PMOS in turn, as the first differential amplifier circuit and The DC bias of the third differential amplifier circuit.

In a possible design, the gate of the first transistor is used to receive the first signal, the source of the first transistor is coupled to ground, the drain of the first transistor is coupled to the load of the amplifying device; the source of the second transistor is coupled Ground, the drain of the second transistor is coupled to the load of the amplifying device; the gate of the third transistor is used to receive the second signal, the source of the third transistor is coupled to ground, and the drain of the third transistor is coupled to the load of the amplifying device; The source of the fourth transistor is coupled to ground, and the drain of the fourth transistor is coupled to the load of the amplifying device.

With the above solution, a specific connection manner of the first transistor, the second transistor, the third transistor and the fourth transistor is provided.

Description of the drawings

FIG. 1 is a schematic diagram of the structure of an amplifier provided in the prior art;

Fig. 2 is a schematic structural diagram of a feedback circuit provided in the prior art;

3 is a schematic structural diagram of an amplifier provided by an embodiment of the application;

FIG. 4 is a schematic structural diagram of another amplifier provided by an embodiment of the application;

FIG. 5 is a schematic structural diagram of an amplification device provided by an embodiment of the application;

FIG. 6 is a schematic structural diagram of a series resistor provided by an embodiment of the application;

FIG. 7 is a schematic structural diagram of another series resistor provided by an embodiment of the application;

8 is a schematic structural diagram of a closed-loop feedback circuit provided by an embodiment of the application;

9 is a schematic structural diagram of another closed-loop feedback circuit provided by an embodiment of the application;

FIG. 10 is a schematic diagram of a variation curve of the total gain of an amplifier provided by an embodiment of the application.

Detailed ways

As described in the background art, with the development of broadband wireless communications, RF front-end amplifiers need to take into account multiple indicators such as gain, noise, linearity, and power consumption.

In order to improve the linearity of the amplifier, the prior art usually uses the feedback circuit shown in FIG. 2 to provide bias for the active transistors in the amplifier shown in FIG. 1. Although the feedback circuit shown in Figure 2 can improve the linearity of the amplifier, it will cause the amplifier's gain to fluctuate greatly, that is, it is difficult to balance the amplifier's gain, power consumption, and linearity indicators.

The embodiments of the present application provide an amplifier and an amplifying device, which are used to improve the linearity of the amplifier while reducing fluctuations in the gain and power consumption of the amplifier.

The embodiments of the present application will be described in further detail below in conjunction with the accompanying drawings.

It should be noted that in the embodiments of the present application, multiple refers to two or more. In addition, it should be understood that in the description of this application, words such as “first” and “second” are only used for the purpose of distinguishing description, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating Or imply the order. The "coupling" mentioned in this application refers to electrical connection, which specifically may include direct connection or indirect connection.

Referring to FIG. 3, an amplifier 300 provided in an embodiment of this application. The amplifier 300 includes at least one first gain circuit 301 for amplifying a first signal and at least one second gain circuit 302 for amplifying a second signal. Each first gain circuit 301 includes a first transistor 301a and a second transistor 301b; the channel of the first transistor 301a is in a strong inversion state, and the channel of the second transistor 301b is in a weak inversion state. State; each second gain circuit 302 includes a third transistor 302a and a fourth transistor 302b; the channel of the third transistor 302a is in a strong inversion state, and the channel of the fourth transistor 302b is in a weak inversion state. Among them, the first signal and the second signal constitute a differential signal, the gate bias voltages of the first transistor 301a and the third transistor 302a are the first voltage, and the gate bias voltages of the second transistor 301b and the fourth transistor 302b are the first voltage. Two voltage.

Among them, the specific meaning of the strong inversion state can be: the gate-source voltage VGS of the transistor is much larger than the threshold voltage VT of the transistor, an inversion layer (channel) is formed under the gate oxide film, and the transistor drain -There is current activity between the sources. This state is called a strong inversion state. The specific meaning of the weak inversion state can be: the gate-source voltage VGS of the transistor is less than the threshold voltage VT of the transistor and the drain still has a small current activity. This state is called the weak inversion state.

Specifically, in the amplifier 300, since the channel of the first transistor 301a is in a strong inversion state and the channel of the second transistor 301b is in a weak inversion state, the first transistor 301a can be used to amplify the first signal and the second transistor 301b can be used for nonlinear compensation of the output signal of the first transistor 301a; since the channel of the third transistor 302a is in a strong inversion state and the channel of the fourth transistor 302b is in a weak inversion state, the third transistor 302a can be used for Amplifying the second signal, the fourth transistor 302b can be used to perform nonlinear compensation on the output signal of the third transistor 302a.

In the amplifier 300 shown in FIG. 3, the first signal and the second signal can be amplified by the first transistor 301a and the third transistor 302a respectively, and the first transistor can be amplified by the second transistor 301b and the fourth transistor 302b respectively. The output signal of 301a and the output signal of the third transistor 302a perform nonlinear compensation to improve the linearity of the amplifier 300.

In addition, in the amplifier 300, the channels of the second transistor 301b and the fourth transistor 302b are in a weak inversion state, and their gain is small and the power consumption is small. Therefore, the gain and power consumption of the amplifier 300 are mainly determined by the first transistor 301a and the third transistor 302a; the second transistor 301b and the fourth transistor 302b are responsible for canceling the nonlinearity, and only contribute a very low proportion of power consumption and gain. Therefore, in the amplifier 300, the linearity of the amplifier 300 can be improved through the second transistor 301b and the fourth transistor 302b, and the gain fluctuation and power consumption fluctuation of the amplifier 300 can be reduced.

In specific implementation, in the amplifier 300, the specific connection mode of the first transistor 301a, the second transistor 301b, the third transistor 302a and the fourth transistor 302b may be: the gate of the first transistor 301a is used to receive the first signal, The source of the transistor 301a is coupled to ground, the drain of the first transistor 301a is coupled to the load of the amplifier 300; the source of the second transistor 301b is coupled to ground, and the drain of the second transistor 301b is coupled to the load of the amplifier 300; the third transistor 302a The gate of the third transistor 302a is used to receive the second signal, the source of the third transistor 302a is coupled to ground, the drain of the third transistor 302a is coupled to the load of the amplifier 300; the source of the fourth transistor 302b is coupled to ground, and the drain of the fourth transistor 302b The pole is coupled to the load of the amplifier 300.

Wherein, the source of the first transistor 301a is coupled to ground, which may mean that the first transistor 301a is directly grounded, or the first transistor 301a is grounded through an inductor, a capacitor, or other devices. In addition, in other examples of the embodiments of the present application, the meaning of coupling to ground is the same, which will not be explained in detail later.

It should be noted that in the description of the embodiments of the present application, the transistor adopts a CMOS process as an example for illustration. In practical applications, the transistor can also use other processes. When the transistor adopts other processes, the names of the various ports of the transistor will be different, but the functions are basically the same. Exemplarily, when the transistor is a bipolar junction transistor (BJT), the base in BJT is equivalent to the gate in CMOS; the collector in BJT is equivalent to the drain in CMOS; the emitter in BJT The pole is equivalent to the source in CMOS. Therefore, the amplifier based on the CMOS tube in this application can be equivalent to the amplifier based on the BJT.

Since the implementation methods and principles of the transistors using other processes are similar to those of the CMOS process, the embodiments of the present application take the transistors using the CMOS process as an example for illustration, and the specific implementation methods when using other processes are not described in detail.

In addition, in each example of this application, the transistors adopt the method of gate input signal and source coupling grounding. In practical applications, the transistor can also adopt the method of source input signal and gate coupling grounding. This is not specifically limited.

Exemplarily, when each transistor in the amplifier 300 adopts the above-mentioned connection mode and the amplifier 300 includes a parallel resonant load, a possible schematic diagram of the structure of the amplifier 300 may be as shown in FIG. 4.

In the amplifier 300 shown in FIG. 4, the transistor whose gate is coupled to the positive input terminal Vip can be regarded as the first transistor 301a, and the transistor whose gate is coupled to the negative input terminal Vin can be regarded as the third transistor 302a, and the first transistor The transistor connected to 301a and biased by Vgs_Aux can be regarded as the second transistor 301b, and the transistor connected to the third transistor 302a and biased by Vgs_Aux can be regarded as the fourth transistor 302b. The RLC network forms an equivalent parallel resonant load, Vop is the positive output terminal, and Von is the negative output terminal. The first transistor 301a and the third transistor 302a respectively amplify the differential signal output from the positive input terminal and the negative input terminal, which can be collectively referred to as the "main pipe"; the second transistor 301b pair and the fourth transistor 302b respectively affect the first transistor 301a and the second transistor 302b. The output signal of the three transistors 302a performs nonlinear compensation, which can be collectively referred to as an "auxiliary compensation tube". The interconnected "main pipe" and "auxiliary compensation pipe" can be called a "Gm unit".

Based on the same inventive concept, an embodiment of the present application also provides an amplifying device. Referring to FIG. 5, the amplifying device 500 includes an amplifier 501 and a closed loop feedback circuit 502. The amplifier 501 includes at least one first gain circuit for amplifying the first signal and at least one second gain circuit for amplifying the second signal.

Wherein, each first gain circuit includes a first transistor and a second transistor; the channel of the first transistor is in a strong inversion state, and the channel of the second transistor is in a weak inversion state; each second gain circuit includes a third Transistor and fourth transistor; the channel of the third transistor is in a strong inversion state, and the channel of the fourth transistor is in a weak inversion state; the first signal and the second signal constitute a differential signal; the gates of the first transistor and the third transistor The pole bias voltage is the first voltage generated by the first current source, and the gate bias voltages of the second transistor and the fourth transistor are the second voltage; the closed loop feedback circuit is used to generate the second voltage.

Specifically, since the channel of the first transistor is in a strong inversion state and the channel of the second transistor is in a weak inversion state, the first transistor can be used to amplify the first signal, and the second transistor can be used to output the first transistor. The signal is nonlinearly compensated; since the channel of the third transistor is in a strong inversion state and the channel of the fourth transistor is in a weak inversion state, the third transistor can be used to amplify the second signal, and the fourth transistor can be used to The output signal of the transistor performs nonlinear compensation.

In the amplifying device 500, the specific implementation of the amplifier 501 can be referred to the related description in the amplifier 300 shown in FIG. 3, which will not be repeated here.

In the amplifying device 500 shown in FIG. 5, the first signal and the second signal can be amplified by the first transistor and the third transistor, respectively. Since the first transistor and the third transistor are biased by the first current source, it is difficult to ensure that the first transistor and the third transistor can be set at the bias point with the smallest n-th order nonlinearity. In the embodiment of the present application, the second transistor and the fourth transistor can be used to perform nonlinear compensation on the output signal of the first transistor and the output signal of the third transistor, so that the linearity of the amplifying device 500 can be improved.

In addition, the first transistor and the third transistor are biased by the first current source. This bias mode can be regarded as a fixed bias, and its bias voltage fluctuation is small, so the gain fluctuations of the first transistor and the third transistor are combined. The power consumption fluctuation is also small. When the second transistor and the fourth transistor are biased by the closed-loop feedback circuit 502, although the bias provided by the closed-loop feedback circuit 502 will cause fluctuations in gain and power consumption, the second and fourth transistors are used for nonlinear compensation. The transistor has a small gain and low power consumption. Therefore, even if gain fluctuations and power consumption fluctuations occur, the value of the fluctuations will hardly have a large impact on the first gain circuit and the second gain circuit. Therefore, in the amplifying device 500, the gain fluctuation and power consumption fluctuation of the first gain circuit and the second gain circuit are small.

To sum up, in the amplifying device 500, the gain and power consumption are mainly determined by the first transistor and the third transistor; the second transistor and the fourth transistor are responsible for canceling the nonlinearity, and only contribute a very low proportion of power consumption and gain. Therefore, in the amplifying device 500, the linearity of the amplifier can be improved by the second transistor and the fourth transistor, and the gain fluctuation and power consumption fluctuation of the amplifier can be reduced.

In specific implementation, in the amplifying device 500, the specific connection mode of the first transistor, the second transistor, the third transistor, and the fourth transistor may be: the gate of the first transistor is used to receive the first signal, and the source of the first transistor Coupled to ground, the drain of the first transistor is coupled to the load of the amplifying device 500; the source of the second transistor is coupled to ground, and the drain of the second transistor is coupled to the load of the amplifying device 500; the gate of the third transistor is used to receive the first For two signals, the source of the third transistor is coupled to the ground, the drain of the third transistor is coupled to the load of the amplifying device 500; the source of the fourth transistor is coupled to ground, and the drain of the fourth transistor is coupled to the load of the amplifying device 500.

In a possible implementation manner, the amplifying device 500 may further include a parallel resonant load, and the parallel resonant load may be regarded as an equivalent load of the amplifying device 300. The input terminal of the parallel resonant load is respectively coupled with the output terminal of the first gain circuit and the output terminal of the second gain circuit.

Among them, the parallel resonant load can be an output matching network, or a device such as a balun.

In specific implementation, the closed-loop feedback circuit 302 may include: a first differential amplifier circuit, a second differential amplifier circuit, a third differential amplifier circuit, and a fourth differential amplifier circuit, a first transimpedance amplifier, a second transimpedance amplifier, and error amplification. Wherein, the DC bias of the first differential amplifier circuit and the third differential amplifier circuit is provided by the second current source; the DC bias of the second differential amplifier circuit and the fourth differential amplifier circuit is the output voltage of the closed loop feedback circuit.

Further, the gain coefficient of the third differential amplifier circuit is 1/m of the gain coefficient of the first differential amplifier circuit, and the AC input voltage of the third differential amplifier circuit is m times the AC input voltage of the first differential amplifier circuit, m> 1; The gain coefficient of the fourth differential amplifier circuit is 1/m of the gain coefficient of the second differential amplifier circuit, and the AC input voltage of the fourth differential amplifier circuit is m times the AC input voltage of the second differential amplifier circuit.

It is not difficult to see that with the above solution, the first differential amplifier circuit and the second differential amplifier circuit can be constructed as a differential amplifier circuit with a small input signal and a large gain coefficient, and the third differential amplifier circuit and the fourth differential amplifier circuit can be constructed as a large Input signal, differential amplifier circuit with small gain coefficient.

In addition, the closed loop feedback circuit 502 may also include an error amplifier. The error amplifier is used to compare errors between the combined output signal of the first differential amplifier circuit and the second differential amplifier circuit and the combined output signal of the third differential amplifier circuit and the fourth differential amplifier circuit, and output the second voltage.

The error amplifier can compare the output signal of a differential amplifier circuit with a small input signal and a large gain coefficient with the output signal of a differential amplifier circuit with a large input signal and small gain coefficient. When the two output signals are approximately the same, it is used The non-linear compensation transistor can compensate for the non-linearity of the transistor it compensates, so the gate bias voltage that meets the design requirements can be obtained through the above solution.

Further, the closed-loop feedback circuit 502 may also include a first transimpedance amplifier and a second transimpedance amplifier. Wherein, the positive output terminal of the first differential amplifier circuit and the positive output terminal of the second differential amplifier circuit are coupled to the negative input terminal of the first transimpedance amplifier, the negative output terminal of the first differential amplifier circuit and the negative output terminal of the second differential amplifier circuit The output terminal is coupled to the positive input terminal of the first transimpedance amplifier; the positive output terminal of the third differential amplifier circuit and the positive output terminal of the fourth differential amplifier circuit are coupled to the negative input terminal of the second transimpedance amplifier, and the third differential amplifier circuit The negative output terminal of and the negative output terminal of the fourth differential amplifier circuit are coupled to the positive input terminal of the second transimpedance amplifier; the gain coefficient of the second transimpedance amplifier is the same as that of the first transimpedance amplifier. The positive output terminal of the first transimpedance amplifier and the positive output terminal of the second transimpedance amplifier are coupled to the negative input terminal of the error amplifier, and the negative output terminal of the first transimpedance amplifier and the negative output terminal of the second transimpedance amplifier are coupled to the error The positive input terminal of the amplifier; the output terminal of the error amplifier is used as the output terminal of the closed loop feedback circuit 502.

Then, in a possible example, the closed-loop feedback circuit 502 may include a first differential amplifier circuit, a second differential amplifier circuit, a third differential amplifier circuit, a fourth differential amplifier circuit, a first transimpedance amplifier, and a second transimpedance amplifier. Amplifier and error amplifier.

Assuming that the gain factor of the first differential amplifier circuit is A, the AC input voltage of the positive input terminal of the first differential amplifier circuit is a1, and the AC input voltage of the negative input terminal of the first differential amplifier circuit is a2; the gain factor of the second differential amplifier circuit Is B, the AC input voltage of the positive input terminal of the second differential amplifier circuit is b1, and the AC input voltage of the negative input terminal of the second differential amplifier circuit is b1. Then, the AC input voltage of the third differential amplifier circuit is m*a1 and m*a2, and the gain coefficient is A*1/m; the AC input voltage of the fourth differential amplifier circuit is m*b1 and m*b2, and the gain coefficient is B*1/m. Then, for the first transimpedance amplifier coupled with the first differential amplifier circuit and the second differential amplifier circuit, the input of its positive input terminal is a1*A+b1*B, and the input of its negative input terminal is a2*A+b2* B; For the second transimpedance amplifier coupled with the third differential amplifier circuit and the fourth differential amplifier circuit, the input of the positive input terminal is m*a1*A*1/m+m*b1*B*1/m=a1 *A+b1*B, the input of its negative input terminal is m*a2*A*1/m+m*b2*B*1/m=a2*A+b2*B. Since the gain coefficients of the first transimpedance amplifier and the second transimpedance amplifier are the same, the linearity of the first differential amplifier circuit, the second differential amplifier circuit, the third differential amplifier circuit, and the fourth differential amplifier circuit is relatively high. , The output of the first transimpedance amplifier and the second transimpedance amplifier should be the same.

In the above implementation, the DC bias of the first differential amplifier circuit and the third differential amplifier circuit is provided by the second current source; the DC bias of the second differential amplifier circuit and the fourth differential amplifier circuit is the output voltage of the closed loop feedback circuit . Therefore, the second differential amplifier circuit can perform nonlinear compensation on the first differential amplifier circuit, and the fourth differential amplifier circuit can perform nonlinear compensation on the third differential amplifier circuit. The DC bias of the second differential amplifier circuit and the fourth differential amplifier circuit found by feedback can be used as the DC bias of the second transistor and the fourth transistor in the amplifying device 500, so that the second transistor can output to the first transistor The signal performs nonlinear compensation, and the fourth transistor can perform nonlinear compensation on the output signal of the third transistor.

In specific implementation, the first differential amplifier circuit may include at least one fifth transistor and at least one sixth transistor, the gate of the fifth transistor is coupled to the positive input terminal of the first differential amplifier circuit, and the gate of the sixth transistor is connected to the first The negative input terminal of the differential amplifier circuit is coupled, the number of the fifth transistor is obtained by reducing the number of the first transistor in the amplifying device 500 by a first ratio, and the number of the sixth transistor is obtained by reducing the number of the third transistor in the amplifying device 500 to Obtained after the first scale is reduced.

The second differential amplifier circuit may include at least one seventh transistor and at least one eighth transistor, the gate of the seventh transistor is coupled to the positive input terminal of the second differential amplifier circuit, and the gate of the eighth transistor is connected to the second differential amplifier circuit. The negative input terminal is coupled, the number of the seventh transistor is obtained by reducing the number of the second transistor in the amplifying device 500 by the first ratio, and the number of the eighth transistor is obtained by reducing the number of the fourth transistor in the amplifying device 500 by the first ratio After getting.

The third differential amplifier circuit may include at least one ninth transistor and at least one tenth transistor. The gate of the ninth transistor is coupled to the positive input terminal of the third differential amplifier circuit, and the gate of the tenth transistor is connected to the third differential amplifier circuit. The negative input is coupled, the number of the ninth transistor is obtained by reducing the number of the first transistor in the amplifying device 500 by the second ratio, and the number of the tenth transistor is obtained by reducing the number of the third transistor in the amplifying device 500 by the second ratio After getting. The first ratio is m times the second ratio.

The fourth differential amplifier circuit may include at least one eleventh transistor and at least one twelfth transistor, the gate of the eleventh transistor is coupled to the positive input terminal of the fourth differential amplifier circuit, and the gate of the twelfth transistor is coupled to the fourth The negative input terminal of the differential amplifier circuit is coupled, the number of the eleventh transistor is obtained by reducing the number of the second transistor in the amplifying device 500 by the second ratio, and the number of the twelfth transistor is obtained by reducing the number of the fourth transistor in the amplifying device 500 The quantity is obtained after the second scale is reduced.

In other words, both the first differential amplifier circuit and the third differential amplifier circuit can be formed by removing the second transistor and the fourth transistor in the amplifier 501, and reducing the number of the first transistor and the third transistor. Both a differential amplifying circuit and a third differential amplifying circuit can be used to simulate the working state of the transistor used to amplify the input signal in the amplifier 501, the difference is only that the gain coefficients of the first differential amplifying circuit and the second differential amplifying circuit are different; Both the second differential amplifier circuit and the fourth differential amplifier circuit can be formed by removing the first transistor and the third transistor in the amplifier 501 and reducing the number of the second transistor and the fourth transistor to a certain extent. The second differential amplifier circuit Both the fourth differential amplifier circuit and the fourth differential amplifier circuit can be used to simulate the working state of the transistor used for nonlinear compensation in the amplifier 501.

By reducing the number of transistors in the amplifier 501 to a certain extent to form four differential amplifier circuits, the power consumption of the closed-loop feedback circuit 502 can be reduced, so that the power consumption of the amplifier device 500 is mainly used for amplifying the input signal, and only a smaller The power consumption determines the bias of the second transistor and the fourth transistor to compensate for the non-linearity of the output signal.

The fifth transistor and the first transistor may have the same specifications, the sixth transistor and the third transistor may have the same specifications; the seventh transistor and the second transistor may have the same specifications, and the eighth transistor and the fourth transistor may have the same specifications; The ninth transistor and the first transistor may have the same specifications, the tenth transistor and the third transistor may have the same specifications; the eleventh transistor and the second transistor may have the same specifications, and the twelfth transistor and the fourth transistor may have the same specifications.

In addition, the closed-loop feedback circuit 502 may also include: a second current source for providing a DC bias for the first differential amplifier circuit and the third differential amplifier circuit; a buffer for the second differential amplifier circuit and the fourth differential amplifier circuit The circuit provides a DC bias, the input of the buffer is coupled with the output of the closed loop feedback circuit 502; the first resistor, the second resistor, the third resistor, and the fourth resistor are connected in series; the fifth resistor and the sixth resistor are connected in series , The seventh resistor and the eighth resistor.

Wherein, the second current source can be obtained by mirror biasing of the first current source. The buffer can store and output the output voltage of the closed-loop feedback circuit 502, so that the DC bias of the second differential amplifying circuit and the fourth differential amplifying circuit is a stable voltage value, and will not fluctuate with current changes.

Specifically, the specific connection manner of the first resistor to the fourth resistor in series may be: the first resistor is coupled to the first power source, the fourth resistor is coupled to the ground, and the second resistor and the third resistor are coupled to the second current source; The resistance ratio of the resistance to the second resistance is m-1, the resistance ratio of the fourth resistance to the third resistance is m-1, and the resistances of the second resistance and the third resistance are the same; where the first resistance is equal to The connection of the first power supply is coupled with the positive input terminal of the third differential amplifier circuit, and the coupling ground terminal of the fourth resistor is coupled with the negative input terminal of the third differential amplifier circuit; the connection between the first resistor and the second resistor is coupled with the first The positive input terminal of the differential amplifier circuit is coupled, and the connection of the third resistor and the fourth resistor is coupled with the negative input terminal of the first differential amplifier circuit. Wherein, the first power source may be an alternating current source.

Specifically, the specific connection manner of the fifth resistor to the eighth resistor in series may be: the fifth resistor is coupled to the second power source, the eighth resistor is coupled to the ground, and the sixth resistor and the seventh resistor are coupled to the output terminal of the buffer; The resistance ratio of the fifth resistor to the sixth resistor is m-1, the resistance ratio of the eighth resistor to the seventh resistor is m-1, and the resistance values of the sixth resistor and the seventh resistor are the same; among them, the fifth resistor The connection with the second power supply is coupled with the positive input end of the fourth differential amplifier circuit, the coupling ground end of the eighth resistor is coupled with the negative input end of the fourth differential amplifier circuit; the connection between the fifth resistor and the sixth resistor is coupled with the first The positive input ends of the two differential amplifier circuits are coupled, and the junction of the seventh resistor and the eighth resistor is coupled with the negative input end of the second differential amplifier circuit. Wherein, the second power source may be an alternating current source.

By adopting the above implementation scheme, the AC input and DC bias can be provided for the four differential amplifier circuits through the second current source, the buffer and the multiple resistors.

Exemplarily, the first resistor, the second resistor, the third resistor, and the fourth resistor connected in series in sequence and the output of each node therein may be as shown in FIG. 6. It can be seen from FIG. 6 that the DC bias of the first differential amplifier circuit and the third differential amplifier circuit are both provided by the second current source. Since the resistance ratio of the first resistance to the second resistance is m-1, the resistance ratio of the fourth resistance to the third resistance is m-1, and the resistances of the second resistance and the third resistance are the same, then, The input of the positive input terminal of the three differential amplifier circuit is m times the input of the positive input terminal of the first differential amplifier circuit, and the input of the negative input terminal of the third differential amplifier circuit is m times the input of the negative input terminal of the first differential amplifier circuit. Therefore, through the four resistors in series as shown in Figure 6, it is possible to realize that "the AC input voltage of the third differential amplifier circuit is m times the AC input voltage of the first differential amplifier circuit, the first differential amplifier circuit and the third differential amplifier circuit The DC bias is provided by the second current source".

Exemplarily, the fifth resistor, the sixth resistor, the seventh resistor, and the eighth resistor connected in series in sequence and the output of each node therein may be as shown in FIG. 7. In FIG. 7, the input terminal of the buffer is coupled with the output terminal of the closed loop feedback circuit, so the DC bias of the second differential amplifier circuit and the fourth differential amplifier circuit is the output voltage of the closed loop feedback circuit 502. Since the resistance ratio of the fifth resistor to the sixth resistor is m-1, the resistance ratio of the eighth resistor to the seventh resistor is m-1, and the resistance values of the sixth and seventh resistors are the same, then, The input of the positive input terminal of the four differential amplifier circuit is m times the input of the positive input terminal of the second differential amplifier circuit, and the input of the negative input terminal of the fourth differential amplifier circuit is m times the input of the negative input terminal of the second differential amplifier circuit. Therefore, through the four resistors in series as shown in Figure 7, it is possible to realize that "the AC input voltage of the fourth differential amplifier circuit is m times the AC input voltage of the second differential amplifier circuit, the second differential amplifier circuit and the fourth differential amplifier circuit The DC bias is the output voltage of the closed-loop feedback circuit".

In combination with the above introduction to the closed-loop feedback circuit 502, a possible structural schematic diagram of the closed-loop feedback circuit 502 may be shown in FIG. 8. In FIG. 8, the closed loop feedback circuit 502 includes a first differential amplifier circuit, a second differential amplifier circuit, a third differential amplifier circuit, a fourth differential amplifier circuit, a first transimpedance amplifier, a second transimpedance amplifier, an error amplifier, and a second Two current sources, buffers, and series resistors (first resistor, second resistor, third resistor, and fourth resistor connected in series, and fifth resistor, sixth resistor, seventh resistor, and eighth resistor connected in series). The closed-loop feedback circuit 502 shown in FIG. 8 can be used to provide a bias for the second transistor and the fourth transistor in the amplifying device 500 shown in FIG. 5, so that the second transistor performs nonlinear compensation on the first transistor and the fourth transistor Perform nonlinear compensation on the third transistor.

Exemplarily, for the amplifier shown in FIG. 4, the closed loop feedback circuit shown in FIG. 9 can be used to provide Vgs_Aux (equivalent to the bias voltage of the second transistor and the fourth transistor) for the amplifier. That is, the closed loop feedback circuit shown in FIG. 9 is connected to the Vgs_Aux terminal in FIG. 4. The amplifier shown in FIG. 4 and the closed loop feedback circuit shown in FIG. 9 can form an amplifying device, which can be regarded as a specific example of the amplifying device 500 shown in FIG. 5.

In Figure 9, the Main Gm in the upper part (marked with 4x) is equivalent to removing the "auxiliary compensation tube" in Figure 4, and the "main pipe" is formed by reducing the number according to the ratio of 4/n, and the Aux Gm in the upper half It is equivalent to removing the "main pipe" in Figure 4 and the "auxiliary compensation pipe" is formed by reducing the number according to the ratio of 4/n; Main Gm in the lower half (marked by 1x) is equivalent to removing the "auxiliary compensation pipe" in Figure 4 "Remove," the "main pipe" is formed after the number is reduced according to the ratio of 1/n. The Aux Gm in the lower half is equivalent to the removal of the "main pipe" in Figure 4 and the "auxiliary compensation pipe" is formed after the number is reduced according to the ratio of 1/n. Illustratively, n may be 100. In other words, the Gm unit in FIG. 9 can be obtained by duplicating the "main pipe" and the "auxiliary compensation pipe" in the Gm unit in FIG. 4, respectively, with sizes 1/n and 4/n. The common mode of the main pipe (Main Gm) is biased by the conventional mirror image, and the common mode of the auxiliary compensation pipe (Aux Gm) is biased by the voltage of the closed loop feedback circuit (ie, Vgs_aux).

Through the buffer and current source in FIG. 9, differential signals of different sizes can be applied to the Gm cell in the upper half and the Gm cell in the lower half. For example, the ratio of the gain coefficient of the upper half of the Gm unit to the lower half of the Gm unit is 4:1, then the ratio of the input signal of the upper half of the Gm unit to the lower half of the Gm unit can be 1:4 . Then, the two differential output currents are converted into voltages through transimpedance amplifiers of opposite proportions. The two differential voltages are amplified by an error amplifier (EA) and used to control the state of the "auxiliary compensation tube" in Figure 4 to form a closed loop negative feedback.

Among them, the function of closed-loop negative feedback is to make the small signal path (in the upper part of Figure 9, the input signal is 1x, called the small signal path) and the large signal path (in the lower half of Figure 9, the input signal is 4x, called the small signal path) The output of the large signal path is the same, and the output of the upper and lower parts is equal to achieve the so-called "linear". At this time, the output "Vgs_Aux" voltage found by the closed-loop feedback circuit just enables the "auxiliary compensation tube" to compensate for the non-linear fluctuations of the "main pipe" and realize the "adaptive" closed-loop adjustment.

In summary, with the amplifying device 500 provided by the embodiment of the present application, since the channels of the first transistor 301a and the third transistor 302a are in a strong inversion state, the first transistor 301a and the third transistor 302a can be used to realize the Amplification of the signal and the second signal; since the channels of the second transistor 301b and the fourth transistor 302b are in a weak inversion state, the output signal and the second transistor of the first transistor 301a can be transmitted through the second transistor 301b and the fourth transistor 302b, respectively The output signal of the three-transistor 302a performs nonlinear compensation to improve the linearity of the amplifier 501.

Since the first transistor and the third transistor are biased by the first current source, this bias mode can be regarded as a fixed bias, and its bias voltage fluctuation is small, so the gain fluctuation and power of the first transistor and the third transistor The consumption fluctuation is also small. When the second transistor and the fourth transistor are biased through the closed-loop feedback circuit 502, although the bias provided by the closed-loop feedback circuit 502 will cause fluctuations in gain and power consumption, the channels of the second and fourth transistors are in weak inversion. In the state, the gain is small and the power consumption is small. Therefore, even if gain fluctuations and power consumption fluctuations occur, the value of the fluctuations will hardly have a large impact on the first gain circuit and the second gain circuit. Therefore, in the amplifying device 500, the gain fluctuation and power consumption fluctuation of the first gain circuit and the second gain circuit are small.

In summary, in the amplifying device 500 provided by the embodiment of the present application, the gain and power consumption are mainly determined by the first transistor and the third transistor; the second transistor and the fourth transistor are responsible for canceling the nonlinearity, and only contribute a very low proportion of the power. Consumption and gain. Therefore, in the amplifying device 500, the linearity of the amplifier 501 can be improved by the second transistor and the fourth transistor, and the gain fluctuation and power consumption fluctuation of the amplifier 501 can be reduced.

Exemplarily, using the amplifying device 500 provided by the embodiment of the present application, the total gain of the amplifier, the gain of the main pipe (ie the first transistor and the third transistor) and the auxiliary compensation tube (ie the second transistor and the fourth transistor) gain vary with the input signal The changes can be shown in Figure 10. It can be seen from Figure 10 that the overall gain of the amplifier has better linearity. When the input signal changes, the auxiliary compensation tube can compensate the main pipe nonlinearly, so that the total gain of the amplifier is stable with the input signal.

In particular, if the gain of the auxiliary compensation tube fluctuates due to the process, temperature, and model accuracy of each device in the closed-loop feedback circuit (for example, 50% fluctuation), since the gain of the main tube is much greater than the gain of the auxiliary compensation tube, the auxiliary compensation tube The gain fluctuation will not have a great impact on the overall gain of the amplifier. Therefore, compared with the solution provided in the prior art, the amplifying device 500 provided by the embodiment of the present application can reduce the gain and power consumption fluctuation of the amplifier.

In addition, under different temperatures and processes, before the auxiliary compensation tube is used for compensation and after the auxiliary compensation tube is used for compensation, the total gain of the amplifier and the input referred 3rd-order intercept point (IIP3) can be changed as follows: Shown in Table 1 and Table 2. Among them, before compensation refers to a situation where the amplifier does not include an auxiliary compensation tube and the main pipe is biased by a current source; after compensation refers to a situation where the amplifying device provided in the embodiment of the present application is used.

Table 1

Gm (gain)	No compensation (Gm)	After compensation (Gm)
tt 55	10.6	11.1
ss-40	11.6	11.9
ss 125	9.4	10
ff-40	12.4	12.7
ff 125	10	10.6

Table 2

IIP3	No compensation (dBm)	After compensation (dBm)
tt 55	10.2	16.7

ss-40	10.3	17.3
ss 125	11.3	17.9
ff-40	10.1	16.2
ff 125	11.2	16.6

In Table 1 and Table 2, "tt", "ss", and "ff" represent different process angles, and the following numbers represent temperature. It can be seen from Table 1 that under different processes and temperatures, the fluctuation of the total gain of the compensated amplifier can be reduced (the gain fluctuation before compensation is 9.4～12.4, and the gain fluctuation after compensation is 10～12.7); from Table 2 It can be seen that, after the amplifier is compensated under different processes and temperatures, IIP3 is significantly improved, that is, the linearity of the amplifier is improved.

In addition, it should be noted that the amplifier 300 and the amplifier 500 provided in the embodiments of the present application can be applied to a variety of terminal devices, for example, can be applied to mobile phones, tablets, virtual reality (virtual reality). , VR) terminal, augmented reality (augmented reality, AR) terminal and other terminal equipment.

Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the scope of the embodiments of the present application. In this way, if these modifications and variations of the embodiments of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these modifications and variations.

Claims (13)

1. An amplifier, characterized in that it comprises:

   At least one first gain circuit is used to amplify the first signal; each first gain circuit includes a first transistor and a second transistor; the channel of the first transistor is in a strong inversion state, and the channel of the second transistor Tao is in a weakly inverse state;

   At least one second gain circuit is used to amplify the second signal; each second gain circuit includes a third transistor and a fourth transistor; the channel of the third transistor is in a strong inversion state, and the channel of the fourth transistor The track is in a weak inversion state; the first signal and the second signal constitute a differential signal;

   Wherein, the gate bias voltages of the first transistor and the third transistor are the first voltage, and the gate bias voltages of the second transistor and the fourth transistor are the second voltage.
2. The amplifier according to claim 1, wherein the first transistor is used to amplify a first signal, and the second transistor is used to perform nonlinear compensation on the output signal of the first transistor; The transistor is used to amplify the second signal, and the fourth transistor is used to perform nonlinear compensation on the output signal of the third transistor.
3. The amplifier of claim 1 or 2, wherein the gate of the first transistor is used to receive the first signal, the source of the first transistor is coupled to ground, and the drain of the first transistor is Pole is coupled to the load of the amplifier;

   The source of the second transistor is coupled to ground, and the drain of the second transistor is coupled to the load of the amplifier;

   The gate of the third transistor is used to receive the second signal, the source of the third transistor is coupled to ground, and the drain of the third transistor is coupled to the load of the amplifier;

   The source of the fourth transistor is coupled to ground, and the drain of the fourth transistor is coupled to the load of the amplifier.
4. An amplifying device, characterized in that it comprises an amplifier and a closed-loop feedback circuit; the amplifier comprises at least one first gain circuit for amplifying a first signal and at least one second gain circuit for amplifying a second signal;

   Wherein, each first gain circuit includes a first transistor and a second transistor; the channel of the first transistor is in a strong inversion state, and the channel of the second transistor is in a weak inversion state; at least one second gain Each second gain circuit includes a third transistor and a fourth transistor; the channel of the third transistor is in a strong inversion state, and the channel of the fourth transistor is in a weak inversion state; the first signal And the second signal constitute a differential signal; wherein the gate bias voltage of the first transistor and the third transistor is a first voltage generated by a first current source, and the second transistor and the first transistor The gate bias voltage of the four transistors is the second voltage;

   The closed loop feedback circuit is used to generate the second voltage.
5. 5. The amplifying device according to claim 4, wherein the first transistor is used to amplify a first signal, and the second transistor is used to perform nonlinear compensation on the output signal of the first transistor; The three transistors are used to amplify the second signal, and the fourth transistor is used to perform nonlinear compensation on the output signal of the third transistor.
6. The amplifying device according to claim 4 or 5, wherein the closed-loop feedback circuit comprises a first differential amplifying circuit, a second differential amplifying circuit, a third differential amplifying circuit, and a fourth differential amplifying circuit;

   Wherein, the DC bias of the first differential amplifier circuit and the third differential amplifier circuit is generated by a second current source; the DC bias of the second differential amplifier circuit and the fourth differential amplifier circuit is the The output voltage of the closed loop feedback circuit.
7. The amplifying device according to claim 6, wherein the gain coefficient of the third differential amplifying circuit is 1/m of the gain coefficient of the first differential amplifying circuit, and the AC input of the third differential amplifying circuit The voltage is m times the AC input voltage of the first differential amplifier circuit, m>1;

   The gain coefficient of the fourth differential amplifying circuit is 1/m of the gain coefficient of the second differential amplifying circuit, and the AC input voltage of the fourth differential amplifying circuit is a ratio of the AC input voltage of the second differential amplifying circuit m times.
8. 8. The amplifying device according to claim 6 or 7, wherein the closed loop feedback circuit further comprises:

   Error amplifier, used to combine the output signal of the first differential amplifier circuit and the second differential amplifier circuit and the output signal of the third differential amplifier circuit and the fourth differential amplifier circuit. The errors are compared, and the second voltage is output.
9. 8. The amplifying device of claim 8, wherein the closed-loop feedback circuit further comprises:

   A first transimpedance amplifier, the positive output terminal of the first differential amplifier circuit and the positive output terminal of the second differential amplifier circuit are coupled to the negative input terminal of the first transimpedance amplifier, the first differential amplifier circuit The negative output terminal of the second differential amplifier circuit and the negative output terminal of the second differential amplifier circuit are coupled to the positive input terminal of the first transimpedance amplifier;

   The second transimpedance amplifier, the positive output terminal of the third differential amplifier circuit and the positive output terminal of the fourth differential amplifier circuit are coupled to the negative input terminal of the second transimpedance amplifier, and the third differential amplifier circuit The negative output terminal of the fourth differential amplifier circuit and the negative output terminal of the fourth differential amplifier circuit are coupled to the positive input terminal of the second transimpedance amplifier; the amplification factor of the second transimpedance amplifier and the amplification of the first transimpedance amplifier Same multiples;

   Wherein, the positive output terminal of the first transimpedance amplifier and the positive output terminal of the second transimpedance amplifier are coupled to the negative input terminal of the error amplifier, and the negative output terminal of the first transimpedance amplifier and the The negative output terminal of the second transimpedance amplifier is coupled to the positive input terminal of the error amplifier.
10. The amplifying device according to any one of claims 7-9, wherein the first differential amplifying circuit includes at least one fifth transistor and at least one sixth transistor, and the gate of the fifth transistor is connected to the The positive input terminal of the first differential amplifier circuit is coupled, the gate of the sixth transistor is coupled with the negative input terminal of the first differential amplifier circuit, and the number of the fifth transistor is determined by the first transistor in the amplifier device. The number of the sixth transistors is reduced by a first ratio, and the number of the sixth transistors is obtained by reducing the number of third transistors in the amplifying device by the first ratio;

    The second differential amplifier circuit includes at least one seventh transistor and at least one eighth transistor, the gate of the seventh transistor is coupled to the positive input terminal of the second differential amplifier circuit, and the gate of the eighth transistor Coupled with the negative input terminal of the second differential amplifier circuit, the number of the seventh transistor is obtained by reducing the number of the second transistor in the amplifying device by the first ratio, the number of the eighth transistor Obtained by reducing the number of fourth transistors in the amplifying device by the first ratio;

    The third differential amplifier circuit includes at least one ninth transistor and at least one tenth transistor, the gate of the ninth transistor is coupled to the positive input terminal of the third differential amplifier circuit, and the gate of the tenth transistor Is coupled to the negative input terminal of the third differential amplifier circuit, the number of the ninth transistor is obtained by reducing the number of the first transistor in the amplifying device by a second ratio, and the number of the tenth transistor is obtained by reducing The number of third transistors in the amplifying device is obtained after being reduced by the second ratio; the first ratio is m times the second ratio;

    The fourth differential amplifier circuit includes at least one eleventh transistor and at least one twelfth transistor. The gate of the eleventh transistor is coupled to the positive input terminal of the fourth differential amplifier circuit. The gate of the transistor is coupled to the negative input terminal of the fourth differential amplifier circuit, and the number of the eleventh transistor is obtained by reducing the number of the second transistor in the amplifying device by the second ratio. The number of the twelfth transistor is obtained by reducing the number of the fourth transistor in the amplifying device by the second ratio.
11. The amplifying device according to any one of claims 7 to 10, wherein the closed-loop feedback circuit further comprises:

    The second current source is used to provide a DC bias for the first differential amplifier circuit and the third differential amplifier circuit;

    A buffer for providing a DC bias for the second differential amplifying circuit and the fourth differential amplifying circuit, the input end of the buffer is coupled with the output end of the closed loop feedback circuit;

    The first resistor, the second resistor, the third resistor, and the fourth resistor are connected in series; the first resistor is coupled to the first power source, the fourth resistor is coupled to the ground, and the second resistor and the third resistor are connected to the The second current source is coupled; the resistance ratio of the first resistor to the second resistance is m-1, and the resistance ratio of the fourth resistance to the third resistance is m-1, The second resistor and the third resistor have the same resistance value; wherein the connection between the first resistor and the first power source is coupled to the positive input terminal of the third differential amplifier circuit, and the fourth The coupling ground end of the resistor is coupled to the negative input end of the third differential amplifier circuit; the connection between the first resistor and the second resistor is coupled to the positive input end of the first differential amplifier circuit, and the first The junction of the three resistors and the fourth resistor is coupled with the negative input terminal of the first differential amplifier circuit;

    The fifth resistor, the sixth resistor, the seventh resistor, and the eighth resistor are connected in series; the fifth resistor is coupled to the second power source, the eighth resistor is coupled to the ground, and the sixth resistor and the seventh resistor are connected to the The output terminal of the buffer is coupled; the resistance ratio of the fifth resistor to the sixth resistor is m-1, and the resistance ratio of the eighth resistor to the seventh resistor is m-1 , The sixth resistor has the same resistance value as the seventh resistor; wherein the connection between the fifth resistor and the second power source is coupled to the positive input terminal of the fourth differential amplifier circuit, and the first The coupling ground end of the eight resistor is coupled to the negative input end of the fourth differential amplifier circuit; the connection of the fifth resistor and the sixth resistor is coupled to the positive input end of the second differential amplifier circuit, the The junction of the seventh resistor and the eighth resistor is coupled with the negative input terminal of the second differential amplifier circuit.
12. The amplifying device according to any one of claims 3 to 11, wherein the second current source is obtained after being mirror-biased by the first current source.
13. The amplifying device according to any one of claims 1 to 12, wherein the gate of the first transistor is used to receive the first signal, the source of the first transistor is coupled to ground, and the The drain of a transistor is coupled to the load of the amplifying device;

    The source of the second transistor is coupled to ground, and the drain of the second transistor is coupled to the load of the amplifying device;

    The gate of the third transistor is used to receive the second signal, the source of the third transistor is coupled to ground, and the drain of the third transistor is coupled to the load of the amplifying device;

    The source of the fourth transistor is coupled to ground, and the drain of the fourth transistor is coupled to the load of the amplifying device.

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