WO2020174628A1 - Limiting amplification circuit - Google Patents

Limiting amplification circuit Download PDF

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Publication number
WO2020174628A1
WO2020174628A1 PCT/JP2019/007672 JP2019007672W WO2020174628A1 WO 2020174628 A1 WO2020174628 A1 WO 2020174628A1 JP 2019007672 W JP2019007672 W JP 2019007672W WO 2020174628 A1 WO2020174628 A1 WO 2020174628A1
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WO
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Prior art keywords
signal
differential
amplifier circuit
offset
circuit
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PCT/JP2019/007672
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French (fr)
Japanese (ja)
Inventor
聡 吉間
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2019530514A priority Critical patent/JP6661057B1/en
Priority to PCT/JP2019/007672 priority patent/WO2020174628A1/en
Publication of WO2020174628A1 publication Critical patent/WO2020174628A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/08—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/34—Dc amplifiers in which all stages are dc-coupled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G11/00—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general

Definitions

  • the present invention relates to a limiting amplifier circuit that amplifies an input signal to a predetermined amplitude.
  • the PON system is a single OLT (Optical Line Terminal) that is a station side device, a plurality of ONUs (Optical Network Units) that are subscriber side devices, and an optical star that is a passive element that connects the OLT and the ONU. It is composed of a coupler and an optical fiber connecting the OLT, ONU and optical star coupler.
  • OLT Optical Line Terminal
  • ONUs Optical Network Units
  • optical star optical star that is a passive element that connects the OLT and the ONU. It is composed of a coupler and an optical fiber connecting the OLT, ONU and optical star coupler.
  • the optical signal is converted into a current signal and then identified by a clock data recovery circuit.
  • the converted current signal is linearly amplified by the transimpedance amplifier and then the amplitude determined in advance by the limiting amplifier circuit is used. It is input to the clock data recovery circuit after being limited to.
  • Non-Patent Document 1 discloses a technique of canceling a voltage offset, which is a difference in a DC voltage component between a positive-phase signal and a negative-phase signal of a differential signal, by using feedback from an output of a limiting amplifier circuit to an input. Has been done.
  • Non-Patent Document 1 there is a problem that the code error rate may increase in the signal reception section.
  • the photoelectric conversion element generally used in the PON system has a characteristic that noise increases as the power of an input optical signal increases. That is, the noise on the mark side of the OOK (On Off Keying) signal increases more than the noise on the space side. Therefore, if the midpoints of the amplitudes of the positive phase signal and the negative phase signal are simply taken, the code error rate may increase.
  • the present invention has been made in view of the above, and an object thereof is to obtain a limiting amplifier circuit capable of reducing a code error rate.
  • a limiting amplifier circuit is provided with a difference in DC voltage component between a positive-phase signal and a negative-phase signal of an input first differential signal.
  • a first differential amplifier circuit which has a function of adjusting a voltage offset, amplifies the first differential signal, and outputs a second differential signal which is the amplified signal;
  • a second differential amplifier circuit that amplifies the differential signal to a predetermined amplitude, a signal detection circuit that determines whether the second differential signal includes a received signal, and a determination result of the signal detection circuit.
  • an offset control circuit for controlling the adjustment amount of the voltage offset based on the above.
  • the limiting amplifier circuit according to the present invention has the effect of reducing the code error rate.
  • FIG. 3 is a diagram for explaining the operation of the limiting amplifier circuit shown in FIG.
  • the figure which shows a part structure of the 1st differential amplifier circuit shown in FIG. The figure which shows the structure of the limiting amplifier circuit concerning Embodiment 2 of this invention.
  • FIG. 1 is a diagram showing a configuration of a limiting amplifier circuit 3 according to the first exemplary embodiment of the present invention.
  • the limiting amplifier circuit 3 is included in the burst optical receiver.
  • the limiting amplifier circuit 3 includes an APD (Avalanche Photo Diode) 1, which is an optoelectric conversion element that converts an input optical signal into a current signal, and a transimpedance amplifier 2 that converts a current signal output from the APD 1 into a voltage signal.
  • a signal is input via and.
  • the limiting amplifier circuit 3 amplifies the output signal of the transimpedance amplifier 2 to a predetermined amplitude, and inputs the amplified signal to the CDR 5 via the AC coupling capacitors 41 and 42.
  • FIG. 1 shows only the part of the configuration of the burst optical receiver that is related to the invention according to the present embodiment, and the burst optical receiver has components other than those shown in FIG. May be.
  • APD1 converts the input optical signal into a current signal and outputs it.
  • the APD 1 has a characteristic that noise increases as the power of the input signal increases. For example, the noise on the mark side of the OOK signal is larger than the noise on the space side.
  • the current signal output from the APD 1 is input to the transimpedance amplifier 2.
  • the transimpedance amplifier 2 is a preamplifier having a high gain and converts an input current signal into a voltage signal.
  • the transimpedance amplifier 2 amplifies the input signal and outputs a first differential signal which is the amplified signal.
  • the amplitude of the voltage signal output from the transimpedance amplifier 2 depends on the power of the input signal.
  • the transimpedance amplifier 2 is, for example, a linear amplifier.
  • the first differential signal output from the transimpedance amplifier 2 is input to the limiting amplification circuit 3.
  • the first differential signal includes a pair of positive and negative phase signals.
  • the limiting amplifier circuit 3 includes a first differential amplifier circuit 31, a second differential amplifier circuit 32, an output buffer 33, a signal detection circuit 34, an offset control circuit 35, and a switch 36.
  • the first differential amplifier circuit 31 amplifies the first differential signal and outputs a second differential signal that is the amplified signal.
  • the larger the power of the input signal the larger the power of the output signal.
  • the first differential amplifier circuit 31 is, for example, a linear amplifier that linearly amplifies an input signal.
  • the first differential amplifier circuit 31 has a function of adjusting a voltage offset that is a difference in DC voltage component between the positive phase signal and the negative phase signal of the input first differential signal.
  • the second differential amplifier circuit 32 is a limiting amplifier that amplifies the second differential signal output from the first differential amplifier circuit 31 to a predetermined amplitude. It can be said that the second differential amplifier circuit 32 limits the amplitude of the output signal of the limiting amplifier circuit 3 to a predetermined value.
  • the output buffer 33 converts the amplified second differential signal into a signal passing level to the CDR5.
  • the output buffer 33 outputs the converted second differential signal to the output terminal connected to the CDR5.
  • the signal detection circuit 34 determines whether or not the second differential signal output from the first differential amplifier circuit 31 includes the received signal from the opposite device.
  • the signal detection circuit 34 determines whether or not the second differential signal includes the received signal, for example, based on the amplitude of the input differential signal. More specifically, the signal detection circuit 34 can determine that the second differential signal includes the reception signal when the amplitude of the input differential signal is larger than a predetermined threshold value. In this case, the signal detection circuit 34 determines that the second differential signal does not include the received signal when the amplitude of the input differential signal is less than or equal to the threshold value.
  • the threshold used by the signal detection circuit 34 may have a hysteresis property in order to reduce the possibility of malfunction. Further, the threshold may be a value held in advance inside or a value given externally as appropriate.
  • the determination method used by the signal detection circuit 34 is not limited to the above.
  • the signal detection circuit 34 compares a predetermined signal pattern with the signal pattern of the second differential signal, and based on the comparison result, determines whether the second differential signal includes the reception signal. Determine whether.
  • the signal detection circuit 34 can detect the signal pattern by calculating the number of clocks of the input signal using the counter circuit, and can determine whether or not the second differential signal includes the reception signal. Further, the signal detection circuit 34 may detect a signal disconnection instead of detecting the received signal.
  • the signal detection circuit 34 outputs the first value indicating that the received signal is not detected as the determination result.
  • the signal detection circuit 34 outputs a second value indicating that the received signal is detected as the determination result.
  • the offset control circuit 35 controls the adjustment amount of the voltage offset based on the offset control signal input from the outside of the limiting amplification circuit 3.
  • the offset control circuit 35 can output an offset setting signal for controlling the voltage offset of the first differential amplifier circuit 31.
  • the offset control circuit 35 can output two types of offset setting signals.
  • the first offset setting signal of the two types of offset setting signals is the first adjustment amount used when the second differential signal does not include the received signal, that is, in the no-signal section in which the received signal is not detected. Show.
  • the second offset setting signal of the two types of offset setting signals indicates the second adjustment amount used when the second differential signal includes the reception signal, that is, in the signal section in which the reception signal is detected. ..
  • the first adjustment amount is a value that minimizes the voltage offset, that is, approaches zero.
  • the second adjustment amount is a value different from the first adjustment amount.
  • the offset control circuit 35 determines the first offset setting signal and the second offset setting signal based on the offset control signal input from the outside.
  • the offset control signal may be input using a digital signal interface such as I2C (Inter-Integrated Circuit) and held in a register in the limiting amplifier circuit 3, or may be input as an analog voltage signal. ..
  • I2C Inter-Integrated Circuit
  • the offset control signal is directly input in FIG. 1, an external command may be input, for example, and the offset control circuit 35 may perform arithmetic processing based on the input command. Further, if a similar effect is obtained, the offset control signal does not have to hold a constant value during operation, and may be a value that changes with time after performing arithmetic processing.
  • the switch 36 switches the offset setting signal input to the first differential amplifier circuit 31 from the two types of offset setting signals output by the offset control circuit 35.
  • the switch 36 can switch the offset setting signal input to the first differential amplifier circuit 31 based on the value output by the signal detection circuit 34.
  • the output of the limiting amplifier circuit 3 is AC-coupled to the CDR5 by the AC coupling capacitors 41 and 42.
  • the CDR 5 retimes the signal output from the limiting amplifier circuit 3 and discriminates the input differential signal.
  • the transimpedance amplifier 2 and the limiting amplifier circuit 3 require a power supply voltage of about 3.3 V to secure analog characteristics. Since the CDR 5 can be realized by a digital circuit, it can be driven with a power supply voltage lower than the power supply voltages of the transimpedance amplifier 2 and the limiting amplification circuit 3.
  • the drive voltage of CDR5 is 1.8V, for example.
  • FIG. 2 is a diagram for explaining the operation of the limiting amplifier circuit 3 shown in FIG. FIG. 2 shows the positive phase voltage which is the voltage of the positive phase signal input to the limiting amplifier circuit 3 from above, the output voltage from the signal detection circuit 34, and the positive phase voltage input to the CDR5.
  • the output voltage from the signal detection circuit 34 becomes the first value “Low”.
  • the switch 36 is in a state of inputting the first offset setting signal for the no-signal section to the first differential amplifier circuit 31.
  • the first offset setting signal is input to the first differential amplifier circuit 31
  • the voltage offset of the differential signal output from the first differential amplifier circuit 31 is controlled so as to approach zero.
  • the center voltage of the positive phase signal input to the limiting amplifier circuit 3 is the voltage VCM3
  • the center voltage of the positive phase signal input to the CDR5 is the voltage VCM5.
  • the signal detection circuit 34 detects the amplitude of the output signal of the first differential amplifier circuit 31, and changes the output voltage from the first value “Low” to the second value. Transition to a certain "High”.
  • the switch 36 switches the offset setting signal input to the first differential amplifier circuit 31 so that the second offset setting signal is the first differential amplifier circuit. 31 is input.
  • the center voltage of the positive phase signal input to the limiting amplifier circuit 3 shifts to the higher voltage side than the voltage VCM3.
  • the center voltage of the positive phase signal input to the CDR5 is constant regardless of the input optical power and does not shift from the voltage VCM5.
  • the voltage offset can be transited to a desired optimum point.
  • the time constant of the DC voltage drift due to the AC coupling between the limiting amplifier circuit 3 and the CDR 5 is usually several tens ⁇ s, whereas the operation delay of the signal detection circuit 34, the switching time of the switch 36, and the offset control.
  • the operation delay of the circuit 35 is usually several ns to several tens of ns. Therefore, the DC drift of the differential signal at the CDR5 input terminal is almost negligible due to the AC coupling. Further, during the operation delay of the signal detection circuit 34, the switching time of the switch 36, and the operation delay of the offset control circuit 35, the accuracy of signal determination decreases and effective communication cannot be established.
  • G. T International Telecommunication Union Telecommunication standardization sector Since the preamble length assigned to the 10 Gbps upstream signal defined in 9807.1 is 128.6 ns to 610.9 ns, it is possible to satisfy these values.
  • FIG. 3 is a diagram showing a partial configuration of the first differential amplifier circuit 31 shown in FIG.
  • the first differential amplifier circuit 31 has terminating resistors 311 and 312 at its input portion so that reflection does not occur when a high frequency signal is input.
  • the first differential amplifier circuit 31 has a differential pair 313 and variable current sources 314 and 315.
  • the differential pair 313 amplifies the differential signal.
  • Each of the variable current sources 314 and 315 is connected between the signal input terminal and the ground GND.
  • the offset control circuit 35 determines the current value to be passed through each of the variable current sources 314 and 315. It is possible to change the voltage offset of the differential signal by relatively changing the value of the current flowing through each of the variable current sources 314 and 315.
  • variable current sources 314 and 315 are connected between the signal input terminal and the ground GND in FIG. 3, the variable current sources 314 and 315 are connected between the terminating resistors 311 and 312 and the signal input terminal. It may be connected or a combination thereof. Further, in FIG. 3, the variable current sources 314 and 315 are connected to each of the two differential lines, but the current source connected to one of the positive phase signal and the negative phase signal is a fixed current source. The other may be a variable current source. Further, the portion of the first differential amplifier circuit 31 to which the current source for adjusting the voltage offset is connected is not limited to the input portion. For example, a current source may be connected to the inside of the first differential amplifier circuit 31, such as the output unit of the differential pair 313, or the current may be supplied to the input unit of the first differential amplifier circuit 31 and a plurality of positions inside. The source may be connected.
  • the input to the CDR 5 is performed in both the no-signal section and the signal reception section. It is possible to keep the center voltage of the signal constant. Therefore, even when the limiting amplifier circuit 3 and the CDR 5 are AC-coupled, the code error rate can be reduced. Also, highly efficient communication with a shortened preamble length becomes possible. Further, the limiting amplifier circuit 3 uses the signal that has been sufficiently amplified to perform a process of determining whether or not the received signal is included. For this reason, it is not necessary to integrate the signal components, or the integration for the minimum time is sufficient, so that the presence or absence of the received signal can be determined at high speed. Therefore, the voltage offset can be adjusted at high speed, and the code error rate can be reduced while maintaining the upstream transmission efficiency.
  • FIG. 4 is a diagram showing a configuration of the limiting amplifier circuit 3-1 according to the second exemplary embodiment of the present invention.
  • the limiting amplifier circuit 3 using two offset control signals input from the outside is shown, but in the second embodiment, the number of offset control signals input from the outside is one.
  • a limiting amplifier circuit 3-1 that can obtain the same effect as that of the first embodiment will be described.
  • the same configurations as those of the first embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted, and portions different from the first embodiment will be mainly described.
  • the limiting amplifier circuit 3-1 has two offset control circuits 351 and 352.
  • the offset control circuit 351 outputs a first offset setting signal used when the input signal does not include the reception signal
  • the offset control circuit 352 is used when the input signal includes the reception signal.
  • Output a second offset setting signal.
  • the differential signal output from the second differential amplifier circuit 32 is input to the offset control circuit 351, and the adjustment amount of the voltage offset is controlled based on the output of the second differential amplifier circuit 32.
  • One offset control signal is input to the offset control circuit 352 from the outside of the limiting amplification circuit 3-1.
  • the offset control circuit 352 controls the adjustment amount of the voltage offset based on the input offset control signal.
  • the offset control circuit 351 is, for example, an integrating circuit using an operational amplifier.
  • the offset control circuit 351 may include an ADC (Analog-to-Digital Converter) that samples the differential signal and a digital filter that integrates the differential signal.
  • ADC Analog-to-Digital Converter
  • the second embodiment of the present invention it is possible to obtain the same effect as that of the first embodiment, and it is possible to reduce the number of offset control signals input to the limiting amplifier circuit 3-1. Can be one. In this case, since the number of offset control signals is reduced as compared with the limiting amplifier circuit 3, it is possible to reduce the number of memories required outside the limiting amplifier circuit 3-1, and also to perform the offset There is an advantage that pre-adjustment of the control signal is unnecessary.
  • FIG. 5 is a diagram showing a configuration of the limiting amplifier circuit 3-2 according to the third exemplary embodiment of the present invention.
  • the signal detection circuit 34 determines the value of the output voltage based on the amplitude of the output signal of the first differential amplifier circuit 31 both when the optical signal is received and when there is no signal transition. I had decided when to switch.
  • the signal detection circuit 34-1 uses the reset signal input from the outside of the limiting amplification circuit 3-2 as a trigger to change the output voltage value from “High” to “Low”. Transition to. That is, when the signal detection circuit 34-1 receives the reset signal, the signal detection circuit 34-1 outputs a determination result indicating that the second differential signal output from the first differential amplifier circuit 31 does not include the received signal.
  • the signal detection circuit 34-1 can be configured using a single latch circuit. Therefore, there is an advantage that the configuration of the signal detection circuit 34-1 can be simplified.
  • FIG. 5 shows the limiting amplification circuit 3-2 in which the signal detection circuit 34 of the limiting amplification circuit 3 according to the first exemplary embodiment is replaced with the signal detection circuit 34-1 corresponding to the reset signal
  • the present embodiment is not limited to this example.
  • the signal detection circuit 34-1 corresponding to the reset signal may be used.
  • only one offset control signal is input from the outside, so that the number of memories required outside the limiting amplifier circuit 3-2 can be reduced and the offset can be reduced. This has the advantage that pre-adjustment of the control signal is unnecessary.
  • FIG. 6 is a diagram showing a configuration of the limiting amplifier circuit 3-3 according to the fourth exemplary embodiment of the present invention.
  • the output of the first differential amplifier circuit 31 is input to the signal detection circuits 34, 34-1, whereas in the fourth embodiment, the limiting amplifier circuit 3- 3 is branched before being input to the first differential amplifier circuit 31, is amplified by the third differential amplifier circuit 37, and is input to the signal detection circuit 34-2. To do.
  • the third differential amplifier circuit 37 is arranged in front of the signal detection circuit 34-2.
  • the third differential amplifier circuit 37 amplifies the first differential signal and inputs it to the signal detection circuit 34-2.
  • the signal detection circuit 34-2 determines whether or not the second differential signal includes the received signal based on the amplified first differential signal output from the third differential amplifier circuit 37.
  • the signal line finally connected to the CDR5 and the signal line connected to the signal detection circuit 34-2 are separated in the limiting amplifier circuit 3-3. Will be possible. Therefore, there is an advantage that it is possible to optimize each signal line and set each amplifier.
  • the third differential amplifier circuit 37 is a linear amplifier in which the amplitude of the output signal depends on the amplitude of the input signal, like the first differential amplifier circuit 31. Further, if it does not adversely affect the signal line connected to the CDR 5 finally, the signal line may be directly connected to the signal detection circuit 34-2 without passing through the third differential amplifier circuit 37.
  • the limiting amplifier circuit 3-3 is not limited to the configuration shown in FIG.
  • the limiting amplifier circuit 3-3 may include two offset control circuits 351, 352, and the signal detection circuit 34-2 may receive the reset signal.
  • the limiting amplifier circuit 3-3 may have two offset control circuits 351 and 352, and the signal detection circuit 34-2 may receive the reset signal.

Abstract

A limiting amplification circuit (3) according to the invention is characterized by being provided with: a first differential amplification circuit (31) that has a function to adjust a voltage offset, which is a difference in DC voltage component between a positive-phase signal of an inputted first differential signal and a negative-phase signal thereof, amplifies the first differential signal and outputs a second differential signal that is the signal as amplified; a second differential amplification circuit (32) that amplifies the second differential signal up to a predetermined amplitude; a signal detection circuit (34) that determines whether the second differential signal includes any reception signal; and an offset control circuit (35) that controls the adjustment amount for the voltage offset on the basis of the determination result of the signal detection circuit.

Description

リミッティング増幅回路Limiting amplifier circuit
　本発明は、入力された信号を予め定められた振幅まで増幅するリミッティング増幅回路に関する。 The present invention relates to a limiting amplifier circuit that amplifies an input signal to a predetermined amplitude.
　近年、１本の光ファイバを複数のユーザで共有することができるＰＯＮ（Passive　Optical　Network）システムと呼ばれる１対多数のアクセス系光通信システムが広く用いられている。ＰＯＮシステムは、局側装置である１台のＯＬＴ（Optical　Line　Terminal）と、加入者側の装置である複数のＯＮＵ（Optical　Network　Unit）と、ＯＬＴとＯＮＵとを接続する受動素子である光スターカプラと、ＯＬＴ、ＯＮＵおよび光スターカプラを接続する光ファイバとで構成される。 In recent years, a one-to-many access type optical communication system called a PON (Passive Optical Network) system that allows one user to share one optical fiber has been widely used. The PON system is a single OLT (Optical Line Terminal) that is a station side device, a plurality of ONUs (Optical Network Units) that are subscriber side devices, and an optical star that is a passive element that connects the OLT and the ONU. It is composed of a coupler and an optical fiber connecting the OLT, ONU and optical star coupler.
　ＰＯＮシステムに収容するＯＮＵの数を増加させるために、ＯＬＴとＯＮＵとの間の最大接続距離を長くし、ＯＮＵの分岐数を増加することが求められている。このため、ＯＮＵ毎にＯＬＴとの間の距離の差が大きくなり、ＯＬＴは信号強度差の大きなパケット信号を受信することになる。一般的に、光ファイバを介して伝送された光信号の受信処理では、光信号は、電流信号に変換された後、クロックデータリカバリ回路で信号識別される。このとき、クロックデータリカバリ回路への入力信号の信号レベルを一定に保つために、変換された電流信号は、トランスインピーダンスアンプでリニア増幅された後、リミッティング増幅回路を用いて予め定められた振幅に制限されてからクロックデータリカバリ回路に入力される。 In order to increase the number of ONUs accommodated in the PON system, it is required to increase the maximum connection distance between the OLT and ONU and increase the number of ONU branches. Therefore, the difference in distance from the OLT becomes large for each ONU, and the OLT receives a packet signal having a large signal strength difference. Generally, in the reception processing of an optical signal transmitted through an optical fiber, the optical signal is converted into a current signal and then identified by a clock data recovery circuit. At this time, in order to keep the signal level of the input signal to the clock data recovery circuit constant, the converted current signal is linearly amplified by the transimpedance amplifier and then the amplitude determined in advance by the limiting amplifier circuit is used. It is input to the clock data recovery circuit after being limited to.
　トランスインピーダンスアンプおよびリミッティング増幅回路で必要とされる電源電圧と、クロックデータリカバリ回路以降のデジタル回路で必要とされる電源電圧とは異なるため、リミッティング増幅回路とクロックデータリカバリ回路との間はＡＣ（Alternative　Current）結合されることが多い。受信信号の先頭で差動信号の正相信号および逆相信号間の直流電圧成分の大きさの差異が変化すると、信号歪みが発生して符号誤りが発生する。 Since the power supply voltage required by the transimpedance amplifier and the limiting amplification circuit is different from the power supply voltage required by the digital circuits after the clock data recovery circuit, there is a difference between the limiting amplification circuit and the clock data recovery circuit. AC (Alternative Current) is often combined. When the difference in the magnitude of the DC voltage component between the positive phase signal and the negative phase signal of the differential signal changes at the head of the received signal, signal distortion occurs and a code error occurs.
　非特許文献１には、リミッティング増幅回路の出力から入力へのフィードバックを用いて、差動信号の正相信号および逆相信号間の直流電圧成分の差である電圧オフセットをキャンセルする技術が開示されている。 Non-Patent Document 1 discloses a technique of canceling a voltage offset, which is a difference in a DC voltage component between a positive-phase signal and a negative-phase signal of a differential signal, by using feedback from an output of a limiting amplifier circuit to an input. Has been done.
　しかしながら、非特許文献１に開示された技術によれば、信号受信区間では、符号誤り率が上昇する場合があるという問題があった。具体的には、ＰＯＮシステムで一般的に用いられる光電気変換素子は、入力される光信号のパワーが高いほど雑音が増加するという特性がある。つまり、ＯＯＫ（On　Off　Keying）信号のマーク側の雑音がスペース側の雑音よりも増加する。このため、単純に正相信号と逆相信号のそれぞれの振幅の中点をとると、符号誤り率が上昇する場合があった。 However, according to the technique disclosed in Non-Patent Document 1, there is a problem that the code error rate may increase in the signal reception section. Specifically, the photoelectric conversion element generally used in the PON system has a characteristic that noise increases as the power of an input optical signal increases. That is, the noise on the mark side of the OOK (On Off Keying) signal increases more than the noise on the space side. Therefore, if the midpoints of the amplitudes of the positive phase signal and the negative phase signal are simply taken, the code error rate may increase.
　本発明は、上記に鑑みてなされたものであって、符号誤り率を低減することが可能なリミッティング増幅回路を得ることを目的とする。 The present invention has been made in view of the above, and an object thereof is to obtain a limiting amplifier circuit capable of reducing a code error rate.
　上述した課題を解決し、目的を達成するために、本発明にかかるリミッティング増幅回路は、入力される第１の差動信号の正相信号と逆相信号との間の直流電圧成分の差である電圧オフセットを調整する機能を有し、第１の差動信号を増幅して、増幅後の信号である第２の差動信号を出力する第１の差動増幅回路と、第２の差動信号を予め定められた振幅まで増幅する第２の差動増幅回路と、第２の差動信号が受信信号を含むか否かを判定する信号検出回路と、信号検出回路の判定結果に基づいて、電圧オフセットの調整量を制御するオフセット制御回路と、を備えることを特徴とする。 In order to solve the above-mentioned problems and to achieve the object, a limiting amplifier circuit according to the present invention is provided with a difference in DC voltage component between a positive-phase signal and a negative-phase signal of an input first differential signal. A first differential amplifier circuit which has a function of adjusting a voltage offset, amplifies the first differential signal, and outputs a second differential signal which is the amplified signal; A second differential amplifier circuit that amplifies the differential signal to a predetermined amplitude, a signal detection circuit that determines whether the second differential signal includes a received signal, and a determination result of the signal detection circuit. And an offset control circuit for controlling the adjustment amount of the voltage offset based on the above.
　本発明にかかるリミッティング増幅回路は、符号誤り率を低減することが可能になるという効果を奏する。 The limiting amplifier circuit according to the present invention has the effect of reducing the code error rate.
本発明の実施の形態１にかかるリミッティング増幅回路の構成を示す図The figure which shows the structure of the limiting amplifier circuit concerning Embodiment 1 of this invention. 図１に示すリミッティング増幅回路の動作を説明するための図FIG. 3 is a diagram for explaining the operation of the limiting amplifier circuit shown in FIG. 図１に示す第１の差動増幅回路の一部構成を示す図The figure which shows a part structure of the 1st differential amplifier circuit shown in FIG. 本発明の実施の形態２にかかるリミッティング増幅回路の構成を示す図The figure which shows the structure of the limiting amplifier circuit concerning Embodiment 2 of this invention. 本発明の実施の形態３にかかるリミッティング増幅回路の構成を示す図The figure which shows the structure of the limiting amplifier circuit concerning Embodiment 3 of this invention. 本発明の実施の形態４にかかるリミッティング増幅回路の構成を示す図The figure which shows the structure of the limiting amplifier circuit concerning Embodiment 4 of this invention.
　以下に、本発明の実施の形態にかかるリミッティング増幅回路を図面に基づいて詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。 The limiting amplifier circuit according to the embodiment of the present invention will be described below in detail with reference to the drawings. The present invention is not limited to this embodiment.
実施の形態１．
　図１は、本発明の実施の形態１にかかるリミッティング増幅回路３の構成を示す図である。リミッティング増幅回路３は、バースト光受信器に備えられている。リミッティング増幅回路３には、入力される光信号を電流信号に変換する光電気変換素子であるＡＰＤ（Avalanche　Photo　Diode）１と、ＡＰＤ１の出力する電流信号を電圧信号に変換するトランスインピーダンスアンプ２とを介して信号が入力される。リミッティング増幅回路３は、トランスインピーダンスアンプ２の出力信号を予め定められた振幅まで増幅して、増幅後の信号をＡＣ結合容量４１，４２を介して、ＣＤＲ５に入力する。なお、図１では、バースト光受信器の構成のうち、本実施の形態に係る発明に関係する部分だけを示しており、バースト光受信器は、図１に示す以外の構成要素を有していてもよい。 Embodiment 1.
FIG. 1 is a diagram showing a configuration of a limiting amplifier circuit 3 according to the first exemplary embodiment of the present invention. The limiting amplifier circuit 3 is included in the burst optical receiver. The limiting amplifier circuit 3 includes an APD (Avalanche Photo Diode) 1, which is an optoelectric conversion element that converts an input optical signal into a current signal, and a transimpedance amplifier 2 that converts a current signal output from the APD 1 into a voltage signal. A signal is input via and. The limiting amplifier circuit 3 amplifies the output signal of the transimpedance amplifier 2 to a predetermined amplitude, and inputs the amplified signal to the CDR 5 via the AC coupling capacitors 41 and 42. It should be noted that FIG. 1 shows only the part of the configuration of the burst optical receiver that is related to the invention according to the present embodiment, and the burst optical receiver has components other than those shown in FIG. May be.
　ＡＰＤ１は、入力される光信号を電流信号に変換して出力する。ＡＰＤ１は、入力信号のパワーが高いほど雑音が増加するという特性を有している。例えばＯＯＫ信号のマーク側の雑音はスペース側の雑音よりも大きい。ＡＰＤ１が出力する電流信号は、トランスインピーダンスアンプ２に入力される。 APD1 converts the input optical signal into a current signal and outputs it. The APD 1 has a characteristic that noise increases as the power of the input signal increases. For example, the noise on the mark side of the OOK signal is larger than the noise on the space side. The current signal output from the APD 1 is input to the transimpedance amplifier 2.
　トランスインピーダンスアンプ２は、高利得を有するプリアンプであり、入力される電流信号を電圧信号に変換する。トランスインピーダンスアンプ２は、入力信号を増幅して増幅後の信号である第１の差動信号を出力する。トランスインピーダンスアンプ２の出力する電圧信号の振幅は、入力される信号のパワーに依存する。トランスインピーダンスアンプ２は、例えば、リニアアンプである。トランスインピーダンスアンプ２が出力する第１の差動信号は、リミッティング増幅回路３に入力される。第１の差動信号は、一対の正相信号および逆相信号を含む。 The transimpedance amplifier 2 is a preamplifier having a high gain and converts an input current signal into a voltage signal. The transimpedance amplifier 2 amplifies the input signal and outputs a first differential signal which is the amplified signal. The amplitude of the voltage signal output from the transimpedance amplifier 2 depends on the power of the input signal. The transimpedance amplifier 2 is, for example, a linear amplifier. The first differential signal output from the transimpedance amplifier 2 is input to the limiting amplification circuit 3. The first differential signal includes a pair of positive and negative phase signals.
　リミッティング増幅回路３は、第１の差動増幅回路３１と、第２の差動増幅回路３２と、出力バッファ３３と、信号検出回路３４と、オフセット制御回路３５と、スイッチ３６とを有する。 The limiting amplifier circuit 3 includes a first differential amplifier circuit 31, a second differential amplifier circuit 32, an output buffer 33, a signal detection circuit 34, an offset control circuit 35, and a switch 36.
　第１の差動増幅回路３１は、第１の差動信号を増幅して、増幅後の信号である第２の差動信号を出力する。第１の差動増幅回路３１は、入力される信号のパワーが大きいほど出力される信号のパワーが大きい。第１の差動増幅回路３１は、例えば入力信号をリニア増幅するリニアアンプである。第１の差動増幅回路３１は、入力される第１の差動信号の正相信号と逆相信号との間の直流電圧成分の差である電圧オフセットを調整する機能を有する。 The first differential amplifier circuit 31 amplifies the first differential signal and outputs a second differential signal that is the amplified signal. In the first differential amplifier circuit 31, the larger the power of the input signal, the larger the power of the output signal. The first differential amplifier circuit 31 is, for example, a linear amplifier that linearly amplifies an input signal. The first differential amplifier circuit 31 has a function of adjusting a voltage offset that is a difference in DC voltage component between the positive phase signal and the negative phase signal of the input first differential signal.
　第２の差動増幅回路３２は、第１の差動増幅回路３１が出力する第２の差動信号を予め定められた振幅まで増幅するリミッティングアンプである。第２の差動増幅回路３２は、リミッティング増幅回路３の出力信号の振幅を、予め定められた値に制限しているともいえる。 The second differential amplifier circuit 32 is a limiting amplifier that amplifies the second differential signal output from the first differential amplifier circuit 31 to a predetermined amplitude. It can be said that the second differential amplifier circuit 32 limits the amplitude of the output signal of the limiting amplifier circuit 3 to a predetermined value.
　出力バッファ３３は、増幅後の第２の差動信号をＣＤＲ５への信号受け渡しレベルに変換する。出力バッファ３３は、変換後の第２の差動信号を、ＣＤＲ５に接続される出力端子に出力する。 The output buffer 33 converts the amplified second differential signal into a signal passing level to the CDR5. The output buffer 33 outputs the converted second differential signal to the output terminal connected to the CDR5.
　信号検出回路３４は、第１の差動増幅回路３１の出力する第２の差動信号が対向装置からの受信信号を含むか否かを判定する。信号検出回路３４は、例えば、入力される差動信号の振幅に基づいて、第２の差動信号が受信信号を含むか否かを判定する。より具体的には、信号検出回路３４は、入力される差動信号の振幅が予め定められた閾値よりも大きい場合、第２の差動信号が受信信号を含むと判定することができる。この場合、信号検出回路３４は、入力される差動信号の振幅が閾値以下である場合、第２の差動信号が受信信号を含まないと判定する。信号検出回路３４が用いる閾値は、誤作動の可能性を低減するためにヒステリシス性を持たせてもよい。また、閾値は、内部で予め保持された値であってもよいし、外部から適宜与えられる値であってもよい。 The signal detection circuit 34 determines whether or not the second differential signal output from the first differential amplifier circuit 31 includes the received signal from the opposite device. The signal detection circuit 34 determines whether or not the second differential signal includes the received signal, for example, based on the amplitude of the input differential signal. More specifically, the signal detection circuit 34 can determine that the second differential signal includes the reception signal when the amplitude of the input differential signal is larger than a predetermined threshold value. In this case, the signal detection circuit 34 determines that the second differential signal does not include the received signal when the amplitude of the input differential signal is less than or equal to the threshold value. The threshold used by the signal detection circuit 34 may have a hysteresis property in order to reduce the possibility of malfunction. Further, the threshold may be a value held in advance inside or a value given externally as appropriate.
　信号検出回路３４が用いる判定方法は上記に限定されない。例えば、信号検出回路３４は、予め定められた信号パターンと、第２の差動信号の信号パターンとを比較して、比較結果に基づいて、第２の差動信号が受信信号を含むか否かを判定する。信号検出回路３４は、カウンタ回路を用いて入力信号のクロック数を算出することで信号パターン検出をし、第２の差動信号が受信信号を含むか否かを判定することができる。また、信号検出回路３４は、受信信号を検出するのではなく、信号断を検出してもよい。信号検出回路３４は、第２の差動信号が受信信号を含まない場合、判定結果として受信信号を検出しなかったことを示す第１の値を出力する。信号検出回路３４は、第２の差動信号が受信信号を含む場合、判定結果として受信信号を検出したことを示す第２の値を出力する。 The determination method used by the signal detection circuit 34 is not limited to the above. For example, the signal detection circuit 34 compares a predetermined signal pattern with the signal pattern of the second differential signal, and based on the comparison result, determines whether the second differential signal includes the reception signal. Determine whether. The signal detection circuit 34 can detect the signal pattern by calculating the number of clocks of the input signal using the counter circuit, and can determine whether or not the second differential signal includes the reception signal. Further, the signal detection circuit 34 may detect a signal disconnection instead of detecting the received signal. When the second differential signal does not include the received signal, the signal detection circuit 34 outputs the first value indicating that the received signal is not detected as the determination result. When the second differential signal includes the received signal, the signal detection circuit 34 outputs a second value indicating that the received signal is detected as the determination result.
　オフセット制御回路３５は、リミッティング増幅回路３の外部から入力されるオフセット制御信号に基づいて、電圧オフセットの調整量を制御する。オフセット制御回路３５は、第１の差動増幅回路３１の電圧オフセットを制御するためのオフセット設定信号を出力することができる。オフセット制御回路３５は、２種類のオフセット設定信号を出力することができる。２種類のオフセット設定信号のうちの第１のオフセット設定信号は、第２の差動信号が受信信号を含まない場合、つまり、受信信号が検出されない無信号区間に用いられる第１の調整量を示す。２種類のオフセット設定信号のうちの第２のオフセット設定信号は、第２の差動信号が受信信号を含む場合、つまり、受信信号が検出される信号区間に用いられる第２の調整量を示す。第１の調整量は、電圧オフセットを最小化する、つまりゼロに近づけるための値である。第２の調整量は、第１の調整量と異なる値である。 The offset control circuit 35 controls the adjustment amount of the voltage offset based on the offset control signal input from the outside of the limiting amplification circuit 3. The offset control circuit 35 can output an offset setting signal for controlling the voltage offset of the first differential amplifier circuit 31. The offset control circuit 35 can output two types of offset setting signals. The first offset setting signal of the two types of offset setting signals is the first adjustment amount used when the second differential signal does not include the received signal, that is, in the no-signal section in which the received signal is not detected. Show. The second offset setting signal of the two types of offset setting signals indicates the second adjustment amount used when the second differential signal includes the reception signal, that is, in the signal section in which the reception signal is detected. .. The first adjustment amount is a value that minimizes the voltage offset, that is, approaches zero. The second adjustment amount is a value different from the first adjustment amount.
　オフセット制御回路３５は、第１のオフセット設定信号および第２のオフセット設定信号を、外部から入力されるオフセット制御信号に基づいて決定する。例えば、オフセット制御信号は、Ｉ２Ｃ（Inter－Integrated　Circuit）などのデジタル信号インタフェースを用いて入力されてリミッティング増幅回路３内のレジスタに保持されてもよいし、アナログ電圧信号で入力されてもよい。また、図１ではオフセット制御信号が直接入力されることとしたが、例えば何らかの外部コマンドが入力されて、オフセット制御回路３５が、入力されたコマンドに基づいて演算処理を行ってもよい。また、同様の効果を得られれば、オフセット制御信号は、動作中に一定の値を保持するものでなくてもよく、演算処理を行って経時的に変化する値であってもよい。 The offset control circuit 35 determines the first offset setting signal and the second offset setting signal based on the offset control signal input from the outside. For example, the offset control signal may be input using a digital signal interface such as I2C (Inter-Integrated Circuit) and held in a register in the limiting amplifier circuit 3, or may be input as an analog voltage signal. .. Although the offset control signal is directly input in FIG. 1, an external command may be input, for example, and the offset control circuit 35 may perform arithmetic processing based on the input command. Further, if a similar effect is obtained, the offset control signal does not have to hold a constant value during operation, and may be a value that changes with time after performing arithmetic processing.
　スイッチ３６は、オフセット制御回路３５が出力する２種類のオフセット設定信号の中から、第１の差動増幅回路３１に入力するオフセット設定信号を切り替える。スイッチ３６は、信号検出回路３４が出力する値に基づいて、第１の差動増幅回路３１に入力するオフセット設定信号を切り替えることができる。 The switch 36 switches the offset setting signal input to the first differential amplifier circuit 31 from the two types of offset setting signals output by the offset control circuit 35. The switch 36 can switch the offset setting signal input to the first differential amplifier circuit 31 based on the value output by the signal detection circuit 34.
　リミッティング増幅回路３の出力は、ＡＣ結合容量４１，４２によってＣＤＲ５にＡＣ結合される。ＣＤＲ５は、リミッティング増幅回路３の出力する信号をリタイミングすると共に、入力される差動信号を信号識別する。トランスインピーダンスアンプ２およびリミッティング増幅回路３は、アナログ特性を確保するために３．３Ｖ程度の電源電圧が必要である。ＣＤＲ５は、デジタル回路で実現することができるため、トランスインピーダンスアンプ２およびリミッティング増幅回路３の電源電圧よりも低い電源電圧で駆動することができる。ＣＤＲ５の駆動電圧は、例えば１．８Ｖである。 The output of the limiting amplifier circuit 3 is AC-coupled to the CDR5 by the AC coupling capacitors 41 and 42. The CDR 5 retimes the signal output from the limiting amplifier circuit 3 and discriminates the input differential signal. The transimpedance amplifier 2 and the limiting amplifier circuit 3 require a power supply voltage of about 3.3 V to secure analog characteristics. Since the CDR 5 can be realized by a digital circuit, it can be driven with a power supply voltage lower than the power supply voltages of the transimpedance amplifier 2 and the limiting amplification circuit 3. The drive voltage of CDR5 is 1.8V, for example.
　図２は、図１に示すリミッティング増幅回路３の動作を説明するための図である。図２は、上からリミッティング増幅回路３へ入力される正相信号の電圧である正相電圧、信号検出回路３４からの出力電圧、ＣＤＲ５へ入力される正相電圧を示している。 FIG. 2 is a diagram for explaining the operation of the limiting amplifier circuit 3 shown in FIG. FIG. 2 shows the positive phase voltage which is the voltage of the positive phase signal input to the limiting amplifier circuit 3 from above, the output voltage from the signal detection circuit 34, and the positive phase voltage input to the CDR5.
　まず、無信号区間では、信号検出回路３４からの出力電圧が第１の値である「Ｌｏｗ」となる。この場合、スイッチ３６は、無信号区間用の第１のオフセット設定信号を第１の差動増幅回路３１に入力する状態となる。第１のオフセット設定信号が第１の差動増幅回路３１に入力されると、第１の差動増幅回路３１の出力する差動信号の電圧オフセットがゼロに近づくように制御される。このとき、リミッティング増幅回路３へ入力される正相信号の中心電圧は、電圧ＶＣＭ３であり、ＣＤＲ５へ入力される正相信号の中心電圧は、電圧ＶＣＭ５である。 First, in the no-signal section, the output voltage from the signal detection circuit 34 becomes the first value “Low”. In this case, the switch 36 is in a state of inputting the first offset setting signal for the no-signal section to the first differential amplifier circuit 31. When the first offset setting signal is input to the first differential amplifier circuit 31, the voltage offset of the differential signal output from the first differential amplifier circuit 31 is controlled so as to approach zero. At this time, the center voltage of the positive phase signal input to the limiting amplifier circuit 3 is the voltage VCM3, and the center voltage of the positive phase signal input to the CDR5 is the voltage VCM5.
　信号受信区間となると、まず、信号検出回路３４は、第１の差動増幅回路３１の出力信号の振幅を検知して、出力電圧を第１の値である「Ｌｏｗ」から第２の値である「Ｈｉｇｈ」に遷移させる。信号検出回路３４の出力が「Ｈｉｇｈ」に遷移すると、スイッチ３６は、第１の差動増幅回路３１に入力するオフセット設定信号を切り替えて、第２のオフセット設定信号が第１の差動増幅回路３１に入力される。第２のオフセット設定信号に従って第１の差動増幅回路３１が動作することで、リミッティング増幅回路３に入力される正相信号の中心電圧は、電圧ＶＣＭ３よりも高電圧側にシフトする。ＣＤＲ５に入力される正相信号の中心電圧は、入力光パワーによらず一定であり、電圧ＶＣＭ５からシフトしない。 In the signal reception section, first, the signal detection circuit 34 detects the amplitude of the output signal of the first differential amplifier circuit 31, and changes the output voltage from the first value “Low” to the second value. Transition to a certain "High". When the output of the signal detection circuit 34 transits to “High”, the switch 36 switches the offset setting signal input to the first differential amplifier circuit 31 so that the second offset setting signal is the first differential amplifier circuit. 31 is input. When the first differential amplifier circuit 31 operates according to the second offset setting signal, the center voltage of the positive phase signal input to the limiting amplifier circuit 3 shifts to the higher voltage side than the voltage VCM3. The center voltage of the positive phase signal input to the CDR5 is constant regardless of the input optical power and does not shift from the voltage VCM5.
　上記の動作によって、信号検出回路３４の動作遅延時間、スイッチ３６の切り替え時間、およびオフセット制御回路３５の動作遅延時間の経過後は、電圧オフセットを所望の最適点へと遷移させることができる。 By the above operation, after the operation delay time of the signal detection circuit 34, the switching time of the switch 36, and the operation delay time of the offset control circuit 35 have elapsed, the voltage offset can be transited to a desired optimum point.
　リミッティング増幅回路３とＣＤＲ５との間のＡＣ結合による直流電圧ドリフトの時定数は、通常、数１０μｓであるのに対して、信号検出回路３４の動作遅延、スイッチ３６の切り替え時間、およびオフセット制御回路３５の動作遅延は、通常、数ｎｓから数１０ｎｓである。このため、ＡＣ結合によりＣＤＲ５入力端における差動信号の直流ドリフトは、ほとんど無視できるレベルとなる。また、信号検出回路３４の動作遅延、スイッチ３６の切り替え時間、およびオフセット制御回路３５の動作遅延の間は、信号判定精度が低下して有効な通信を確立することができないが、例えば、ＩＴＵ－Ｔ（International　Telecommunication　Union　Telecommunication　standardization　sector）Ｇ．９８０７．１に規定された１０Ｇｂｐｓ上り信号に割り当てられたプリアンブル長は、１２８．６ｎｓから６１０．９ｎｓであるため、これらの値を満たすことも可能である。 The time constant of the DC voltage drift due to the AC coupling between the limiting amplifier circuit 3 and the CDR 5 is usually several tens μs, whereas the operation delay of the signal detection circuit 34, the switching time of the switch 36, and the offset control. The operation delay of the circuit 35 is usually several ns to several tens of ns. Therefore, the DC drift of the differential signal at the CDR5 input terminal is almost negligible due to the AC coupling. Further, during the operation delay of the signal detection circuit 34, the switching time of the switch 36, and the operation delay of the offset control circuit 35, the accuracy of signal determination decreases and effective communication cannot be established. G. T (International Telecommunication Union Telecommunication standardization sector) Since the preamble length assigned to the 10 Gbps upstream signal defined in 9807.1 is 128.6 ns to 610.9 ns, it is possible to satisfy these values.
　図３は、図１に示す第１の差動増幅回路３１の一部構成を示す図である。第１の差動増幅回路３１は、入力部分に、高周波信号を入力した際に反射が発生しないように終端抵抗３１１，３１２を有する。また第１の差動増幅回路３１は、差動対３１３と、可変電流源３１４，３１５とを有する。差動対３１３は、差動信号を増幅する。可変電流源３１４，３１５のそれぞれは、信号入力端子とグランドＧＮＤとの間に接続されている。可変電流源３１４，３１５のそれぞれに流す電流値は、オフセット制御回路３５において決定される。可変電流源３１４，３１５のそれぞれに流す電流値を相対的に変化させることで、差動信号の電圧オフセットを変更することが可能になる。 FIG. 3 is a diagram showing a partial configuration of the first differential amplifier circuit 31 shown in FIG. The first differential amplifier circuit 31 has terminating resistors 311 and 312 at its input portion so that reflection does not occur when a high frequency signal is input. The first differential amplifier circuit 31 has a differential pair 313 and variable current sources 314 and 315. The differential pair 313 amplifies the differential signal. Each of the variable current sources 314 and 315 is connected between the signal input terminal and the ground GND. The offset control circuit 35 determines the current value to be passed through each of the variable current sources 314 and 315. It is possible to change the voltage offset of the differential signal by relatively changing the value of the current flowing through each of the variable current sources 314 and 315.
　なお、図３では信号入力端子とグランドＧＮＤとの間に可変電流源３１４，３１５が接続されているが、終端抵抗３１１，３１２のそれぞれと信号入力端との間に可変電流源３１４，３１５を接続してもよいし、それらの組み合わせであってもよい。また、図３では、２つの差動ラインのそれぞれに１つずつ可変電流源３１４，３１５を接続しているが、正相信号および逆相信号の一方に接続する電流源を固定の電流源とし、他方を可変の電流源としてもよい。さらに、第１の差動増幅回路３１のうち、電圧オフセットを調整するための電流源を接続する部分は、入力部分に限定されない。例えば、差動対３１３の出力部など、第１の差動増幅回路３１の内部に電流源を接続してもよいし、第１の差動増幅回路３１の入力部および内部の複数箇所に電流源を接続してもよい。 Although the variable current sources 314 and 315 are connected between the signal input terminal and the ground GND in FIG. 3, the variable current sources 314 and 315 are connected between the terminating resistors 311 and 312 and the signal input terminal. It may be connected or a combination thereof. Further, in FIG. 3, the variable current sources 314 and 315 are connected to each of the two differential lines, but the current source connected to one of the positive phase signal and the negative phase signal is a fixed current source. The other may be a variable current source. Further, the portion of the first differential amplifier circuit 31 to which the current source for adjusting the voltage offset is connected is not limited to the input portion. For example, a current source may be connected to the inside of the first differential amplifier circuit 31, such as the output unit of the differential pair 313, or the current may be supplied to the input unit of the first differential amplifier circuit 31 and a plurality of positions inside. The source may be connected.
　以上説明したように、処理対象の差動信号が受信信号を含むか否かに基づいて、電圧オフセットの調整量を変更することで、無信号区間および信号受信区間の両方において、ＣＤＲ５への入力信号の中心電圧を一定に保つことが可能になる。したがって、リミッティング増幅回路３およびＣＤＲ５の間をＡＣ結合した場合においても、符号誤り率を低減することが可能になる。また、プリアンブル長を短縮化した高効率な通信が可能となる。また、リミッティング増幅回路３は、十分に増幅した後の信号を用いて、受信信号を含むか否かを判定する処理を行う。このため、信号成分を積分する必要がない、または最低限の時間の積分でよいため、高速に受信信号の有無を判別可能である。したがって、高速に電圧オフセットを調整することができ、上りの伝送効率を維持したまま、符号誤り率を低減することが可能である。 As described above, by changing the adjustment amount of the voltage offset based on whether or not the differential signal to be processed includes the reception signal, the input to the CDR 5 is performed in both the no-signal section and the signal reception section. It is possible to keep the center voltage of the signal constant. Therefore, even when the limiting amplifier circuit 3 and the CDR 5 are AC-coupled, the code error rate can be reduced. Also, highly efficient communication with a shortened preamble length becomes possible. Further, the limiting amplifier circuit 3 uses the signal that has been sufficiently amplified to perform a process of determining whether or not the received signal is included. For this reason, it is not necessary to integrate the signal components, or the integration for the minimum time is sufficient, so that the presence or absence of the received signal can be determined at high speed. Therefore, the voltage offset can be adjusted at high speed, and the code error rate can be reduced while maintaining the upstream transmission efficiency.
実施の形態２．
　図４は、本発明の実施の形態２にかかるリミッティング増幅回路３－１の構成を示す図である。上記の実施の形態１では、外部から入力される２つのオフセット制御信号を用いたリミッティング増幅回路３を示したが、実施の形態２では、外部から入力されるオフセット制御信号の数を１つとしても実施の形態１と同様の効果を得ることができるリミッティング増幅回路３－１について説明する。以下、実施の形態１と同様の構成については、同じ符号を付することによって詳細な説明を省略し、実施の形態１と異なる部分について主に説明する。 Embodiment 2.
FIG. 4 is a diagram showing a configuration of the limiting amplifier circuit 3-1 according to the second exemplary embodiment of the present invention. In the above-described first embodiment, the limiting amplifier circuit 3 using two offset control signals input from the outside is shown, but in the second embodiment, the number of offset control signals input from the outside is one. Also, a limiting amplifier circuit 3-1 that can obtain the same effect as that of the first embodiment will be described. Hereinafter, the same configurations as those of the first embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted, and portions different from the first embodiment will be mainly described.
　リミッティング増幅回路３－１は、２つのオフセット制御回路３５１，３５２を有する。オフセット制御回路３５１は、入力される信号が受信信号を含まない場合に使用される第１のオフセット設定信号を出力し、オフセット制御回路３５２は、入力される信号が受信信号を含む場合に使用される第２のオフセット設定信号を出力する。オフセット制御回路３５１には、第２の差動増幅回路３２の出力する差動信号が入力され、第２の差動増幅回路３２の出力に基づいて電圧オフセットの調整量を制御する。オフセット制御回路３５２には、リミッティング増幅回路３－１の外部から１つのオフセット制御信号が入力される。オフセット制御回路３５２は、入力されるオフセット制御信号に基づいて電圧オフセットの調整量を制御する。 The limiting amplifier circuit 3-1 has two offset control circuits 351 and 352. The offset control circuit 351 outputs a first offset setting signal used when the input signal does not include the reception signal, and the offset control circuit 352 is used when the input signal includes the reception signal. Output a second offset setting signal. The differential signal output from the second differential amplifier circuit 32 is input to the offset control circuit 351, and the adjustment amount of the voltage offset is controlled based on the output of the second differential amplifier circuit 32. One offset control signal is input to the offset control circuit 352 from the outside of the limiting amplification circuit 3-1. The offset control circuit 352 controls the adjustment amount of the voltage offset based on the input offset control signal.
　オフセット制御回路３５１は、例えば、オペアンプを用いた積分回路である。また、オフセット制御回路３５１は、差動信号をサンプリングするＡＤＣ（Analog－to－Digital　Converter）と、差動信号を積分するデジタルフィルタとを備えてもよい。 The offset control circuit 351 is, for example, an integrating circuit using an operational amplifier. The offset control circuit 351 may include an ADC (Analog-to-Digital Converter) that samples the differential signal and a digital filter that integrates the differential signal.
　以上説明したように、本発明の実施の形態２によれば、実施の形態１と同様の効果を奏することが可能であると共に、リミッティング増幅回路３－１に入力するオフセット制御信号の数を１つにすることができる。この場合、リミッティング増幅回路３と比較して、オフセット制御信号の数が低減されるため、リミッティング増幅回路３－１の外部で必要となるメモリ数を削減することが可能であると共に、オフセット制御信号の事前調整が不要となる利点がある。 As described above, according to the second embodiment of the present invention, it is possible to obtain the same effect as that of the first embodiment, and it is possible to reduce the number of offset control signals input to the limiting amplifier circuit 3-1. Can be one. In this case, since the number of offset control signals is reduced as compared with the limiting amplifier circuit 3, it is possible to reduce the number of memories required outside the limiting amplifier circuit 3-1, and also to perform the offset There is an advantage that pre-adjustment of the control signal is unnecessary.
実施の形態３．
　図５は、本発明の実施の形態３にかかるリミッティング増幅回路３－２の構成を示す図である。上記の実施の形態１，２では、信号検出回路３４は、光信号受信時および無信号遷移時のいずれも第１の差動増幅回路３１の出力信号の振幅に基づいて、出力電圧の値を切り替えるタイミングを決定していた。これに対して、実施の形態３では、信号検出回路３４－１は、リミッティング増幅回路３－２の外部から入力されるリセット信号をトリガとして、出力電圧の値を「Ｈｉｇｈ」から「Ｌｏｗ」に遷移させる。つまり、信号検出回路３４－１は、リセット信号を受信すると、第１の差動増幅回路３１が出力する第２の差動信号が受信信号を含まないことを示す判定結果を出力する。 Embodiment 3.
FIG. 5 is a diagram showing a configuration of the limiting amplifier circuit 3-2 according to the third exemplary embodiment of the present invention. In the above-described first and second embodiments, the signal detection circuit 34 determines the value of the output voltage based on the amplitude of the output signal of the first differential amplifier circuit 31 both when the optical signal is received and when there is no signal transition. I had decided when to switch. On the other hand, in the third embodiment, the signal detection circuit 34-1 uses the reset signal input from the outside of the limiting amplification circuit 3-2 as a trigger to change the output voltage value from “High” to “Low”. Transition to. That is, when the signal detection circuit 34-1 receives the reset signal, the signal detection circuit 34-1 outputs a determination result indicating that the second differential signal output from the first differential amplifier circuit 31 does not include the received signal.
　信号検出回路３４－１は、ラッチ回路単体を用いて構成することができる。このため、信号検出回路３４－１の構成を単純にすることができるという利点がある。 The signal detection circuit 34-1 can be configured using a single latch circuit. Therefore, there is an advantage that the configuration of the signal detection circuit 34-1 can be simplified.
　なお、図５では、実施の形態１にかかるリミッティング増幅回路３の信号検出回路３４を、リセット信号に対応する信号検出回路３４－１に代えたリミッティング増幅回路３－２を示したが、本実施の形態はかかる例に限定されない。例えば、リミッティング増幅回路３－１で示した２つのオフセット制御回路３５１，３５２を備える構成において、リセット信号に対応する信号検出回路３４－１を用いてもよい。この場合、実施の形態２と同様に、外部から入力されるオフセット制御信号は１つで済むため、リミッティング増幅回路３－２の外部で必要となるメモリ数を削減することができると共に、オフセット制御信号の事前調整が不要になるという利点がある。 Although FIG. 5 shows the limiting amplification circuit 3-2 in which the signal detection circuit 34 of the limiting amplification circuit 3 according to the first exemplary embodiment is replaced with the signal detection circuit 34-1 corresponding to the reset signal, The present embodiment is not limited to this example. For example, in the configuration including the two offset control circuits 351 and 352 shown in the limiting amplifier circuit 3-1, the signal detection circuit 34-1 corresponding to the reset signal may be used. In this case, as in the second embodiment, only one offset control signal is input from the outside, so that the number of memories required outside the limiting amplifier circuit 3-2 can be reduced and the offset can be reduced. This has the advantage that pre-adjustment of the control signal is unnecessary.
実施の形態４．
　図６は、本発明の実施の形態４にかかるリミッティング増幅回路３－３の構成を示す図である。実施の形態１，２，３では、第１の差動増幅回路３１の出力を信号検出回路３４，３４－１に入力しているのに対し、実施の形態４では、リミッティング増幅回路３－３へ入力される第１の差動信号を第１の差動増幅回路３１に入力する前に分岐して、第３の差動増幅回路３７で増幅して、信号検出回路３４－２に入力する。 Fourth Embodiment
FIG. 6 is a diagram showing a configuration of the limiting amplifier circuit 3-3 according to the fourth exemplary embodiment of the present invention. In the first, second, and third embodiments, the output of the first differential amplifier circuit 31 is input to the signal detection circuits 34, 34-1, whereas in the fourth embodiment, the limiting amplifier circuit 3- 3 is branched before being input to the first differential amplifier circuit 31, is amplified by the third differential amplifier circuit 37, and is input to the signal detection circuit 34-2. To do.
　第３の差動増幅回路３７は、信号検出回路３４－２の前段に配置される。第３の差動増幅回路３７は、第１の差動信号を増幅して信号検出回路３４－２に入力する。信号検出回路３４－２は、第３の差動増幅回路３７の出力する増幅後の第１の差動信号に基づいて、第２の差動信号が受信信号を含むか否かを判定する。 The third differential amplifier circuit 37 is arranged in front of the signal detection circuit 34-2. The third differential amplifier circuit 37 amplifies the first differential signal and inputs it to the signal detection circuit 34-2. The signal detection circuit 34-2 determines whether or not the second differential signal includes the received signal based on the amplified first differential signal output from the third differential amplifier circuit 37.
　図６に示すような構成をとることで、最終的にＣＤＲ５に接続される信号ラインと、信号検出回路３４－２に接続される信号ラインとをリミッティング増幅回路３－３内で分離することが可能になる。このため、それぞれの信号ラインに最適化して各アンプの設定を行うことが可能になるという利点がある。 By adopting the configuration shown in FIG. 6, the signal line finally connected to the CDR5 and the signal line connected to the signal detection circuit 34-2 are separated in the limiting amplifier circuit 3-3. Will be possible. Therefore, there is an advantage that it is possible to optimize each signal line and set each amplifier.
　なお、第３の差動増幅回路３７は、第１の差動増幅回路３１と同様に、出力信号の振幅が入力信号の振幅に依存するリニアアンプである。また、最終的にＣＤＲ５に接続される信号ラインに対して悪影響を及ぼさないのであれば、第３の差動増幅回路３７を介さずに直接信号検出回路３４－２に接続してもよい。 Note that the third differential amplifier circuit 37 is a linear amplifier in which the amplitude of the output signal depends on the amplitude of the input signal, like the first differential amplifier circuit 31. Further, if it does not adversely affect the signal line connected to the CDR 5 finally, the signal line may be directly connected to the signal detection circuit 34-2 without passing through the third differential amplifier circuit 37.
　また、実施の形態４にかかるリミッティング増幅回路３－３は、図６に示す構成に限定されない。例えば、リミッティング増幅回路３－３は、２つのオフセット制御回路３５１，３５２を有してもよいし、信号検出回路３４－２がリセット信号を受け付けてもよい。或いは、リミッティング増幅回路３－３は、２つのオフセット制御回路３５１，３５２を有し、且つ、信号検出回路３４－２がリセット信号を受け付ける構成であってもよい。 The limiting amplifier circuit 3-3 according to the fourth embodiment is not limited to the configuration shown in FIG. For example, the limiting amplifier circuit 3-3 may include two offset control circuits 351, 352, and the signal detection circuit 34-2 may receive the reset signal. Alternatively, the limiting amplifier circuit 3-3 may have two offset control circuits 351 and 352, and the signal detection circuit 34-2 may receive the reset signal.
　以上の実施の形態に示した構成は、本発明の内容の一例を示すものであり、別の公知の技術と組み合わせることも可能であるし、本発明の要旨を逸脱しない範囲で、構成の一部を省略、変更することも可能である。 The configurations shown in the above embodiments are examples of the content of the present invention, and can be combined with other known techniques, and the configurations of the configurations are not departing from the scope of the present invention. It is also possible to omit or change parts.
　１　ＡＰＤ、２　トランスインピーダンスアンプ、３，３－１，３－２，３－３　リミッティング増幅回路、５　ＣＤＲ、３１　第１の差動増幅回路、３２　第２の差動増幅回路、３３　出力バッファ、３４，３４－１，３４－２　信号検出回路、３５，３５１，３５２　オフセット制御回路、３６　スイッチ、３７　第３の差動増幅回路、４１，４２　ＡＣ結合容量、３１１，３１２　終端抵抗、３１３　差動対、３１４，３１５　可変電流源。 1 APD, 2 transimpedance amplifier, 3,3-1,3-2,3-3 limiting amplifier circuit, 5 CDR, 31 first differential amplifier circuit, 32 second differential amplifier circuit, 33 output buffer , 34, 34-1, 34-2 signal detection circuit, 35, 351, 352 offset control circuit, 36 switch, 37 third differential amplification circuit, 41, 42 AC coupling capacitance, 311, 312 termination resistance, 313 difference Dynamic pair, 314, 315, variable current source.

Claims (9)

  1. 　入力される第１の差動信号の正相信号と逆相信号との間の直流電圧成分の差である電圧オフセットを調整する機能を有し、前記第１の差動信号を増幅して、増幅後の信号である第２の差動信号を出力する第１の差動増幅回路と、
    　前記第２の差動信号を予め定められた振幅まで増幅する第２の差動増幅回路と、
    　前記第２の差動信号が受信信号を含むか否かを判定する信号検出回路と、
    　前記信号検出回路の判定結果に基づいて、前記電圧オフセットの調整量を制御するオフセット制御回路と、
    　を備えることを特徴とするリミッティング増幅回路。     It has a function of adjusting a voltage offset which is a difference in DC voltage component between a positive phase signal and a negative phase signal of the input first differential signal, and amplifies the first differential signal, A first differential amplifier circuit that outputs a second differential signal that is a signal after amplification;
    A second differential amplifier circuit for amplifying the second differential signal to a predetermined amplitude;
    A signal detection circuit for determining whether or not the second differential signal includes a reception signal,
    An offset control circuit that controls the adjustment amount of the voltage offset based on the determination result of the signal detection circuit,
    A limiting amplifier circuit comprising:
  2. 　前記信号検出回路は、前記第２の差動信号が受信信号を含まない場合、前記判定結果として受信信号を検出していないことを示す第１の値を出力し、前記第２の差動信号が受信信号を含む場合、前記判定結果として受信信号を検出したことを示す第２の値を出力することを特徴とする請求項１に記載のリミッティング増幅回路。 When the second differential signal does not include a received signal, the signal detection circuit outputs a first value indicating that the received signal is not detected as the determination result, and the second differential signal is output. The limiting amplifier circuit according to claim 1, wherein, when the received signal includes a received signal, a second value indicating that the received signal is detected is output as the determination result.
  3. 　前記オフセット制御回路は、前記判定結果が前記第１の値である場合、前記電圧オフセットを最小化する調整量を示す第１のオフセット設定信号を前記第１の差動増幅回路に入力し、前記判定結果が前記第２の値である場合、前記第１のオフセット設定信号と異なる調整量を示す第２のオフセット設定信号を前記第１の差動増幅回路に入力することを特徴とする請求項２に記載のリミッティング増幅回路。 When the determination result is the first value, the offset control circuit inputs a first offset setting signal indicating an adjustment amount that minimizes the voltage offset to the first differential amplifier circuit, When the determination result is the second value, a second offset setting signal indicating an adjustment amount different from that of the first offset setting signal is input to the first differential amplifier circuit. The limiting amplifier circuit according to item 2.
  4. 　前記信号検出回路は、前記第２の差動信号の振幅が予め定めた閾値よりも大きい場合、前記第２の差動信号が前記受信信号を含むと判定し、前記第２の差動信号の振幅が前記閾値以下である場合、前記第２の差動信号が前記受信信号を含まないと判定することを特徴とする請求項１から３のいずれか１項に記載のリミッティング増幅回路。 When the amplitude of the second differential signal is larger than a predetermined threshold value, the signal detection circuit determines that the second differential signal includes the received signal, and determines whether the second differential signal includes the received signal. The limiting amplifier circuit according to claim 1, wherein when the amplitude is equal to or less than the threshold value, it is determined that the second differential signal does not include the received signal.
  5. 　前記信号検出回路は、前記第２の差動信号の信号パターンと、予め定めた信号パターンとの比較結果に基づいて、前記第２の差動信号が受信信号を含むか否かを判定することを特徴とする請求項１から３のいずれか１項に記載のリミッティング増幅回路。 The signal detection circuit determines whether or not the second differential signal includes a received signal based on a comparison result between the signal pattern of the second differential signal and a predetermined signal pattern. The limiting amplifier circuit according to any one of claims 1 to 3, wherein:
  6. 　前記オフセット制御回路は、外部から入力されるオフセット制御信号に基づいて、前記調整量を制御することを特徴とする請求項１から５のいずれか１項に記載のリミッティング増幅回路。 The limiting amplifier circuit according to any one of claims 1 to 5, wherein the offset control circuit controls the adjustment amount based on an offset control signal input from the outside.
  7. 　前記オフセット制御回路は、前記第２の差動信号が受信信号を含まない場合、前記第２の差動増幅回路の出力に基づいて前記電圧オフセットの調整量を制御し、前記第２の差動信号が受信信号を含む場合、外部から入力されるオフセット制御信号に基づいて前記電圧オフセットの調整量を制御することを特徴とする請求項１から５のいずれか１項に記載のリミッティング増幅回路。 When the second differential signal does not include the received signal, the offset control circuit controls the adjustment amount of the voltage offset based on the output of the second differential amplifier circuit, 6. The limiting amplifier circuit according to claim 1, wherein when the signal includes a reception signal, the adjustment amount of the voltage offset is controlled based on an offset control signal input from the outside. ..
  8. 　前記信号検出回路は、リセット信号を受信すると、前記第２の差動信号が受信信号を含まないことを示す前記判定結果を出力することを特徴とする請求項１から７のいずれか１項に記載のリミッティング増幅回路。 The signal detection circuit, when receiving a reset signal, outputs the determination result indicating that the second differential signal does not include a received signal. The limiting amplifier circuit described.
  9. 　前記信号検出回路の前段に配置され、前記第１の差動信号を増幅する第３の差動増幅回路をさらに備え、
    　前記信号検出回路は、前記第３の差動増幅回路の出力に基づいて、前記第２の差動信号が受信信号を含むか否かを判定することを特徴とする請求項１から３のいずれか１項に記載のリミッティング増幅回路。     Further comprising a third differential amplifier circuit which is arranged in the preceding stage of the signal detection circuit and which amplifies the first differential signal,
    4. The signal detection circuit according to claim 1, wherein the signal detection circuit determines whether or not the second differential signal includes a reception signal based on the output of the third differential amplifier circuit. The limiting amplifier circuit according to item 1.
PCT/JP2019/007672 2019-02-27 2019-02-27 Limiting amplification circuit WO2020174628A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114244441A (en) * 2021-11-09 2022-03-25 云南电网有限责任公司 Optical communication module for power transmission line
WO2022195684A1 (en) * 2021-03-15 2022-09-22 三菱電機株式会社 Optical receiver and station-side device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113114126A (en) * 2021-04-21 2021-07-13 西安交通大学 Eye diagram intersection point adjusting circuit and design method thereof

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08163051A (en) * 1994-12-01 1996-06-21 Nec Corp Burst mode digital receiver
JP2003168933A (en) * 2001-11-30 2003-06-13 Nef:Kk Photoreceiving circuit
JP2009038556A (en) * 2007-08-01 2009-02-19 Ntt Electornics Corp Limiter amplifier circuit
JP2011109721A (en) * 2011-03-03 2011-06-02 Nippon Telegr & Teleph Corp <Ntt> Amplitude limit amplifier circuit
JP2011250137A (en) * 2010-05-27 2011-12-08 Sumitomo Electric Ind Ltd Saturated amplifier circuit
JP2014053835A (en) * 2012-09-10 2014-03-20 Mitsubishi Electric Corp Saturated amplification circuit
JP2016063345A (en) * 2014-09-17 2016-04-25 三菱電機株式会社 Receiver circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3334794B2 (en) * 1999-01-14 2002-10-15 日本電気株式会社 Amplitude limiting amplifier circuit
JP3967065B2 (en) * 2000-06-12 2007-08-29 三菱電機株式会社 Amplifier circuit
JP5861363B2 (en) * 2011-09-30 2016-02-16 住友電気工業株式会社 Amplifier
JP6247150B2 (en) * 2014-05-16 2017-12-13 日本電信電話株式会社 Optical signal receiving apparatus and optical signal receiving method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08163051A (en) * 1994-12-01 1996-06-21 Nec Corp Burst mode digital receiver
JP2003168933A (en) * 2001-11-30 2003-06-13 Nef:Kk Photoreceiving circuit
JP2009038556A (en) * 2007-08-01 2009-02-19 Ntt Electornics Corp Limiter amplifier circuit
JP2011250137A (en) * 2010-05-27 2011-12-08 Sumitomo Electric Ind Ltd Saturated amplifier circuit
JP2011109721A (en) * 2011-03-03 2011-06-02 Nippon Telegr & Teleph Corp <Ntt> Amplitude limit amplifier circuit
JP2014053835A (en) * 2012-09-10 2014-03-20 Mitsubishi Electric Corp Saturated amplification circuit
JP2016063345A (en) * 2014-09-17 2016-04-25 三菱電機株式会社 Receiver circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022195684A1 (en) * 2021-03-15 2022-09-22 三菱電機株式会社 Optical receiver and station-side device
CN114244441A (en) * 2021-11-09 2022-03-25 云南电网有限责任公司 Optical communication module for power transmission line

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