WO2020115874A1 - Error correction decoding device and error correction decoding method - Google Patents

Error correction decoding device and error correction decoding method Download PDF

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Publication number
WO2020115874A1
WO2020115874A1 PCT/JP2018/044968 JP2018044968W WO2020115874A1 WO 2020115874 A1 WO2020115874 A1 WO 2020115874A1 JP 2018044968 W JP2018044968 W JP 2018044968W WO 2020115874 A1 WO2020115874 A1 WO 2020115874A1
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data
error correction
decoding
reliability
result
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PCT/JP2018/044968
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French (fr)
Japanese (ja)
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中村　隆彦
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三菱電機株式会社
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Priority to JP2019518319A priority Critical patent/JP6552776B1/en
Priority to PCT/JP2018/044968 priority patent/WO2020115874A1/en
Publication of WO2020115874A1 publication Critical patent/WO2020115874A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes

Definitions

  • the present invention relates to an error correction decoding device and an error correction decoding method.
  • data is error correction coded to detect errors that occur in the transmission path.
  • the error correction code there is a case where a convolutional code, a turbo code, or the like that can obtain only the information bit portion of the data by decoding is applied to the data.
  • the error correction decoding device that decodes the error correction code performs error detection on the error-correction-decoded data using an error detection code such as CRC (Cyclic Redundancy Check), and when an error is detected, The reliability of the decoding result is improved by retransmitting the data.
  • CRC Cyclic Redundancy Check
  • the present invention has been made in view of the above, and an object thereof is to obtain an error correction decoding device capable of suppressing the decrease in the amount of information that can be transmitted while determining the reliability of the decoding result.
  • an error correction decoding device includes a decoding unit that performs a decoding process of received data that has been error correction coded with a systematic code, and outputs a decoding result, and a received data. It is characterized by further comprising: a comparison unit that determines whether or not the reliability of the decoding result is high by comparing the first data to be reproduced with the decoding result.
  • the error correction decoding apparatus has the effect of making redundant bits for error detection unnecessary by determining the reliability of the decoding result and increasing the amount of information that can be transmitted.
  • FIG. 1 is a diagram showing a configuration of a wireless communication system according to a first exemplary embodiment
  • FIG. 3 is a diagram showing functional blocks of the error correction decoding apparatus according to the first embodiment.
  • FIG. 3 is a diagram showing a control circuit according to the first embodiment.
  • 3 is a flowchart showing the operation of the error correction decoding apparatus according to the first embodiment.
  • FIG. 3 is a diagram showing functional blocks of an error correction decoding device according to a second embodiment. 6 is a flowchart showing the operation of the error correction decoding apparatus according to the second embodiment.
  • FIG. 3 is a diagram showing functional blocks of an error correction decoding device according to a third embodiment. 6 is a flowchart showing the operation of the error correction decoding apparatus according to the third embodiment.
  • FIG. 6 is a diagram showing functional blocks of an error correction decoding device according to a fourth embodiment. Flowchart showing the operation of the error correction decoding apparatus according to the fourth embodiment
  • FIG. 1 is a diagram showing a configuration of a wireless communication system according to the first exemplary embodiment.
  • the wireless communication system 20 includes a transmitting device 30 and a receiving device 40.
  • the transmitting device 30 and the receiving device 40 communicate with each other by a wireless system or a wired system.
  • the transmitter 30 turbo-encodes the data, modulates the turbo-encoded data, and transmits the modulated data to the receiver 40.
  • the receiving device 40 receives the data transmitted from the transmitting device 30.
  • FIG. 2 is a diagram showing functional blocks of the error correction decoding apparatus according to the first embodiment.
  • the error correction decoding device 100 is included in the reception device 40. Alternatively, the error correction decoding device 100 has a function as the reception device 40.
  • the error correction decoding device 100 includes a first storage unit 1, a turbo decoding unit 2, a first comparison unit 3, and a selection unit 4.
  • the received data received by the error correction decoding apparatus 100 is soft decision data demodulated by the demodulation unit.
  • the soft-decision data is composed of hard-decision data that is determined to be 0 or 1, and the reliability of the hard-decision data.
  • the demodulation unit may be included in the error correction decoding device 100, or may be included in a device other than the error correction decoding device 100 included in the reception device 40.
  • the hard decision data is also called the first data.
  • the first storage unit 1 stores information data corresponding to the information bit portion of the hard decision data.
  • the first storage unit 1 transmits the stored information data to the first comparison unit 3.
  • the first comparison unit 3 is also called a comparison unit.
  • the comparison unit determines whether or not the reliability of the decoding result is high by comparing the first data and the decoding result.
  • the turbo decoding unit 2 repeatedly performs a decoding process of turbo decoding on the received data a predetermined number of times.
  • the turbo decoding unit 2 also transmits the decoding result, which is the result of the decoding process, to the first comparison unit 3.
  • the first comparison unit 3 compares the information data with the decoding result, and counts the number of bits whose bits are inverted.
  • the first comparing unit 3 also determines whether the counted value is larger than a predetermined threshold value.
  • the selection unit 4 uses the transmission of the first comparison unit 3 to select and transmit any one of the information data and the decoding result.
  • the turbo decoding unit 2, the first comparison unit 3, and the selection unit 4 are realized by a processing circuit that is an electronic circuit that performs each process.
  • This processing circuit may be dedicated hardware, or may be a control circuit including a memory and a CPU (Central Processing Unit) that executes a program stored in the memory.
  • the memory corresponds to, for example, a nonvolatile or volatile semiconductor memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), and a flash memory, a magnetic disk, an optical disk, and the like.
  • FIG. 3 is a diagram illustrating the control circuit according to the first embodiment.
  • the control circuit is, for example, the control circuit 200 having the configuration shown in FIG.
  • the control circuit 200 includes a processor 200a, which is a CPU, and a memory 200b.
  • a processor 200a which is a CPU
  • a memory 200b When implemented by the control circuit 200 shown in FIG. 3, it is implemented by the processor 200a reading and executing a program stored in the memory 200b and corresponding to each process.
  • the memory 200b is also used as a temporary memory in each processing executed by the processor 200a.
  • the first storage unit 1 is realized by the memory 200b.
  • FIG. 4 is a flowchart showing the operation of the error correction decoding device 100 according to the first embodiment.
  • the error correction decoding apparatus 100 receives the reception data from the demodulation unit provided in the preceding stage of the error correction decoding apparatus 100 (step S1).
  • the first storage unit 1 stores the information data included in the received data (step S2).
  • the turbo decoding unit 2 receives the received data, and convolves the received data with one of the two convolutional coding circuits forming an information bit sequence and a turbo encoder that performs turbo coding included in the transmission device 30.
  • the information bit sequence is called the first bit sequence.
  • the check bit sequence transmitted in order by the transmitter 30 is referred to as a second bit sequence.
  • the check bit sequence interleaved by the transmitter 30 is called a third bit sequence.
  • the turbo decoding unit 2 performs soft input/soft output decoding processing using the first bit sequence and the third bit sequence to generate first information. Further, the turbo decoding unit 2 performs a soft input/soft output decoding process using the first information, the first bit sequence, and the second bit sequence (step S4).
  • the turbo decoding unit 2 performs the process of step S4 a predetermined number of times, generates a decoding result for the reception sequence of the information bit part obtained in the final decoding process, and outputs the decoding result to the first comparing unit 3 and the selecting unit. 4 (step S5).
  • the information generated in step S4 is not the final decoding result of turbo decoding.
  • the operations in steps S3 to S5 are general turbo decoding operations.
  • error correction decoding apparatus 100 does not perform error detection using a CRC code.
  • the first storage unit 1 transmits the information data to the first comparing unit 3 and the selecting unit 4 (step S6).
  • the first comparison unit 3 compares the decoding result with the information data and counts the number of bits that are bit-inverted (step S7). The first comparison unit 3 also determines whether the counted value is larger than a predetermined threshold value (step S8). When the counted value is larger than the threshold value (Yes in step S8), the first signal is transmitted to the selection unit 4 (step S9). When the counted value is not larger than the threshold value (No in step S8), the first comparison unit 3 does not transmit the first signal to the selection unit 4 (step S10).
  • the selection unit 4 determines whether the first signal has been received (step S11). When the first signal is received (step S11, Yes), the selection unit 4 transmits the information data to the functional unit in the subsequent stage (not shown) (step S12). When the first signal is not received (step S11, No), the selection unit 4 transmits the decoding result to the functional unit in the subsequent stage (not shown) (step S13).
  • the first signal is a signal indicating that the decoding result has low reliability
  • the selection unit 4 transmits the information data to the functional unit in the subsequent stage.
  • the first comparison unit 3 Transmits the first signal and the turbo-decoded result to the functional unit in the subsequent stage, and the processing by the functional unit in the subsequent stage determines whether to select the information data or the decoded result obtained by the turbo decoding. Good.
  • the turbo decoding unit 2 If the number of bits that have been bit-inverted is larger than a predetermined threshold value, in general, the turbo decoding unit 2 is highly likely to perform erroneous error correction decoding, and the reliability of the decoding result is low. .. For this reason, it is possible to suppress the use of the decoding result that is erroneously error-corrected by the first comparing unit 3 transmitting the first signal indicating that the reliability of the decoding result is low. Further, by comparing the first data and the decoding result, the reliability of the decoding result can be determined.
  • the decoding process is performed without using the CRC code, the amount of information included in the received data can be increased, and a decrease in the amount of information that the error correction decoding device 100 can transmit can be suppressed.
  • the error correction code is not limited to a turbo code, and any systematic code in which the information bit portion is output to the transmission path may be used. .. If the error correction code is a systematic code, the decoding result and the received sequence are associated with each other, and therefore the same effect as this embodiment can be obtained.
  • FIG. 5 is a diagram showing functional blocks of the error correction decoding apparatus according to the second embodiment.
  • the constituent elements having the same functions as those in the first embodiment are designated by the same reference numerals as those in the first embodiment, and the duplicate description will be omitted.
  • the error correction decoding device 100a includes a first storage unit 1, a turbo decoding unit 2, a selection unit 4, a second storage unit 5, a second comparison unit 6, and a third comparison unit 7. Equipped with.
  • the second storage unit 5 stores the reliability information of the information bit portion included in the received data.
  • the second comparison unit 6 compares the transmission of the first storage unit 1 with the transmission of the turbo decoding unit 2, and transmits the second signal indicating the portion performing the bit inversion to the third comparison unit 7. To do.
  • the third comparison unit 7 adds the reliability information of the position determined to be bit-inverted by the second comparison unit 6 to the reliability of the information bit portion stored in the second storage unit 5, and adds the reliability information. Then, it is compared whether or not the calculated value is larger than a predetermined threshold value.
  • the second comparison unit 6 and the third comparison unit 7 are also collectively referred to as a comparison unit.
  • the second comparison unit 6 and the third comparison unit 7 are realized by a processing circuit that is an electronic circuit that performs each process shown in FIG.
  • the second storage unit 5 is realized by a memory.
  • FIG. 6 is a flowchart showing the operation of the error correction decoding device 100a according to the second embodiment.
  • the first storage unit 1 stores information data (step S21).
  • the second storage unit 5 generates reliability information from the soft decision information of each received data and stores the generated reliability information (step S22).
  • the turbo decoding unit 2 repeats the decoding process a predetermined number of times, generates a decoding result for the reception sequence of the information bit part from the result obtained in the last decoding process, and sends the decoding result to the second comparing unit 6. It is transmitted (step S23).
  • the first storage unit 1 transmits the information data to the second comparison unit 6 at the timing when the decoding result is transmitted (step S24).
  • the second storage unit 5 transmits the reliability information of the information bit portion of the received data to the third comparison unit 7 (step S25).
  • the second comparison unit 6 compares the decoding result transmitted from the turbo decoding unit 2 with the information data stored in the first storage unit 1 (step S26).
  • the second comparison unit 6 also transmits the reliability information of the position where the bit inversion is performed to the third comparison unit 7 (step S27).
  • the third comparison unit 7 adds the reliability information of the bit-inverted position to the reliability of the information bit portion stored in the second storage unit 5, and adds the reliability information based on the value added for the data of one code. It is determined whether the calculated value is larger than a predetermined threshold value (step S28). When the added value is larger than the predetermined threshold value (step S28, Yse), the third comparison unit 7 transmits the first signal to the selection unit 4 (step S29). When the added value is not larger than the predetermined threshold value (step S28, No), the third comparison unit 7 does not transmit the first signal (step S30).
  • the selection unit 4 determines whether the first signal has been received (step S31). When the first signal is received (Yes in step S31), the selection unit 4 transmits the information data read from the first storage unit 1 to the functional unit in the subsequent stage (step S32). When the first signal is not received (step S31, No), the selection unit 4 transmits the decoding result transmitted from the turbo decoding unit 2 to the functional unit at the subsequent stage (step S33).
  • the selection unit 4 when the value obtained by adding the reliability information of the bit-inverted position is larger than a predetermined threshold value, the selection unit 4 transmits the information data to the functional unit in the subsequent stage.
  • the third comparison unit 7 transmits the first signal and the turbo-decoded decoding result to the functional unit at the subsequent stage, and which of the information data and the decoding result is selected by the processing by the functional unit at the subsequent stage. You may make a judgment.
  • the third comparison unit 7 transmits the first signal indicating that the reliability of the decoding result is low, and the decoding result obtained by performing the error correction is used. This can be suppressed, and deterioration of reliability of the decoding result can be suppressed.
  • FIG. 7 is a diagram showing functional blocks of the error correction decoding apparatus according to the third embodiment.
  • the constituent elements having the same functions as those in the first embodiment are designated by the same reference numerals as those in the first embodiment, and the duplicate description will be omitted.
  • the error correction decoding device 100b includes a turbo decoding unit 2, a first comparison unit 3, a selection unit 4, a third storage unit 8, an information bit selection unit 9, and a re-encoding unit 10. ..
  • the third storage unit 8 stores the second data including the information bit and the check bit of the received data.
  • the information bit selection unit 9 selects the information bit portion, that is, the information data, of the second data read from the third storage unit 8 and transmits it to the selection unit 4.
  • the re-encoding unit 10 turbo-encodes the turbo-decoded result again.
  • the third storage unit 8, the information bit selection unit 9, and the re-encoding unit 10 are realized by a processing circuit that is an electronic circuit that performs the processes illustrated in FIG.
  • the third storage unit 8 is realized by a memory.
  • FIG. 8 is a flowchart showing the operation of the error correction decoding apparatus 100b according to the third embodiment.
  • the third storage unit 8 stores the second data included in the received data (step S41).
  • the turbo decoding unit 2 receives the received data, performs the iterative decoding process a predetermined number of times, and transmits the decoding result to the selection unit 4 and the re-encoding unit 10 (step S42).
  • the re-encoding unit 10 re-encodes using the decoding result (step S43).
  • the re-encoding unit 10 also transmits the result of re-encoding to the first comparing unit 3 (step S44).
  • the third storage unit 8 transmits the second data to the first comparison unit 3 at the timing when the re-encoding unit 10 transmits the re-encoding result (step S45).
  • the first comparing unit 3 compares the second data with the result of re-encoding, and counts the number of bits that are bit-inverted (step S46). The first comparison unit 3 determines whether the counted value is larger than a predetermined threshold value (step S47). When the counted value is larger than the predetermined threshold value (step S47, Yes), the first comparison unit 3 transmits the first signal to the selection unit 4 (step S48). When the counted value is not larger than the predetermined value (step S47, No), the first comparing section 3 does not transmit the first signal to the selecting section 4 (step S49).
  • the information bit selection unit 9 receives the second data from the third storage unit 8 and transmits the information bit portion of the second data, that is, the information data to the selection unit 4 (step S50).
  • the selection unit 4 determines whether the first signal has been received (step S51). When the first signal is received (Yes in step S51), the selection unit 4 transmits the information data to the external functional unit (step S52). When the first signal has not been received (step S51, No), the decoding result transmitted from the turbo decoding unit 2 is transmitted to the external functional unit (step S53).
  • the selection unit 4 transmits the information data to the external functional unit.
  • the first comparison unit 3 transmits the first signal and the turbo-decoded result to an external functional unit, and the external functional unit processes either the information data or the turbo-decoded decoding result. You may decide whether to select.
  • the re-encoding unit 10 performs the re-encoding process of the decoding result, only the part generating the check bits is turbo-encoded, and the re-encoding process of receiving the information bits in the interleaved order is not performed.
  • the first comparison unit 3 compares the information bit and the check bit obtained by receiving the information bit in the transmission order and performing the re-encoding process, it is not necessary to perform the interleaving process in the re-encoding process and the delay is reduced. In addition to being small, the same effect of improving the reliability after decoding can be obtained.
  • the first comparison unit 3 transmits the first signal indicating that the reliability of the decoding result is low, and the decoding result obtained by performing the error correction is used. This can be suppressed, and deterioration in reliability of the decoding result can be suppressed.
  • the decoding result is re-encoded, even if an error correction code other than the systematic code is used, the same effect as that when the turbo code is used can be obtained.
  • FIG. 9 is a diagram showing functional blocks of the error correction decoding apparatus according to the fourth embodiment.
  • the constituent elements having the same functions as those in the first to third embodiments are designated by the same reference numerals as those in the first to third embodiments, and the duplicated description will be omitted.
  • the error correction decoding device 100c includes a turbo decoding unit 2, a selection unit 4, a second comparison unit 6, a third comparison unit 7, a third storage unit 8, an information bit selection unit 9, and a re-composition unit.
  • the encoding unit 10 and the fourth storage unit 11 are provided.
  • storage part 11 memorize
  • the fourth storage unit 11 is realized by a memory.
  • FIG. 10 is a flowchart showing the operation of the error correction decoding device 100c according to the fourth embodiment.
  • storage part 11 produces
  • the turbo decoding unit 2 performs iterative decoding processing a predetermined number of times and transmits the decoding result to the selection unit 4 and the re-encoding unit 10 (step S62).
  • the re-encoding unit 10 uses the decoding result to perform re-encoding processing (step S63).
  • the third storage unit 8 transmits the second data to the second comparison unit 6 at the timing when the re-encoding unit 10 transmits the re-encoding result (step S64).
  • the fourth storage unit 11 transmits the reliability information of the soft decision data to the third comparison unit 7 (step S65).
  • the second comparing unit 6 compares the re-encoding result transmitted from the re-encoding unit 10 with the second data, and transmits the reliability information of the bit-inverted position to the third comparing unit 7. Yes (step S66).
  • the third comparison unit 7 adds the reliability information of the bit-inverted position to the reliability of the soft-decision data stored in the fourth storage unit 11, and adds the reliability information of one code based on the added value. It is determined whether the calculated value is larger than a predetermined threshold value (step S67). When the added value is larger than the predetermined threshold value (step S67, Yse), the 3rd comparison part 7 transmits a 1st signal to the selection part 4 (step S68). When the added value is not larger than the predetermined threshold value (step S67, No), the third comparison unit 7 does not transmit the first signal to the selection unit 4 (step S69).
  • the information bit selection unit 9 receives the second data from the third storage unit 8 and transmits the information bit portion of the second data, that is, the information data to the selection unit 4 (step S70).
  • the selection unit 4 determines whether the first signal has been received (step S71). When the selection unit 4 receives the first signal (Yes in step S71), the selection unit 4 transmits the information data to the external functional unit (step S72). When the first signal has not been received (step S71, No), the selection unit 4 transmits the decoding result transmitted from the turbo decoding unit 2 to the external functional unit (step S73).
  • the selection unit 4 when the sum of the reliability values of the bits inverted not only in the information bit portion but also in the check bit portion is larger than a predetermined threshold value, the selection unit 4 outputs the information data to the outside.
  • the third comparison unit 7 transmits the first signal and the result of turbo decoding to the external functional unit, and the information data is processed by the external functional unit. Alternatively, it may be determined which of the turbo decoding results is selected.
  • the re-encoding unit 10 performs the re-encoding process of the decoding result, only the part in which the check bits are generated is turbo-encoded, and the re-encoding process of receiving the information bits in the interleaved order is not performed.
  • the second comparison unit 6 compares the information bit and the check bit obtained by receiving the information bit in the transmission order and performing the re-encoding process, it is not necessary to perform the interleaving process in the re-encoding process, and the delay is reduced. In addition to being small, the same effect of improving the reliability after decoding can be obtained.
  • the reliability of the decoding result is higher than that in the first embodiment.
  • the reliability of the decoding result is higher than that in the first embodiment.
  • the decoding result is re-encoded, even if an error correction code other than the systematic code is used, the same effect as in the case of using the turbo code can be obtained.

Abstract

An error correction decoding device (100) is characterized by being provided with a turbo decoding unit (2) which performs decoding processing of reception data error correction encoded with systematic codes and outputs the decoding result, and a first comparison unit (3) which determines whether the decoding result has high reliability by comparing first data included in the reception data with the decoding result.

Description

誤り訂正復号装置および誤り訂正復号方法Error correction decoding device and error correction decoding method
　本発明は、誤り訂正復号装置および誤り訂正復号方法に関する。 The present invention relates to an error correction decoding device and an error correction decoding method.
　従来の無線通信システムでは、伝送路において生じる誤りを検出するために、データは誤り訂正符号化される。誤り訂正符号としては、復号によりデータの情報ビット部分だけが得られる畳み込み符号、ターボ符号などがデータに適用されている場合がある。この場合、誤り訂正符号を復号する誤り訂正復号装置は、誤り訂正復号処理されたデータに対してＣＲＣ（Cyclic　Redundancy　Check）などの誤り検出符号を用い誤り検出を行い、誤りが検出された場合、データを再送させることにより復号結果の信頼性を向上させている。特許文献１は、ＣＲＣ符号が付加された送信データを用いて誤り訂正復号を行う誤り訂正復号装置を開示する。 In conventional wireless communication systems, data is error correction coded to detect errors that occur in the transmission path. As the error correction code, there is a case where a convolutional code, a turbo code, or the like that can obtain only the information bit portion of the data by decoding is applied to the data. In this case, the error correction decoding device that decodes the error correction code performs error detection on the error-correction-decoded data using an error detection code such as CRC (Cyclic Redundancy Check), and when an error is detected, The reliability of the decoding result is improved by retransmitting the data. Patent Document 1 discloses an error correction decoding device that performs error correction decoding using transmission data to which a CRC code is added.
特開２０１０－２３２９９２号公報JP, 2010-232992, A
　しかしながら、特許文献１に記載の誤り訂正復号装置が受信するデータはＣＲＣ符号を含むため、伝送できる情報量が低下するという問題があった。 However, since the data received by the error correction decoding device described in Patent Document 1 includes a CRC code, there is a problem that the amount of information that can be transmitted is reduced.
　本発明は、上記に鑑みてなされたものであって、復号結果の信頼度の判定をしつつ、伝送できる情報量の低下を抑制することができる誤り訂正復号装置を得ることを目的とする。 The present invention has been made in view of the above, and an object thereof is to obtain an error correction decoding device capable of suppressing the decrease in the amount of information that can be transmitted while determining the reliability of the decoding result.
　上述した課題を解決し、目的を達成するために、誤り訂正復号装置は、組織符号で誤り訂正符号化された受信データの復号処理を行い、復号結果を出力する復号部と、受信データに含まれる第１のデータと、復号結果とを比較することにより、復号結果の信頼度が高いか否かを判定する比較部と、を備えることを特徴とする。 In order to solve the above problems and achieve the object, an error correction decoding device includes a decoding unit that performs a decoding process of received data that has been error correction coded with a systematic code, and outputs a decoding result, and a received data. It is characterized by further comprising: a comparison unit that determines whether or not the reliability of the decoding result is high by comparing the first data to be reproduced with the decoding result.
　本発明にかかる誤り訂正復号装置は、復号結果の信頼度の判定することにより、誤り検出を行うための冗長ビットが不要となり、伝送できる情報量を大きくできる効果がある。 The error correction decoding apparatus according to the present invention has the effect of making redundant bits for error detection unnecessary by determining the reliability of the decoding result and increasing the amount of information that can be transmitted.
実施の形態１にかかる無線通信システムの構成を示す図1 is a diagram showing a configuration of a wireless communication system according to a first exemplary embodiment 実施の形態１にかかる誤り訂正復号装置の機能ブロックを示す図FIG. 3 is a diagram showing functional blocks of the error correction decoding apparatus according to the first embodiment. 実施の形態１にかかる制御回路を示す図FIG. 3 is a diagram showing a control circuit according to the first embodiment. 実施の形態１にかかる誤り訂正復号装置の動作を示すフローチャート3 is a flowchart showing the operation of the error correction decoding apparatus according to the first embodiment. 実施の形態２にかかる誤り訂正復号装置の機能ブロックを示す図FIG. 3 is a diagram showing functional blocks of an error correction decoding device according to a second embodiment. 実施の形態２にかかる誤り訂正復号装置の動作を示すフローチャート6 is a flowchart showing the operation of the error correction decoding apparatus according to the second embodiment. 実施の形態３にかかる誤り訂正復号装置の機能ブロックを示す図FIG. 3 is a diagram showing functional blocks of an error correction decoding device according to a third embodiment. 実施の形態３にかかる誤り訂正復号装置の動作を示すフローチャート6 is a flowchart showing the operation of the error correction decoding apparatus according to the third embodiment. 実施の形態４にかかる誤り訂正復号装置の機能ブロックを示す図FIG. 6 is a diagram showing functional blocks of an error correction decoding device according to a fourth embodiment. 実施の形態４にかかる誤り訂正復号装置の動作を示すフローチャートFlowchart showing the operation of the error correction decoding apparatus according to the fourth embodiment
　以下に、本発明の実施の形態にかかる誤り訂正復号装置および誤り訂正復号方法を図面に基づいて詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。 An error correction decoding device and an error correction decoding method according to an embodiment of the present invention will be described in detail below with reference to the drawings. The present invention is not limited to this embodiment.
実施の形態１．
　図１は、実施の形態１にかかる無線通信システムの構成を示す図である。無線通信システム２０は、送信装置３０と、受信装置４０とを備える。送信装置３０と受信装置４０とは、無線方式または有線方式で通信する。送信装置３０は、データをターボ符号化し、ターボ符号化したデータを変調し受信装置４０に送信する。受信装置４０は、送信装置３０から送信されたデータを受信する。 Embodiment 1.
FIG. 1 is a diagram showing a configuration of a wireless communication system according to the first exemplary embodiment. The wireless communication system 20 includes a transmitting device 30 and a receiving device 40. The transmitting device 30 and the receiving device 40 communicate with each other by a wireless system or a wired system. The transmitter 30 turbo-encodes the data, modulates the turbo-encoded data, and transmits the modulated data to the receiver 40. The receiving device 40 receives the data transmitted from the transmitting device 30.
　図２は、実施の形態１にかかる誤り訂正復号装置の機能ブロックを示す図である。誤り訂正復号装置１００は、受信装置４０に備えられる。または、誤り訂正復号装置１００は、受信装置４０としての機能を有す。誤り訂正復号装置１００は、第１の記憶部１と、ターボ復号部２と、第１の比較部３と、選択部４と、を備える。誤り訂正復号装置１００が受信する受信データは、復調部によって復調された軟判定データである。軟判定データは０または１のいずれかに判定される硬判定データと、硬判定データの信頼度とから構成される。復調部は、誤り訂正復号装置１００に備えられていても良いし、受信装置４０が備える、誤り訂正復号装置１００とは別の装置に備えられても良い。硬判定データは第１のデータとも呼ばれる。第１の記憶部１は、硬判定データの情報ビット部分に相当する情報データを記憶する。また、第１の記憶部１は、記憶した情報データを第１の比較部３に送信する。第１の比較部３は、比較部とも呼ばれる。比較部は、第１のデータと、復号結果とを比較することにより、復号結果の信頼度が高いか否かを判定する。ターボ復号部２は、受信データに対して、あらかじめ定められた回数のターボ復号の復号処理を繰り返し行う。また、ターボ復号部２は、復号処理の結果である復号結果を第１の比較部３に送信する。第１の比較部３は、情報データと復号結果とを比較して、ビットが反転しているビット数をカウントする。また、第１の比較部３は、カウントした値があらかじめ定められている閾値よりも大きいか判定する。選択部４は、第１の比較部３の送信を用いて、情報データ、復号結果のいずれか１つを選択し送信する。 FIG. 2 is a diagram showing functional blocks of the error correction decoding apparatus according to the first embodiment. The error correction decoding device 100 is included in the reception device 40. Alternatively, the error correction decoding device 100 has a function as the reception device 40. The error correction decoding device 100 includes a first storage unit 1, a turbo decoding unit 2, a first comparison unit 3, and a selection unit 4. The received data received by the error correction decoding apparatus 100 is soft decision data demodulated by the demodulation unit. The soft-decision data is composed of hard-decision data that is determined to be 0 or 1, and the reliability of the hard-decision data. The demodulation unit may be included in the error correction decoding device 100, or may be included in a device other than the error correction decoding device 100 included in the reception device 40. The hard decision data is also called the first data. The first storage unit 1 stores information data corresponding to the information bit portion of the hard decision data. In addition, the first storage unit 1 transmits the stored information data to the first comparison unit 3. The first comparison unit 3 is also called a comparison unit. The comparison unit determines whether or not the reliability of the decoding result is high by comparing the first data and the decoding result. The turbo decoding unit 2 repeatedly performs a decoding process of turbo decoding on the received data a predetermined number of times. The turbo decoding unit 2 also transmits the decoding result, which is the result of the decoding process, to the first comparison unit 3. The first comparison unit 3 compares the information data with the decoding result, and counts the number of bits whose bits are inverted. The first comparing unit 3 also determines whether the counted value is larger than a predetermined threshold value. The selection unit 4 uses the transmission of the first comparison unit 3 to select and transmit any one of the information data and the decoding result.
　ターボ復号部２、第１の比較部３、および選択部４は、各処理を行う電子回路である処理回路により実現される。 The turbo decoding unit 2, the first comparison unit 3, and the selection unit 4 are realized by a processing circuit that is an electronic circuit that performs each process.
　本処理回路は、専用のハードウェアであっても、メモリ及びメモリに格納されるプログラムを実行するＣＰＵ（Central　Processing　Unit、中央演算装置）を備える制御回路であってもよい。ここでメモリとは、例えば、ＲＡＭ（Random　Access　Memory）、ＲＯＭ（Read　Only　Memory）、フラッシュメモリなどの、不揮発性または揮発性の半導体メモリ、磁気ディスク、光ディスクなどが該当する。図３は、実施の形態１にかかる制御回路を示す図である。本処理回路がＣＰＵを備える制御回路である場合、この制御回路は例えば、図３に示す構成の制御回路２００となる。 This processing circuit may be dedicated hardware, or may be a control circuit including a memory and a CPU (Central Processing Unit) that executes a program stored in the memory. Here, the memory corresponds to, for example, a nonvolatile or volatile semiconductor memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), and a flash memory, a magnetic disk, an optical disk, and the like. FIG. 3 is a diagram illustrating the control circuit according to the first embodiment. When the processing circuit is a control circuit including a CPU, the control circuit is, for example, the control circuit 200 having the configuration shown in FIG.
　図３に示すように、制御回路２００は、ＣＰＵであるプロセッサ２００ａと、メモリ２００ｂとを備える。図３に示す制御回路２００により実現される場合、プロセッサ２００ａがメモリ２００ｂに記憶された、各処理に対応するプログラムを読みだして実行することにより実現される。また、メモリ２００ｂは、プロセッサ２００ａが実施する各処理における一時メモリとしても使用される。第１の記憶部１は、メモリ２００ｂにより実現される。 As shown in FIG. 3, the control circuit 200 includes a processor 200a, which is a CPU, and a memory 200b. When implemented by the control circuit 200 shown in FIG. 3, it is implemented by the processor 200a reading and executing a program stored in the memory 200b and corresponding to each process. The memory 200b is also used as a temporary memory in each processing executed by the processor 200a. The first storage unit 1 is realized by the memory 200b.
　次に、誤り訂正復号装置１００の動作について説明する。図４は、実施の形態１にかかる誤り訂正復号装置１００の動作を示すフローチャートである。誤り訂正復号装置１００は、誤り訂正復号装置１００の前段に設けられる復調部から受信データを受信する（ステップＳ１）。第１の記憶部１は、受信データに含まれる情報データを記憶する（ステップＳ２）。また、ターボ復号部２は受信データを受信し、受信データを、情報ビット系列と、送信装置３０が備えるターボ符号化を行うターボ符号器を構成する２つの畳み込み符号化回路のうちの一方の畳み込み符号化回路によって符号化し送信された順の検査ビット系列と、送信装置３０によってインタリーブした後に２つの畳み込み符号化回路のうちの他方の畳み込み符号化回路によって符号化し送信された検査ビット系列と、の３つの系列に分離する（ステップＳ３）。この３つの系列は、送信装置３０によってターボ符号化されたデータであり、誤り訂正復号装置１００に送信するデータである。情報ビット系列を第１のビット系列と呼ぶ。送信装置３０によって送信された順の検査ビット系列を第２のビット系列と呼ぶ。送信装置３０によってインタリーブされた検査ビット系列を第３のビット系列と呼ぶ。 Next, the operation of the error correction decoding device 100 will be described. FIG. 4 is a flowchart showing the operation of the error correction decoding device 100 according to the first embodiment. The error correction decoding apparatus 100 receives the reception data from the demodulation unit provided in the preceding stage of the error correction decoding apparatus 100 (step S1). The first storage unit 1 stores the information data included in the received data (step S2). In addition, the turbo decoding unit 2 receives the received data, and convolves the received data with one of the two convolutional coding circuits forming an information bit sequence and a turbo encoder that performs turbo coding included in the transmission device 30. A check bit sequence in the order encoded and transmitted by the encoding circuit, and a check bit sequence encoded and transmitted by the other convolutional encoding circuit of the two convolutional encoding circuits after being interleaved by the transmission device 30. It is separated into three series (step S3). These three sequences are data that have been turbo-encoded by the transmission device 30 and are data that will be transmitted to the error correction decoding device 100. The information bit sequence is called the first bit sequence. The check bit sequence transmitted in order by the transmitter 30 is referred to as a second bit sequence. The check bit sequence interleaved by the transmitter 30 is called a third bit sequence.
　ターボ復号部２は、第１のビット系列と、第３のビット系列とを用いて軟入力軟出力の復号処理を行い第１の情報を生成する。また、ターボ復号部２は、第１の情報と第１のビット系列と第２のビット系列とを用いて軟入力軟出力の復号処理を行う（ステップＳ４）。ターボ復号部２は、ステップＳ４の処理をあらかじめ定められた回数行い、最後の復号処理で得られる情報ビット部分の受信系列に対する復号結果を生成し、復号結果を第１の比較部３および選択部４に送信する（ステップＳ５）。なお、ステップＳ４で生成された情報はターボ復号による最終的な復号結果ではない。なお、ステップＳ３からステップＳ５の動作は一般的なターボ復号の動作である。また、本実施の形態では、誤り訂正復号装置１００は、ＣＲＣ符号を用いた誤り検出をしない。第１の記憶部１は、復号結果がターボ復号部２から送信されるときに、情報データを第１の比較部３および選択部４に送信する（ステップＳ６）。 The turbo decoding unit 2 performs soft input/soft output decoding processing using the first bit sequence and the third bit sequence to generate first information. Further, the turbo decoding unit 2 performs a soft input/soft output decoding process using the first information, the first bit sequence, and the second bit sequence (step S4). The turbo decoding unit 2 performs the process of step S4 a predetermined number of times, generates a decoding result for the reception sequence of the information bit part obtained in the final decoding process, and outputs the decoding result to the first comparing unit 3 and the selecting unit. 4 (step S5). The information generated in step S4 is not the final decoding result of turbo decoding. The operations in steps S3 to S5 are general turbo decoding operations. Further, in the present embodiment, error correction decoding apparatus 100 does not perform error detection using a CRC code. When the decoding result is transmitted from the turbo decoding unit 2, the first storage unit 1 transmits the information data to the first comparing unit 3 and the selecting unit 4 (step S6).
　第１の比較部３は、復号結果と情報データとを比較し、ビット反転しているビット数をカウントする（ステップＳ７）。また、第１の比較部３は、カウントした値があらかじめ定められた閾値より大きいか判定する（ステップＳ８）。カウントした値が閾値よりも大きい場合（ステップＳ８，Ｙｅｓ）、第１の信号を選択部４に送信する（ステップＳ９）。カウントした値が閾値よりも大きくない場合（ステップＳ８，Ｎｏ）、第１の比較部３は、第１の信号を選択部４に送信しない（ステップＳ１０）。選択部４は、第１の信号を受信したか判定する（ステップＳ１１）。第１の信号を受信した場合（ステップＳ１１，Ｙｅｓ）、選択部４は、情報データを図示しない後段の機能部に送信する（ステップＳ１２）。第１の信号を受信しない場合（ステップＳ１１，Ｎｏ）、選択部４は、復号結果を図示しない後段の機能部に送信する（ステップＳ１３）。第１の信号は、復号結果の信頼度が低いことを示す信号である。 The first comparison unit 3 compares the decoding result with the information data and counts the number of bits that are bit-inverted (step S7). The first comparison unit 3 also determines whether the counted value is larger than a predetermined threshold value (step S8). When the counted value is larger than the threshold value (Yes in step S8), the first signal is transmitted to the selection unit 4 (step S9). When the counted value is not larger than the threshold value (No in step S8), the first comparison unit 3 does not transmit the first signal to the selection unit 4 (step S10). The selection unit 4 determines whether the first signal has been received (step S11). When the first signal is received (step S11, Yes), the selection unit 4 transmits the information data to the functional unit in the subsequent stage (not shown) (step S12). When the first signal is not received (step S11, No), the selection unit 4 transmits the decoding result to the functional unit in the subsequent stage (not shown) (step S13). The first signal is a signal indicating that the decoding result has low reliability.
　また、本実施の形態ではビット反転したビット数があらかじめ定められた閾値よりも大きい場合、選択部４は情報データを後段の機能部に送信するが、これに加えて、第１の比較部３が第１の信号とターボ復号化した結果とを後段の機能部に送信し、後段の機能部による処理で、情報データ、ターボ復号化した復号結果のどちらを選択するか判断するようにしてもよい。 In addition, in the present embodiment, when the number of bits that have been bit-inverted is larger than a predetermined threshold value, the selection unit 4 transmits the information data to the functional unit in the subsequent stage. In addition to this, the first comparison unit 3 Transmits the first signal and the turbo-decoded result to the functional unit in the subsequent stage, and the processing by the functional unit in the subsequent stage determines whether to select the information data or the decoded result obtained by the turbo decoding. Good.
　ビット反転したビット数があらかじめ定められた閾値よりも大きい場合、一般的には、ターボ復号部２は誤った誤り訂正復号を行っている可能性が高くなり、復号結果としての信頼性が低くなる。このため、復号結果の信頼度が低いことを示す第１の信号を第１の比較部３が送信することにより、誤った誤り訂正を行った復号結果が用いられることを抑制することができる。また、第１のデータと復号結果とを比較することにより、復号結果の信頼度の判定をすることができる。また、ＣＲＣ符号を用いず復号処理を行うため、受信データに含まれる情報量を多くすることができ、誤り訂正復号装置１００が伝送できる情報量の低下を抑制することができる。なお、本実施の形態では、誤り訂正符号がターボ符号である場合について説明したが、誤り訂正符号はターボ符号に限定されず、情報ビットの部分が伝送路に出力される組織符号であればよい。誤り訂正符号が組織符号であれば、復号結果と受信系列との対応が付くため、本実施の形態と同様の効果を奏することができる。 If the number of bits that have been bit-inverted is larger than a predetermined threshold value, in general, the turbo decoding unit 2 is highly likely to perform erroneous error correction decoding, and the reliability of the decoding result is low. .. For this reason, it is possible to suppress the use of the decoding result that is erroneously error-corrected by the first comparing unit 3 transmitting the first signal indicating that the reliability of the decoding result is low. Further, by comparing the first data and the decoding result, the reliability of the decoding result can be determined. Moreover, since the decoding process is performed without using the CRC code, the amount of information included in the received data can be increased, and a decrease in the amount of information that the error correction decoding device 100 can transmit can be suppressed. It should be noted that although a case has been described with the present embodiment where the error correction code is a turbo code, the error correction code is not limited to a turbo code, and any systematic code in which the information bit portion is output to the transmission path may be used. .. If the error correction code is a systematic code, the decoding result and the received sequence are associated with each other, and therefore the same effect as this embodiment can be obtained.
実施の形態２．
　図５は、実施の形態２にかかる誤り訂正復号装置の機能ブロックを示す図である。なお、実施の形態１と同一の機能を有する構成要素は、実施の形態１と同一の符号を付して重複する説明を省略する。誤り訂正復号装置１００ａは、第１の記憶部１と、ターボ復号部２と、選択部４と、第２の記憶部５と、第２の比較部６と、第３の比較部７と、を備える。第２の記憶部５は、受信データに含まれる情報ビット部分の信頼度情報を記憶する。第２の比較部６は、第１の記憶部１の送信とターボ復号部２の送信とを比較し、ビット反転を行っている部分を示す第２の信号を第３の比較部７に送信する。第３の比較部７は、第２の比較部６においてビット反転されていると判断された位置の信頼度情報を第２の記憶部５が記憶する情報ビット部分の信頼度に加算し、加算した値があらかじめ定められている閾値よりも大きいかを比較する。第２の比較部６と第３の比較部７とは、合わせて比較部とも呼ばれる。第２の比較部６、および第３の比較部７は、図３に示される各処理を行う電子回路である処理回路により実現される。第２の記憶部５は、メモリにより実現される。 Embodiment 2.
FIG. 5 is a diagram showing functional blocks of the error correction decoding apparatus according to the second embodiment. The constituent elements having the same functions as those in the first embodiment are designated by the same reference numerals as those in the first embodiment, and the duplicate description will be omitted. The error correction decoding device 100a includes a first storage unit 1, a turbo decoding unit 2, a selection unit 4, a second storage unit 5, a second comparison unit 6, and a third comparison unit 7. Equipped with. The second storage unit 5 stores the reliability information of the information bit portion included in the received data. The second comparison unit 6 compares the transmission of the first storage unit 1 with the transmission of the turbo decoding unit 2, and transmits the second signal indicating the portion performing the bit inversion to the third comparison unit 7. To do. The third comparison unit 7 adds the reliability information of the position determined to be bit-inverted by the second comparison unit 6 to the reliability of the information bit portion stored in the second storage unit 5, and adds the reliability information. Then, it is compared whether or not the calculated value is larger than a predetermined threshold value. The second comparison unit 6 and the third comparison unit 7 are also collectively referred to as a comparison unit. The second comparison unit 6 and the third comparison unit 7 are realized by a processing circuit that is an electronic circuit that performs each process shown in FIG. The second storage unit 5 is realized by a memory.
　次に動作について説明する。図６は、実施の形態２にかかる誤り訂正復号装置１００ａの動作を示すフローチャートである。第１の記憶部１は、情報データを記憶する（ステップＳ２１）。第２の記憶部５は各受信データの軟判定情報から信頼度情報を生成し、生成した信頼度情報を記憶する（ステップＳ２２）。ターボ復号部２は、あらかじめ定められた回数の復号処理を繰り返し行い、最後の復号処理で得られる結果から情報ビット部分の受信系列に対する復号結果を生成し、復号結果を第２の比較部６に送信する（ステップＳ２３）。このときに、復号結果が送信されるタイミングに合わせて、第１の記憶部１は、情報データを第２の比較部６に送信する（ステップＳ２４）。第２の記憶部５は、受信データの情報ビット部分の信頼度情報を第３の比較部７に送信する（ステップＳ２５）。 Next, the operation will be explained. FIG. 6 is a flowchart showing the operation of the error correction decoding device 100a according to the second embodiment. The first storage unit 1 stores information data (step S21). The second storage unit 5 generates reliability information from the soft decision information of each received data and stores the generated reliability information (step S22). The turbo decoding unit 2 repeats the decoding process a predetermined number of times, generates a decoding result for the reception sequence of the information bit part from the result obtained in the last decoding process, and sends the decoding result to the second comparing unit 6. It is transmitted (step S23). At this time, the first storage unit 1 transmits the information data to the second comparison unit 6 at the timing when the decoding result is transmitted (step S24). The second storage unit 5 transmits the reliability information of the information bit portion of the received data to the third comparison unit 7 (step S25).
　第２の比較部６は、ターボ復号部２から送信された復号結果と第１の記憶部１に記憶されている情報データとを比較する（ステップＳ２６）。また、第２の比較部６は、ビット反転を行っている位置の信頼度情報を第３の比較部７に送信する（ステップＳ２７）。第３の比較部７は、ビット反転した位置の信頼度情報を第２の記憶部５が記憶する情報ビット部分の信頼度に加算し、１符号分のデータについて加算した値に基づいて、加算した値があらかじめ定められた閾値よりも大きいか判定する（ステップＳ２８）。加算した値があらかじめ定められた閾値よりも大きい場合（ステップＳ２８，Ｙｓｅ）、第３の比較部７は、第１の信号を選択部４に送信する（ステップＳ２９）。加算した値があらかじめ定められた閾値よりも大きくない場合（ステップＳ２８，Ｎｏ）、第３の比較部７は、第１の信号を送信しない（ステップＳ３０）。 The second comparison unit 6 compares the decoding result transmitted from the turbo decoding unit 2 with the information data stored in the first storage unit 1 (step S26). The second comparison unit 6 also transmits the reliability information of the position where the bit inversion is performed to the third comparison unit 7 (step S27). The third comparison unit 7 adds the reliability information of the bit-inverted position to the reliability of the information bit portion stored in the second storage unit 5, and adds the reliability information based on the value added for the data of one code. It is determined whether the calculated value is larger than a predetermined threshold value (step S28). When the added value is larger than the predetermined threshold value (step S28, Yse), the third comparison unit 7 transmits the first signal to the selection unit 4 (step S29). When the added value is not larger than the predetermined threshold value (step S28, No), the third comparison unit 7 does not transmit the first signal (step S30).
　選択部４は第１の信号を受信したか判定する（ステップＳ３１）。第１の信号を受信した場合（ステップＳ３１，Ｙｅｓ）、選択部４は、第１の記憶部１から読み出された情報データを後段の機能部に送信する（ステップＳ３２）。第１の信号を受信しない場合（ステップＳ３１，Ｎｏ）、選択部４は、ターボ復号部２から送信された復号結果を後段の機能部に送信する（ステップＳ３３）。 The selection unit 4 determines whether the first signal has been received (step S31). When the first signal is received (Yes in step S31), the selection unit 4 transmits the information data read from the first storage unit 1 to the functional unit in the subsequent stage (step S32). When the first signal is not received (step S31, No), the selection unit 4 transmits the decoding result transmitted from the turbo decoding unit 2 to the functional unit at the subsequent stage (step S33).
　また、実施の形態２ではビット反転した位置の信頼度情報を加算した値が、あらかじめ定められた閾値よりも大きい場合、選択部４は、情報データを後段の機能部に送信するが、これに加えて、第３の比較部７が第１の信号とターボ復号化した復号結果とを後段の機能部に送信し、後段の機能部による処理で、情報データ、復号結果のどちらを選択するか判断するようにしてもよい。 In addition, in the second embodiment, when the value obtained by adding the reliability information of the bit-inverted position is larger than a predetermined threshold value, the selection unit 4 transmits the information data to the functional unit in the subsequent stage. In addition, the third comparison unit 7 transmits the first signal and the turbo-decoded decoding result to the functional unit at the subsequent stage, and which of the information data and the decoding result is selected by the processing by the functional unit at the subsequent stage. You may make a judgment.
　ビット反転した位置の信頼度情報を加算した値が、あらかじめ定められた閾値よりも大きい場合は、実施の形態１で説明したビット個数の場合よりも誤った誤り訂正復号を行っている可能性が高くなり、復号結果の信頼性が低くなる。このため、実施の形態１の効果に加えて、復号結果の信頼度が低いことを示す第１の信号を第３の比較部７が送信し、誤った誤り訂正を行った復号結果が用いられることを抑制することができ、復号結果の信頼性の低下を抑制することができる。 If the value obtained by adding the reliability information of the bit-inverted position is larger than a predetermined threshold value, there is a possibility that error correction decoding is performed more incorrectly than in the case of the number of bits described in the first embodiment. However, the decoding result becomes less reliable. For this reason, in addition to the effect of the first embodiment, the third comparison unit 7 transmits the first signal indicating that the reliability of the decoding result is low, and the decoding result obtained by performing the error correction is used. This can be suppressed, and deterioration of reliability of the decoding result can be suppressed.
実施の形態３．
　図７は、実施の形態３にかかる誤り訂正復号装置の機能ブロックを示す図である。なお、実施の形態１と同一の機能を有する構成要素は、実施の形態１と同一の符号を付して重複する説明を省略する。誤り訂正復号装置１００ｂは、ターボ復号部２と、第１の比較部３と、選択部４と、第３の記憶部８と、情報ビット選択部９と、再符号化部１０と、を備える。第３の記憶部８は、受信データのうちの情報ビットおよびチェックビットを含む第２のデータを記憶する。情報ビット選択部９は、第３の記憶部８から読み出した第２のデータのうち情報ビット部分つまり情報データを選択し、選択部４に送信する。再符号化部１０は、ターボ復号化された結果を再度ターボ符号化する。第３の記憶部８、情報ビット選択部９、および再符号化部１０は、図３に示される各処理を行う電子回路である処理回路により実現される。第３の記憶部８は、メモリにより実現される。 Embodiment 3.
FIG. 7 is a diagram showing functional blocks of the error correction decoding apparatus according to the third embodiment. The constituent elements having the same functions as those in the first embodiment are designated by the same reference numerals as those in the first embodiment, and the duplicate description will be omitted. The error correction decoding device 100b includes a turbo decoding unit 2, a first comparison unit 3, a selection unit 4, a third storage unit 8, an information bit selection unit 9, and a re-encoding unit 10. .. The third storage unit 8 stores the second data including the information bit and the check bit of the received data. The information bit selection unit 9 selects the information bit portion, that is, the information data, of the second data read from the third storage unit 8 and transmits it to the selection unit 4. The re-encoding unit 10 turbo-encodes the turbo-decoded result again. The third storage unit 8, the information bit selection unit 9, and the re-encoding unit 10 are realized by a processing circuit that is an electronic circuit that performs the processes illustrated in FIG. The third storage unit 8 is realized by a memory.
　次に動作について説明する。図８は、実施の形態３にかかる誤り訂正復号装置１００ｂの動作を示すフローチャートである。第３の記憶部８は、受信データに含まれる第２のデータを記憶する（ステップＳ４１）。ターボ復号部２は、受信データを受信し、あらかじめ定められた回数の繰り返し復号処理を行ない、選択部４および再符号化部１０に復号結果を送信する（ステップＳ４２）。再符号化部１０は、復号結果を用いて再符号化を行う（ステップＳ４３）。また、再符号化部１０は、再符号化の結果を第１の比較部３に送信する（ステップＳ４４）。第３の記憶部８は、再符号化部１０が再符号化の結果を送信するタイミングに合わせて第２のデータを第１の比較部３に送信する（ステップＳ４５）。 Next, the operation will be explained. FIG. 8 is a flowchart showing the operation of the error correction decoding apparatus 100b according to the third embodiment. The third storage unit 8 stores the second data included in the received data (step S41). The turbo decoding unit 2 receives the received data, performs the iterative decoding process a predetermined number of times, and transmits the decoding result to the selection unit 4 and the re-encoding unit 10 (step S42). The re-encoding unit 10 re-encodes using the decoding result (step S43). The re-encoding unit 10 also transmits the result of re-encoding to the first comparing unit 3 (step S44). The third storage unit 8 transmits the second data to the first comparison unit 3 at the timing when the re-encoding unit 10 transmits the re-encoding result (step S45).
　第１の比較部３は、第２のデータと再符号化の結果とを比較し、ビット反転しているビット数をカウントする（ステップＳ４６）。第１の比較部３は、カウントした値があらかじめ定められた閾値よりも大きいか判定する（ステップＳ４７）。カウントした値があらかじめ定められた閾値よりも大きい場合（ステップＳ４７，Ｙｅｓ）、第１の比較部３は、第１の信号を選択部４に送信する（ステップＳ４８）。カウントした値があらかじめ定められた値よりも大きくない場合（ステップＳ４７，Ｎｏ）、第１の比較部３は、第１の信号を選択部４に送信しない（ステップＳ４９）。 The first comparing unit 3 compares the second data with the result of re-encoding, and counts the number of bits that are bit-inverted (step S46). The first comparison unit 3 determines whether the counted value is larger than a predetermined threshold value (step S47). When the counted value is larger than the predetermined threshold value (step S47, Yes), the first comparison unit 3 transmits the first signal to the selection unit 4 (step S48). When the counted value is not larger than the predetermined value (step S47, No), the first comparing section 3 does not transmit the first signal to the selecting section 4 (step S49).
　情報ビット選択部９は、第３の記憶部８から第２のデータを受信し、第２のデータの情報ビット部分、つまり情報データを選択部４に送信する（ステップＳ５０）。選択部４は、第１の信号を受信したか判定する（ステップＳ５１）。第１の信号を受信した場合（ステップＳ５１，Ｙｅｓ）、選択部４は、情報データを外部の機能部に送信する（ステップＳ５２）。第１の信号を受信していない場合（ステップＳ５１，Ｎｏ）、ターボ復号部２から送信される復号結果を外部の機能部に送信する（ステップＳ５３）。 The information bit selection unit 9 receives the second data from the third storage unit 8 and transmits the information bit portion of the second data, that is, the information data to the selection unit 4 (step S50). The selection unit 4 determines whether the first signal has been received (step S51). When the first signal is received (Yes in step S51), the selection unit 4 transmits the information data to the external functional unit (step S52). When the first signal has not been received (step S51, No), the decoding result transmitted from the turbo decoding unit 2 is transmitted to the external functional unit (step S53).
　また、本実施の形態ではチェックビットを含めた状態でビット反転したビット数が、あらかじめ定められた閾値よりも大きい場合、選択部４は、情報データを外部の機能部に送信するが、これに加えて、第１の比較部３が第１の信号とターボ復号化した結果とを外部の機能部に送信し、外部の機能部による処理で、情報データ、ターボ復号化した復号結果のどちらを選択するか判断するようにしてもよい。 Further, in the present embodiment, when the number of bits inverted with the check bit included is larger than a predetermined threshold value, the selection unit 4 transmits the information data to the external functional unit. In addition, the first comparison unit 3 transmits the first signal and the turbo-decoded result to an external functional unit, and the external functional unit processes either the information data or the turbo-decoded decoding result. You may decide whether to select.
　また、再符号化部１０が復号結果の再符号化処理を行うときに、チェックビットを生成している一部分だけをターボ符号化し、情報ビットをインタリーブ順に受信する再符号化処理は行わずに、情報ビットと情報ビットを送信順に受信して再符号化処理を行って得られるチェックビットとを、第１の比較部３で比較を行うと再符号化処理でインタリーブ処理を行う必要がなくなり遅延を小さくできたうえで、同様の復号後の信頼度を向上させる効果が得られる。 Further, when the re-encoding unit 10 performs the re-encoding process of the decoding result, only the part generating the check bits is turbo-encoded, and the re-encoding process of receiving the information bits in the interleaved order is not performed, When the first comparison unit 3 compares the information bit and the check bit obtained by receiving the information bit in the transmission order and performing the re-encoding process, it is not necessary to perform the interleaving process in the re-encoding process and the delay is reduced. In addition to being small, the same effect of improving the reliability after decoding can be obtained.
　チェックビットを含めた状態でビット反転したビット数があらかじめ定められた閾値よりも大きい場合、一般的には誤った誤り訂正復号を行っている可能性が高くなり、復号結果としての信頼性が低くなる。このため、実施の形態１の効果に加えて、復号結果の信頼度が低いことを示す第１の信号を第１の比較部３が送信し、誤った誤り訂正を行った復号結果が用いられることを抑制することができ、復号結果の信頼性が低下することを抑制することができる。なお、本実施の形態では、復号結果に対し再符号化を行っているため、組織符号以外の誤り訂正符号を用いてもターボ符号を用いた場合と同様の効果を奏することができる。 If the number of bits that are bit-inverted with check bits included is larger than a predetermined threshold value, it is generally more likely that erroneous error correction decoding has been performed and the reliability of the decoding result is low. Become. Therefore, in addition to the effect of the first embodiment, the first comparison unit 3 transmits the first signal indicating that the reliability of the decoding result is low, and the decoding result obtained by performing the error correction is used. This can be suppressed, and deterioration in reliability of the decoding result can be suppressed. In addition, in the present embodiment, since the decoding result is re-encoded, even if an error correction code other than the systematic code is used, the same effect as that when the turbo code is used can be obtained.
実施の形態４．
　図９は、実施の形態４にかかる誤り訂正復号装置の機能ブロックを示す図である。なお、実施の形態１～３と同一の機能を有する構成要素は、実施の形態１～３と同一の符号を付して重複する説明を省略する。誤り訂正復号装置１００ｃは、ターボ復号部２と、選択部４と、第２の比較部６と、第３の比較部７と、第３の記憶部８と、情報ビット選択部９と、再符号化部１０と、第４の記憶部１１と、を備える。第４の記憶部１１は、軟判定データの信頼度情報を記憶する。第４の記憶部１１は、メモリにより実現される。 Fourth Embodiment
FIG. 9 is a diagram showing functional blocks of the error correction decoding apparatus according to the fourth embodiment. The constituent elements having the same functions as those in the first to third embodiments are designated by the same reference numerals as those in the first to third embodiments, and the duplicated description will be omitted. The error correction decoding device 100c includes a turbo decoding unit 2, a selection unit 4, a second comparison unit 6, a third comparison unit 7, a third storage unit 8, an information bit selection unit 9, and a re-composition unit. The encoding unit 10 and the fourth storage unit 11 are provided. The 4th memory|storage part 11 memorize|stores the reliability information of soft decision data. The fourth storage unit 11 is realized by a memory.
　次に動作について説明する。図１０は、実施の形態４にかかる誤り訂正復号装置１００ｃの動作を示すフローチャートである。第４の記憶部１１は、受信データのうちの軟判定データの信頼度情報を生成し記憶する（ステップＳ６１）。ターボ復号部２は、あらかじめ定められた回数の繰り返し復号処理を行ない、復号結果を選択部４および再符号化部１０に送信する（ステップＳ６２）。再符号化部１０は復号結果を用いて、再符号化処理を行う（ステップＳ６３）。再符号化部１０が再符号化の結果を送信するタイミングに合わせて、第３の記憶部８は第２のデータを第２の比較部６に送信する（ステップＳ６４）。第４の記憶部１１は、軟判定データの信頼度情報を第３の比較部７に送信する（ステップＳ６５）。 Next, the operation will be explained. FIG. 10 is a flowchart showing the operation of the error correction decoding device 100c according to the fourth embodiment. The 4th memory|storage part 11 produces|generates and memorize|stores the reliability information of the soft decision data of received data. The turbo decoding unit 2 performs iterative decoding processing a predetermined number of times and transmits the decoding result to the selection unit 4 and the re-encoding unit 10 (step S62). The re-encoding unit 10 uses the decoding result to perform re-encoding processing (step S63). The third storage unit 8 transmits the second data to the second comparison unit 6 at the timing when the re-encoding unit 10 transmits the re-encoding result (step S64). The fourth storage unit 11 transmits the reliability information of the soft decision data to the third comparison unit 7 (step S65).
　第２の比較部６は、再符号化部１０から送信された再符号化の結果と、第２のデータとを比較し、ビット反転した位置の信頼度情報を第３の比較部７に送信する（ステップＳ６６）。第３の比較部７は、ビット反転した位置の信頼度情報を第４の記憶部１１が記憶する軟判定データの信頼度に加算し、１符号分のデータについて加算した値に基づいて、加算した値があらかじめ定められた閾値よりも大きいか判定する（ステップＳ６７）。加算した値があらかじめ定められた閾値よりも大きい場合（ステップＳ６７，Ｙｓｅ）、第３の比較部７は、第１の信号を選択部４に送信する（ステップＳ６８）。加算した値があらかじめ定められた閾値よりも大きくない場合（ステップＳ６７，Ｎｏ）、第３の比較部７は、第１の信号を選択部４に送信しない（ステップＳ６９）。 The second comparing unit 6 compares the re-encoding result transmitted from the re-encoding unit 10 with the second data, and transmits the reliability information of the bit-inverted position to the third comparing unit 7. Yes (step S66). The third comparison unit 7 adds the reliability information of the bit-inverted position to the reliability of the soft-decision data stored in the fourth storage unit 11, and adds the reliability information of one code based on the added value. It is determined whether the calculated value is larger than a predetermined threshold value (step S67). When the added value is larger than the predetermined threshold value (step S67, Yse), the 3rd comparison part 7 transmits a 1st signal to the selection part 4 (step S68). When the added value is not larger than the predetermined threshold value (step S67, No), the third comparison unit 7 does not transmit the first signal to the selection unit 4 (step S69).
　情報ビット選択部９は、第３の記憶部８から第２のデータを受信し、第２のデータの情報ビット部分、つまり情報データを選択部４に送信する（ステップＳ７０）。選択部４は、第１の信号を受信したか判定する（ステップＳ７１）。選択部４は、第１の信号を受信した場合（ステップＳ７１，Ｙｅｓ）、情報データを外部の機能部に送信する（ステップＳ７２）。第１の信号を受信していない場合（ステップＳ７１，Ｎｏ）、選択部４は、ターボ復号部２から送信される復号結果を外部の機能部に送信する（ステップＳ７３）。 The information bit selection unit 9 receives the second data from the third storage unit 8 and transmits the information bit portion of the second data, that is, the information data to the selection unit 4 (step S70). The selection unit 4 determines whether the first signal has been received (step S71). When the selection unit 4 receives the first signal (Yes in step S71), the selection unit 4 transmits the information data to the external functional unit (step S72). When the first signal has not been received (step S71, No), the selection unit 4 transmits the decoding result transmitted from the turbo decoding unit 2 to the external functional unit (step S73).
　また、本実施の形態では情報ビット部分だけでなくチェックビット部分で反転しているビットの信頼度の値の合計が、あらかじめ定められた閾値よりも大きい場合、選択部４は、情報データを外部の機能部に送信するが、これに加えて、第３の比較部７が第１の信号とターボ復号化した結果とを外部の機能部に送信し、外部の機能部による処理で、情報データ、ターボ復号化した復号結果のどちらを選択するか判断するようにしてもよい。 Further, in the present embodiment, when the sum of the reliability values of the bits inverted not only in the information bit portion but also in the check bit portion is larger than a predetermined threshold value, the selection unit 4 outputs the information data to the outside. In addition to this, the third comparison unit 7 transmits the first signal and the result of turbo decoding to the external functional unit, and the information data is processed by the external functional unit. Alternatively, it may be determined which of the turbo decoding results is selected.
　また、再符号化部１０が復号結果の再符号化処理を行うときに、チェックビットを生成している一部分だけをターボ符号化し、情報ビットをインタリーブ順に受信する再符号化処理は行わずに、情報ビットと情報ビットを送信順に受信して再符号化処理を行って得られるチェックビットとを、第２の比較部６で比較を行うと再符号化処理でインタリーブ処理を行う必要がなくなり遅延を小さくできたうえで、同様の復号後の信頼度を向上させる効果が得られる。 Further, when the re-encoding unit 10 performs the re-encoding process of the decoding result, only the part in which the check bits are generated is turbo-encoded, and the re-encoding process of receiving the information bits in the interleaved order is not performed, When the second comparison unit 6 compares the information bit and the check bit obtained by receiving the information bit in the transmission order and performing the re-encoding process, it is not necessary to perform the interleaving process in the re-encoding process, and the delay is reduced. In addition to being small, the same effect of improving the reliability after decoding can be obtained.
　情報ビット部分だけでなくチェックビット部分で反転しているビットの信頼度の値の合計が、あらかじめ定められた閾値よりも大きい場合、一般的には誤った誤り訂正復号を行っている可能性が実施の形態１よりも高くなり、復号結果としての信頼性が低くなる。このため、実施の形態１の効果に加えて、第１の信号を復号結果の信頼度が低いことを示す信号として扱うことにより、復号結果の信頼性を実施の形態１で記載した場合よりも増大させることができる。なお、本実施の形態では、復号結果に対し再符号化を行っているため、組織符号以外の誤り訂正符号を用いてもターボ符号を用いた場合と同様の効果を奏することができる。 If the sum of the reliability values of the bits that are inverted not only in the information bit portion but also in the check bit portion is larger than a predetermined threshold value, it is generally possible that erroneous error correction decoding is performed. This is higher than in the first embodiment, and the reliability of the decoding result is low. Therefore, in addition to the effect of the first embodiment, by treating the first signal as a signal indicating that the reliability of the decoding result is low, the reliability of the decoding result is higher than that in the first embodiment. Can be increased. In addition, in the present embodiment, since the decoding result is re-encoded, even if an error correction code other than the systematic code is used, the same effect as in the case of using the turbo code can be obtained.
　以上の実施の形態に示した構成は、本発明の内容の一例を示すものであり、別の公知の技術と組み合わせることも可能であるし、本発明の要旨を逸脱しない範囲で、構成の一部を省略、変更することも可能である。 The configurations described in the above embodiments are examples of the content of the present invention, and can be combined with another known technique, and the configurations of the configurations are not departing from the scope of the present invention. It is also possible to omit or change parts.
　１　第１の記憶部、２　ターボ復号部、３　第１の比較部、４　選択部、５　第２の記憶部、６　第２の比較部、７　第３の比較部、８　第３の記憶部、９　情報ビット選択部、１０　再符号化部、１１　第４の記憶部、２０　無線通信システム、３０　送信装置、４０　受信装置、１００，１００ａ，１００ｂ，１００ｃ　誤り訂正復号装置、２００　制御回路、２００ａ　プロセッサ、２００ｂ　メモリ。 1 first storage unit, 2 turbo decoding unit, 3 first comparison unit, 4 selection unit, 5 second storage unit, 6 second comparison unit, 7 third comparison unit, 8 third storage unit , 9 information bit selection unit, 10 re-encoding unit, 11 fourth storage unit, 20 wireless communication system, 30 transmitting device, 40 receiving device, 100, 100a, 100b, 100c error correction decoding device, 200 control circuit, 200a Processor, 200b memory.

Claims (14)

  1. 　組織符号で誤り訂正符号化された受信データの復号処理を行い、復号結果を出力する復号部と、
    　前記受信データに含まれる第１のデータと、前記復号結果とを比較することにより、前記復号結果の信頼度が高いか否かを判定する比較部と、
    　を備えることを特徴とする誤り訂正復号装置。     A decoding unit that performs a decoding process on the reception data that has been error correction coded with the systematic code, and outputs the decoding result;
    A comparison unit that determines whether or not the reliability of the decoding result is high by comparing the first data included in the received data and the decoding result;
    An error correction decoding device comprising:
  2. 　前記比較部は、
    　前記復号結果の信頼度が低いと判定した場合に、前記復号結果の信頼度が低いことを示す第１の信号を出力し、
    　前記誤り訂正復号装置は、
    　前記第１の信号の有無に応じて前記復号結果、前記受信データに含まれる情報ビット部分のデータのいずれか１つを出力する選択部、
    　を備えることを特徴とする請求項１に記載の誤り訂正復号装置。     The comparison unit is
    When it is determined that the reliability of the decoding result is low, a first signal indicating that the reliability of the decoding result is low is output,
    The error correction decoding device,
    A selection unit that outputs one of the decoding result and the data of the information bit portion included in the received data according to the presence or absence of the first signal;
    The error correction decoding apparatus according to claim 1, further comprising:
  3. 　前記第１のデータは、
    　前記受信データの情報ビット部分のデータを含み、
    　前記比較部は、
    　前記第１のデータと前記復号結果とを比較し、ビットが反転している数を示すカウント値を算出し、前記カウント値が閾値より大きい場合、前記復号結果の信頼度が低いと判定することを特徴とする請求項２に記載の誤り訂正復号装置。     The first data is
    Including data of the information bit portion of the received data,
    The comparison unit is
    Comparing the first data with the decoding result, calculating a count value indicating the number of bits inverted, and determining that the decoding result has low reliability when the count value is larger than a threshold value. The error correction decoding device according to claim 2.
  4. 　前記第１のデータは、
    　前記受信データの情報ビット部分のデータを含み、
    　前記比較部は、
    　前記第１のデータと前記復号結果とを比較し、ビットが反転している位置の信頼度を前記第１のデータの信頼度に加算し、加算した値が閾値よりも大きい場合、前記復号結果の信頼度が低いと判定することを特徴とする請求項２に記載の誤り訂正復号装置。     The first data is
    Including data of the information bit portion of the received data,
    The comparison unit is
    The first data and the decoding result are compared, the reliability of the position where the bit is inverted is added to the reliability of the first data, and when the added value is larger than a threshold value, the decoding result is obtained. The error correction decoding apparatus according to claim 2, wherein the reliability of is determined to be low.
  5. 　前記誤り訂正復号装置は、
    　前記復号結果を再度誤り訂正符号化し、再符号化の結果を出力する再符号化部を備え、
    　前記第１のデータは、
    　前記受信データの情報ビットおよび前記受信データのチェックビットを含み、
    　前記比較部は、
    　前記第１のデータと前記再符号化の結果を比較し、ビットが反転している数を示すカウント値を算出し、前記カウント値が閾値より大きい場合、前記復号結果の信頼度が低いと判定することを特徴とする請求項２に記載の誤り訂正復号装置。     The error correction decoding device,
    The decoding result is error-correction coded again, and a re-encoding unit that outputs the re-encoding result is provided,
    The first data is
    Including an information bit of the received data and a check bit of the received data,
    The comparison unit is
    The first data and the result of the re-encoding are compared, a count value indicating the number of inverted bits is calculated, and when the count value is larger than a threshold value, it is determined that the decoding result has low reliability. The error correction decoding device according to claim 2, wherein
  6. 　前記誤り訂正復号装置は、
    　前記復号結果を再度誤り訂正符号化し再符号化の結果を出力する再符号化部を備え、
    　前記第１のデータは、
    　前記受信データの情報ビットおよび前記受信データのチェックビットを含み、
    　前記比較部は、
    　前記第１のデータと前記再符号化の結果を比較し、ビットが反転している位置の信頼度を前記第１のデータの信頼度に加算し、加算した値が閾値よりも大きい場合、前記復号結果の信頼度が低いと判定することを特徴とする請求項２に記載の誤り訂正復号装置。     The error correction decoding device,
    A re-encoding unit that outputs the result of re-encoding by performing error correction encoding on the decoding result again,
    The first data is
    Including an information bit of the received data and a check bit of the received data,
    The comparison unit is
    Comparing the first data and the result of the re-encoding, adding the reliability of the position where the bit is inverted to the reliability of the first data, and if the added value is larger than a threshold value, The error correction decoding apparatus according to claim 2, wherein the reliability of the decoding result is determined to be low.
  7. 　前記再符号化部は、
    　チェックビットを生成している一部分だけを誤り訂正符号化することを特徴とする請求項５または６に記載の誤り訂正復号装置。     The re-encoding unit,
    7. The error correction decoding apparatus according to claim 5, wherein only a part of the check bits that is generated is error correction coded.
  8. 　組織符号で誤り訂正符号化された受信データの復号処理を行い、復号結果を出力する第１のステップと、
    　前記受信データに含まれる第１のデータと、前記復号結果とを比較することにより、前記復号結果の信頼度が高いか否かを判定する第２のステップと、
    　を含むことを特徴とする誤り訂正復号方法。     A first step of performing a decoding process on the reception data that has been error-correction coded with a systematic code, and outputting the decoding result;
    A second step of determining whether or not the reliability of the decoding result is high by comparing the first data included in the received data with the decoding result;
    An error correction decoding method comprising:
  9. 　前記第２のステップは、
    　前記復号結果の信頼度が低いと判定した場合に、前記復号結果の信頼度が低いことを示す第１の信号を出力し、
    　前記誤り訂正復号方法は、
    　前記第１の信号の有無に応じて前記復号結果、前記受信データに含まれる情報ビット部分のデータのいずれか１つを出力する第３のステップ、
    　を含むことを特徴とする請求項８に記載の誤り訂正復号方法。     The second step is
    When it is determined that the reliability of the decoding result is low, a first signal indicating that the reliability of the decoding result is low is output,
    The error correction decoding method,
    A third step of outputting any one of the decoding result and the data of the information bit portion included in the received data according to the presence or absence of the first signal,
    9. The error correction decoding method according to claim 8, further comprising:
  10. 　前記第１のデータは、
    　前記受信データの情報ビット部分のデータを含み、
    　前記第２のステップは、
    　前記第１のデータと前記復号結果とを比較し、ビットが反転している数を示すカウント値を算出し、前記カウント値が閾値より大きい場合、前記復号結果の信頼度が低いと判定することを特徴とする請求項９に記載の誤り訂正復号方法。     The first data is
    Including data of the information bit portion of the received data,
    The second step is
    Comparing the first data with the decoding result, calculating a count value indicating the number of bits inverted, and determining that the decoding result has low reliability when the count value is larger than a threshold value. The error correction decoding method according to claim 9.
  11. 　前記第１のデータは、
    　前記受信データの情報ビット部分のデータを含み、
    　前記第２のステップは、
    　前記第１のデータと前記復号結果とを比較し、ビットが反転している位置の信頼度を前記第１のデータの信頼度に加算し、加算した値が閾値よりも大きい場合、前記復号結果の信頼度が低いと判定することを特徴とする請求項９に記載の誤り訂正復号方法。     The first data is
    Including data of the information bit portion of the received data,
    The second step is
    The first data and the decoding result are compared, the reliability of the position where the bit is inverted is added to the reliability of the first data, and when the added value is larger than a threshold value, the decoding result is obtained. 10. The error correction decoding method according to claim 9, wherein the reliability of is determined to be low.
  12. 　前記誤り訂正復号方法は、
    　前記復号結果を再度誤り訂正符号化し再符号化の結果を出力する第４のステップを含み、
    　前記第１のデータは、
    　前記受信データの情報ビットおよび前記受信データのチェックビットを含み、
    　前記第２のステップは、
    　前記第１のデータと前記再符号化の結果を比較し、ビットが反転している数を示すカウント値を算出し、前記カウント値が閾値より大きい場合、前記復号結果の信頼度が低いと判定することを特徴とする請求項９に記載の誤り訂正復号方法。     The error correction decoding method,
    A fourth step of performing error correction coding on the decoding result again and outputting the result of the recoding,
    The first data is
    Including an information bit of the received data and a check bit of the received data,
    The second step is
    The first data and the re-encoding result are compared, a count value indicating the number of bits inverted is calculated, and if the count value is larger than a threshold value, it is determined that the decoding result has low reliability. The error correction decoding method according to claim 9, wherein
  13. 　前記誤り訂正復号方法は、
    　前記復号結果を再度誤り訂正符号化し再符号化の結果を出力する第４のステップを含み、
    　前記第１のデータは、
    　前記受信データの情報ビットおよび前記受信データのチェックビットを含み、
    　前記第２のステップは、
    　前記第１のデータと前記再符号化の結果を比較し、ビットが反転している位置の信頼度を前記第１のデータの信頼度に加算し、加算した値が閾値よりも大きい場合、前記復号結果の信頼度が低いと判定することを特徴とする請求項９に記載の誤り訂正復号方法。     The error correction decoding method,
    A fourth step of performing error correction coding on the decoding result again and outputting the result of the recoding,
    The first data is
    Including an information bit of the received data and a check bit of the received data,
    The second step is
    Comparing the first data and the result of the re-encoding, adding the reliability of the position where the bit is inverted to the reliability of the first data, and if the added value is larger than a threshold value, The error correction decoding method according to claim 9, wherein the reliability of the decoding result is determined to be low.
  14. 　前記第４のステップは、
    　送信順でチェックビットを生成している一部分だけを誤り訂正符号化することを特徴とする請求項１２または１３に記載の誤り訂正復号方法。     The fourth step is
    14. The error correction decoding method according to claim 12, wherein only a part of the check bits generated in the transmission order is subjected to error correction coding.
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