WO2020102663A1 - VECTOR NETWORK ANALYZER USING COMPLEMENTARY CURRENT-INJECTION FIELD-EFFECT TRANSISTOR (CiFET) DEVICES - Google Patents

Abstract

This invention relates to a unique compact vector network analyzer (VNA) that uses current to excite a device under test (DUT). The current through the DUT is terminated / received by a complementary current-injection field-effect transistor (CiFET) which is used to convert the current through the DUT into a voltage which is, then, compared to a differential voltage across the DUT for determining the phase relationships along with amplitude. The simplified VNA can be arrayed to further extend the VNA characterization data set for analysis.

Description

TITLE OF THE INVENTION

[0001] VECTOR NETWORK ANALYZER USING COMPLEMENTARY CURRENT- INJECTION FIELD-EFFECT TRANSISTOR (CiFET) DEVICES

CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to US Provisional Application No. 62/768,421, filed on November 16, 2018, the content of which is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

[0003] The present invention relates to a vector network analyzer (VNA), which is based on the realization that a VNA containing Complementary Current-Injection Field-Effect Transistors (CiFETs) provides a simple configuration that permits positioning the analyzer at the tip of probes, thus reducing complexity, cost, size, parasitics, and many sources of noise to circumvent post processing out unwanted information, while opening up new VNA applications.

BACKGROUND OF THE INVENTION

[0004] The instrument called a vector network analyzer (VNA) became reality when circuits provided the ability to measure the phase difference between two same frequency sinusoids. The core of the VNA is the ability to accurately measure at least two signals in such a fashion that the amplitude record of both signals and the phase difference between them is faithfully generated. The VNA is a contemporary electronic instrument.

[0005] Once the amplitudes and phase difference are determined it has become a practice to follow these measurements with various processing and communication devices in order to calculate derivations and transmit those conclusions for further uses.

[0006] Prior / conventional VNA often has a very complex structure, which is more costly and increases size. Due to such complex structure, such a conventional VNA may be vulnerable to or sensitive to various parasitics or noises.

[0007] In general, prior / conventional VNAs have been built to be either a standalone instrument or one connected to a controlling computer. The devices are designed to provide the vector relationship between two or more signals and use that data computationally to provide a range of data presentations. A display screen is most often included.

[0008] Shortcomings of the prior / conventional VNAs may be summarized as follows:

[0009] A professional VNA that offers wideband performance across several channels and post processing of its data, along with a display interfaced to other systems for data sharing is priced from $100,000 to a few thousand for a limited POC device. [0010] They are serious instruments that make complex calculations to deduce properties of the systems they are attached to. A VNA is a profoundly useful instrument. Its main limitations, beyond its noise floor and bandwidth performance, are cost and size.

[0011] These characteristics mean the VNA will be applied to a circuit rather than be incorporated into the net system circuit functions, like a Phase Locked Loop (PLL).

[0012] Furthermore, prior / conventional VNAs are, in general, voltage sensing devices. A prior / conventional VNA may be configured to measure voltage or current. Typically, the current signal is terminated into a specific resistance, such as the widely used 50-ohm termination where that current is turned into a voltage to be measured as a voltage, ultimately with a high input impedance voltage amplifier. Another common current-to-voltage convertor uses a virtual node amplifier circuit that measures current by using feedback to null the differential voltage between the input nodes of a high input impedance voltage operational amplifier. However, in such configuration or arrangement, the input current disturbs the operational amplifier enforced differential node null. This disturbance drives the operational amplifier output voltage such that a nulling current to signal current flows as dictated by the output voltage of the operational amplifier and the feedback impedance that is connected to the nulling node, thus cancelling the disturbance. The output voltage reaction to the input current is an indirect measurement of the input current.

[0013] Accordingly, there is a long-felt need(s) for addressing one or more of these shortcomings.

SUMMARY OF INVENTION

[0014] The present invention relates to a vector network analyzer (VNA) based on Complementary Current-Injection Field-Effect Transistors (CiFETs) for providing a simple configuration that permits positioning its VNA capability at the tip of probes, thus reducing complexity, cost, size, parasitics, and many sources of noise to circumvent post processing out unwanted information, while opening up new VNA applications.

[0015] According to one aspect of the present invention, it provides a novel CiFET VNA implementation that produces a uniquely simple physical circuit implementation of the VNA’s core function, including, but not limited to acquiring a linear phase and flat wideband amplitude transduction of a system response to an excitation signal. During its usage, a test signal may be a current through a device under test (DUT). The novel CiFET VNA comprises a CiFET, which includes an iPort that may be resistively terminates (Rin) or function as input impedance, and absorbs all the DUT excitation current for providing an in-phase voltage at the CiFET drain output, using a trans-resistance / or trans-impedance (rm) gain factor, which is one of the unique characteristics that CiFET possesses. CiFET drain voltage output is compared to the differential voltage across the DUT to provide phase information with a Phase-Frequency Detector (PFD). Combining this phase information with the DUT excitation current, the DUT signal path characteristics may be computed.

|0016] The simplest VNA requires two phase accurate signals to be passed to a PFD where the phase difference between two same frequencies sinusoids is measured and generates an averaged real time signal proportional to that phase difference. A CiFET -based PFD is shown in the PCT international patent application publication No. WO 2016/118936, the content of which is incorporated herein by reference in its entirety; the signals are voltage across the DUT and the current through the DUT. Typically, these signals are low amplitude making low noise wide bandwidth amplifier operation of the various CiFET amplifiers advantageous. Such low noise sensor amplifier and trans -impedance amplifiers using CiFET circuits are detailed in the PCT international patent application publication No. WO 2018/098389, the content of which is incorporated herein by reference in its entirety.

[0017] In a CiFET-based VNA system, these real time signals may be passed to a CiFET-based Analog to Digital Convertor system, which is shown in the PCT international patent application publication No. WO 2017/106835, the content of which is incorporated herein by reference in its entirety, and the signals may be digitized at a desired sampling rate. This digitized data becomes available for further processing from its real time data stream. This data stream can pass through complex digital circuits including microprocessors, digital signal processors (DSPs), and data formatters to interconnect standards such as USB, Bluetooth, WIFI, LAN, SD Cards or any custom support for a custom protocol.

[0018] According to a preferred embodiment of the present invention, it provides a CiFET- based VNA, which approaches the core measurements of the VNA by measuring the response to a voltage or current input signal drive by directly measuring the current flow through the DUT using CiFET’s trans-resistance (rm). Both signals’ amplitude and phase difference can be measured in totally CiFET structures with the advantages of the range of operating at extreme temperatures and ultra-low VDD operation as referenced in the PCT international patent application publication No. WO 2018/098389, the content of which is incorporated herein by reference in its entirety. A front end constructed using CiFET (s) would sink the signal current and linearly transforms the signal current to the CiFET output voltage. This transformation may be a key, as the DUT response current is usually much fainter than the drive signal and must be transduced using a device with a very low baseline noise device such as a CiFET Trans-Impedance Amplifier (TIA), as proposed in the PCT international patent application publication No. WO 2018/098389, or a single CiFET VNA amplifier which operates at low supply voltage as opposed to the more traditional +/- 15Vdc amplifier circuits. This approach would allow a front end including CiFET to provide the so important initial amplification which will improve total system performance and yet allow this front end to be interfaced with existing system product designs.

[0019] As has been shown in the PCT international patent application publication No. WO 2018/098389, the CiFET can also be electronically tuned to have its input impedance changed over a limited range by active circuitry applicable to the CiFET VNA. It may be advantageous to change or modulate the loading presented as input impedance by dynamically changing the CiFET iPort input impedance. The CiFET input impedance is set by the designed-in iRatio at circuit design and multiple CiFETs can be placed in parallel.

[0020] There are many reasons to be able to measure at different drive frequencies simultaneously - some are presented in the PCT international patent application publication No. WO 1993/018821, the content of which is incorporated herein by reference in its entirety. The CIFET VNA is the first device that can make such measurements at the electrode electrolyte tissue interface because of its size and the needed VDD, which can be located at the point of tissue contact. Once this impedance vs time signature is made for that person’s various types of heart beats, NSR, PVC and the others that may present deviations from that impedance signature norm would be noticed and reported as a diagnostic aid that would lead to helping to modulate the pharmacologic therapy.

[0021] The CiFET process is fully compatible with, and relies upon, the unmodified CMOS PDK (Product Design Kit) that hosts its designs. This produces a System-on-Chip (SoC) that fully integrates CiFET analog with CMOS digital. This unique ability for the CiFET analog to intermix with CMOS allows the statement that the CiFET can produce high performance micro VNAs that can be placed in contact with the DUT; this will enable higher frequency impedance DUT examinations to be made and open application spaces currently unreachable.

[0022] This micro VNA can and needs to be integrated with the circuit function as well as applied to it. The single chip VNA would have the chip integrated digital capability of CiFET or CMOS A/D’s and CiFET or CMOS Logic or existent CMOS microprocessors, DSP units and system integrative and communication chips that provide Wi-Fi, LAN, hardline communication to further processing like a laptop. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 illustrates a block diagram of a CiFET-based VNA for measuring a device under test (DUT);

[0024] Figure 2 illustrates a block diagram of an alternate CiFET-based VNA front-end with a CiFET translated driving signal in accordance with the present invention;

[0025] Figure 3 illustrates a CiFET symbol and 3-D cross section with port locations;

[0026] Figure 4 illustrates a multi-port actively VNA input structure; and

[0027] Figure 5 illustrates a symbol diagram of a variation of CiFET.

DETAILED DESCRIPTION OF THE INVENTION

[0028] Figure 1 shows a block diagram of a CiFET-based VNA 100 for measuring a device under test (or DUT) 20 in accordance with a preferred embodiment of the present invention. The CiFET-based VNA 100 includes a signal driver I_Dri_ve 10 (derived from a Norton current source) drives a current IDUT, which is applied to the DUT 20. The signal driver I_Drive 10 may drive AC or DC signals to DUT 20. The voltage across the DUT 20 is differentially measured by a differential amplifier 40, such as a CiFET differential amplifier or some other differential amplifiers. The current through the DUT 20 would pass into an NiPort 31 of a CiFET 300 to produce a wideband phase linear voltage at the CiFETs common drain output 39 (VOUT = rm*Ii_N_NiPort, where rm is a trans-resistance of CiFET 300; and, I_|\j_NiPort is current input at NiPort 31 of CiFET 300). The input resistance Rin of the NiPort 31 of CiFET 300 is set by its iRatio during design and may be dynamically altered by other circuit means. In one example, it could be desirable to use a low Ri_n resistance such as 50-ohms for wideband high frequency operation, while using a VDD of 1.2V for sub-micron IC process technologies. The DC offset at the NiPort 31 under these conditions is about 1 millivolt.

[0029] The CiFET approach is different from the conventional approach for realizing VNA functionalities in that CiFET 300 directly transforms the injected current at iPort 31 (or 32 in some cases) directly into output voltage VOUT at the common drain output 39 through the device’s trans-resistance (rm) transfer function as performed by CiFET. This VNA 100 measures current through DUT 20 directly to utilize CiFETs wide band, high gain, and phase linear transfer output voltage. CiFET 300 operates over 8 to 9 decades of linear current-in to voltage-out trans-impedance or trans-resistance transfer function capability. The CiFET’ s power supply and input to output isolation along with its extraordinary high S/N ratio ensure low baseline noise performance, thus, in turn, it allows accurate signal measurements, even at low signal phase amplitudes. [0030] By measuring the signal current directly as an input parameter, many physical measurement problems are bypassed. Specifically, the fixed CiFET iPort input impedance Ri_n is a current signal termination for the DUT 20. For low iPort resistance Rin, the node voltage would be low, and in some cases essentially zero minimizing any parasitic capacitance input.

[0031] Output voltage V_out at common drain output 39 of the CiFET 300 is compared to the differential voltage OVDUT across DUT 20 to provide phase information Zq with a Phase- Frequency Detector (PFD) 45. Combining this phase information with the DUT excitation current, the DUT signal path characteristics may be computed.

[0032] Figure 2 illustrates a block diagram of an alternate CiFET-based VNA front-end with a CiFET translated driving signal in accordance with the present invention. An excitation current L_oad is applied to the DUT 20’ by a current inj ection into the CiFETl 300a PiPort 32a. Because replica CiFETl 300a and CiFET2 300b are tied together at the NiPorts 31a and 31b through the DUT 20’, the injected current Iom_c is mirrored through the DUT 20’. This excitation current source L_oad could also be applied by a Thevenin-equivalent voltage source in place of the current source 10’.

[0033] This signal current flowing through the DUT 20’ is terminated into CiFET2 300b NiPort 31b in which CiFET2 300b converts its trans-impedance or trans-resistance rm into a voltage representation V_out2 and presented at its common drain output 39b, where V_out2 = l_Dur*rm, where V_out2 is the voltage output at the common drain output 39b, IDUT is current through the DUT 20’. This output voltage V_out2 is proportional to the amplitude of the input current IDUT’ at NiPort 31b of the CiFET2 300b and accurately reflects its phase. A differential amplifier 40’, such as a CiFET differential amplifier (not shown) as disclosed in PCT international patent application publication No. WO 2018/098389, the content of which is incorporated herein by reference in its entirety, or other type of differential amplifier measures the voltage across the device V_Load, between the NiPorts 31a and 31b, or over DUT 20’. As an example, iRatio can be arranged at iPort to provide a low DC voltage. To many systems, this would be considered as ground, and the voltage across the device VDUT 20’ could be taken as the Vi_oad applied voltage. In other systems, a differential measurement across the DUT 20’ might be employed to produce a signal proportional to the voltage across the DUT 20’. The drive could also be taken from the common drain node 39a of CiFETl 300a with AC and DC control signals applied to the PiPort 32a or NiPort 31a.

[0034] This single CiFET 300a replaces often complex circuitry that implements an active virtual input node for a VNA device while actively producing a current-in to voltage-out trans- resistance / trans-impedance transformation at CiFET2300b to render the output voltage signal proportional to the current through the DUT 20’. Such characteristics has been disclosed in the PCT international patent application publication No. WO 2017/019064, the content of which is incorporated herein by reference in its entirety. According to the present invention, CiFET-VNA is a totally new approach to a local VNA by utilizing such characteristic and its implementation in standard digital CMOS processes. VNAs using the CiFET would reduce the cost sufficiently that they could be used in disposable applications, for instance, rancidity of butter or other oils stored on the table could be tested over time. VNAs would become so small in terms of IC surface area they would become part of the product rather than being applied to it.

[0035] The capabilities of CiFET come from its unique structure shown in Figure 3. CiFET 300 comprises a complimentary pair of iFET, NiFET 301 and PiFET 302. NiFET 301, for example, has a source s33d, drain d35d, gate 30d, and diffusion or NiPort 31d, where the source s33d and the NiPort 31d defines a source channel 33d; and, the drain d35d and NiPort 31d defines a drain channel 35d. Gate 30d is capacitively coupled with the source channel 33d and the drain channel 35d. Similarly, PiFET 302 has a source s34d, drain d36d, gate 30d and diffusion or PiPort 32d where the source s34d and the PiPort 32d defines a source channel 34d; and, the drain d36d and PiPort 32d defines a drain channel 36d. Gate 30d is capacitively coupled with the source channel 34d and the drain channel 36d. Drain d35d of the NiFET 301 and drain d36d are connected together to form a common drain 39d (or 39a). Similarly, drains 30d of the NiFET 301 and PiFET 302 are connected together, and thus forms a common gate 30d. Access to the channel current that passes through a gate voltage biased channel stack is obtained by the addition of the iPort terminals 31d and 32d diffusions that split the iFET channels into two unequal parts. The iRatio of an iFET 301 or 302 is defined as the W/L of the source channel (adjacent to the power supply) /W/L of the Drain channel (connected to the common-Drain Output).

[0036] iRatio = { WS/LS /WD/LD }, where Ws is width of a source channel of an iFET between source and diffusion (iPort); Ls is length of the source channel of the iFET between source and iPort; WD is width of a drain channel of the iFET between source and diffusion (iPort); and, LD is length of the drain channel of the iFET between source and iPort.

|0037] This iRatio sets the CiFET input-resistance (Rin) and trans-resistance gain factor (rm) that converts iPort input current to common-drain output voltage. A ~VDD/2 gate voltage biases the stack with a current that passes through the stack. An external signal current applied to an iPort directly alters this bias current passing through the chain of channels, yielding a rapid high-gain change based on trans-resistance (r_m) of CiFET in common-drain output voltage. This makes CiFET operate similar to a BJT amplifier with a single composite CMOS device.

[0038] Referring to Figure 3 the CiFET 300 comprises PiFET 302 and NiFET 301, laid out on the substrate (or body B + and B - respectively) like a mirror image along well border shown therein. PiFET 302 comprises source terminal S + s34d, drain terminal D + d36d, and iPort control terminal Pi 32d (or 32a), defining source + channel 34d between the source terminal S+ s34d and the iPort control terminal Pi diffusion region 32d (or 32a), and drain+ channel 36d between the drain terminal D+ d36d and the iPort control terminal Pi diffusion region 32d (or 32a); NiFET 301 also comprises source terminal S- s33d, drain terminal D- d35d, and iPort control terminal Ni 31d (or 31a), defining source- channel 33d between source- terminal S- s33d and the iPort control terminal Ni diffusion region 31d(or 31a), and drain- channel 35d between drain- terminal D- d35d and the iPort control terminal Ni diffusion region 31d (or 31a). CiFET 300 further comprises a common gate terminal 30d over source+ channel 34d, drain+ channel 36d, source- channel 33d, and drain- channel 35d. Accordingly, the common gate terminal 30d (or 30a) is electrically coupled to the iPort control terminals Pi 32d (or 32a) and Ni 3 Id (or 31a).

[0039] In Figure 4, one I_Drive is provided by using a CiFET 300e for measuring DUT 20” with a multiple CiFETs 300f, 300g, 300h, and 300i in which various current pathes are terminated with CiFETs 300f, 300g, 300h, and 300i. CiFETs 300f, 300g, 300h, and 300i are used as sensors for analyzing various volumetric current paths, sensed at several different portals with an array of delicately placed electrodes at V_outE 39e, V_outF 39f, V_outG 39g, V_outH 39h and V_outi 39i. More than one CiFET could also be used to source different drive current(s). CiFETs 300f, 300g, 300h, and 300i transduce current into voltage at the corresponding V_outE 39e, V_outF 39f, VoutG 39g, VoutH 39h and V_outi 39i, respectively, for a PFD (not shown) interfacing with the CiFETs. Physical size of the VNA would shrink dramatically when constructed with CiFETs.

[0040] I_Dri_ve could be the same or different frequencies applied at different locations and from both intrinsic and extrinsic sources. I_Dri_ve could also be a complex waveform of a specific Fourier frequency mix. An example of such an internal complex source would be the rhythmic drive of an engine in operation against any number of sensed signals ranging from oil pressure ejection, to resonance in the engine block, to sound in the passenger cabin, etc. Virtually anything that produces a rhythmic disturbance can be transduced to a measurable drive signal can be examined as a multiport system with data developed with a CiFET VNA and this device can be placed locally.

[0041] Note, too, in Figure 4, different regions on conductivity are shown as different patterns within the structure. By using the information gained with different electrode pairs, these different regions of impedivity could be mapped to an extent enabling the number of electrode pair readings taken. These measurements can be employed to model conductive volumes as impedances and impedivities in conventional multiport matrix electronic models. CiFET- based VNA in accordance with the present invention would be able to transduce conductive volume three-dimensional vector field measurements into scalar phasor impedance values.

[0042] Figure 5 shows another embodiment of a CiFET or a complementary pair of super saturated current field effect transistors (or CxiFET) 500. CxiFET 500 comprises a N-type super-saturated current field effect transistor (or NxiFET) 501 and a P-type super-saturated current field effect transistor (or PxiFET) 502. The first gate terminals of NxiFET 501 and PxiFET 502 are connected together to receive input 50a, the drain terminals of NxiFET 501 and PxiFET 502 are also connected together to form output 59a. The source terminal 53 of NxiFET 501 receives negative power supply and the source terminal 54 of PxiFET 502 receives positive power supply. CxiFET 500 further comprises diffusion ports, PiPort 52 and NiPort 51. PiPort 52 divides a channel between the drain and source of PxiFET 502 into a source channel segment between the source and PiPort 52 and a drain channel segment between the drain and PiPort 52; while NiPort 51 divides a channel between the drain and source of NxiFET 502 into a source channel segment between the source and NiPort 51 and a drain channel segment between the drain and NiPort 51. The input 50a is capacitively coupled to the drain channel segments of PxiFET 502 and NxiFET 501; the second gate 57-a of NxiFET 501 is capacitively coupled to the source channel segment of NxiFET 501; and the second gate 57+a of PxiFET 502 is capacitively coupled to the source channel segment of PxiFET 502.

[0043] Providing this second gate control inputs 57-a and 57+a in this complementary configuration 500 as shown in Figure 5 affords similar linearization to that of a CiFET device structure as previously shown.

[0044] When either of the second gate terminals 57-a, 57+a are taken to their respective power supply rail, NxiFET 501 and PxiFET 502 are turned OFF, thus saving power when the amplifier is not in use. Because of the large and uniform distribution of source channel ionized charge carriers, and low channel iPort voltage change between OFF to saturated, and back OFF is extremely fast, approaching logic speed for analog signals. The source channel quickly cuts OFF or immediately reaches its stable bias point. The low resistance and minimal voltage change drive rapid exponential settling to a stable bias point.

[0045] In addition, when either or both second gates 57-a, 57+a are taken to an intermediate voltage, the current through the CxiFET device 500 from Power+ to Power- and trans impedance rm gain is controlled, making gain and power consumption verses speed electrically controllable. When these source channel gates are switched to the common gate voltage, CxiFET becomes a CiFET.

Claims

1. A vector network analyzer for analyzing an impedance of a device under test (DUT) comprising: a. a phase detector having first and second inputs and an output, b. a complementary pair of field effect transistors (CiFET) comprising a first transistor and a second transistor, each comprising a gate, a source, a drain and a diffusion, wherein said source and said drain defines a channel, and said diffusion divides said channel into a source channel segment between said source and said diffusion and a drain channel segment between said drain and said diffusion, and said gate is capacitively coupled to said source channel segment and said drain channel segment, wherein said drains of said first and second transistors are connected together to form an output, and said gates of said first and second transistors are connected together; said source of said first transistor receives a negative power supply voltage, and said source of said second transistor receives a positive power supply voltage; and c. a differential amplifier; wherein said DUT is adapted to have a first probe for receiving a current signal from a signal driver and a second probe for providing an output current signal through said DUT based on said current signal; said diffusion of said second transistor receives said output current signal to provide an output voltage at said output of said CiFET; and said differential amplifier receives said current signal from said first probe and said output current signal at said second probe for outputting a differential voltage therebetween; said phase detector receives said output voltage from said CiFET and said differential voltage from said differential amplifier for a phase differential measurement between said first and second probes.

2. The analyzer as recited in claim 1, wherein said signal driver comprises a second complementary pair of transistors, wherein said diffusion of said second transistor receives said current signal, and said diffusion of said first transistor is in communication with said first probe of said DUT.

3. The analyzer as recited in claim 1, wherein said current signal is an AC signal.

4. The analyzer as recited in claim 1, wherein said current signal is a DC signal.

5. The analyzer as recited in claim 1, wherein said gate of each transistor comprises a first gate and a second gate, wherein said first gate and said second gate are connected together.

6. A multiport vector network analyzer comprising a plurality of said vector network analyzers as recited in claim 1, wherein said DUT provides a corresponding number of said second probes at different spaced apart positions on said DUT for said plurality of said vector network analyzers.