WO2020079838A1

WO2020079838A1 - Capacitance sensor substrate and electronic device

Info

Publication number: WO2020079838A1
Application number: PCT/JP2018/039045
Authority: WO
Inventors: 港　浩一; 福吉　健蔵
Original assignee: 凸版印刷株式会社
Priority date: 2018-10-19
Filing date: 2018-10-19
Publication date: 2020-04-23

Abstract

This capacitance sensor substrate comprises: a substrate having a first surface and a second surface; a dielectric layer which includes carbon and which is disposed above the second surface; a thin-film transistor which is disposed above the second surface and which comprises a gate electrode, a source electrode, a drain electrode, a channel layer formed from an oxide semiconductor layer, and a gate insulation layer; a first conducting layer which comprises a metal layer, is disposed above the second surface, and forms at least a capacitor pattern and the gate electrode; and a second conducting layer which comprises a metal layer and is disposed above the second surface. The gate electrode is electrically joined to the capacitor pattern. In a plan view, the dielectric layer overlaps with the capacitor pattern, and in the thickness direction of the substrate, the dielectric layer is positioned nearer to a touch sensing input surface than the capacitor pattern.

Description

Capacitance sensor substrate and electronic device

The present invention relates to a capacitance sensor substrate having a capacitance type touch sensing function, and an electronic device having the capacitance sensor substrate.

A display device that can directly input to the display screen with a finger or a pointer, such as a smartphone or a tablet terminal having a capacitance-based touch sensing function, is becoming common. Capacitive touch sensing technology is also used as fingerprint authentication technology for detecting uneven shapes such as fingerprints. Various types of detection are possible, such as pen input, feather touch input (light touch input that is close to non-contact), and touch input that applies a large pressing force to the board, and it is expanded and applied to detect the pressing force on the board. Is being done.

ㆍ Self-capacity type touch sensing method and mutual capacitance type touch sensing method are known as touch sensing methods. The self-capacitance type touch sensing method uses an individual electrode pattern in which a plurality of electrodes formed of a transparent conductive film such as ITO are electrically independently formed to measure the capacitance generated in each electrode. This is a detection method. The mutual capacitance type touch sensing method is a method of arranging touch sensing wirings (hereinafter, abbreviated as touch wirings) in the X direction and the Y direction, and detecting a capacitance generated between the X direction wiring and the Y direction wiring. Is. The mutual capacitance type touch sensing method can realize a simple circuit configuration. However, it is often inferior to the self-capacitance type touch sensing method from the viewpoint of touch signal accuracy.

Capacitive touch sensing technology has long been considered as a fingerprint authentication technology. Patent Document 1 discloses a fingerprint input device using MOS-FETs arranged in a grid. However, the fingerprint input device disclosed in Patent Document 1 is formed on a silicon substrate. Silicon substrates are expensive and easily broken. Further, from the viewpoint of substrate size, it is difficult to apply a silicon substrate to an electronic device including a large substrate or a resin substrate that constitutes a display device or the like.

Patent Document 2 discloses a fingerprint sensor that employs glass for a substrate and employs sensor electrodes in which conductive layers such as ITO are arranged in a matrix in the X and Y directions. As described in paragraph [0030], it is suggested that, as the first semiconductor layer SC1 formed in the sensor circuit, for example, an oxide semiconductor or amorphous silicon formed of polycrystalline silicon may be used. ing. This technique solves the problem of the fingerprint sensor using a silicon substrate.

Patent Document 3 discloses a mutual capacitance type touch panel having a dielectric structure having a relative dielectric constant in the range of about 20 to about 100. The touch panel 100 is an ITO touch panel having drive electrodes 102 such as ITO drive traces / tracks that intersect each other (crossover), as shown in paragraph [0010]. Disclosed in paragraph [0015] is a dielectric structure 104 of a ferroelectric such as barium titanate, or a dielectric material such as niobium pentoxide or titanium dioxide. In the description of paragraph [0014], the dielectric structure 104 is disposed on the sensor electrode 110 with a film thickness ranging from about 10 nanometers to about 100 nanometers. Although Patent Document 3 does not specifically disclose the method for forming the dielectric material, it is assumed from the description in paragraph [0002] that a display is provided below the touch panel. In addition, as described above, since the dielectric structure is a thin film having a thickness of 10 to 100 nanometers, it is assumed to be a visible light transparent laminated thin film including an ITO underlayer in a thin film process such as vacuum film formation. It Patent Document 3 discloses an increase in power consumption due to a large dielectric loss (tan δ) when a ferroelectric material such as barium titanate is used as a dielectric material, and further after touch input by a pointer such as a finger or a pen ( Or before resetting the capacitance that occurs before the next touch input) is not considered.

Patent Document 4 discloses a liquid crystal display device having a touch sensing function that utilizes the capacitance between the electrode 37 and the common electrode 33 for touch sensing. As described in paragraph [0054], a color filter and an interlayer insulating film are provided between the electrode 37 and the electrode 33. As described in paragraphs [0055] and [0057], the electrode 37 and the electrode 33 have translucency. As described in paragraphs [0040] and [0052], the transistor 31 is a transistor including an oxide semiconductor in a semiconductor layer.

Patent Document 5 discloses a technique for providing a thin film transistor having improved field effect mobility by using a multilayer structure including an oxide semiconductor film or by devising composition and crystallinity of a multilayer oxide semiconductor. Disclosure. However, the film thickness of the oxide semiconductor which is the channel layer of the thin film transistor is a very thin film thickness region of several tens nm. For example, paragraphs [0170] to [0176] disclose respective film thicknesses in a multilayer oxide semiconductor of 1 nm or more and less than 20 nm, or 20 nm or more and 100 nm or less. In the process of forming a multi-layer film in the region of several tens of nm, for example, variations easily occur between film formation lots. In addition, in order to form films by changing the composition of the multilayer oxide semiconductor film, for example, a plurality of sputtering targets (starting materials) are prepared, and a film formation apparatus having different chambers (film formation chambers) is prepared. It must be done, and there is a problem in terms of manufacturing cost.

Patent Document 6 discloses a laminated structure of a light absorbing resin layer pattern and a metal layer pattern, and it is shown that the metal layer pattern is an alloy layer containing copper as a main material and a copper layer. In claim 4 of Patent Document 6, the light absorbing material is carbon, and the optical density for suppressing light reflection is described. No transistor is provided on the first transparent substrate (counter substrate) having such a laminated structure, and for example, as a dielectric layer, electrical characteristics required for touch sensing are not disclosed.

Japanese Patent No. 3418479 Japanese Unexamined Patent Publication No. 2017-187478 Japanese Patent Laid-Open No. 2017-518586 Japanese Patent Laid-Open No. 2016-1301 Japanese Patent Laid-Open No. 2018-6731 Japanese Patent No. 5924452

The present invention has been made in view of the above background art and problems, and is a capacitive sensor substrate applicable to high-definition and highly accurate fingerprint authentication and pen input, and an electronic device including the capacitive sensor substrate. I will provide a.

A capacitive sensor substrate according to a first aspect of the present invention includes a substrate having a first surface and a second surface, a dielectric layer including carbon, the dielectric layer being provided above the second surface, and a gate electrode. A thin film transistor which has a source electrode, a drain electrode, a channel layer formed of an oxide semiconductor layer, and a gate insulating layer and is provided above the second surface; and a metal layer, which is above the second surface. And a second conductive layer having a metal layer and provided above the second surface, the first conductive layer being provided on the first surface and forming at least the capacitor pattern and the gate electrode. The gate electrode is electrically associated with the capacitor pattern, the dielectric layer overlaps the capacitor pattern in a plan view, and the dielectric layer is more touch-sensitive than the capacitor pattern in the thickness direction of the substrate. It is near the input surface.

In the capacitive sensor substrate according to the first aspect of the present invention, the dielectric layer is carbon, and at least one or more fine particles selected from the group consisting of metal oxides, metal oxynitrides, and metal nitrides, It may be a resin dispersion containing.

In the capacitive sensor substrate according to the first aspect of the present invention, the dielectric layer may have an electrical resistivity of 1 × 10 ⁸ Ωcm or more and less than 1 × 10 ¹³ Ωcm.

In the capacitive sensor substrate according to the first aspect of the present invention, the dielectric loss of the dielectric layer may be 0.01 or more and less than 0.2.

In the capacitive sensor substrate according to the first aspect of the present invention, the film thickness of the dielectric layer may be in the range of 0.2 μm or more and 10 μm or less.

In the capacitive sensor substrate according to the first aspect of the present invention, each of the first conductive layer and the second conductive layer may have a three-layer structure in which the metal layer is sandwiched by conductive oxide layers. Good.

In the capacitive sensor substrate according to the first aspect of the present invention, in a cross-sectional view along the thickness direction of the thin film transistor, the thin film transistor has an overlapping portion in which an end portion of the channel layer is covered with the second conductive layer. An interface where the conductive oxide layer and the channel layer contact each other may be formed in the overlapping portion.

In the capacitive sensor substrate according to the first aspect of the present invention, the conductive oxide layer may include indium oxide.

In the capacitive sensor substrate according to the first aspect of the present invention, the oxide semiconductor layer may include indium oxide and at least one of antimony oxide and bismuth oxide.

In the capacitive sensor substrate according to the first aspect of the present invention, the oxide semiconductor layer may include at least one of cerium oxide and tin oxide.

The electronic device according to the second aspect of the present invention includes the capacitive sensor substrate according to the first aspect and the antenna.

An electronic device according to a third aspect of the present invention includes the capacitance sensor substrate according to the first aspect, an array substrate having a substrate surface on which a thin film transistor array is arranged, and a display functional layer, and the capacitance sensor substrate The display function layer is sandwiched between the capacitive sensor substrate and the array substrate so that the second surface of the array substrate faces the substrate surface of the array substrate.

According to the aspects of the present invention, it is possible to provide a capacitance sensor substrate applicable to high-definition and high-precision fingerprint authentication and pen input, and an electronic device equipped with this capacitance sensor substrate.

FIG. 3 is a partially enlarged view showing the configuration of the capacitive sensor substrate according to the first embodiment of the present invention, which is a circuit diagram showing a unit cell including a capacitor pattern and a thin film transistor (first thin film transistor). FIG. 3 is a partial cross-sectional view showing the configuration of the capacitive sensor substrate according to the first embodiment of the present invention, which is a cross-sectional view showing a unit cell taken along the line A-A ′ shown in FIG. 1. FIG. 3 is a partial cross-sectional view showing the configuration of the capacitive sensor substrate according to the first embodiment of the present invention, which is an enlarged cross-sectional view showing the thin film transistor in FIG. 1. FIG. 5 is an enlarged cross-sectional view illustrating a portion where the end surface of the first channel layer and the conductive layer in the first thin film transistor according to the first embodiment of the present invention overlap with each other. It is an expanded sectional view explaining a reference example of a thin film transistor which has a portion where an end face of a conductive layer and a channel layer contact. FIG. 7 is a partially enlarged view showing the configuration of the capacitance sensor substrate according to the modified example of the first embodiment of the present invention, and a circuit diagram showing a unit cell including a capacitor pattern and a thin film transistor (second thin film transistor). FIG. 7 is a partial cross-sectional view showing the configuration of the capacitance sensor substrate according to the modified example of the first embodiment of the present invention, which is a cross-sectional view showing a unit cell taken along line B-B ′ shown in FIG. 6. FIG. 7 is a partial cross-sectional view showing the configuration of a capacitance sensor substrate according to a modification of the first embodiment of the present invention, which is a cross-sectional view showing the thin film transistor in FIG. 6. It is a circuit diagram which shows the unit cell of the capacitance sensor board | substrate which concerns on the modification of 1st Embodiment of this invention. It is a circuit diagram which shows the unit cell of the capacitance sensor board | substrate which concerns on the modification of 1st Embodiment of this invention. FIG. 6 is a cross-sectional view partially showing a display device which is an electronic device according to a second embodiment of the invention. FIG. 6 is a plan view showing a capacitive sensor substrate that constitutes a display device that is an electronic device according to a second embodiment of the invention. FIG. 6 is a circuit diagram illustrating a circuit configuration of an array substrate of a display device that is an electronic device according to a second embodiment of the present invention. FIG. 6 is a plan view showing a unit cell of a display device which is an electronic device according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view showing a thin film transistor included in a capacitive sensor substrate that constitutes a display device that is an electronic device according to a second embodiment of the present invention. It is a top view which shows the IC card which is an electronic device which concerns on 3rd Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In the following description, the same or substantially the same function and component will be denoted by the same reference numeral, and the description thereof will be omitted or simplified, or will be described only when necessary. In each drawing, in order to make each constituent element recognizable in the drawings, the dimensions and proportions of each constituent element are appropriately different from the actual ones. As necessary, illustrations of some elements that are difficult to illustrate, such as the configuration of a plurality of layers forming a semiconductor channel layer, the configuration of a plurality of layers forming a conductive layer, and the like, are omitted.
Further, in order to explain the embodiments of the present invention in an easy-to-understand manner, illustration of electrical circuit elements, display function layers, and the like may be simplified.
In each of the embodiments described below, a characteristic part will be described, and for example, a description will be omitted for a part that is not different from a component used in a normal electronic device and the electronic device according to the present embodiment. Sometimes.

In the specification, the wording "planar view" means "planar view from the first surface" and "planar view from the second surface". Further, the “plan view seen from the first surface” is the “plan view” in the configuration in which the dielectric layer, the insulating layer, and the capacitor pattern stacked on the second surface (back surface) of the substrate are stacked in this order. Means The phrase “planar view seen from the second surface” means a planar view seen from a direction opposite to the “planar view seen from the first surface”. The “plan view seen from the second surface” means “plan view” in the configuration in which the capacitor pattern, the insulating layer, and the dielectric layer are laminated in this order on the second surface of the substrate. In other words, in the embodiment of the present invention, it means that the pointer (finger or the like) used for touch sensing is arranged in a position closer to the pointer than the capacitor pattern in the direction in which the substrate approaches. To do.

Also, in the specification, ordinal numbers such as “first” and “second” are added to avoid confusion among constituent elements, and the quantity is not limited. The first conductive pattern and the second conductive pattern may be simply referred to as a conductive pattern or a conductive layer. Each of the conductive layers (conductive patterns) has a three-layer structure in which a metal layer or an alloy layer is sandwiched by conductive oxide layers. A structure or pattern obtained by processing a conductive layer so as to have a shape of a wiring, a capacitor, an electrode, or the like may be referred to as a conductive pattern.

In the embodiment of the present invention, the main thin film transistor includes an oxide semiconductor layer as a channel layer. Further, the thin film transistor may include a polysilicon semiconductor layer as a channel layer, if necessary. In addition, the drain electrode and the source electrode in the embodiments described later may be arranged interchangeably. In the following embodiments, the scanning line may also serve as the power supply line in some cases.

In the embodiment of the present invention, the “display function layer” included in the electronic device (including the display device) includes a plurality of light emitting diode elements referred to as LEDs (Light Emitting Diodes) and a plurality of organic EL elements referred to as OLEDs ( Either an organic electroluminescence device or a liquid crystal layer can be used.

(First embodiment)
(Circuit structure and planar structure of the capacitive sensor substrate)
FIG. 1 is a partially enlarged view showing a configuration of a unit cell (sensing element) of a capacitive sensor substrate 100A according to the first embodiment of the present invention, which shows a unit cell including a capacitor pattern 12 and a thin film transistor (first thin film transistor 31). It is a circuit diagram shown. In the circuit diagram shown in FIG. 1, for the sake of easy understanding of the description, the minimum element configuration is shown as the configuration of the unit cell. That is, FIG. 1 exemplifies the minimum element configuration in which the first thin film transistor 31 includes only one in the partitioned region partitioned by the scanning line 13 and the output line 21.
Note that, although FIG. 1 shows a circuit diagram, a schematic configuration of the rectangular capacitor pattern 12 and the unit cell (detecting element) is shown for the sake of easy understanding of the subsequent description. The capacitor pattern 12 is arranged in a unit cell 19 defined by a scanning line and an output line. The capacitor pattern 12 may have a parallelogram shape instead of a rectangular shape, and an opening may be formed inside the capacitor pattern 12.

(Unit cell)
The unit cell 19 detects the electrostatic capacity of an operation including the contact of a pointer such as a finger, or the electrostatic capacity of a minute uneven portion such as a fingerprint. In the present embodiment, the “fingerprint sensor” means a sensor that detects the unevenness of the skin of the living body by capacitance and is not limited to the “fingerprint”. For example, the fingerprint authentication may be alternative authentication using a part of the body (body) such as a palm wider than the area of the finger.

The unit cell 19 is a region divided by the scanning line 13 that drives the first thin film transistor 31 and the output line 21 to which an output signal is applied from the first thin film transistor 31. As will be described later, if it is limited to the outermost periphery of the display area, apparently one of the scanning line 13 and the output line 21 is not arranged, and the unit cell is not partitioned by the scanning line 13 and the output line 21. However, in the embodiment of the present invention, such a unit cell is also treated as a “unit cell”. In addition, the unit cell can also be referred to as a “sensing unit related to touch sensing”.

Further, as described later, a conductive layer (conductive pattern) in which a dielectric layer, a metal layer or an alloy layer is sandwiched by conductive oxides, a first thin film transistor, one capacitor pattern, a light absorbing layer, etc., if necessary. The sensing element constituted by is defined as a unit cell 19. A plurality of unit cells 19 are arranged in a matrix on the capacitive sensor substrate 100A. In the following description, the sensing element or the unit cell may be used as a technical term for the description. The sensing element or unit cell 19 has the same meaning as a region where the capacitor pattern 12 is formed, that is, a region defined by the scanning line 13 and the output line 21. In plan view, the scanning line 13 extends parallel to the first direction, and the output line 21 extends parallel to the second direction orthogonal to the first direction. In the first embodiment, the scanning line also serves as the power supply line. Further, the roles (functions) of the scanning line and the output line can be interchanged.

The change in capacitance when a pointer such as a finger comes into contact with or comes close to the capacitance sensor substrate 100A is a change in capacitance of the dielectric layer 3 on each capacitor pattern 12 via the first thin film transistor 31. Detected. From this point of view, a general mutual capacitance type touch sensing technology for detecting a capacitance change between conductive wirings such as a plurality of orthogonal ITO (transparent conductive films) and the technology according to the first embodiment of the present invention are basically. Differently. The technology according to the first embodiment of the present invention is a technology close to the self-capacitance method.

(Detection element)
As shown in FIG. 1, the sensing element (unit cell 19) includes a first conductive pattern 10P, a second conductive pattern 20P, a first thin film transistor 31, and a capacitor pattern 12.
The first thin film transistor 31 includes a first source electrode 22 and a first drain electrode 23 that are a part of the second conductive pattern 20P, and a first gate electrode 11 that is a part of the first conductive pattern 10P. The first thin film transistor 31 includes at least a first source electrode 22, a first drain electrode 23, and a first gate electrode 11.

In detail, the first thin film transistor 31 has a first gate electrode 11, a first source electrode 22, a first drain electrode 23, a first channel layer 16 (described later, an oxide semiconductor layer), and a gate insulating layer 18. . The first source electrode 22 is connected to the scanning line 13 via the contact hole 29. The first drain electrode 23 is electrically linked to the output line 21.

The output line 21, the first source electrode 22, and the first drain electrode 23 form a second conductive pattern 20P. In other words, the second conductive pattern 20P is formed of the second conductive layer 20.
The capacitor pattern 12, the first gate electrode 11, and the scanning line 13 form a first conductive pattern 10P. In other words, the first conductive pattern 10P is formed of the first conductive layer 10.

The first conductive pattern 10P and the second conductive pattern 20P may be simply referred to as a conductive pattern. The first conductive layer 10 and the second conductive layer 20 may be simply referred to as conductive layers. As described later, the conductive layer preferably has a structure in which a metal layer or an alloy layer is sandwiched between conductive oxide layers.

(Cross-sectional structure of capacitive sensor substrate)
FIG. 2 is a partial cross-sectional view showing the configuration of the capacitive sensor substrate 100A according to the first embodiment of the present invention, which is a cross-sectional view showing a unit cell along the line AA ′ shown in FIG. FIG. 2 mainly shows the cross-sectional structure of the capacitor pattern 12 and the first thin film transistor 31.

As shown in FIG. 2, the capacitive sensor substrate 100A has a substrate 102 having a first surface 1 and a second surface 2. The first surface 1 is a touch input surface (touch sensing input surface) with which a pointer such as a finger approaches or touches (touches). Reference numeral TD in FIG. 2 indicates a direction in which a pointer such as a finger approaches or contacts the first surface 1.
A dielectric layer 3 is formed above the second surface 2, and a first conductive pattern 10P and a second conductive pattern 20P are formed on the dielectric layer 3. In the structure shown in FIG. 2, the dielectric layer 3 is formed on the second surface 2 so as to cover the entire surface of the unit cell 19. In the thickness direction of the substrate 102, the dielectric layer 3 is located closer to the first surface 1 (touch sensing input surface) than the capacitor pattern 12.

In the region of the unit cell 19 where the first thin film transistor 31 is not formed, the first insulating layer 17, the scanning line 13 and the capacitor pattern 12 forming the first conductive pattern 10P are formed on the dielectric layer 3. Has been done. The dielectric layer 3 overlaps with the capacitor pattern 12 in a plan view.

In the region of the unit cell 19 where the first thin film transistor 31 is formed, the first insulating layer 17 and the first source electrode 22 and the first drain electrode forming the second conductive pattern 20P are formed on the dielectric layer 3. 23 and an output line 21 are formed. Further, the first channel layer 16 which is a component of the first thin film transistor 31 is formed on the first insulating layer 17, and the first channel layer 16 is formed on the first channel layer 16 with the gate insulating layer 18 interposed therebetween. The first gate electrode 11 forming the conductive pattern 10P is formed.

In other words, in the region where the first thin film transistor 31 is formed, the dielectric layer 3, the first insulating layer 17, and the second conductive layer 20 (second conductive pattern) are formed on the second surface 2 of the substrate 102. 20P) are laminated in this order. Further, the first conductive layer 10 (first conductive pattern 10P) is formed on the second conductive layer 20 via the gate insulating layer 18. Further, the second insulating layer 27 and the third insulating layer 28 are stacked in this order on the first conductive layer 10. That is, the first conductive layer 10 and the second conductive layer 20 are provided above the second surface 2.

As shown in FIG. 2, the dielectric layer 3 and the first insulating layer 17 are laminated in this order on the second surface 2 of the substrate 102. In other words, the dielectric layer 3 is provided on the second surface 2, and the first insulating layer 17 is provided so as to cover the exposed surface (surface) of the second surface 2 and the surface of the dielectric layer 3. ing. Further, on the first insulating layer 17, the output line 21, the first source electrode 22, the first drain electrode 23, and the like that form the second conductive pattern 20P, and the first channel layer 16 are provided. A gate insulating layer 18 is provided so as to cover the first channel layer 16, the first source electrode 22, the first drain electrode 23, and the like. Further, on the gate insulating layer 18, the capacitor pattern 12 and the first gate electrode 11 which form the first conductive pattern 10P are provided. As shown in FIG. 1, the capacitor pattern 12 and the first gate electrode 11 are electrically linked.

The dielectric layer 3 is provided closer to the touch input surface (first surface 1) than the capacitor pattern 12. The position of the first channel layer 16 which is an oxide semiconductor will be described in detail later.

The second insulating layer 27 and the third insulating layer 28 may be formed of, for example, an inorganic insulating film made of silicon oxide or silicon nitride, or a flattening film made of a transparent resin is laminated. It may have a different configuration.
The third insulating layer 28 serves as a protective substrate that protects the capacitive sensor substrate 100A when a finger or a pointer contacts (touches) the capacitive sensor substrate 100A. As the third insulating layer 28, a substrate having strength such as tempered glass and sapphire substrate can be adopted.
When the capacitance sensor substrate 100A is applied to a plastic card such as an IC card, a hard resin plate can be used as the third insulating layer 28. Although the thickness of the third insulating layer 28 is appropriately set, the resolution related to touch sensing in the capacitive sensor substrate 100A can be easily improved when the thickness of the third insulating layer 28 is thin.

As a specific substrate material of the substrate 102 applicable to the capacitance sensor substrate 100A, a sapphire substrate, a substrate made of aluminosilicate glass, an acrylic substrate, a polyester film, a polyimide film, or a TAC film used for a polarizing plate, Various substrates such as a resin substrate laminated with polyvinyl chloride used for IC cards (including security cards, data cards, smart cards) and the like can be used. The substrate 102 does not need to be transparent, and a substrate colored in white or another color may be used as the substrate 102. However, when the capacitive sensor substrate 100A is used in a device that performs fingerprint authentication, it is desirable that the capacitive sensor substrate 100A be a substrate that is rigid like a glass substrate and has a highly accurate flatness and flatness. A glass substrate reinforced by an ion exchange method or a quenching method can be applied to the substrate 102.

The thickness of the substrate 102 can be selected from the range of 0.1 mm to 1.5 mm, for example. However, the thickness of the substrate 102 is not limited to this thickness range. In the case of the present embodiment, the resolution of touch sensing can be improved by reducing the thickness of the substrate 102. When the capacitive sensor substrate 100A according to the present embodiment is applied to a laminated body of resin substrates such as an IC card, an antenna, a control IC chip, and an antenna and a control IC are provided on a resin sheet called an inlet. Conductor wiring for electrically connecting to the IC chip may be provided, and then a plurality of layers of resin sheets may be attached to the capacitive sensor substrate 100A to form a card-shaped laminated body.

(Dielectric layer)
The dielectric layer 3 according to the embodiment of the present invention contains carbon. Therefore, the dielectric layer according to the embodiment of the present invention can also be referred to as a black dielectric layer.
Specifically, the dielectric layer 3 is composed of a dispersion in which carbon is dispersed in a resin, or a dispersion in which fine particles such as a metal oxide or a metal nitride are further added to carbon. That is, the dielectric layer 3 is a resin dispersion containing carbon and at least one fine particle selected from the group consisting of metal oxides, metal oxynitrides, and metal nitrides.

As shown below, the present inventors have found that the carbon dispersion can be adjusted in various electrical characteristics as a dielectric for touch sensing applications. The carbon dispersion is suitable as a dielectric used for capacitance-type touch sensing because it can adjust electrical characteristics such as relative permittivity, dielectric loss, and resistivity in a wide range.

Note that in the following description, fine particles may be simply referred to as powder. The dielectric layer 3 covers at least the capacitor pattern 12 in plan view. The size of the dielectric layer 3 in plan view may be equal to the size of the capacitor pattern 12. Alternatively, the dielectric layer 3 may be formed so as to cover the whole of the plurality of unit cells.

By adjusting the dispersion state, concentration, composition, film thickness, etc. of carbon or the like in the dielectric layer 3, it is possible to adjust the electrical characteristics of the dielectric layer 3 so as to have a high relative dielectric constant such as 10 to 700. It is possible. The relative permittivity of the dielectric layer 3 can be set to 150 or more by adjusting the dispersed state of carbon or adding fine particles of ferroelectric substance or fine particles of paraelectric substance to the dielectric layer 3.
When the capacitive sensor substrate 100A according to the present embodiment is applied to an electronic device in which an increase in power consumption is a problem due to the dielectric loss (tan δ) of the dielectric layer 3 (for example, mobile device), the dielectric layer 3 of The relative dielectric constant may be suppressed within the range of 15 to 100.

As a material forming the dielectric layer 3 according to the embodiment of the present invention, a dispersion in which carbon is dispersed in a resin such as acryl, epoxy, or polyimide can be used. Furthermore, carbon nanotubes, carbon nanohorns, carbon nanobrushes, etc. may be mixed and dispersed in the resin. Alternatively, part of the structure of the dielectric layer 3 may be replaced with carbon and the carbon nanotubes may be dispersed in the resin. Hereinafter, the dielectric layer 3 may be simply referred to as a dielectric.

Regarding the above dielectric, it is desirable to add paraelectric powder to the dielectric for the purpose of improving the dispersed state of carbon in the dielectric layer 3 and not increasing the dielectric loss. A paraelectric material is a dielectric material that does not have electric polarization in a state where an electric field is not applied and has a small dielectric loss. In the embodiment of the present invention, the paraelectric metal oxide or metal nitride has a relative dielectric constant of 110 or less and a dielectric loss of 0.00001 to 0.1. It is defined as the powder of the product. Here, the measurement frequency of these electrical characteristics is a touch sensing frequency described below, and is measured at room temperature of 20 ° C., for example. These electrical characteristics including the resistivity can be measured by a technique such as a parallel plate capacitor method using a measuring instrument such as an impedance analyzer or an LCR meter. The measurement voltage may be in the range of 0.5V to 10V, for example. As the measurement voltage and the measurement frequency, it is desirable to use values close to the measurement voltage and the measurement frequency used for actual touch sensing.

In addition to carbon, the dielectric layer 3 includes extender pigments such as calcium oxide, calcium carbonate, barium sulfate, silicon dioxide, kaolin, and clay for the purpose of adjusting the dispersed state of carbon and adjusting the relative dielectric constant. Can be added to the dielectric layer 3. Alternatively, in addition to carbon, a dispersion of resin in which titanium oxide, titanium nitride, titanium oxynitride, titanium black, barium zirconate, magnesium titanate, calcium sulfate, or another dielectric powder having a high dielectric constant is added. Can be used. The fine particles are, for example, fine particles having an average particle diameter in the range of 0.02 μm or more and 2 μm or less. Note that barium titanate, which is known as a ferroelectric material, is not a preferable material as a dielectric material used for touch sensing because it has toxicity and dielectric loss often exceeds 0.4.

The dielectric layer 3 according to the embodiment of the present invention is composed of fine particles of metal oxide such as carbon or titanium oxide dispersed in a resin and having a relative dielectric constant of 10 to 700, or 15 to 100. There is. The dielectric loss (tan δ) of the dispersion (solid) of the dielectric layer 3 may be in the range of 0.01 or more and less than 0.2 at the touch sensing frequency in the range of 200 Hz to 500 KHz, for example. Further, the value of the dielectric loss is preferably 0.08 or less. If the value of dielectric loss exceeds 0.2, power consumption related to touch sensing increases, which is not preferable. When a dispersion having a small dielectric loss of 0.01 or less is used in a dielectric layer using a resin dispersion such as carbon or titanium oxide, it may be difficult to secure a large relative dielectric constant.

When resetting the potential of the capacitor pattern 12 to be described later, the resistivity of the dielectric layer 3 may be adjusted so that the reset is completed within the reset period. In other words, in order to set the potential of the capacitor pattern 12 to the reset potential such as ground, the resistivity of the dielectric is set to less than 1 × 10 ¹³ Ωcm, and the relaxation time (or time constant) is shortened. You can

Further, for the purpose of maintaining the electrostatic capacity by touching, for example, the resistivity of the dielectric layer 3 may be 1 × 10 ¹³ Ωcm or more. However, if the resistivity of the dielectric is set to 1 × 10 ¹⁴ Ωcm or more, the relaxation time may be adversely affected. Therefore, the technical value of making the resistivity of the dielectric material 1 × 10 ¹⁴ Ωcm or more is low. For example, when the dielectric layer 3 has a resistivity of 1 × 10 ¹⁴ Ωcm or more, and further 1 × 10 ¹⁵ Ωcm or more, the potential of the capacitor pattern 12 is reset (in the reset period after touch sensing by a pointer such as a finger). For example, it may be difficult to completely perform (return to the ground potential). By setting the resistivity of the dielectric layer 3 to 1 × 10 ⁸ Ωcm or more and less than 1 × 10 ¹³ Ωcm, the reset period can be shortened. If the dielectric layer has a resistivity lower than 1 × 10 ⁷ Ωcm, sufficient capacitance cannot be ensured, and there is a concern that touch sensing accuracy may be reduced.

As the structure of the dielectric layer 3, it is possible to adopt a multilayer structure in which a plurality of layers having different electrical characteristics such as relative permittivity and resistivity are laminated. Alternatively, the relative permittivity or the resistivity in the direction in which the pointer such as a finger approaches or contacts the first surface 1 of the capacitive sensor substrate 100A (normal direction to the first surface 1), that is, in the film thickness direction of the dielectric layer 3. It is possible to change electrical characteristics such as. In this film thickness direction, the relative dielectric constant of the dielectric located near the capacitor pattern 12 may be increased, and the relative dielectric constant of the dielectric located away from the capacitor pattern 12 may be decreased. From the viewpoint described above, the carbon concentration contained in the dielectric layer 3 may be adjusted along the thickness direction of the dielectric layer 3. Furthermore, the dispersion state of carbon may be changed along the thickness direction of the dielectric layer 3.

The dielectric layer 3 may have a gradient of dielectric constant along the thickness direction. The dielectric layer 3 may partially have a high relative dielectric constant near the interface between the capacitor pattern 12 and the first insulating layer 17.

As the substrate 102, a substrate having a low relative permittivity or a material having a relative permittivity of 8 or less can be used. The relative dielectric constant of the substrate 102 may be, for example, 5 or less. Further, it is desirable that the member located at the interface between the substrate 102 and the capacitor pattern 12 has a high relative dielectric constant. In other words, it is desirable that the dielectric layer 3 located at the interface between the substrate 102 and the capacitor pattern 12 has a high relative permittivity. For example, when a protective substrate such as a glass substrate or a resin substrate is used as the third insulating layer 28 shown in FIG. 2, in the configuration in which the protective substrate is arranged on the capacitive sensor substrate 100A, the protective substrate (eg, cover glass) is used. It is desirable that the dielectric layer 3 have a relative dielectric constant that is three times or more the relative dielectric constant of.

The electrical characteristics of the dielectric layer 3 can be adjusted variously according to the content of touch sensing as described above. The fine particles are, for example, fine particles having an average particle size in the range of 0.02 to 2 μm.

The distance Pz between the pointer such as a finger and the dielectric layer may practically be in the range of 0.1 mm to 1.5 mm. When the capacitive sensor substrate 100A is applied to a display device such as a liquid crystal, the distance Pz includes the thickness of a cover glass for protection, a polarizing plate, a retardation plate and the like. When the capacitive sensor substrate 100A is not applied to the display device, for example, when the capacitive sensor substrate 100A is applied to a fingerprint sensor, the above members are unnecessary and the distance Pz between the pointer such as a finger and the dielectric layer is small. it can.

The distance Pz is important for the resolution of the capacitive sensor substrate 100A. The thickness of the dielectric layer 3 is not so important from this point of view. In the embodiment of the present invention, the resin dispersion containing mainly carbon is used for the dielectric layer 3, and the thickness of the dielectric layer 3 may be in the range of 0.2 μm to 10 μm. The viscosity of the resin dispersion containing mainly carbon is adjusted by adding an organic solvent and the like, and the resin dispersion can be formed by using a general coating technique such as a curtain coater or a spin coater. In the method of coating and forming a dispersion, it is difficult to realize a uniform film having a thickness of 0.1 μm or less, and conversely, when a film thickness of the dielectric exceeds 10 μm. Is likely to cause unevenness. The need for a dielectric layer having a thickness greater than 10 μm is low.

(First thin film transistor)
FIG. 3 is a partial cross-sectional view showing the configuration of the capacitive sensor substrate 100A according to the first embodiment of the present invention, which is a partially enlarged view of the first thin film transistor 31 shown in FIG.
The dielectric layer 3 is formed on the substrate 102, and the first insulating layer 17 is formed on the dielectric layer 3. The first channel layer 16, the first source electrode 22, the first drain electrode 23, the first gate electrode 11, and the like, which form the first thin film transistor, are formed on the first insulating layer 17. That is, the first thin film transistor 31 is provided above the second surface 2.

The first thin film transistor 31 shown in FIG. 3 is a top-gate transistor. That is, the first gate electrode 11 is provided above the first source electrode 22, the first drain electrode 23, and the first channel layer 16 in a cross-sectional view.
Each of the first source electrode 22, the first drain electrode 23, and the first gate electrode 11 is formed of a conductive layer, and a metal layer or an alloy layer is sandwiched between conductive oxide layers as described later. (Three-layer structure).
On the other hand, the first channel layer 16 is made of an oxide semiconductor. Both ends of the first channel layer 16 are covered with a conductive oxide layer (reference numeral 41 in FIG. 4) forming the second conductive layer 20. That is, as shown in FIG. 4 to be described later, in the cross-sectional view along the thickness direction of the first thin film transistor 31, the first thin film transistor 31 has an overlapping portion in which the end portion of the first channel layer 16 is covered with the second conductive layer 20. It has a section 44. The overlapping portion 44 forms an interface where the first conductive oxide layer 41 and the first channel layer 16 are in contact with each other.

(Oxide semiconductor layer)
Examples of the oxide semiconductor applicable to the first channel layer 16 include oxide semiconductors selected from two or more of indium oxide, zinc oxide, gallium oxide, silicon oxide, antimony oxide, bismuth oxide, cerium oxide, tin oxide and the like. For example, the oxide semiconductor layer may include indium oxide and at least one of antimony oxide and bismuth oxide. Further, the oxide semiconductor layer may include at least one of cerium oxide and tin oxide.

The film thickness of the oxide semiconductor layer can be, for example, 30 nm or more and 90 nm or less. An oxide semiconductor obtained by adding at least one of antimony oxide and bismuth oxide to indium oxide has an advantage that it can be crystallized by low temperature annealing at 340 ° C. or lower. The heat treatment at a temperature higher than 350 ° C. has a problem that copper contained in the conductive layer (conductive pattern) is diffused in the semiconductor layer. The diffusion of copper impairs the problem that the resistance value of the copper wiring increases and the characteristics of the thin film transistor. Therefore, it is preferable to employ an oxide semiconductor that is crystallized by annealing at 350 ° C. or lower.

When the first channel layer 16 is formed using the above oxide semiconductor, the film can be formed at room temperature (20 ° C.), for example. Therefore, a resin substrate having poor heat resistance can be applied to the substrate 102. On the other hand, when the first channel layer 16 is composed of a polysilicon semiconductor, it is difficult to apply a resin substrate because the semiconductor forming step includes a laser annealing step of heating the semiconductor at around 600 ° C.

Generally, as a structure of a thin film transistor, a structure in which a channel layer is made of an amorphous silicon semiconductor or a structure made of a polysilicon semiconductor is known. The structure using an amorphous silicon semiconductor has a low electron mobility and is insufficient as a semiconductor for a touch sensor application. In the case of a structure using a polysilicon semiconductor, the polysilicon semiconductor has a high electron mobility, but there is a drawback in that the leakage current becomes large as the performance of the transistor and it is difficult to maintain the electrostatic capacity during touch sensing. In particular, both the amorphous silicon semiconductor and the polysilicon semiconductor have a low electrical breakdown voltage, and there is a drawback that the transistor is destroyed depending on the degree of change in capacitance during touch sensing.

On the other hand, the electrical resistance of the oxide semiconductor according to this embodiment is 10 times or more higher than that of the silicon-based semiconductor, and the electron mobility is also high. An oxide semiconductor is preferable as a channel layer of a thin film transistor which drives a touch sensor. An oxide semiconductor is suitable as a semiconductor material forming a fingerprint sensor.

Furthermore, the oxide semiconductor forming the first channel layer 16 may include cerium oxide in the oxide semiconductor. At this time, assuming that the total of elements not counting oxygen is 100 at% (metal element conversion), the amount of cerium is 0.2 at% or more and 10 at% or less. More specifically, the oxide semiconductor is a complex oxide containing indium oxide, antimony oxide, indium oxide, and cerium oxide having an amount less than each amount of antimony oxide, and counting oxygen. If the total of the elements not to be added is 100 at%, the amount of each of indium and antimony is 40 at% or more. For example, when the total of elements that do not count oxygen in this oxide semiconductor is 100 at%, the amount of each of indium and antimony is 48 at%, and the amount of cerium is 4 at%. Unlike gallium oxide and indium oxide, antimony oxide and cerium oxide have high industrial value because they can be obtained at a low price. In the above, cerium oxide may be replaced with tin oxide. In this case, the same effect can be obtained. Further, as the oxide semiconductor, a complex oxide containing one or both of cerium oxide and tin oxide in an amount smaller than the amounts of indium oxide, antimony oxide, indium oxide, and antimony oxide is adopted. Good. As described above, a complex oxide containing indium oxide as a base material (in an oxide semiconductor, a base material is defined as containing 40 at% of indium in terms of indium which does not count oxygen) is added to cerium oxide or an oxide. By adding tin, it is possible to obtain a composite oxide having enhanced acid resistance.

It is assumed that the carrier (electron) Fermi levels of the oxide semiconductor layer including indium oxide as a base material and the conductive oxide layer including indium oxide as a base material are close to each other. It becomes easy to supply carriers to the channel layer from the overlapping portion 44 (interface described later) where the conductive oxide layer (first conductive oxide layer 41 described below) and the channel layer overlap. For example, the carrier concentration of the oxide semiconductor layer can be 1 × 10 ¹⁸ / cm ³ or lower and 1 × 10 ¹² / cm ³ or higher. The carrier concentration of the conductive oxide layer can be set within the range of 1 × 10 ²¹ / cm ³ or less and 1 × 10 ¹⁹ / cm ³ or more.

In order to adjust the electrical characteristics and mobility of the oxide semiconductor, for example, the indium oxide concentration or the cerium oxide concentration may be changed in the thickness direction of the first channel layer 16. Further, tin oxide may be added to such an oxide semiconductor to change the tin oxide concentration. Alternatively, the acid resistance of the first channel layer 16 can be increased by making the composition of the surface layer of the first channel layer 16 rich in cerium oxide or tin oxide in order to extend the wet etching processability of the source electrode or the like. . Although an etching stopper layer may be laminated on the first channel layer 16, the complex oxide thin film containing cerium oxide or tin oxide becomes a film with high acid resistance by annealing at 180 ° C. or higher. Therefore, it is not necessary to positively insert the etching stopper layer, and the step of forming the etching stopper layer can be omitted. This acid resistance can also be obtained by increasing the concentrations of cerium oxide and tin oxide in the composite oxide film.

The annealing temperature may be in the range of 180 ° C to 340 ° C, and a temperature higher than 200 ° C is more preferable. By performing pre-annealing at about 220 ° C. before forming the pattern of the source electrode or the like, the resistance of the oxide semiconductor layer (composite oxide film) to the etchant can be improved. This pre-annealing may be performed before forming the second conductive layer 20 that forms the source electrode and the drain electrode.

Note that the oxide semiconductor layer described above can be applied to other thin film transistors different from the first thin film transistor 31, in addition to the first channel layer 16 forming the first thin film transistor 31.

(First conductive layer)
The first gate electrode 11, the capacitor pattern 12 (capacitor electrode), and the scan line 13 form a first conductive pattern 10P. In an embodiment described below, the first conductive pattern 10P may have a configuration including a reset line or a power line. These first conductive patterns 10P are formed of the first conductive layer 10. The shape of the capacitor pattern 12 in plan view is not limited to the rectangular shape shown in FIG. 1, but may be a parallelogram or a polygonal shape (dog-leg pattern) in which the center line is a dogleg, and a plurality of parallelograms with different angles are continuous. Shape). The capacitor pattern 12 is connected to the first gate electrode 11. The capacitor pattern 12 supplies the first thin film transistor 31 with a change in capacitance when a pointer such as a finger comes into contact with or approaches the first surface 1 as a signal. In this sense, the capacitor pattern 12 may be referred to as a capacitor electrode.

The first conductive layer 10 includes at least a metal layer having high conductivity. Similarly, the second conductive layer 20 also includes at least a highly conductive metal layer. The second conductive layer 20 includes at least a source electrode and a drain electrode as the second conductive pattern 20P. The structure of a thin film transistor is roughly classified into a bottom gate structure (see FIG. 8) in which a gate electrode is formed before forming a source electrode and a top gate structure (see FIG. 3) in which a gate electrode is formed after forming a source electrode. It Therefore, the structure of the thin film transistor may be reversed depending on the order of forming the first conductive layer 10 and the second conductive layer 20.

Note that in the embodiment of the present invention, the structure of the thin film transistor may be a multi-gate structure in which one transistor is provided with a plurality of gate electrodes, or the back gate electrode may be formed on the opposite surface via the channel layer. It may be a back gate structure provided. The potential of the back gate electrode can be 0 V or ground, for example. The threshold value (Vth) can be controlled by controlling the voltage applied to the back gate electrode.

(Second conductive layer)
The output line 21, the first source electrode 22, and the first drain electrode 23 form the second conductive layer 20 having the second conductive pattern 20P. The roles (functions) of the scanning line and the output line can be interchanged. Further, the roles (functions) of the source electrode and the drain electrode can be switched. That is, in FIG. 1, reference numeral 13 may be an output line, reference numeral 21 may be a scanning line, reference numeral 22 may be a first drain electrode, and reference numeral 23 may be a first source electrode.

In the embodiment of the present invention, the capacitor pattern 12 is laminated on the dielectric layer 3, and the dielectric layer 3 is closer to the first surface 1 where the touch sensing is input than the capacitor pattern 12. The capacitor pattern 12 and the first gate electrode 11 are formed of the same first conductive layer 10. In other words, in the top gate structure shown in FIGS. 2 and 3, the first conductive layer 10 is located farther from the first conductive layer 20 than the second conductive layer 20 from which the touch sensing input is made.

(Structure of first conductive layer and second conductive layer)
The first conductive layer 10 and the second conductive layer 20 have a structure (three-layer structure) in which a metal layer or an alloy layer is sandwiched between conductive oxide layers.
The film thickness of the metal layer forming each of the first conductive layer 10 and the second conductive layer 20 can be, for example, 500 nm or more and 3000 nm or less. The thickness of the conductive oxide layer forming each of the first conductive layer 10 and the second conductive layer 20 can be, for example, 200 nm or more and 2000 nm or less. When the metal layer is made of a metal containing copper, the thickness of the conductive oxide layer can be 200 nm or more to suppress the diffusion of copper in the thickness direction. The formation of the metal layer having a film thickness of 3000 nm or more and the formation of the conductive oxide layer having a film thickness of 2000 nm or more are inefficient in terms of production.

(Metal layer, alloy layer)
As the metal layer or alloy layer, a metal having excellent conductivity such as silver, copper, aluminum or zinc, or an alloy layer of the above metals can be applied. Hereinafter, copper and a copper alloy will be described as typical examples, but the basic technical means according to the embodiment of the present invention can be applied to metals such as silver and zinc.

As the alloying element to be added to copper, it is possible to select an alloying element whose specific resistance increase rate of the copper alloy layer is 1 μΩcm / at% or less. The specific resistance (electrical resistivity) of the copper alloy layer can be set within the range of 1.9 μΩcm to 6 μΩcm, for example.

As an element added to the copper alloy, an additive element (copper alloy element) having a small effect on the electric resistivity of the copper alloy (alloy element of copper) is palladium (Pd), magnesium (Mg), beryllium (Be), Examples include gold (Au), calcium (Ca), cadmium (Cd), zinc (Zn), and silver (Ag). The increase in electrical resistivity when such an element is added to pure copper at 1 at% is approximately 1 μΩcm or less. The increase in electrical resistivity when calcium (Ca), cadmium (Cd), zinc (Zn), and silver (Ag) are added to pure copper is 0.4 μΩcm / at% or less. Therefore, it is preferable to use calcium (Ca), cadmium (Cd), zinc (Zn), and silver (Ag) as alloy elements. Considering economical efficiency and environmental load, it is preferable to use zinc and calcium as alloying elements. Zinc and calcium can each be added as alloying elements to copper up to 5 at%.

When the thickness of the copper layer or copper alloy layer is 100 nm or more or 150 nm or more, the conductive layer hardly transmits visible light. Therefore, if the copper layer or the copper alloy layer forming the conductive layer according to the present embodiment has a film thickness of 100 nm to 500 nm, for example, sufficient light shielding properties can be obtained. The thickness of the copper alloy layer may exceed 500 nm. As will be described later, the material of the conductive layer can be applied to wirings and electrodes provided on the substrates of electronic devices and display devices. Further, in the present embodiment, as a structure of a wiring electrically associated with an active element (thin film transistor), for example, as a structure of a gate electrode or a gate line, a laminated structure in which a copper alloy layer is sandwiched by conductive metal oxide layers A structure can be adopted. In other words, the conductive layer (conductive pattern) according to the embodiment of the present invention may have a laminated structure in which a copper alloy layer is sandwiched by conductive metal oxide layers.

(Conductive oxide layer)
As a material for the conductive oxide layer, a mixed oxide containing 40 at% or more of indium oxide can be exemplified. As a method of forming a three-layer structure in which a copper layer or a copper alloy layer is sandwiched by two conductive oxide layers, first, for example, a mixed oxide layer A / copper alloy layer is formed on a substrate such as glass. Deposit three layers consisting of B / mixed oxide layer C). After that, the three layers are processed by a wet etching process so as to have almost equal line widths. Alternatively, the line widths of the mixed oxide layer A, the copper alloy layer B, and the mixed oxide layer C, which are sequentially formed on the surface of the glass substrate by the wet etching step, are determined by the condition "line width of mixed oxide layer A> It is preferable that the line width of the copper alloy layer B> the line width of the mixed oxide layer C is satisfied so that the line width becomes smaller in order.

Normally, ITO (mixed oxide containing indium oxide and tin oxide) has a more noble oxide than copper and copper alloys. Therefore, copper is selectively etched, and the line widths of the three layers do not satisfy the above conditions. Therefore, the corrosion potential is adjusted by adding an easily soluble oxide such as zinc oxide, gallium oxide, or antimony oxide to indium oxide to obtain a mixed oxide layer having the same corrosion potential as the metal layer such as copper.

As described above, each of the first conductive layer 10 and the second conductive layer 20 is composed of a structure (three-layer structure) in which a metal layer or an alloy layer is sandwiched by conductive oxide layers. That is, the first gate electrode 11, the capacitor pattern 12, the scanning line 13, which forms the first conductive layer 10, and the output line 21, which forms the second conductive layer 20, are made of a metal or alloy having excellent conductivity. Therefore, the responsiveness of capacitance detection and the S / N ratio can be improved. Examples of the metal having a high conductivity as described above include silver, copper, aluminum and the like. In consideration of reliability, silver alloy, copper alloy, aluminum alloy may be adopted. Since silver and copper have higher conductivity than aluminum, it is preferable to use silver or copper, or a silver alloy or a copper alloy for the metal layer. By using a conductive layer in which a metal layer or an alloy layer is sandwiched by conductive oxide layers as the configuration of the capacitor pattern 12, the scanning line 13, and the output line 21, a plurality of advantages described below can be obtained.

First merit: Adhesiveness For example, when wiring having a single layer of copper alloy (copper alloy wiring) is used as the structure of the conductive layer (in the case of a structure not using conductive oxide), a pointer such as a finger Depending on the magnitude of the electrostatic capacity of the copper alloy, electrostatic breakdown may occur and the copper alloy wiring may be chipped or peeled off. Furthermore, silver, silver alloys, copper, or copper alloys have insufficient adhesion to resin or glass. Further, electrostatic breakdown often occurs during pure water cleaning in the manufacturing process.

On the other hand, in the present embodiment, a conductive layer in which a metal layer or an alloy layer is sandwiched by conductive oxide layers is adopted. The conductive oxide has extremely high adhesion to silver, a silver alloy, copper, a copper alloy, or the like, and further has extremely high adhesion to resin or glass. Therefore, the copper alloy wiring is hardly chipped or peeled off due to electrostatic breakdown.

Second merit: Improvement of reliability For example, when silver alloy wiring or copper alloy wiring is adopted as the structure of the conductive layer (in the case where the conductive oxide is not used), silver or copper is resin or glass-based. It may diffuse into the material and cause a decrease in reliability. In particular, when the manufacturing process has a treatment process at a temperature higher than 250 ° C., copper or copper alloy is easily oxidized.

On the other hand, when the conductive layer in which the metal layer or the alloy layer is sandwiched by the conductive oxide layers is adopted as in the present embodiment, the conductive oxide layer diffuses silver or copper into the glass substrate. Suppress and suppress copper oxidation. By suppressing the diffusion and oxidation of silver and copper, the reliability of the capacitive sensor substrate 100A can be improved.

Third advantage: improvement in mountability Silver, silver alloy, copper, or copper alloy is a relatively soft metal. Therefore, the wiring made of silver, a silver alloy, copper, or a copper alloy is easily scratched when electrically mounted at the end of the touch panel.

On the other hand, when the conductive layer in which the metal layer or the alloy layer is sandwiched by the conductive oxide layers is adopted as in the present embodiment, the conductive oxide is also one of the ceramic materials, and thus the conductive oxide By sandwiching the oxide layer with silver, silver alloy, copper, or copper alloy, it is possible to perform a hard and reliable mounting.

Fourth Merit: Ohmic Contact In the present embodiment, the first source electrode 22 is electrically connected to the scanning line 13 via the contact hole 29. The conductive oxide layer provides good electrical connection in the contact hole 29. As described above, copper oxide is easily formed on the surface of copper or copper alloy. Copper oxide increases the thickness over time and destabilizes electrical packaging. Similarly, oxides and sulfides are easily formed on the surface of silver. In a structure in which copper or a copper alloy is sandwiched by conductive oxide layers, a conductive oxide layer is formed on the surface of the conductive layer (conductive pattern), and ohmic contact is possible. Similarly, it is also effective to apply a conductive layer having a structure in which a metal layer or an alloy layer is sandwiched by conductive oxide layers to the structure of a thin film transistor. In other words, the conductive layer according to the embodiment of the present invention can be applied to source wirings, source electrodes, drain electrodes, gate electrodes, gate wirings, and touch sensing wirings of various TFTs (thin film transistors).

Fifth advantage: Improvement of transistor characteristics and improvement of reliability The fifth advantage will be described with reference to FIGS. 2 to 5.
FIG. 4 is an enlarged cross-sectional view illustrating a portion where the end surface of the first channel layer 16 and the conductive layer in the first thin film transistor 31 according to the first embodiment of the present invention overlap with each other.
As shown in FIG. 4, the first source electrode 22 and the first drain electrode 23 that form the second conductive layer 20 are stacked on the first channel layer 16. As described above, the second conductive layer 20 has a structure in which the metal layer 5 (alloy layer) is sandwiched between the conductive oxide layers (the first conductive oxide layer 41 and the second conductive oxide layer 42). Have.

The first source electrode 22 and the first drain electrode 23 having such a structure have high conductivity. The high conductivity obtained by the conductive oxide is expressed by the product of electron mobility and high electron concentration. The first conductive oxide layer 41, which is a part of the first source electrode 22 and the first drain electrode 23 stacked on the first channel layer 16, is composed of a conductive oxide having high conductivity. . In other words, since the first conductive oxide layer 41 is laminated on both ends of the first channel layer 16, the first conductive oxide layer 41 can compensate for the lack of electron mobility and carrier concentration. The characteristics of the thin film transistor can be improved.

As shown in FIG. 4, in the first channel layer 16, carriers (electrons) deficient in the oxide semiconductor from the overlapping portion 44 (interface) of the first conductive oxide layer 41 and the first channel layer 16 are included. In addition to being supplied, the high conductivity of the first conductive oxide layer 41 can be utilized. The conductivity can be expressed by the product of electron concentration and electron mobility. The characteristics of the first channel layer 16 can be made close to the characteristics of a single-layer intrinsic semiconductor with few carriers. The threshold value (Vth) of the first thin film transistor including the first channel layer 16 having characteristics close to that of an intrinsic semiconductor can be easily made positive (normally off), and reliability of the thin film transistor can be improved. By reducing the channel length L of the first channel layer 16 having characteristics close to those of an intrinsic semiconductor, the switching of the thin film transistor according to the first embodiment of the present invention can be operated more steeply. A conductive layer having a three-layer structure in which a metal layer such as copper is sandwiched between conductive oxide layers can be easily patterned by wet etching, unlike the laminated structure of copper / titanium, and has a channel length L. It is also possible to form a thin film transistor having a small size.

As a prior art relating to an oxide semiconductor, a technique of forming a channel layer with a multi-layer structure including oxide semiconductors having different electrical characteristics is known. However, the thickness of the channel layer is extremely thin, for example, about 50 nm. Forming a channel layer (thin film) having such a film thickness with a three-layer structure (multilayer structure) including an oxide semiconductor tends to cause variations in the manufacturing process. In other words, variations in the characteristics of thin film transistors are likely to occur. As proposed by the embodiments of the present invention, by adopting a single-layer channel layer for a thin film transistor, it is possible to provide a thin film transistor with less variation in characteristics. Further, in the embodiment of the present invention, it becomes possible to form a (single-layer) oxide semiconductor layer having characteristics close to what is called an intrinsic semiconductor in a portion corresponding to the channel length L. Accordingly, by utilizing the conductive oxide layer laminated on the end of the channel layer, a thin film transistor having excellent characteristics can be provided.

FIG. 5 is a cross-sectional view illustrating a reference example of a thin film transistor having a portion where an end surface of a conductive layer and a channel layer are in contact with each other. In FIG. 5,

reference numerals

141 and 142 denote conductive oxide layers, and reference numeral 105 denotes a metal layer.
In the structure in which the channel layer 116 is stacked on the drain electrode 123 (and the source electrode 122) shown in FIG. 5, the channel layer 116 contacts the exposed cross section of the metal layer 105 as shown in the Dd portion (and Ds portion). To do. There is a problem in that the oxide semiconductor included in the channel layer 116 is reduced by coming into contact with the metal layer 105 and the carrier concentration is easily changed. When the metal layer 105 contains copper or silver, there is a problem that copper or the like diffuses into the oxide semiconductor layer (channel layer 116) and the semiconductor characteristics are easily deteriorated. Therefore, in order to solve such a problem, the end of the channel layer 116 needs to be covered with the second conductive layer 20 (conductive oxide layer) as shown in FIG. The conductive oxide layer containing indium oxide suppresses the diffusion of metal from the metal layer in the temperature range of 340 ° C. or lower, and easily stabilizes the characteristics of the thin film transistor. As proposed in FIG. 4 and the like, it is preferable that the first channel layer 16 does not contact the metal layer 5.

Next, modifications 1 to 3 of the first embodiment, the second embodiment, and the third embodiment will be described. In the following description, the same members as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted or simplified.

(Modification 1 of the first embodiment)
FIG. 6 is a partially enlarged view showing the configuration of the capacitance sensor substrate 100B according to the first modification of the first embodiment of the present invention, and is a circuit diagram showing a unit cell including a capacitor pattern 12 and a thin film transistor (second thin film transistor 32). Is.
FIG. 7 is a partial cross-sectional view showing the configuration of the capacitive sensor substrate 100B according to the modified example of the first embodiment of the present invention, and is a cross-sectional view showing the unit cell along the line BB ′ shown in FIG.
FIG. 8 is a partial cross-sectional view showing the configuration of the capacitance sensor substrate 100B according to the modified example of the first embodiment of the present invention, and is a cross-sectional view showing the second thin film transistor 32 in FIG. Reference numeral TD in FIG. 7 indicates the direction in which a pointer such as a finger approaches or contacts the touch input surface 28T.

The second thin film transistor 32 shown in FIG. 8 is a bottom-gate transistor. That is, in the cross-sectional view, the first gate electrode 11 is provided below the first source electrode 22, the first drain electrode 23, and the first channel layer 16. As described above, both ends of the first channel layer 16 are covered with the conductive oxide layer.

As shown in FIG. 6, the unit cell of the capacitive sensor substrate 100B has a structure similar to that of the capacitive sensor substrate 100A shown in FIG. On the other hand, as shown in FIG. 7, in the capacitive sensor substrate 100B, the second conductive pattern 20P (first source electrode 22, first drain electrode 23, and output line 21) is connected to the first conductive pattern 10P (first It is arranged on the gate electrode 11, the capacitor pattern 12, and the scanning line 13). That is, the configuration of the capacitance sensor substrate 100B shown in FIG. 7 is the reverse of the configuration of the capacitance sensor substrate 100A shown in FIG.

Specifically, the first insulating layer 17 is formed on the substrate 202 that constitutes the capacitance sensor substrate 100B, and the capacitor pattern 12 is formed on the first insulating layer 17. Further, the first gate electrode 11, the capacitor pattern 12, and the scan line 13 that form the first conductive layer 10 are formed on the first insulating layer 17. A gate insulating layer 18 is formed so as to cover the first gate electrode 11, the capacitor pattern 12, and the scanning line 13.

The dielectric layer 3 is formed above the capacitor pattern 12 with the gate insulating layer 18 interposed therebetween. That is, the dielectric layer 3 is formed above the second surface 2. The dielectric layer 3 overlaps with the capacitor pattern 12 in a plan view. In the thickness direction of the substrate 202, the dielectric layer 3 is located closer to the touch input surface 28T (touch sensing input surface) than the capacitor pattern 12.
In FIG. 2, the dielectric layer 3 is formed on the second surface 2 on the entire surface of the unit cell 19, whereas in the example shown in FIG. 7, the planar shape of the dielectric layer 3 and the capacitor pattern are formed. 12 corresponds to the planar shape. In other words, in the unit cell 19, the dielectric layer 3 is locally formed. The planar shape of the dielectric layer 3 does not necessarily have to match the planar shape of the capacitor pattern 12, but the dielectric layer 3 is disposed between the touch input surface 28T and the capacitor pattern 12. There is a need. Therefore, the dielectric layer 3 needs to be formed so as to cover the capacitor pattern 12 in a plan view.

The first channel layer 16 is formed above the first gate electrode 11 via the gate insulating layer 18. Further, on the first channel layer 16, a first source electrode 22 and a first drain electrode 23 forming the second conductive layer 20 are formed so as to cover both ends of the first channel layer 16. At the same time when the first source electrode 22 and the first drain electrode 23 are formed, the output line 21 (second conductive layer 20) is formed.

(Modification 2 of the first embodiment)
FIG. 9 is a circuit diagram showing a unit cell that constitutes a capacitive sensor substrate 100C according to Modification 2 of the first embodiment. As shown in FIG. 9, the capacitive sensor substrate 100C according to the second modification includes a unit cell 119. The unit cell 119 includes a third thin film transistor 33 (reset transistor) in addition to the configuration of the unit cell 19 including the second thin film transistor 32 shown in FIG.

The third thin film transistor 33 is second via the second gate electrode 127 (first conductive layer 10), the second source electrode 25 (second conductive layer 20), and the contact hole 129 that are electrically connected to the first gate electrode 11. This is a bottom-gate transistor including the second drain electrode 26 (second conductive layer 20) electrically connected (short-circuited) to the gate electrode 127, the second channel layer 24, and the gate insulating layer 118.

A part of the first conductive pattern 10P constitutes the second gate electrode 127. A part of the second conductive pattern 20P constitutes the second source electrode 25 and the second drain electrode 26. A part of the oxide semiconductor layer forms the second channel layer 24. A part of the gate insulating layer 18 constitutes the gate insulating layer 118 of the third thin film transistor 33. The second channel layer 24 is formed at the same time when the above-mentioned first channel layer 16 is formed. Similarly, the gate insulating layer 118 of the third thin film transistor 33 is formed at the same time when the gate insulating layer 18 is formed.

In the second modification, the scanning line 13 not only supplies the scanning signal to the first source electrode 22 of the second thin film transistor 32, but also supplies the reset signal (for example, the ground potential) to the second source electrode 25 of the third thin film transistor 33. ) Supply.

(Modification 3 of the first embodiment)
FIG. 10 is a circuit diagram showing a unit cell that constitutes a capacitive sensor substrate 100D according to Modification 3 of the first embodiment. As shown in FIG. 10, the capacitive sensor substrate 100D according to the third modification includes unit cells 219. The unit cell 219 includes a third thin film transistor 33 shown in FIG. 9, a source extended line 128 (second conductive layer 20) obtained by extending the second source electrode 25 of the third thin film transistor 33, and a reset line 15 (first conductive layer). 10) and are provided. The source extension line 128 is not connected to the scanning line 13 but is connected to the reset line 15 via the contact hole 229. The reset line 15 supplies a reset signal to the third thin film transistor 33 via the source extension line 128 and the second source electrode 25.

In the circuit diagram shown in FIG. 10, the unit cell 219 can receive the reset signal from the reset line 15 independently of the scanning signal from the scanning line 13. In the unit cell 219, it is not necessary to supply both the scanning signal and the reset signal to the scanning line 13 as shown in FIG. The reset line 15 may supply only the reset signal to the third thin film transistor 33, and the scanning line 13 may supply only the scanning signal to the second thin film transistor 32.

Note that FIG. 1 shows a circuit diagram in which one unit cell includes one thin film transistor, and FIGS. 9 and 10 show circuit diagrams in which one unit cell includes two thin film transistors. The number of thin film transistors in one unit cell can be increased as necessary.

In the modified examples 1 to 3 of the first embodiment having the above-described configuration, the same effect as that of the capacitive sensor substrate 100A according to the above-described first embodiment can be obtained.

(Second embodiment)
(Electronic device / Liquid crystal display)
FIG. 11 is a sectional view partially showing a liquid crystal display device 200 (display device) which is an electronic device according to the second embodiment of the invention.
FIG. 12 is a plan view showing a capacitance sensor substrate 201 that constitutes the liquid crystal display device 200. It should be noted that FIG. 12 shows the capacitance as viewed in the direction opposite to the touch direction TD (the direction in which a pointer such as a finger approaches or contacts the first surface 1), that is, the direction from the second surface 2 to the first surface 1. 3 is a plan view showing a sensor substrate 201. FIG.
FIG. 13 is a typical circuit diagram illustrating the circuit configuration of the array substrate of the liquid crystal display device 200, and is a circuit diagram including a thin film transistor that drives the liquid crystal layer 60.
FIG. 14 is a plan view showing the unit cell 19 of the capacitance sensor substrate 201 that constitutes the liquid crystal display device 200. The DD ′ section shown in FIG. 14 corresponds to the DD ′ section shown in FIG. Note that FIG. 14 is a plan view representatively showing two unit cells including the red pixel R and the green pixel G indicated by the chain double-dashed line in FIG. 11.
FIG. 15 is a diagram showing a thin film transistor included in the capacitance sensor substrate 201 that constitutes the liquid crystal display device 200, and is a cross-sectional view taken along the line CC ′ of FIG. 14.

The liquid crystal display device 200 includes a capacitance sensor substrate 201, an array substrate 203, and a liquid crystal layer 60 (display function layer) sandwiched between the capacitance sensor substrate 201 and the array substrate 203.
The array substrate 203 has a substrate surface 203T on which the thin film transistor array is arranged. That is, in the liquid crystal display device 200, the capacitance sensor substrate 201 and the array substrate 203 are separated from each other via the liquid crystal layer 60 so that the second surface 2 of the capacitance sensor substrate 201 and the substrate surface 203T of the array substrate 203 face each other. Pasted together.

In FIG. 11, illustration of an optical film including a polarizing plate, an alignment film, a backlight unit, and the like, which compose the liquid crystal display device 200, is omitted. Further, the array substrate 203 includes a plurality of active elements (thin film transistor array) such as thin film transistors that drive the liquid crystal layer 60, but since such active elements are well known, they are omitted in FIG. 11.

The capacitance sensor substrate 201 includes the capacitance sensor substrate 100A according to the first embodiment described above and the color filter CF. The color filter CF includes a red pixel R, a green pixel G, a blue pixel B, and a black matrix 8 (light absorption layer).

As shown in FIG. 12, a capacitor pattern 12, a scanning line 13, a power supply line 14, an output line 21 and the like are formed on the dielectric layer 103. The dielectric layer 103 has basically the same configuration as the dielectric layer 3 according to the above-described first embodiment, but the dielectric layer 103 of the present embodiment is different in that the dielectric layer 103 includes the opening Op. , And is different from the dielectric layer 3 of the first embodiment.

The opening Op of the dielectric layer 103 is a portion where the dielectric layer 103 is removed, and corresponds to a pixel that transmits light (corresponding to a red pixel R, a green pixel G, and a blue pixel B). The plurality of scanning lines 13 are connected to the scanning line driver 205 (scanning signal circuit). The plurality of output lines 21 are connected to the output line driver 204 (output signal circuit). Reference symbols RGB in FIGS. 11 and 12 indicate the arrangement of the color filters CF of the red pixel R, the green pixel G, and the blue pixel B, respectively.

As shown in FIG. 13, the thin film transistors (reference numeral 71 in FIG. 13) formed on the array substrate 203 are arranged in a matrix and drive the liquid crystal layer 60.
A plurality of gate lines 64 extending from the scanning signal circuit 72 and a plurality of source lines 65 extending from the video signal circuit 73 are formed on the array substrate 203. The thin film transistor 71 is driven by the gate signal output from the gate line 64 and the video signal output from the source line 65. In FIG. 13, the liquid crystal 63 (liquid crystal layer 60) is described as a capacitive element.

The liquid crystal display device 200 has a configuration in which the second surface 2 of the capacitive sensor substrate 201 in which the plurality of unit cells 19 are formed and the array substrate 203 are bonded together via the liquid crystal layer 60.

As shown in the sectional view of FIG. 11, the capacitive sensor substrate 201 has a dielectric layer 103 provided on the second surface 2 of the substrate 202. Further, on the dielectric layer 103, the capacitor pattern 12 forming the first conductive pattern 10P, the scanning line 13, and the power supply line 14 are laminated. As shown in the touch direction TD, when a pointer such as a finger approaches or contacts the first surface 1, touch sensing is performed by the capacitive sensor substrate 201. The dielectric layer 103 is located closer to the touch sensing input surface (first surface 1) than the capacitor pattern 12.

The fourth thin film transistor 34 shown in FIG. 15 has the same configuration as the first thin film transistor 31 according to the first embodiment described above. However, the dielectric layer 103 according to the second embodiment has a role of a black matrix of the liquid crystal display device 200. The dielectric layer 103 of the second embodiment has an opening Op that is indispensable for the liquid crystal display device 200. The opening Op has a role of transmitting light of a backlight not shown in FIG. 11 and displaying an image. The opening Op is an opening corresponding to each pixel of RGB, as illustrated in FIGS. 11, 12, and 14, and the like.

FIG. 14 shows two unit cells as a typical example. Each unit cell includes two transistors, a fourth thin film transistor 34 and a fifth thin film transistor 35 (selection transistor). The change in capacitance of the capacitor pattern 12 is output to the output line 21 as a signal from the fourth thin film transistor 34 in response to the selection signal from the scanning line 13. The fourth thin film transistor 34 has the function of amplifying the signal from the capacitor pattern 12.

(Third Embodiment)
(Electronic device / IC card)
FIG. 16 is a plan view showing an IC card 300 which is an electronic device according to the third embodiment.

The IC card 300 includes a capacitance sensor substrate 301 having the same configuration as the capacitance sensor substrate 100A according to the first embodiment described above, an antenna 310, and an IC chip. The capacitance sensor substrate 301 functions as a fingerprint sensor that performs fingerprint authentication in the IC card 300.
The capacitance sensor substrate 301, the antenna 310, the memory 313, the IC chip, and the like are previously attached to a resin film called an inlet. The IC chip may be an IC chip in which the control circuit 312, the antenna power supply unit 314, and the sensor control circuit 316 are integrated. A secondary battery 317 (or a large-capacity capacitor) or a charge control unit 311 may be added to the IC card 300 as needed.

The inlet is attached to the capacitance sensor substrate 301, the antenna 310, the IC chip, etc. via a spacer. As the spacer, a hard polyvinyl chloride sheet base material, a polyvinyl chloride sheet also called an overlay, and PET (polyethylene terephthalate) are used.

An opening is formed in the spacer in accordance with the shapes of the capacitance sensor substrate 301 and the IC chip, and the IC card 300 having a flat surface can be obtained by a bonding process using a heat-sensitive adhesive. The IC card 300 has a structure in which a plurality of layers of sheets are stacked. As the above-mentioned sheet base material, inlet base material, and spacer base material, in addition to the above, vinyl chloride-vinyl acetate copolymer, polyamide, polyimide, polyamideimide, cellulose triacetate and other resin sheets can be used. Further, resin-impregnated paper on which a face photograph or the like is printed may be laminated on the IC card 300 as a part of the plurality of layers.

The capacitance sensor substrate 301 has, for example, a structure in which the unit cells shown in FIG. 10 are arranged in a matrix at a pitch of 50 μm on a high-strength glass substrate having an outer diameter of 15 mm □ and a thickness of 200 μm. An output line driver 303 and a scanning line driver 304 each including a thin film transistor (switching element) using an oxide semiconductor as a channel layer are wired around the capacitance sensor substrate 301. As shown in FIG. 7, the fingerprint-authenticated finger contacts the touch input surface 28T near the dielectric layer 3 in the touch direction TD.

The antenna 310 is formed by patterning a copper foil attached to a resin sheet into a loop antenna shape by wet etching.

The IC card 300 includes a tuning circuit, a rectification circuit, and the like that use the antenna 310 to communicate with and receive power from an IC card reader / writer at a frequency of 13.56 MHz, for example. The frequency involved in this communication may be higher than 13.56 MHz. A secondary battery may be built in the IC card 300.

When the capacitive sensor substrate according to the above-described embodiment is used for fingerprint detection or detection of a fine pointer such as a pen, the resolution (pitch) of the unit cell can be set within the range of 10 μm to 100 μm, for example. Since the pitch of the ridgeline of the fingerprint is approximately 300 μm, it may be set to the lower limit (100 μm or less) of the resolution of the unit cell for resolving this. Since the sharp pen tip has a size of several tens of μm, this can be set to the upper limit of resolution of 10 μm. When the capacitive sensor substrate according to the embodiment of the present invention is used for normal touch recognition of a finger, a coarse resolution of about 1 mm is sufficient. Coarse sensing is possible by performing touch sensing so as to thin out a plurality of cell rows (rows in which a plurality of unit cells are arranged in one direction) formed on the capacitive sensor substrate according to the embodiment of the present invention. .

While the preferred embodiments of the invention have been described and described above, it should be understood that these are exemplary of the invention and should not be considered limiting. Additions, omissions, substitutions, and other changes can be made without departing from the scope of the invention. Therefore, the present invention should not be considered limited by the foregoing description, but is defined by the claims.

Note that the circuit configuration of the capacitive sensor substrate according to the above-described embodiment is a typical circuit configuration, and for example, output lines (also referred to as signal lines), scanning lines, reset lines, power supply lines, etc. described in the circuit diagram. The number and combination of can be changed according to the purpose. Further, one wiring may have two or more functions (combined use).
One sensing element (unit cell) includes at least one capacitor pattern, and forms a plurality of capacitor patterns, a plurality of output lines, a plurality of scanning lines orthogonal to the output lines, and a matrix of sensing elements. The shape of the capacitor pattern and the number of thin film transistors provided in one sensing element can be adjusted according to the purpose.

The electronic device to which the capacitive sensor substrate according to the above-described embodiment can be applied includes a display device, a mobile phone, a portable game machine, a personal digital assistant, a personal computer, an electronic book, an electronic watch, a video camera, a digital still camera, and a head. Mounted display, navigation system, sound reproduction device (car audio, digital audio player, etc.), copier, facsimile, printer, printer complex machine, vending machine, automatic teller machine (ATM), personal authentication device, optical communication device , Medical data cards, IC cards and the like. In particular, the capacitive sensor substrate according to the above-described embodiment can be incorporated into the electronic devices listed above, and functions as a fingerprint authentication device.

It is easy to use the capacitive sensor substrate incorporated as a fingerprint authentication device as both a power switch and an enable switch after personal authentication. The enable switch is a switch for ensuring the security of the electronic device after fingerprint authentication, and is a switch for ensuring security.
The above embodiments can be freely combined and used. An antenna is mounted on these electronic devices to enable non-contact communication and non-contact power supply / reception. The conductive layer according to the first embodiment can be applied to a conductor forming an antenna and wiring in an electronic device.

1st surface (touch sensing input surface)
2 ...

Second surface

3, 103 ... Dielectric layer 5 ... Metal layer 8 ... Black matrix 10 ... First conductive layer 10P ... First conductive pattern 11 ... First Gate electrode 12 ... Capacitor pattern 13 ... Scan line 14 ... Power supply line 15 ... Reset line 16 ... First channel layer 17 ... First insulating layer 18, 118 ...

Gate insulation Layer

19, 119, 219 ... Unit cell 20 ... Second conductive layer 20P ... Second conductive pattern 21 ... Output line 22 ... First source electrode 23 ... First drain electrode 24・・・ Second channel layer 25 ・・・ Second source electrode 26 ・・・ Second drain electrode 27 ・・・ Second insulating layer 28 ・・・ Third insulating layer 28T ・・・ Touch input surface (touch sensing input) surface)
29, 129, 229 ... Contact hole 31 ... First thin film transistor (thin film transistor)
32 ... Second thin film transistor (thin film transistor)
33 ... Third thin film transistor (thin film transistor)
34 ... Fourth thin film transistor (thin film transistor)
35 ... Fifth thin film transistor (thin film transistor)
41 ... First conductive oxide layer 42 ... Second conductive oxide layer 44 ... Superposed portion 60 ... Liquid crystal layer 63 ... Liquid crystal 64 ... Gate line 65 ... Source Line 71 ... Thin film transistor 72 ... Scan signal circuit 73 ...

Video signal circuit

100A, 100B, 100C, 100D, 201, 301 ...

Capacitance sensor substrate

102, 202 ... Substrate 116 ... Channel layer 122 ... Source electrode 123 ... Drain electrode 127 ... Second gate electrode 128 ... Source wire extension 200 ... Liquid crystal display device (electronic device)
203 ... Array substrate 203T ...

Substrate surface

204, 303 ... Output line driver 205, 304 ... Scan line driver 300 ... IC card (electronic device)
310 ... Antenna 311 ... Charge control unit 312 ... Control circuit 313 ... Memory 314 ... Antenna power supply unit 316 ... Sensor control circuit 317 ... Secondary battery B ... Blue pixel CF ... Color filter G ... Green pixel R ... Red pixel TD ... Touch direction

Claims

A substrate having a first surface and a second surface,
A dielectric layer containing carbon and provided above the second surface;
A thin film transistor having a gate electrode, a source electrode, a drain electrode, a channel layer formed of an oxide semiconductor layer, and a gate insulating layer, the thin film transistor provided above the second surface;
A first conductive layer that has a metal layer and is provided above the second surface and that forms at least the capacitor pattern and the gate electrode;
A second conductive layer having a metal layer and provided above the second surface;
Equipped with
The gate electrode is electrically associated with the capacitor pattern,
In a plan view, the dielectric layer overlaps with the capacitor pattern,
In the thickness direction of the substrate, the dielectric layer is closer to the touch sensing input surface than the capacitor pattern is,
Capacitance sensor board.
The dielectric layer is
Carbon,
At least one or more fine particles selected from the group consisting of metal oxides, metal oxynitrides, and metal nitrides;
Is a resin dispersion containing
The capacitive sensor substrate according to claim 1.
The electric resistivity of the dielectric layer is 1 × 10 8 Ωcm or more and less than 1 × 10 13 Ωcm.
The capacitive sensor substrate according to claim 1.
The dielectric loss of the dielectric layer is 0.01 or more and less than 0.2,
The capacitive sensor substrate according to claim 1.
The film thickness of the dielectric layer is in the range of 0.2 μm or more and 10 μm or less,
The capacitive sensor substrate according to claim 1.
Each of the first conductive layer and the second conductive layer has a three-layer structure in which the metal layer is sandwiched by conductive oxide layers,
The capacitive sensor substrate according to claim 1.
In a cross-sectional view along the thickness direction of the thin film transistor, the thin film transistor has an overlapping portion in which an end portion of the channel layer is covered with the second conductive layer,
In the overlapping portion, an interface is formed in which the conductive oxide layer and the channel layer are in contact with each other,
The capacitive sensor substrate according to claim 6.
The conductive oxide layer contains indium oxide,
The capacitive sensor substrate according to claim 6.
The oxide semiconductor layer is
Indium oxide,
At least one of antimony oxide and bismuth oxide,
including,
The capacitive sensor substrate according to claim 1.
The oxide semiconductor layer is
Containing at least one of cerium oxide and tin oxide,
Further including,
The capacitive sensor substrate according to claim 9.
A capacitive sensor substrate according to claim 1;
An antenna,
An electronic device comprising.
A capacitive sensor substrate according to claim 1;
An array substrate having a substrate surface on which a thin film transistor array is arranged;
Display function layer,
Equipped with
The display functional layer is sandwiched between the capacitance sensor substrate and the array substrate such that the second surface of the capacitance sensor substrate and the substrate surface of the array substrate face each other.
Electronic device.