WO2020073882A1

WO2020073882A1 - Video decoder and corresponding methods

Info

Publication number: WO2020073882A1
Application number: PCT/CN2019/109905
Authority: WO
Inventors: Yin ZHAO; Jianle Chen
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2018-10-08
Filing date: 2019-10-08
Publication date: 2020-04-16

Abstract

Systems and method for decoding video data are provided. A vertical transform and a horizontal transform for decoding a coding block may be determined based on an index and/or one or more flags. The coding block may be decoded based on the determined vertical transform and the determined horizontal transform.

Description

VIDEO DECODER AND CORRESPONDING METHODS

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to United States Provisional Application No. 62/742,906, filed on October 8, 2018. The aforementioned application is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

Embodiments of the disclosure generally relates to the field of video decoding and more particularly to systems and methods for decoding video data.

BACKGROUND

Video coding (video encoding and decoding) is used in a wide range of digital video applications, for example broadcast digital TV, video transmission over internet and mobile networks, real-time conversational applications such as video chat, video conferencing, DVD and Blu-ray discs, video content acquisition and editing systems, and camcorders of security applications.

Since the development of the block-based hybrid video coding approach in the H. 261 standard in 1990, new video coding techniques and tools were developed and formed the basis for new video coding standards. Further video coding standards comprise MPEG-1 video, MPEG-2 video, ITU-T H. 262/MPEG-2, ITU-T H. 263, ITU-T H. 264/MPEG-4, Part 10, Advanced Video Coding (AVC) , ITU-T H. 265/High Efficiency Video Coding (HEVC) , ITU-T H. 266/Versatile video coding (VVC) and extensions, e.g. scalability and/or three-dimensional (3D) extensions, of these standards. As the video creation and use have become more and more ubiquitous, video traffic is the biggest load on communication networks and data storage, accordingly, one of the goals of most of the video coding standards was to achieve a bitrate reduction compared to its predecessor without sacrificing picture quality. Even the latest High Efficiency video coding (HEVC) can compress video about twice as much as AVC without sacrificing quality, it is hunger for new technical to further compress video as compared with HEVC.

SUMMARY

Various embodiments and aspects of the disclosures will be described with reference to details discussed below, and the accompanying drawings will illustrate the various embodiments. The following description and drawings are illustrative of the disclosure and are not to be construed as limiting the disclosure. Numerous specific details are described to provide a thorough understanding of various embodiments of the present disclosure. However, in certain instances, well-known or conventional details are not described in order to provide a concise discussion of embodiments of the present disclosures.

Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in conjunction with the embodiment can be included in at least one embodiment of the disclosure. The appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment.

In one embodiment, a method of decoding video data is provided. The method includes determining a set of transforms for decoding an intra luma coding block based on a syntax structure associated with the intra luma coding block. The set of transforms include a horizontal transform and a vertical transform. The method also includes obtaining an inverse transform block for the intra luma coding block based on the horizontal transform and the vertical transform. The method further includes obtaining a reconstructed block based on the inverse transform block for the intra luma coding block. The method further includes obtaining a decoded picture corresponding to the intra luma coding block based on the reconstructed block.

In one embodiment, obtaining the inverse transform block includes applying an inverse transform on de-quantized coefficients of the intra luma coding block based on the determined horizontal transform and the determined vertical, so as to obtain an inverse transform block of the intra luma coding block.

In one embodiment, determining the set of transforms includes deriving an index for indicating the horizontal transform and the vertical transform based on the syntax structure associated with the intra luma coding block and determining the horizontal transform and the vertical transform based on the derived index.

In one embodiment, determining the set of transforms includes determining a horizontal transform and a vertical transform based on a first flag and a second flag. The first flag and the second flag are obtained based on the syntax structure. The first flag indicates whether multiple transform selection is used. The second flag indicates whether adaptive transform selection is used.

In one embodiment, the first flag indicates that multiple transform selection is not used, the second flag indicates that adaptive transform selection is not used, and the horizontal transform and the vertical transform include a discrete cosine transform II (DCT-II transform) .

In one embodiment, the first flag indicates that multiple transform selection is not used and the second flag indicates that adaptive transform selection is used. The horizontal transform and the vertical transform include a discrete cosine transform II (DCT-II transform) when a width of the intra luma coding block is equal a height of the intra luma coding block. The horizontal transform includes a discrete sine transform VII (DST-VII transform) and the vertical transform includes the DCT-II transform when the width of the intra luma coding block is less than the height of the intra luma coding block. The horizontal transform includes the DCT-II transform and the vertical transform includes the DST-VII transform when the width of the intra luma coding block is greater than the height of the intra luma coding block.

In one embodiment, the first flag indicates that multiple transform selection is not used and the second flag indicates that adaptive transform selection is used. The horizontal transform and the vertical transform include a discrete cosine transform II (DCT-II transform) when a width of the intra luma coding block is equal a height of the intra luma coding block. the horizontal transform includes a discrete sine transform VII (DST-VII transform) and the vertical transform includes the DCT-II transform when the width of the intra luma coding block is less than the height of the intra luma coding block and when the width of the intra luma coding block is less than a threshold. The horizontal transform and the vertical transform include a discrete cosine transform II (DCT-II transform) when the width of the intra luma coding block is less than the height of the intra luma coding block and when the width of the intra luma coding block greater than or equal to the threshold. The horizontal transform includes the DCT-II transform and the vertical transform includes the DST-VII transform when the width of the intra luma coding block is greater than the height of the intra luma coding block and when the width of the intra luma coding block is less than the threshold. The horizontal transform and the vertical transform include a discrete cosine transform II (DCT-II transform) when the width of the intra luma coding block is greater than the height of the intra luma coding block and when the width of the intra luma coding block is greater than or equal to the threshold.

In one embodiment, the first flag indicates that multiple transform selection is used and the second flag indicates that adaptive transform selection is not used. The horizontal transform is determined further based on a third flag in a received bitstream and the vertical transform is determined further based on a fourth flag in the received bitstream.

In one embodiment, the horizontal transform includes a discrete cosine transform VIII (DCT-VIII transform) when the third flag is 0 and the horizontal transform includes a discrete sine transform VII (DST-VII transform) when the third flag is 1. The vertical transform includes a discrete cosine transform VIII (DCT-VIII transform) when the fourth flag is 0 and the vertical transform includes the DST-VII transform when the fourth flag is 1.

In one embodiment, the first flag indicates that multiple transform selection is used and the second flag indicates that adaptive transform selection is not used. The horizontal transform and the vertical transform are determined further based on an index in a received bitstream.

In one embodiment, the horizontal transform and the vertical transform include a discrete cosine transform VIII (DCT-VIII transform) when the index is 0. The horizontal transform includes the DCT-VIII transform and the vertical transform includes a discrete sine transform VII (DST-VII transform) when the index is 1. The horizontal transform includes the DST-VII transform and the vertical transform includes the DCT-VIII transform when the index is 2. The horizontal transform and the vertical transform include the DST-VII transform when the index is 3.

In one embodiment, a system for decoding video data is provided. The system includes a memory and a processor coupled to the memory. The processor is to determine a set of transforms for decoding an intra luma coding block based on a syntax structure associated with the intra luma coding block. The set of transforms include a horizontal transform and a vertical transform. The processor is further to obtain an inverse transform block for the intra luma coding block based on the horizontal transform and the vertical transform. The processor is further to obtain a reconstructed block based on the inverse transform block for the intra luma coding block. The processor is further to obtain decoded picture corresponding to the intra luma coding block based on the reconstructed block.

In one embodiment, to determine the set of transforms the processor is further to apply an inverse transform on de-quantized coefficients of the intra luma coding block based on the determined horizontal transform and the determined vertical, so as to obtain an inverse transform block of the intra luma coding block.

In one embodiment, to determine the set of transforms the processor is further to derive an index for indicating the horizontal transform and the vertical transform based on the syntax structure associated with the intra luma coding block and determining the horizontal transform and the vertical transform based on the derived index.

In one embodiment, to determine the set of transforms the processor is further to determine a horizontal transform and a vertical transform based on a first flag and a second flag. The first flag and the second flag are obtained based on the syntax structure. The first flag indicates whether multiple transform selection is used. The second flag indicates whether adaptive transform selection is used.

In one embodiment, non-transitory machine-readable medium having instructions stored therein is provided. When executed by a processor, the instructions cause the processor to perform operations. The operations include determining a set of transforms for decoding an intra luma coding block based on a syntax structure associated with the intra luma coding block. The set of transforms include a horizontal transform and a vertical transform. The operations also include obtaining an inverse transform block for the intra luma coding block based on the horizontal transform and the vertical transform. The operations further include obtaining a reconstructed block based on the inverse transform block for the intra luma coding block. The operations further include obtaining a decoded picture corresponding to the intra luma coding block based on the reconstructed block.

A aspect of the present disclosure provides a method of decoding implemented by a decoding device, comprising: deriving, based on a syntax structure, an index for indicating a horizontal transform and a vertical transform of an intra luma coding block; determining, based on the derived index, the horizontal transform and the vertical transform of the intra luma coding block; applying, based on the determined horizontal transform and the determined vertical transform, an inverse transform on dequantized coefficients of the intra luma coding block, so as to obtain an inverse transform block of the intra luma coding block; obtaining, based on the inverse transform block, a reconstructed block of the intra luma coding block; and obtaining, based on the reconstructed block, a decoded picture corresponding to the intra luma coding block.

In one embodiment, the index is derived as following: MtsIntraMode = sps_mts_intra_enabled_flag? 2 : (sps_mts_intra_shape_adaptive_flag? 0 : 1) ; wherein MtsIntraMode represents the index.

In one embodiment, the horizontal transform and the vertical transform are determined as following: when the index MtsIntraMode is equal to 0, the horizontal transform and vertical transform of the intra luma coding block are both DCT-2.

In one embodiment, the horizontal transform and the vertical transform are determined as following: when the index MtsIntraMode is equal to 1, the horizontal transform and vertical transform of the intra luma coding block are determined as following: when the block width is equal to block height, the horizontal transform and vertical transform of the intra luma coding block are both DCT-2; or when the block width is smaller than the block height, the horizontal transform and vertical transform of the intra luma coding block are DST-7 and DCT-2, respectively; or when the block width is greater than the block height, the horizontal transform and vertical transform of the intra luma coding block are DCT-2 and DST-7, respectively.

In one embodiment, the horizontal transform and the vertical transform are determined as following: when the index MtsIntraMode is equal to 1, the horizontal transform and vertical transform of the intra luma coding block are determined as following: when the block width is equal to block height, the horizontal transform and vertical transform of the intra luma coding block are both DCT-2; or when the block width is smaller than the block height and the block width is smaller than a threshold T1, the horizontal transform and vertical transform of the intra luma coding block are DST-7 and DCT-2, respectively; or when the block width is smaller than the block height and the block width is equal to or greater than a threshold T1, the horizontal transform and vertical transform of the intra luma coding block are both DCT-2; or when the block width is greater than the block height and the block height is smaller than the threshold T1, the horizontal transform and vertical transform of the intra luma coding block are DCT-2 and DST-7, respectively; or when the block width is greater than the block height and the block height is equal to or greater than the threshold T1, the horizontal transform and vertical transform of the intra luma coding block are both DCT-2, respectively.

In one embodiment, T1= 32 or 16.

In one embodiment, the horizontal transform and the vertical transform are determined as following: when the index MtsIntraMode is equal to 2, the horizontal transform and vertical transform of the intra luma coding block are determined as following: parsing a received bitstream to obtain a first flag for indicating the horizontal transform and a second flag for indicating the vertical transform; and obtaining the horizontal transform based on the first flag and obtaining the vertical transform based on the second flag.

In one embodiment, when the first flag is 0, the horizontal transform is DCT-8; or when the first flag is 1, the horizontal transform is DST-7; or when the second flag is 0, the horizontal transform is DCT-8; or when the second flag is 1, the horizontal transform is DST-7.

In one embodiment, the horizontal transform and the vertical transform are determined as following: when the index MtsIntraMode is equal to 2, the horizontal transform and vertical transform of the intra luma coding block are determined as following: parsing a received bitstream to obtain an index for indicating the horizontal transform and the vertical transform; and obtaining the horizontal transform and the vertical transform based on the index for indicating the horizontal transform and the vertical transform.

In one embodiment, when the index for indicating the horizontal transform and the vertical transform is 0, the horizontal transform and the vertical transform are both DCT-8; or when the index for indicating the horizontal transform and the vertical transform is 1, the horizontal transform is DCT-8 and the vertical transform is DST-7; or when the index for indicating the horizontal transform and the vertical transform is 2, the horizontal transform is DST-7 and the vertical transform is DCT-8; or when the index for indicating the horizontal transform and the vertical transform is 3, the horizontal transform and the vertical transform are both DST-7.

In one embodiment, the syntax structure is SPS, PPS or slice header.

Details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description, drawings, and claims. It should be understood that beneficial effects obtained by various aspects and corresponding implementable design manners are similar, and are not repeated.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following embodiments of the disclosure are described in more detail with reference to the attached figures and drawings.

FIG. 1A is a block diagram showing an example of a video coding system configured to implement embodiments of the disclosure.

FIG. 1B is a block diagram showing another example of a video coding system configured to implement embodiments of the disclosure.

FIG. 2 is a block diagram showing an example of a video encoder configured to implement embodiments of the disclosure.

FIG. 3 is a block diagram showing an example structure of a video decoder configured to implement embodiments of the disclosure.

FIG. 4 is a block diagram illustrating an example of an encoding apparatus or a decoding apparatus.

FIG. 5 is a block diagram illustrating another example of an encoding apparatus or a decoding apparatus.

FIG. 6 is a block diagram illustrating an example system for encoding and/or decoding video data, according to one embodiment.

FIG. 7 is a flowchart illustrating an example process for decoding a coding block, according to one embodiment.

FIG. 8 is a flowchart illustrating an example process for decoding a coding block, according to one embodiment.

FIG. 9 is a flowchart illustrating an example process for decoding a coding block, according to one embodiment.

In the following identical reference signs refer to identical or at least functionally equivalent features if there is not specific note regarding to the difference of those identical reference signs.

DETAILED DESCRIPTION

In the following description, reference is made to the accompanying figures, which form part of the disclosure, and which show, by way of illustration, specific aspects of embodiments of the disclosure or specific aspects in which embodiments of the present disclosure may be used. It is understood that embodiments of the disclosure may be used in other aspects and comprise structural or logical changes not depicted in the figures. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

For instance, it is understood that a disclosure in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if one or a plurality of specific method operations are described, a corresponding device may include one or a plurality of units, e.g. functional units, to perform the described one or plurality of method operations (e.g. one unit performing the one or plurality of operations, or a plurality of units each performing one or more of the plurality of operations) , even if such one or more units are not explicitly described or illustrated in the figures. On the other hand, for example, if a specific apparatus is described based on one or a plurality of units, e.g. functional units, a corresponding method may include one operation to perform the functionality of the one or plurality of units (e.g. one operation performing the functionality of the one or plurality of units, or a plurality of operations each performing the functionality of one or more of the plurality of units) , even if such one or plurality of operations are not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary embodiments and/or aspects described herein may be combined with each other, unless specifically noted otherwise.

Video coding typically refers to the processing of a sequence of pictures, which form the video or video sequence. Instead of the term “picture” the term “frame” or “image” may be used as synonyms in the field of video coding. Video coding used in the present disclosure indicates either video encoding or video decoding. Video encoding is performed at the source side, typically comprising processing (e.g. by compression) the original video pictures to reduce the amount of data required for representing the video pictures (for more efficient storage and/or transmission) . Video decoding is performed at the destination side and typically comprises the inverse processing compared to the encoder to reconstruct the video pictures. Embodiments referring to “coding” of video pictures (or pictures in general, as will be explained later) shall be understood to relate to either “encoding” or “decoding” for video sequence. The combination of the encoding part and the decoding part is also referred to as CODEC (e.g., Coding and Decoding) .

In case of lossless video coding, the original video pictures can be reconstructed, e.g., the reconstructed video pictures have the same quality as the original video pictures (assuming no transmission loss or other data loss during storage or transmission) . In case of lossy video coding, further compression, e.g. by quantization, is performed, to reduce the amount of data representing the video pictures, which cannot be completely reconstructed at the decoder, e.g., the quality of the reconstructed video pictures is lower or worse compared to the quality of the original video pictures.

Several video coding standards since H. 261 belong to the group of “lossy hybrid video codecs” (e.g., combine spatial and temporal prediction in the sample domain and 2D transform coding for applying quantization in the transform domain) . Each picture of a video sequence is typically partitioned into a set of non-overlapping blocks and the coding is typically performed on a block level. In other words, at the encoder the video is typically processed, e.g., encoded, on a block (video block) level, e.g. by using spatial (intra picture) prediction and temporal (inter picture) prediction to generate a prediction block, subtracting the prediction block from the current block (block currently processed/to be processed) to obtain a residual block, transforming the residual block and quantizing the residual block in the transform domain to reduce the amount of data to be transmitted (compression) , whereas at the decoder the inverse processing compared to the encoder is partially applied to the encoded or compressed block to reconstruct the current block for representation. Furthermore, the encoder duplicates the decoder processing loop such that both will generate identical predictions (e.g. intra-and inter predictions) and/or re-constructions for processing, e.g., coding, the subsequent blocks.

As used herein, the term “block” may a portion of a picture or a frame. For convenience of description, embodiments of the disclosure are described herein in reference to High-Efficiency Video Coding (HEVC) or the reference software of VVC, developed by the Joint Collaboration Team on Video Coding (JCT-VC) of ITU-T Video Coding Experts Group (VCEG) and ISO/IEC Motion Picture Experts Group (MPEG) . One of ordinary skill in the art will understand that embodiments of the disclosure are not limited to HEVC or VVC. It may refer to a coding unit (CU) , a prediction unit (PU) , a transform unit (TU) , etc. In HEVC, a CTU is split into CUs by using a quad-tree structure denoted as coding tree. The decision whether to code a picture area using inter-picture (temporal) or intra-picture (spatial) prediction is made at the CU level. Each CU can be further split into one, two or four PUs according to the PU splitting type. Inside one PU, the same prediction process is applied and the relevant information is transmitted to the decoder on a PU basis. After obtaining the residual block by applying the prediction process based on the PU splitting type, a CU can be partitioned into transform units (TUs) according to another quadtree structure similar to the coding tree for the CU. In the newest development of the video compression technical, Qual-tree and binary tree (QTBT) partitioning frame is used to partition a coding block. In the QTBT block structure, a CU can have either a square or rectangular shape. For example, a coding tree unit (CTU) is first partitioned by a quadtree structure. The quadtree leaf nodes are further partitioned by a binary tree structure. The binary tree leaf nodes are called coding units (CUs) , and that segmentation is used for prediction and transform processing without any further partitioning. This means that the CU, PU and TU have the same block size in the QTBT coding block structure. In parallel, multiply partition, for example, triple tree partition was also proposed to be used together with the QTBT block structure.

In the following embodiments of an encoder 20, a decoder 30 and a coding system 10 are described based on FIGS. 1 to 3.

FIG. 1A is a conceptual or schematic block diagram illustrating an example coding system 10, e.g. a video coding system 10 that may utilize techniques of this present disclosure. Encoder 20 (e.g. Video encoder 20) and decoder 30 (e.g. video decoder 30) of video coding system 10 represent examples of devices that may be configured to perform techniques in accordance with various examples described in the present disclosure. As shown in FIG. 1A, the coding system 10 comprises a source device 12 configured to provide encoded data 13, e.g. an encoded picture 13, e.g. to a destination device 14 for decoding the encoded data 13.

The source device 12 comprises an encoder 20, and may additionally, e.g., optionally, comprise a picture source 16, a pre-processing unit 18, e.g. a picture pre-processing unit 18, and a communication interface or communication unit 22.

The picture source 16 may comprise or be any kind of picture capturing device, for example for capturing a real-world picture, and/or any kind of a picture or comment (for screen content coding, some texts on the screen is also considered a part of a picture or image to be encoded) generating device, for example a computer-graphics processor for generating a computer animated picture, or any kind of device for obtaining and/or providing a real-world picture, a computer animated picture (e.g. a screen content, a virtual reality (VR) picture) and/or any combination thereof (e.g. an augmented reality (AR) picture) .

A (digital) picture is or can be regarded as a two-dimensional array or matrix of samples with intensity values. A sample in the array may also be referred to as pixel (short form of picture element) or a pel. The number of samples in horizontal and vertical direction (or axis) of the array or picture define the size and/or resolution of the picture. For representation of color, typically three color components are employed, e.g., the picture may be represented or include three sample arrays. In RBG format or color space a picture comprises a corresponding red, green and blue sample array. However, in video coding each pixel is typically represented in a luminance/chrominance format or color space, e.g. YCbCr, which comprises a luminance component indicated by Y (sometimes also L is used instead) and two chrominance components indicated by Cb and Cr. The luminance (or short luma) component Y represents the brightness or grey level intensity (e.g. like in a grey-scale picture) , while the two chrominance (or short chroma) components Cb and Cr represent the chromaticity or color information components. Accordingly, a picture in YCbCr format comprises a luminance sample array of luminance sample values (Y) , and two chrominance sample arrays of chrominance values (Cb and Cr) . Pictures in RGB format may be converted or transformed into YCbCr format and vice versa, the process is also known as color transformation or conversion. If a picture is monochrome, the picture may comprise only a luminance sample array.

In monochrome sampling there may be one sample array, which is nominally considered the luma array. In color sampling (e.g., non-monochrome sampling) , multiple sample arrays may be used. For example, two chroma arrays and a luma array may be used. In 4: 2: 0 sampling, each of the two chroma arrays has half the height and half the width of the luma array. In 4: 2: 2 sampling, each of the two chroma arrays has the same height and half the width of the luma array. In 4: 4: 4 sampling, the sample arrays may be determined based on the value of a separate_colour_plane_flag. If separate_colour_plane_flag is equal to 0, each of the two chroma arrays has the same height and width as the luma array. If the separate_colour_plane_flag is equal to 1, the three color planes are separately processed as monochrome sampled pictures.

The picture source 16 (e.g. video source 16) may be, for example a camera for capturing a picture, a memory, e.g. a picture memory, comprising or storing a previously captured or generated picture, and/or any kind of interface (internal or external) to obtain or receive a picture. The camera may be, for example, a local or integrated camera integrated in the source device, the memory may be a local or integrated memory, e.g. integrated in the source device. The interface may be, for example, an external interface to receive a picture from an external video source, for example an external picture capturing device like a camera, an external memory, or an external picture generating device, for example an external computer-graphics processor, computer or server. The interface can be any kind of interface, e.g. a wired or wireless interface, an optical interface, according to any proprietary or standardized interface protocol. The interface for obtaining the picture data 17 may be the same interface as or a part of the communication interface 22.

In distinction to the pre-processing unit 18 and the processing performed by the pre-processing unit 18, the picture or picture data 17 (e.g. video data 16) may also be referred to as raw picture or raw picture data 17.

Pre-processing unit 18 is configured to receive the (raw) picture data 17 and to perform pre-processing on the picture data 17 to obtain a pre-processed picture 19 or pre-processed picture data 19. Pre-processing performed by the pre-processing unit 18 may, e.g., comprise trimming, color format conversion (e.g. from RGB to YCbCr) , color correction, or de-noising. It can be understood that the pre-processing unit 18 may be optional component.

The encoder 20 (e.g. video encoder 20) is configured to receive the pre-processed picture data 19 and provide encoded picture data 21 (further details will be described below, e.g., based on FIG. 2 or FIG. 4) .

Communication interface 22 of the source device 12 may be configured to receive the encoded picture data 21 and to transmit it to another device, e.g. the destination device 14 or any other device, for storage or direct reconstruction, or to process the encoded picture data 21 for respectively before storing the encoded data 13 and/or transmitting the encoded data 13 to another device, e.g. the destination device 14 or any other device for decoding or storing.

The destination device 14 comprises a decoder 30 (e.g. a video decoder 30) , and may additionally, e.g., optionally, comprise a communication interface or communication unit 28, a post-processing unit 32 and a display device 34.

The communication interface 28 of the destination device 14 is configured receive the encoded picture data 21 or the encoded data 13, e.g. directly from the source device 12 or from any other source, e.g. a storage device, e.g. an encoded picture data storage device.

The communication interface 22 and the communication interface 28 may be configured to transmit or receive the encoded picture data 21 or encoded data 13 via a direct communication link between the source device 12 and the destination device 14, e.g. a direct wired or wireless connection, or via any kind of network, e.g. a wired or wireless network or any combination thereof, or any kind of private and public network, or any kind of combination thereof.

The communication interface 22 may be, e.g., configured to package the encoded picture data 21 into an appropriate format, e.g. packets, for transmission over a communication link or communication network.

The communication interface 28, forming the counterpart of the communication interface 22, may be, e.g., configured to de-package the encoded data 13 to obtain the encoded picture data 21.

Both, communication interface 22 and communication interface 28 may be configured as unidirectional communication interfaces as indicated by the arrow for the encoded picture data 13 in FIG. 1A pointing from the source device 12 to the destination device 14, or bi-directional communication interfaces, and may be configured, e.g. to send and receive messages, e.g. to set up a connection, to acknowledge and exchange any other information related to the communication link and/or data transmission, e.g. encoded picture data transmission.

The decoder 30 is configured to receive the encoded picture data 21 and provide decoded picture data 31 or a decoded picture 31 (further details will be described below, e.g., based on FIG. 3 or FIG. 5) .

The post-processor 32 of destination device 14 is configured to post-process the decoded picture data 31 (also called reconstructed picture data) , e.g. the decoded picture 31, to obtain post-processed picture data 33, e.g. a post-processed picture 33. The post-processing performed by the post-processing unit 32 may comprise, e.g. color format conversion (e.g. from YCbCr to RGB) , color correction, trimming, or re-sampling, or any other processing, e.g. for preparing the decoded picture data 31 for display, e.g. by display device 34.

The display device 34 of the destination device 14 is configured to receive the post-processed picture data 33 for displaying the picture, e.g. to a user or viewer. The display device 34 may be or comprise any kind of display for representing the reconstructed picture, e.g. an integrated or external display or monitor. The displays may, e.g. comprise liquid crystal displays (LCD) , organic light emitting diodes (OLED) displays, plasma displays, projectors, micro LED displays, liquid crystal on silicon (LCoS) , digital light processor (DLP) or any kind of other display.

Although FIG. 1A depicts the source device 12 and the destination device 14 as separate devices, embodiments of devices may also comprise both or both functionalities, the source device 12 or corresponding functionality and the destination device 14 or corresponding functionality. In such embodiments the source device 12 or corresponding functionality and the destination device 14 or corresponding functionality may be implemented using the same hardware and/or software or by separate hardware and/or software or any combination thereof.

As will be apparent for the skilled person based on the description, the existence and (exact) split of functionalities of the different units or functionalities within the source device 12 and/or destination device 14 as shown in FIG. 1A may vary depending on the actual device and application.

The encoder 20 (e.g. a video encoder 20) and the decoder 30 (e.g. a video decoder 30) each may be implemented as any of a variety of suitable circuitry, such as one or more microprocessors, digital signal processors (DSPs) , application-specific integrated circuits (ASICs) , field-programmable gate arrays (FPGAs) , discrete logic, hardware, or any combinations thereof. If the techniques are implemented partially in software, a device may store instructions for the software in a suitable, non-transitory computer-readable storage medium and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing (including hardware, software, a combination of hardware and software, etc. ) may be considered to be one or more processors. Each of video encoder 20 and video decoder 30 may be included in one or more encoders or decoders, either of which may be integrated as part of a combined encoder/decoder (CODEC) in a respective device.

Source device 12 may be referred to as a video encoding device or a video encoding apparatus. Destination device 14 may be referred to as a video decoding device or a video decoding apparatus. Source device 12 and destination device 14 may be examples of video coding devices or video coding apparatuses.

Source device 12 and destination device 14 may comprise any of a wide range of devices, including any kind of handheld or stationary devices, e.g. notebook or laptop computers, mobile phones, smart phones, tablets or tablet computers, cameras, desktop computers, set-top boxes, televisions, display devices, digital media players, video gaming consoles, video streaming devices (such as content services servers or content delivery servers) , broadcast receiver device, broadcast transmitter device, or the like and may use no or any kind of operating system.

In some cases, the source device 12 and the destination device 14 may be equipped for wireless communication. Thus, the source device 12 and the destination device 14 may be wireless communication devices.

In some cases, video coding system 10 illustrated in FIG. 1A is merely an example and the techniques of the present disclosure may apply to video coding settings (e.g., video encoding or video decoding) that do not necessarily include any data communication between the encoding and decoding devices. In other examples, data is retrieved from a local memory, streamed over a network, or the like. A video encoding device may encode and store data to memory, and/or a video decoding device may retrieve and decode data from memory. In some examples, the encoding and decoding is performed by devices that do not communicate with one another, but simply encode data to memory and/or retrieve and decode data from memory.

It should be understood that, for each of the above examples described with reference to video encoder 20, video decoder 30 may be configured to perform a reciprocal process. With regard to signaling syntax elements, video decoder 30 may be configured to receive and parse such syntax element and decode the associated video data accordingly. In some examples, video encoder 20 may entropy encode one or more syntax elements into the encoded video bitstream. In such examples, video decoder 30 may parse such syntax element and decode the associated video data accordingly.

FIG. 1B is an illustrative diagram of another example video coding system 40 including encoder 20 of FIG. 2 and/or decoder 30 of FIG. 3 according to an exemplary embodiment. The system 40 can implement techniques in accordance with various examples described in the present disclosure. In the illustrated implementation, video coding system 40 may include imaging device (s) 41, video encoder 100, video decoder 30 (and/or a video coder implemented via logic circuitry 47 of processing unit (s) 46) , an antenna 42, one or more processor (s) 43, one or more memory store (s) 44, and/or a display device 45.

As illustrated, imaging device (s) 41, antenna 42, processing unit (s) 46, logic circuitry 47, video encoder 20, video decoder 30, processor (s) 43, memory store (s) 44, and/or display device 45 may be capable of communication with one another. As discussed, although illustrated with both video encoder 20 and video decoder 30, video coding system 40 may include only video encoder 20 or only video decoder 30 in various examples.

As shown, in some examples, video coding system 40 may include antenna 42. Antenna 42 may be configured to transmit or receive an encoded bitstream of video data, for example. Further, in some examples, video coding system 40 may include display device 45. Display device 45 may be configured to present video data. As shown, in some examples, logic circuitry 47 may be implemented via processing unit (s) 46. Processing unit (s) 46 may include application-specific integrated circuit (ASIC) logic, graphics processor (s) , general purpose processor (s) , or the like. Video coding system 40 also may include optional processor (s) 43, which may similarly include application-specific integrated circuit (ASIC) logic, graphics processor (s) , general purpose processor (s) , or the like. In some examples, logic circuitry 47 may be implemented via hardware, video coding dedicated hardware, or the like, and processor (s) 43 may implemented general purpose software, operating systems, or the like. In addition, memory store (s) 44 may be any type of memory such as volatile memory (e.g., Static Random Access Memory (SRAM) , Dynamic Random Access Memory (DRAM) , etc. ) or non-volatile memory (e.g., flash memory, etc. ) , and so forth. In a non-limiting example, memory store (s) 44 may be implemented by cache memory. In some examples, logic circuitry 47 may access memory store (s) 44 (for implementation of an image buffer for example) . In other examples, logic circuitry 47 and/or processing unit (s) 46 may include memory stores (e.g., cache or the like) for the implementation of an image buffer or the like.

In some examples, video encoder 100 implemented via logic circuitry may include an image buffer (e.g., via either processing unit (s) 46 or memory store (s) 44) ) and a graphics processing unit (e.g., via processing unit (s) 46) . The graphics processing unit may be communicatively coupled to the image buffer. The graphics processing unit may include video encoder 100 as implemented via logic circuitry 47 to embody the various modules as discussed with respect to FIG. 2 and/or any other encoder system or subsystem described herein. The logic circuitry may be configured to perform the various operations as discussed herein.

Video decoder 30 may be implemented in a similar manner as implemented via logic circuitry 47 to embody the various modules as discussed with respect to decoder 30 of FIG. 3 and/or any other decoder system or subsystem described herein. In some examples, video decoder 30 may be implemented via logic circuitry may include an image buffer (e.g., via either processing unit (s) 420 or memory store (s) 44) ) and a graphics processing unit (e.g., via processing unit (s) 46) . The graphics processing unit may be communicatively coupled to the image buffer. The graphics processing unit may include video decoder 30 as implemented via logic circuitry 47 to embody the various modules as discussed with respect to FIG. 3 and/or any other decoder system or subsystem described herein.

In some examples, antenna 42 of video coding system 40 may be configured to receive an encoded bitstream of video data. As discussed, the encoded bitstream may include data, indicators, index values, mode selection data, or the like associated with encoding a video frame as discussed herein, such as data associated with the coding partition (e.g., transform coefficients or quantized transform coefficients, optional indicators (as discussed) , and/or data defining the coding partition) . Video coding system 40 may also include video decoder 30 coupled to antenna 42 and configured to decode the encoded bitstream. The display device 45 configured to present video frames.

FIG. 2 shows a schematic/conceptual block diagram of an example video encoder 20 that is configured to implement the techniques of the present disclosure. In the example of FIG. 2, the video encoder 20 comprises a residual calculation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, and inverse transform processing unit 212, a reconstruction unit 214, a buffer 216, a loop filter unit 220, a decoded picture buffer (DPB) 230, a prediction processing unit 260 and an entropy encoding unit 270. The prediction processing unit 260 may include an inter prediction unit 244, an intra prediction unit 254 and a mode selection unit 262. Inter prediction unit 244 may include a motion estimation unit and a motion compensation unit (not shown) . A video encoder 20 as shown in FIG. 2 may also be referred to as hybrid video encoder or a video encoder according to a hybrid video codec.

For example, the residual calculation unit 204, the transform processing unit 206, the quantization unit 208, the prediction processing unit 260 and the entropy encoding unit 270 form a forward signal path of the encoder 20, whereas, for example, the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the buffer 216, the loop filter 220, the DPB 230, prediction processing unit 260 form a backward signal path of the encoder, wherein the backward signal path of the encoder corresponds to the signal path of the decoder (see decoder 30 in FIG. 3) .

The encoder 20 is configured to receive, e.g. by input 202, a picture 201 or a block 203 of the picture 201, e.g. picture of a sequence of pictures forming a video or video sequence. The picture block 203 may also be referred to as current picture block or picture block to be coded, and the picture 201 as current picture or picture to be coded (in particular in video coding to distinguish the current picture from other pictures, e.g. previously encoded and/or decoded pictures of the same video sequence, e.g., the video sequence which also comprises the current picture) .

Embodiments of the encoder 20 may comprise a partitioning unit (not depicted in FIG. 2) configured to partition the picture 201 into a plurality of blocks, e.g. blocks like block 203, typically into a plurality of non-overlapping blocks. The partitioning unit may be configured to use the same block size for all pictures of a video sequence and the corresponding grid defining the block size, or to change the block size between pictures or subsets or groups of pictures, and partition each picture into the corresponding blocks.

In one example, the prediction processing unit 260 of video encoder 20 may be configured to perform any combination of the partitioning techniques described above.

Like the picture 201, the block 203 again is or can be regarded as a two-dimensional array or matrix of samples with intensity values (sample values) , although of smaller dimension than the picture 201. In other words, the block 203 may comprise, e.g., one sample array (e.g. a luma array in case of a monochrome picture 201) or three sample arrays (e.g. a luma and two chroma arrays in case of a color picture 201) or any other number and/or kind of arrays depending on the color format applied. The number of samples in horizontal and vertical direction (or axis) of the block 203 define the size of block 203.

Encoder 20 as shown in FIG. 2 is configured encode the picture 201 block by block, e.g. the encoding and prediction is performed per block 203.

The residual calculation unit 204 is configured to calculate a residual block 205 based on the picture block 203 and a prediction block 265 (further details about the prediction block 265 are provided later) , e.g. by subtracting sample values of the prediction block 265 from sample values of the picture block 203, sample by sample (pixel by pixel) to obtain the residual block 205 in the sample domain.

The transform processing unit 206 is configured to apply a transform, e.g. a discrete cosine transform (DCT) or discrete sine transform (DST) , on the sample values of the residual block 205 to obtain transform coefficients 207 in a transform domain. The transform coefficients 207 may also be referred to as transform residual coefficients and represent the residual block 205 in the transform domain.

The transform processing unit 206 may be configured to apply integer approximations of DCT/DST, such as the transforms specified for HEVC/H. 265. Compared to an orthogonal DCT transform, such integer approximations are typically scaled by a certain factor. In order to preserve the norm of the residual block which is processed by forward and inverse transforms, additional scaling factors are applied as part of the transform process. The scaling factors are typically chosen based on certain constraints like scaling factors being a power of two for shift operation, bit depth of the transform coefficients, tradeoff between accuracy and implementation costs, etc. Specific scaling factors are, for example, specified for the inverse transform, e.g. by inverse transform processing unit 212, at a decoder 30 (and the corresponding inverse transform, e.g. by inverse transform processing unit 212 at an encoder 20) and corresponding scaling factors for the forward transform, e.g. by transform processing unit 206, at an encoder 20 may be specified accordingly.

The quantization unit 208 is configured to quantize the transform coefficients 207 to obtain quantized transform coefficients 209, e.g. by applying scalar quantization or vector quantization. The quantized transform coefficients 209 may also be referred to as quantized residual coefficients 209. The quantization process may reduce the bit depth associated with some or all of the transform coefficients 207. For example, an n-bit Transform coefficient may be rounded down to an m-bit Transform coefficient during quantization, where n is greater than m. The degree of quantization may be modified by adjusting a quantization parameter (QP) . For example, for scalar quantization, different scaling may be applied to achieve finer or coarser quantization. Smaller quantization step sizes correspond to finer quantization, whereas larger quantization step sizes correspond to coarser quantization. The applicable quantization step size may be indicated by a quantization parameter (QP) . The quantization parameter may for example be an index to a predefined set of applicable quantization step sizes. For example, small quantization parameters may correspond to fine quantization (small quantization step sizes) and large quantization parameters may correspond to coarse quantization (large quantization step sizes) or vice versa. The quantization may include division by a quantization step size and corresponding or inverse dequantization, e.g. by inverse quantization 210, may include multiplication by the quantization step size. Embodiments according to some standards, e.g. HEVC, may be configured to use a quantization parameter to determine the quantization step size. Generally, the quantization step size may be calculated based on a quantization parameter using a fixed point approximation of an equation including division. Additional scaling factors may be introduced for quantization and dequantization to restore the norm of the residual block, which might get modified because of the scaling used in the fixed point approximation of the equation for quantization step size and quantization parameter. In one example implementation, the scaling of the inverse transform and dequantization might be combined. Alternatively, customized quantization tables may be used and signaled from an encoder to a decoder, e.g. in a bitstream. The quantization is a lossy operation, wherein the loss increases with increasing quantization step sizes.

The inverse quantization unit 210 is configured to apply the inverse quantization of the quantization unit 208 on the quantized coefficients to obtain dequantized coefficients 211, e.g. by applying the inverse of the quantization scheme applied by the quantization unit 208 based on or using the same quantization step size as the quantization unit 208. The dequantized coefficients 211 may also be referred to as dequantized residual coefficients 211 and correspond -although typically not identical to the transform coefficients due to the loss by quantization -to the transform coefficients 207.

The inverse transform processing unit 212 is configured to apply the inverse transform of the transform applied by the transform processing unit 206, e.g. an inverse discrete cosine transform (DCT) or inverse discrete sine transform (DST) , to obtain an inverse transform block 213 in the sample domain. The inverse transform block 213 may also be referred to as inverse transform dequantized block 213 or inverse transform residual block 213.

The reconstruction unit 214 (e.g. Summer 214) is configured to add the inverse transform block 213 (e.g., reconstructed residual block 213) to the prediction block 265 to obtain a reconstructed block 215 in the sample domain, e.g. by adding the sample values of the reconstructed residual block 213 and the sample values of the prediction block 265.

Optional, the buffer unit 216 (or short “buffer” 216) , e.g. a line buffer 216, is configured to buffer or store the reconstructed block 215 and the respective sample values, for example for intra prediction. In further embodiments, the encoder may be configured to use unfiltered reconstructed blocks and/or the respective sample values stored in buffer unit 216 for any kind of estimation and/or prediction, e.g. intra prediction.

Embodiments of the encoder 20 may be configured such that, e.g. the buffer unit 216 is not only used for storing the reconstructed blocks 215 for intra prediction 254 but also for the loop filter unit 220 (not shown in FIG. 2) , and/or such that, e.g. the buffer unit 216 and the decoded picture buffer unit 230 form one buffer. Further embodiments may be configured to use filtered blocks 221 and/or blocks or samples from the decoded picture buffer 230 (both not shown in FIG. 2) as input or basis for intra prediction 254.

The loop filter unit 220 (or short “loop filter” 220) , is configured to filter the reconstructed block 215 to obtain a filtered block 221, e.g. to smooth pixel transitions, or otherwise improve the video quality. The loop filter unit 220 is intended to represent one or more loop filters such as a de-blocking filter, a sample-adaptive offset (SAO) filter or other filters, e.g. a bilateral filter or an adaptive loop filter (ALF) or a sharpening or smoothing filters or collaborative filters. Although the loop filter unit 220 is shown in FIG. 2 as being an in loop filter, in other configurations, the loop filter unit 220 may be implemented as a post loop filter. The filtered block 221 may also be referred to as filtered reconstructed block 221. Decoded picture buffer 230 may store the reconstructed coding blocks after the loop filter unit 220 performs the filtering operations on the reconstructed coding blocks.

Embodiments of the encoder 20 (respectively loop filter unit 220) may be configured to output loop filter parameters (such as sample adaptive offset information) , e.g. directly or entropy encoded via the entropy encoding unit 270 or any other entropy coding unit, so that, e.g., a decoder 30 may receive and apply the same loop filter parameters for decoding.

The DPB 230 may be a reference picture memory that stores reference picture data for use in encoding video data by video encoder 20. The DPB 230 may be formed by any of a variety of memory devices, such as dynamic random access memory (DRAM) , including synchronous DRAM (SDRAM) , magnetoresistive RAM (MRAM) , resistive RAM (RRAM) , or other types of memory devices. The DPB 230 and the buffer 216 may be provided by the same memory device or separate memory devices. In some example, the DPB 230 is configured to store the filtered block 221. The decoded picture buffer 230 may be further configured to store other previously filtered blocks, e.g. previously reconstructed and filtered blocks 221, of the same current picture or of different pictures, e.g. previously reconstructed pictures, and may provide complete previously reconstructed, e.g., decoded, pictures (and corresponding reference blocks and samples) and/or a partially reconstructed current picture (and corresponding reference blocks and samples) , for example for inter prediction. In some example, if the reconstructed block 215 is reconstructed but without in-loop filtering, the DPB 230 is configured to store the reconstructed block 215.

The prediction processing unit 260, also referred to as block prediction processing unit 260, is configured to receive or obtain the block 203 (current block 203 of the current picture 201) and reconstructed picture data, e.g. reference samples of the same (current) picture from buffer 216 and/or reference picture data 231 from one or a plurality of previously decoded pictures from decoded picture buffer 230, and to process such data for prediction, e.g., to provide a prediction block 265, which may be an inter-predicted block 245 or an intra-predicted block 255.

Mode selection unit 262 may be configured to select a prediction mode (e.g. an intra or inter prediction mode) and/or a corresponding prediction block 245 or 255 to be used as prediction block 265 for the calculation of the residual block 205 and for the reconstruction of the reconstructed block 215.

Embodiments of the mode selection unit 262 may be configured to select the prediction mode (e.g. from those supported by prediction processing unit 260) , which provides the best match or in other words the minimum residual (minimum residual means better compression for transmission or storage) , or a minimum signaling overhead (minimum signaling overhead means better compression for transmission or storage) , or which considers or balances both. The mode selection unit 262 may be configured to determine the prediction mode based on rate distortion optimization (RDO) , e.g., select the prediction mode which provides a minimum rate distortion optimization or which associated rate distortion at least a fulfills a prediction mode selection criterion.

In the following the prediction processing (e.g. prediction processing unit 260 and mode selection (e.g. by mode selection unit 262) performed by an example encoder 20 will be explained in more detail.

As described above, the encoder 20 is configured to determine or select the best or an optimum prediction mode from a set of (pre-determined) prediction modes. The set of prediction modes may comprise, e.g., intra-prediction modes and/or inter-prediction modes.

The set of intra-prediction modes may comprise 35 different intra-prediction modes, e.g. non-directional modes like DC (or mean) mode and planar mode, or directional modes, e.g. as defined in H. 265, or may comprise 67 different intra-prediction modes, e.g. non-directional modes like DC (or mean) mode and planar mode, or directional modes, e.g. as defined in H. 266 under development.

The set of (or possible) inter-prediction modes depend on the available reference pictures (e.g., previous at least partially decoded pictures, e.g. stored in DPB 230) and other inter-prediction parameters, e.g. whether the whole reference picture or only a part, e.g. a search window area around the area of the current block, of the reference picture is used for searching for a best matching reference block, and/or e.g. whether pixel interpolation is applied, e.g. half/semi-pel and/or quarter-pel interpolation, or not.

Additional to the above prediction modes, skip mode and/or direct mode may be applied.

The prediction processing unit 260 may be further configured to partition the block 203 into smaller block partitions or sub-blocks, e.g. iteratively using quad-tree-partitioning (QT) , binary partitioning (BT) or triple-tree-partitioning (TT) or any combination thereof, and to perform, e.g. the prediction for each of the block partitions or sub-blocks, wherein the mode selection comprises the selection of the tree-structure of the partitioned block 203 and the prediction modes applied to each of the block partitions or sub-blocks.

The inter prediction unit 244 may include motion estimation (ME) unit (not shown in FIG. 2) and motion compensation (MC) unit (not shown in FIG. 2) . The motion estimation unit is configured to receive or obtain the picture block 203 (current picture block 203 of the current picture 201) and a decoded picture 231, or at least one or a plurality of previously reconstructed blocks, e.g. reconstructed blocks of one or a plurality of other/different previously decoded pictures 231, for motion estimation. E. g. a video sequence may comprise the current picture and the previously decoded pictures 231, or in other words, the current picture and the previously decoded pictures 231 may be part of or form a sequence of pictures forming a video sequence.

The encoder 20 may, e.g., be configured to select a reference block from a plurality of reference blocks of the same or different pictures of the plurality of other pictures and provide a reference picture (or reference picture index, …) and/or an offset (spatial offset) between the position (x, y coordinates) of the reference block and the position of the current block as inter prediction parameters to the motion estimation unit (not shown in FIG. 2) . This offset is also called motion vector (MV) .

The motion compensation unit is configured to obtain, e.g. receive, an inter prediction parameter and to perform inter prediction based on or using the inter prediction parameter to obtain an inter prediction block 245. Motion compensation, performed by motion compensation unit (not shown in FIG. 2) , may involve fetching or generating the prediction block based on the motion/block vector determined by motion estimation, possibly performing interpolations to sub-pixel precision. Interpolation filtering may generate additional pixel samples from known pixel samples, thus potentially increasing the number of candidate prediction blocks that may be used to code a picture block. Upon receiving the motion vector for the PU of the current picture block, the motion compensation unit 246 may locate the prediction block to which the motion vector points in one of the reference picture lists. Motion compensation unit 246 may also generate syntax elements associated with the blocks and the video slice for use by video decoder 30 in decoding the picture blocks of the video slice.

The intra prediction unit 254 is configured to obtain, e.g. receive, the picture block 203 (current picture block) and one or a plurality of previously reconstructed blocks, e.g. reconstructed neighbor blocks, of the same picture for intra estimation. The encoder 20 may, e.g., be configured to select an intra prediction mode from a plurality of (predetermined) intra prediction modes.

Embodiments of the encoder 20 may be configured to select the intra-prediction mode based on an optimization criterion, e.g. minimum residual (e.g. the intra-prediction mode providing the prediction block 255 most similar to the current picture block 203) or minimum rate distortion.

The intra prediction unit 254 is further configured to determine based on intra prediction parameter, e.g. the selected intra prediction mode, the intra prediction block 255. In any case, after selecting an intra prediction mode for a block, the intra prediction unit 254 is also configured to provide intra prediction parameter, e.g., information indicative of the selected intra prediction mode for the block to the entropy encoding unit 270. In one example, the intra prediction unit 254 may be configured to perform any combination of the intra prediction techniques described later.

The entropy encoding unit 270 is configured to apply an entropy encoding algorithm or scheme (e.g. a variable length coding (VLC) scheme, an context adaptive VLC scheme (CALVC) , an arithmetic coding scheme, a context adaptive binary arithmetic coding (CABAC) , syntax-based context-adaptive binary arithmetic coding (SBAC) , probability interval partitioning entropy (PIPE) coding or another entropy encoding methodology or technique) on the quantized residual coefficients 209, inter prediction parameters, intra prediction parameter, and/or loop filter parameters, individually or jointly (or not at all) to obtain encoded picture data 21 which can be output by the output 272, e.g. in the form of an encoded bitstream 21. The encoded bitstream 21 may be transmitted to video decoder 30, or archived for later transmission or retrieval by video decoder 30. The entropy encoding unit 270 can be further configured to entropy encode the other syntax elements for the current video slice being coded.

Other structural variations of the video encoder 20 can be used to encode the video stream. For example, a non-transform based encoder 20 can quantize the residual signal directly without the transform processing unit 206 for certain blocks or frames. In another implementation, an encoder 20 can have the quantization unit 208 and the inverse quantization unit 210 combined into a single unit.

FIG. 3 shows an exemplary video decoder 30 that is configured to implement the techniques of this present disclosure. The video decoder 30 configured to receive encoded picture data (e.g. encoded bitstream) 21, e.g. encoded by encoder 100, to obtain a decoded picture 131. During the decoding process, video decoder 30 receives video data, e.g. an encoded video bitstream that represents picture blocks of an encoded video slice and associated syntax elements, from video encoder 100.

In the example of FIG. 3, the decoder 30 comprises an entropy decoding unit 304, an inverse quantization unit 310, an inverse transform processing unit 312, a reconstruction unit 314 (e.g. a summer 314) , a buffer 316, a loop filter 320, a decoded picture buffer 330 and a prediction processing unit 360. The prediction processing unit 360 may include an inter prediction unit 344, an intra prediction unit 354, and a mode selection unit 362. Video decoder 30 may, in some examples, perform a decoding pass generally reciprocal to the encoding pass described with respect to video encoder 100 from FIG. 2.

The entropy decoding unit 304 is configured to perform entropy decoding to the encoded picture data 21 to obtain, e.g., quantized coefficients 309 and/or decoded coding parameters (not shown in FIG. 3) , e.g. (decoded) any or all of inter prediction parameters, intra prediction parameter, loop filter parameters, and/or other syntax elements. Entropy decoding unit 304 is further configured to forward inter prediction parameters, intra prediction parameter and/or other syntax elements to the prediction processing unit 360. Video decoder 30 may receive the syntax elements at the video slice level and/or the video block level.

The inverse quantization unit 310 may be identical in function to the inverse quantization unit 110, the inverse transform processing unit 312 may be identical in function to the inverse transform processing unit 112, the reconstruction unit 314 may be identical in function reconstruction unit 114, the buffer 316 may be identical in function to the buffer 116, the loop filter 320 may be identical in function to the loop filter 120 , and the decoded picture buffer 330 may be identical in function to the decoded picture buffer 130.

The prediction processing unit 360 may comprise an inter prediction unit 344 and an intra prediction unit 354, wherein the inter prediction unit 344 may resemble the inter prediction unit 144 in function, and the intra prediction unit 354 may resemble the intra prediction unit 154 in function. The prediction processing unit 360 are typically configured to perform the block prediction and/or obtain the prediction block 365 from the encoded data 21 and to receive or obtain (explicitly or implicitly) the prediction related parameters and/or the information about the selected prediction mode, e.g. from the entropy decoding unit 304.

When the video slice is coded as an intra coded (I) slice, intra prediction unit 354 of prediction processing unit 360 is configured to generate prediction block 365 for a picture block of the current video slice based on a signaled intra prediction mode and data from previously decoded blocks of the current frame or picture. When the video frame is coded as an inter coded (e.g., B, or P) slice, inter prediction unit 344 (e.g. motion compensation unit) of prediction processing unit 360 is configured to produce prediction blocks 365 for a video block of the current video slice based on the motion vectors and other syntax elements received from entropy decoding unit 304. For inter prediction, the prediction blocks may be produced from one of the reference pictures within one of the reference picture lists. Video decoder 30 may construct the reference frame lists, List 0 and List 1, using default construction techniques based on reference pictures stored in DPB 330.

Prediction processing unit 360 is configured to determine prediction information for a video block of the current video slice by parsing the motion vectors and other syntax elements, and uses the prediction information to produce the prediction blocks for the current video block being decoded. For example, the prediction processing unit 360 uses some of the received syntax elements to determine a prediction mode (e.g., intra or inter prediction) used to code the video blocks of the video slice, an inter prediction slice type (e.g., B slice, P slice, or GPB slice) , construction information for one or more of the reference picture lists for the slice, motion vectors for each inter encoded video block of the slice, inter prediction status for each inter coded video block of the slice, and other information to decode the video blocks in the current video slice.

Inverse quantization unit 310 is configured to inverse quantize, e.g., de-quantize, the quantized transform coefficients provided in the bitstream and decoded by entropy decoding unit 304. The inverse quantization process may include use of a quantization parameter calculated by video encoder 100 for each video block in the video slice to determine a degree of quantization and, likewise, a degree of inverse quantization that should be applied.

Inverse transform processing unit 312 is configured to apply an inverse transform, e.g., an inverse DCT, an inverse integer transform, or a conceptually similar inverse transform process, to the transform coefficients in order to produce residual blocks in the pixel domain.

The reconstruction unit 314 (e.g. Summer 314) is configured to add the inverse transform block 313 (e.g., reconstructed residual block 313) to the prediction block 365 to obtain a reconstructed block 315 in the sample domain, e.g. by adding the sample values of the reconstructed residual block 313 and the sample values of the prediction block 365.

The loop filter unit 320 (either in the coding loop or after the coding loop) is configured to filter the reconstructed block 315 to obtain a filtered block 321, e.g. to smooth pixel transitions, or otherwise improve the video quality. In one example, the loop filter unit 320 may be configured to perform any combination of the filtering techniques described later. The loop filter unit 320 is intended to represent one or more loop filters such as a de-blocking filter, a sample-adaptive offset (SAO) filter or other filters, e.g. a bilateral filter or an adaptive loop filter (ALF) or a sharpening or smoothing filters or collaborative filters. Although the loop filter unit 320 is shown in FIG. 3 as being an in loop filter, in other configurations, the loop filter unit 320 may be implemented as a post loop filter.

The decoded video blocks 321 in a given frame or picture are then stored in decoded picture buffer 330, which stores reference pictures used for subsequent motion compensation.

The decoder 30 is configured to output the decoded picture 331, e.g. via output 332, for presentation or viewing to a user.

Other variations of the video decoder 30 can be used to decode the compressed bitstream. For example, the decoder 30 can produce the output video stream without the loop filtering unit 320. For example, a non-transform based decoder 30 can inverse-quantize the residual signal directly without the inverse-transform processing unit 312 for certain blocks or frames. In another implementation, the video decoder 30 can have the inverse-quantization unit 310 and the inverse-transform processing unit 312 combined into a single unit.

FIG. 4 is a schematic diagram of a video coding device 400 according to an embodiment of the disclosure. The video coding device 400 is suitable for implementing the disclosed embodiments as described herein. In an embodiment, the video coding device 400 may be a decoder such as video decoder 30 of FIG. 1A or an encoder such as video encoder 20 of FIG. 1A. In an embodiment, the video coding device 400 may be one or more components of the video decoder 30 of FIG. 1A or the video encoder 20 of FIG. 1A as described above.

The video coding device 400 comprises ingress ports 410 and receiver units (Rx) 420 for receiving data; a processor, logic unit, or central processing unit (CPU) 430 to process the data; transmitter units (Tx) 440 and egress ports 450 for transmitting the data; and a memory 460 for storing the data. The video coding device 400 may also comprise optical-to-electrical (OE) components and electrical-to-optical (EO) components coupled to the ingress ports 410, the receiver units 420, the transmitter units 440, and the egress ports 450 for egress or ingress of optical or electrical signals.

The processor 430 is implemented by hardware and software. The processor 430 may be implemented as one or more CPU chips, cores (e.g., as a multi-core processor) , FPGAs, ASICs, and DSPs. The processor 430 is in communication with the ingress ports 410, receiver units 420, transmitter units 440, egress ports 450, and memory 460. The processor 430 comprises a coding module 470. The coding module 470 implements the disclosed embodiments described above. For instance, the coding module 470 implements, processes, prepares, or provides the various coding operations. The inclusion of the coding module 470 therefore provides a substantial improvement to the functionality of the video coding device 400 and effects a transformation of the video coding device 400 to a different state. Alternatively, the coding module 470 is implemented as instructions stored in the memory 460 and executed by the processor 430.

The memory 460 comprises one or more disks, tape drives, and solid-state drives and may be used as an over-flow data storage device, to store programs when such programs are selected for execution, and to store instructions and data that are read during program execution. The memory 460 may be volatile and/or non-volatile and may be read-only memory (ROM) , random access memory (RAM) , ternary content-addressable memory (TCAM) , and/or static random-access memory (SRAM) .

FIG. 5 is a simplified block diagram of an apparatus 500 that may be used as either or both of the source device 310 and the destination device 320 from FIG. 1 according to an exemplary embodiment. The apparatus 500 can implement techniques of this present disclosure described above. The apparatus 500 can be in the form of a computing system including multiple computing devices, or in the form of a single computing device, for example, a mobile phone, a tablet computer, a laptop computer, a notebook computer, a desktop computer, and the like.

A processor 502 in the apparatus 500 can be a central processing unit. Alternatively, the processor 502 can be any other type of device, or multiple devices, capable of manipulating or processing information now-existing or hereafter developed. Although the disclosed implementations can be practiced with a single processor as shown, e.g., the processor 502, advantages in speed and efficiency can be achieved using more than one processor.

A memory 504 in the apparatus 500 can be a read only memory (ROM) device or a random access memory (RAM) device in an implementation. Any other suitable type of storage device can be used as the memory 504. The memory 504 can include code and data 506 that is accessed by the processor 502 using a bus 512. The memory 504 can further include an operating system 508 and application programs 510, the application programs 510 including at least one program that permits the processor 502 to perform the methods described here. For example, the application programs 510 can include applications 1 through N, which further include a video coding application that performs the methods described here. The apparatus 500 can also include additional memory in the form of a secondary storage 514, which can, for example, be a memory card used with a mobile computing device. Because the video communication sessions may contain a significant amount of information, they can be stored in whole or in part in the secondary storage 514 and loaded into the memory 504 as needed for processing.

The apparatus 500 can also include one or more output devices, such as a display 518. The display 518 may be, in one example, a touch sensitive display that combines a display with a touch sensitive element that is operable to sense touch inputs. The display 518 can be coupled to the processor 502 via the bus 512. Other output devices that permit a user to program or otherwise use the apparatus 500 can be provided in addition to or as an alternative to the display 518. When the output device is or includes a display, the display can be implemented in various ways, including by a liquid crystal display (LCD) , a cathode-ray tube (CRT) display, a plasma display or light emitting diode (LED) display, such as an organic LED (OLED) display.

The apparatus 500 can also include or be in communication with an image-sensing device 520, for example a camera, or any other image-sensing device 520 now existing or hereafter developed that can sense an image such as the image of a user operating the apparatus 500. The image-sensing device 520 can be positioned such that it is directed toward the user operating the apparatus 500. In an example, the position and optical axis of the image-sensing device 520 can be configured such that the field of vision includes an area that is directly adjacent to the display 518 and from which the display 518 is visible.

The apparatus 500 can also include or be in communication with a sound-sensing device 522, for example a microphone, or any other sound-sensing device now existing or hereafter developed that can sense sounds near the apparatus 500. The sound-sensing device 522 can be positioned such that it is directed toward the user operating the apparatus 500 and can be configured to receive sounds, for example, speech or other utterances, made by the user while the user operates the apparatus 500.

Although FIG. 5 depicts the processor 502 and the memory 504 of the apparatus 500 as being integrated into a single unit, other configurations can be utilized. The operations of the processor 502 can be distributed across multiple machines (each machine having one or more of processors) that can be coupled directly or across a local area or other network. The memory 504 can be distributed across multiple machines such as a network-based memory or memory in multiple machines performing the operations of the apparatus 500. Although depicted here as a single bus, the bus 512 of the apparatus 500 can be composed of multiple buses. Further, the secondary storage 514 can be directly coupled to the other components of the apparatus 500 or can be accessed via a network and can comprise a single integrated unit such as a memory card or multiple units such as multiple memory cards. The apparatus 500 can thus be implemented in a wide variety of configurations.

FIG. 6 is a block diagram illustrating an example system 600 for encoding and/or decoding video data, according to one embodiment. As discussed above, the encoder 20 may encode video and/or picture data to generate encoded picture data 21. The encoded picture data 21 may be provided to the decoder 30 which may generate output 322 (e.g., a picture, a frame, a video, etc. ) based on the encoded picture data. The encoder 20 and the decoder 30 may be located on the same device (e.g., the same computing device) or different devices (e.g., different computing devices) .

In one embodiment, the encoded picture data 21 may use a quadtree plus multi-type tree (QT-MTT) coding tree structure. In the QT-MTT coding tree structure, the block width may not be equal to block height. In H. 266/VVC, multiple transform selection (MTS) may be used, in which the horizontal transform and vertical transform of a block are both signaled in bitstream. MTS may provide a higher coding gain (e.g., around 3%) and may result in a higher increase in encoding complexity.

In some versions of VVC, a shape adaptive transform selection is introduced for intra blocks. When MTS is off for intra blocks, the horizontal and vertical transforms of the block may be adaptively determined according to the shape of an intra block. For example, the horizontal transform and vertical transform of the block are both discrete cosine transform II (DCT-II or DCT-2) if the block width is equal to block height. The horizontal transform and vertical transform of the block are discrete sine transform VII (DST-VII or DST-7) and DCT-II, respectively, if the block width is smaller than the block height. The horizontal transform and vertical transform of the block are DCT-II and DST-VII, respectively, if the block width is greater than the block height. The shape adaptive transform selection may provide a higher coding gain (e.g., around 2%coding gain) and may result in a higher increase in encoding complexity.

The shape adaptive transform selection may use DST-7 when MTS is off for intra blocks. For some lower complexity encoders, only DCT-2 transform may be implemented. Therefore, it is desirable to have a switch for the shape adaptive transform selection, and support the case that for all intra coding blocks, only DCT-2 transform is used.

In addition, different encoders may have different levels of encoder complexity constraints. Therefore, it is also beneficial to configure encoders in different transform settings and deliver this configuration information to a decoder for saving coding bits on coding unit level transform information signaling. For lower complexity encoders, moderate coding gain can be achieved by using the shape adaptive transform selection without explicit signaling of CU-level transform information, and for a higher complexity encoder, higher coding gain can be achieved by explicit signaling of CU-level transform information.

The present disclosure introduces a multiple-type transform framework, in which an index is signaled in syntax structure above coding tree unit. For example, the index may be signaled in a sequence parameter set (SPS) , a picture parameter set (PPS) or a slice header. Based on the index, a decoder may use DCT-2 as the horizontal and vertical transforms of any blocks, or a decoder may use shape adaptive transform selection, or a decoder may use MTS with explicitly signaled horizontal and vertical transform.

The present disclosure introduces a method to derive horizontal and vertical transforms for an intra luma coding block in image/video decoding process, and reconstruct the intra luma coding block based on the derived horizontal and vertical transforms. Embodiment 1

This embodiment may be performed by the decoder 30 as stated above.

Block 1. Derive an index MtsIntraMode from a syntax structure that is above coding tree unit syntax structure, e.g., SPS, PPS, or slice header. This block may be performed by entropy decoding unit 304 or performed by inverse transform processing unit 312.

Take the VVC working draft 2 as an example, an sps_mts_intra_enabled_flag is signaled in SPS. Where sps_mts_intra_enabled_flag equal to 1 specifies that cu_mts_flag may be present in the residual coding syntax for intra coding units. Where sps_mts_intra_enabled_flag equal to 0 specifies that cu_mts_flag is not present in the residual coding syntax for intra coding units.

In present disclosure, an sps_mts_intra_shape_adaptive_flag may be signaled in SPS (as marked in Table 1) if sps_mts_intra_enable_flag is equal to 0. When sps_mts_intra_shape_adaptive_flag is not present in the bitstream, its value is inferred to be 0. Based on sps_mts_intra_shape_adaptive_flag and sps_mts_intra_enable_flag, an index MtsIntraMode is derived as follows:

MtsIntraMode = sps_mts_intra_enabled_flag? 2 : (sps_mts_intra_shape_adaptive_flag? 0 : 1) . sps_mts_intra_shape_adaptive_flag equal to 1 specifies that the horizontal and vertical transform for luma blocks in coding units using intra prediction (i.e., CuPredMode associated with coding unit equal to MODE_INTRA in VVC draft 2) are adaptive according to the width and height of the luma blocks. sps_mts_intra_shape_adaptive_flag equal to 0 specifies that the horizontal and vertical transform for luma blocks in intra coding units are not adaptive according to the width and height of the luma blocks.

Table 1 SPS of VVC working draft 2 with sps_mts_intra_shape_adaptive_flag flag

Block 2: Based on the index MtsIntraMode, decide the horizontal and vertical transform of an intra luma coding block.

This block may be performed by entropy decoding unit 304 or performed by inverse transform processing unit 312. The intra luma coding block may be contained in a coding unit with luma and chroma components or a coding unit with only luma component.

More specifically, Block 2 may be performed according to any of the following:

If the index MtsIntraMode is equal to 0 (i.e., sps_mts_intra_enabled_flag equal to 0 and sps_mts_intra_shape_adaptive_flag equal to 0) , the horizontal transform and vertical transform of the intra luma coding block are both DCT-2.

If the index MtsIntraMode is equal to 1 (i.e., sps_mts_intra_enabled_flag equal to 0 and sps_mts_intra_shape_adaptive_flag equal to 1) , the following processing is conducted:

if the block width is equal to block height, the horizontal transform and vertical transform of the intra luma coding block are both DCT-2;

if the block width is smaller than the block height, the horizontal transform and vertical transform of the intra luma coding block are DST-7 and DCT-2, respectively;

if the block width is greater than the block height, the horizontal transform and vertical transform of the intra luma coding block are DCT-2 and DST-7, respectively.

If the index MtsIntraMode is equal to 2 (i.e., sps_mts_intra_enabled_flag equal to 1 and sps_mts_intra_shape_adaptive_flag equal to 0) , the horizontal transform and vertical transform of the intra luma coding block may be signaled in bitstream. A first flag is parse to determine the horizontal transform of the luma coding block. If the first flag is 0 (or 1) , the horizontal transform of the intra luma coding block is DCT-8 (or DST-7) . A second flag is parse to determine the vertical transform of the luma coding block. If the first flag is 0 (or 1) , the horizontal transform of the intra luma coding block is DCT-8 (or DST-7) .

After deriving the horizontal and vertical transform of the luma block, block 3 and 4 may be performed to reconstruct the pixels in the intra luma block.

Block 3. Apply inverse transform base on the horizontal and vertical transform of the luma block, so as to obtain reconstructed residual of the luma block, e.g., the inverse transform block 313. This block may be performed by inverse transform processing unit 312.

Block 4. Add the reconstructed residual of the luma block with prediction samples of the luma block, so as to obtain the reconstructed samples of the luma block, e.g., the reconstructed block 315. This block may be performed by reconstruction unit 314.

Blocks 3 and 4 are existing methods commonly used in video coding.

The reconstructed block 315 is used to obtain the decoded picture 331 as stated above.

Embodiment 2

Block 1. Derive an index MtsIntraMode from a syntax structure that is above coding tree unit syntax structure, e.g., SPS, PPS, or slice header.

Block 1 in embodiment 1 can be used. This block may be performed by entropy decoding unit 304 or performed by inverse transform processing unit 312.

This block may be performed by entropy decoding unit 304 or performed by inverse transform processing unit 312.

The intra luma coding block may be contained in a coding unit with luma and chroma components or a coding unit with only luma component.

More specifically, Block 2 may be performed according to any of the following:

if the block width is smaller than the block height and the block width is smaller than a threshold T1, the horizontal transform and vertical transform of the intra luma coding block are DST-7 and DCT-2, respectively; wherein T1 is a pre-defined integer, e.g., T1= 32 or 16;

if the block width is smaller than the block height and the block width is equal to or greater than a threshold T1, the horizontal transform and vertical transform of the intra luma coding block are both DCT-2;

if the block width is greater than the block height and the block height is smaller than the threshold T1, the horizontal transform and vertical transform of the intra luma coding block are DCT-2 and DST-7, respectively.

if the block width is greater than the block height and the block height is equal to or greater than the threshold T1, the horizontal transform and vertical transform of the intra luma coding block are both DCT-2, respectively.

Block 3. Apply inverse transform base on the horizontal and vertical transform of the luma block, so as to obtain reconstructed residual of the luma block. This block may be performed by inverse transform processing unit 312.

Block 4. Add the reconstructed residual of the luma block with prediction samples of the luma block, so as to obtain the reconstructed samples of the luma block.

This block may be performed by reconstruction unit 314.

Blocks 3 and 4 are existing methods commonly used in video coding.

The encoded picture data 21 may be a sequence or a stream of bits that may be generated by the encoder 20 and may be decoded by the decoder 30. The encoded picture data 21 may also be referred to as a bitstream. As illustrated in FIG. 6, the encoded picture data 21 may have a format (e.g., a data format, a structure for the portions of the encoding picture data 21, etc. ) . The format may determine how encoded picture data 21 is divided into different portions. The format of the encoded picture data 21 may also be referred to as a syntax structure (or syntax) for the encoded picture data 21. As illustrated in FIG. 6, the encoded picture data 21 is divided into network abstraction layer (NAL) units 610. The encoded picture data 21 includes different types of NAL units 610. For example, the encoded picture data may include a SPS 620, a PPC 630, and one or more slices 640 (e.g., video slices) . Each video slice may include a header 641 (e.g., a slice header) , and one or more coding blocks 642. The coding block 642 may also be referred to as a CU, PU, TU, etc.

In one embodiment, the decoder 30 may determine a set of transforms for decoding a coding block 642 based on a syntax structure (e.g., a format) associated with the coding block 642. The coding block 642 is included in a slice 640. The slice 640 includes a header 641 (e.g., a slice header) . The header 641 may have a syntax structure (e.g., a syntax or format) that indicates one or more flags (e.g., values for the flags) . The decoder may determine a set of transforms that are used to decode a coding block 643 based on the one or more flags (e.g., based on the syntax structure) . A coding block 642 may be a luma block for intra picture (e.g., spatial) prediction Thus, the coding block 643 may be referred to as an intra luma coding block. The coding block may also include one or more chroma blocks.

In one embodiment, the set of transforms may include a horizontal transform and a vertical transform. A horizontal transform may be a transform that is applied to a coding block 643 in a horizontal direction (e.g., from left to right, from right to left, etc. ) . A vertical transform may be a transform that may be applied the coding block 643 in a vertical direction (e.g., from top to bottom, from bottom to top, etc. ) .

In one embodiment, the decoder 30 may obtain an inverse transform block for the coding block 643 base on the horizontal transform and the vertical transform, which were determined based on the syntax structure associated with the coding block 643 (e.g., based on the values of one or more flags which are determined/identified based on a format of the encoded picture data 21. The inverse transform block may be obtained by applying an inverse transform on de-quantized coefficients of the coding block 643 (e.g., an intra luma coding block) using the horizontal transform and the vertical transform. The inverse transform block may correspond to and/or may be associated with the coding block 643.

In one embodiment, the decoder 30 may obtain a reconstructed block based on the inverse transform block for a coding block 643. For example, the decoder may add the inverse transform block to a prediction block to obtain the reconstructed block. The prediction block may be an intra prediction block. The reconstructed block may correspond to and/or may be associated with the coding block 643. The decoder 30 may obtain a decoded picture and/or a portion of a decoded picture corresponding to and/or associated with the coding block 643.

In one embodiment, the decoder 30 may identify the set of transforms for decoding a coding block 643 based on one or more flags in the encoded picture data 21. For example, the syntax structure of the encoded picture data 21 (e.g., the format of the encoded picture data 21) may indicate the location within a NAL 610 and/or the values of a first flag and a second flag. The one or more flags (used to determine/identify the set of transforms) may be in one or more of the SPS 620, the PPS 630, and the header 641. For example, the one or more flags may be in the SPS 620. In another example, one of the flags may be in the SPS 620 and the other flag may be in the PPS 630.

In one embodiment, the decoder 30 may identify a first transform to use for a horizontal transform and a second transform to use for a vertical transform based on the first flag and the second flag. The first flag may be a flag that indicates whether multiple transform selection (MTS) is used when decoding the encoded picture data 21. For example, the first flag may be a sps_mts_intra_enabled_flag. The sps_mts_intra_enabled_flag may be defined in the various versions of the specifications and/or request for comments (RFCs) for VVC. If the sps_mts_intra_enabled_flag is enabled (e.g., the value of the sps_mts_intra_enabled_flag is 1) , the cu_mts_flag may also be present in one of the NAL units 610 (e.g., in the SPS 620) . If the sps_mts_intra_enabled_flag is disabled (e.g., the value of the sps_mts_intra_enabled_flag is 0) , the cu_mts_flag may not be present and/or enabled in one of the NAL units 610. The second flag may be a flag that indicates whether adaptive transform selection (ATS) is use when decoding the encoded picture data 21. For example, the second flag may be a sps_mts_intra_shape_adaptive_flag. The sps_mts_intra_shape_adaptive_flag may be defined in the various versions of the specifications and/or request for comments (RFCs) for VVC. If sps_mts_intra_enabled_flag is disabled (e.g., the value of the sps_mts_intra_enabled_flag is 0) , the sps_mts_intra_shape_adaptive_flag may be present. If the sps_mts_intra_shape_adaptive_flag is not present within the encoded picture data 21 (e.g., is not in the bitstream of the encoded picture data 21) , the value of the sps_mts_intra_shape_adaptive_flag is inferred to be disabled (e.g., 0) .

In one embodiment, if the sps_mts_intra_shape_adaptive_flag is enabled (e.g., equal to 1) , this may indicate that the horizontal and vertical transforms for coding blocks (e.g., intra luma coding blocks) are identified, determined, selected, etc., based on to the width and height of the luma blocks (e.g., the horizontal and vertical transforms are adaptive) . If the sps_mts_intra_shape_adaptive_flag is disabled (e.g., equal to 0) , this may indicate that the horizontal and vertical transforms for coding blocks (e.g., intra luma coding blocks) are not identified, determined, selected, etc., based on to the width and height of the luma blocks (e.g., the horizontal and vertical transforms are not adaptive) .

In one embodiment, if the first flag (e.g., the sps_mts_intra_enabled_flag) is not enabled (e.g., equal to 0) and the second flag (e.g., the sps_mts_intra_shape_adaptive_flag) is not enabled, the discrete cosine transform II (DCT-II) is used as both the horizontal transform and vertical transform for decoding a coding block 642 (e.g., both the horizontal and vertical transforms are DCT-II) .

In one embodiment, if the first flag (e.g., the sps_mts_intra_enabled_flag) is not enabled (e.g., equal to 0) and the second flag (e.g., the sps_mts_intra_shape_adaptive_flag) is enabled (e.g., is equal to 1) , the decoder 30 may determine the height and the width of a coding block 642 (e.g., an intra luma coding block) . If the width of coding block 642 is equal the height of the coding block 642, the discrete cosine transform II (DCT-II or DCT-2) is used as both the horizontal transform and vertical transform for decoding a coding block 642 (e.g., both the horizontal and vertical transforms are DCT-II) . If the width of coding block 642 is less than the height of the coding block 642, a discrete sine transform VII (DST-VII or DST-7) is used as the horizontal transform and the DCT-II is used as the vertical transform for decoding a coding block 642 (e.g., the vertical transform is DST-VII and the horizontal transform is DCT-II) . If the width of coding block 642 greater than the height of the coding block 642, DST-VII is used as the vertical transform and DCT-II is used as the horizontal transform for decoding a coding block 642 (e.g., the vertical transform is DST-VII and the horizontal transform is DCT-II) .

In one embodiment, if the first flag (e.g., the sps_mts_intra_enabled_flag) is not enabled (e.g., equal to 0) and the second flag (e.g., the sps_mts_intra_shape_adaptive_flag) is enabled (e.g., is equal to 0) , the decoder 30 may determine the height and the width of a coding block 642 (e.g., an intra luma coding block) . The decoder may also 30 determine (compare) the width and/or height of the coding block 642 with one or more thresholds. If the width of coding block 642 is equal the height of the coding block 642, DCT-II is used as both the horizontal transform and vertical transform for decoding a coding block 642 (e.g., both the horizontal and vertical transforms are DCT-II) . If the width of coding block 642 is less than the height of the coding block 642 and the width of the intra luma coding block is less than a threshold width, DST-VII is used as the horizontal transform and the DCT-II is used as the vertical transform for decoding a coding block 642 (e.g., the horizontal transform is DST-VII and the vertical transform is DCT-II) . If the width of coding block 642 is less than the height of the coding block 642 and the width of the intra luma coding block is greater than or equal to the threshold width, DCT-II is used as both the horizontal transform and vertical transform for decoding a coding block 642 (e.g., both the horizontal and vertical transforms are DCT-II) . If the width of coding block 642 is greater than or equal to the height of the coding block 642 and the height of the intra luma coding block is less than a threshold height, DCT-II is used as the horizontal transform and the DST-VII is used as the vertical transform for decoding a coding block 642 (e.g., the horizontal transform is DCT-II and the vertical transform is DST-VII) . If the width of coding block 642 is greater than or equal to the height of the coding block 642 and the height of the intra luma coding block is greater than or equal to the threshold height, DCT-II is used as both the horizontal transform and vertical transform for decoding a coding block 642 (e.g., both the horizontal and vertical transforms are DCT-II) . Various threshold widths and/or threshold heights may be used in different embodiments. For example, a threshold width may be 16, 32, or some other appropriate width. In another example, a threshold height may be 16, 32, or some other appropriate height.

In one embodiment, if the first flag (e.g., the sps_mts_intra_enabled_flag) is enabled (e.g., equal to 1) and the second flag (e.g., the sps_mts_intra_shape_adaptive_flag) is not enabled (e.g., equal to 0) , the decoder 30 identify additional flags in the encoded picture data 21 (e.g., in the bitstream of the encoded picture data 21) . For example, the decoder may identify a third flag and a fourth flag in the encoded picture data 21. The third and fourth flag may be located within one of the NAL units 610 (e.g., in the SPS 620, the PPS 630, a header 641, etc. ) . If the third flag is enabled (e.g., equal to 1) , a discrete cosine transform VIII (DCT-VIII) may be used for the horizontal transform (e.g., the horizontal transform may be DCT-VIII) . If the third flag is not enabled (e.g., equal to 0) , DST-VIII may be used for the horizontal transform (e.g., the horizontal transform may be DST-VIII) . If the fourth flag is enabled (e.g., equal to 1) , a discrete cosine transform VIII (DCT-VIII) may be used for the vertical transform (e.g., the vertical transform may be DCT-VIII) . If the fourth flag is not enabled (e.g., equal to 0) , DST-VIII may be used for the vertical transform (e.g., the vertical transform may be DST-VIII) .

In one embodiment, the decoder 30 may identify the set of transforms for decoding a coding block 643 by deriving an index (e.g., a value) which may indicate a horizontal transform and a vertical transform to be used for decoding the coding block 643. The decoder 30 may identify or determine the appropriate transforms to use for the horizontal transform and the vertical transform based on the index. The index may be based on one or more flags which are determined based on a syntax structure (e.g., a format) of the encoded picture data 21, as discussed above. For example, the index may be based on a first flag (e.g., sps_mts_intra_enabled_flag) and a second flag (e.g., sps_mts_intra_shape_adaptive_flag) . The index may be referred to as MtsIntraMode in the various versions of the specifications and/or request for comments (RFCs) for VVC. In other embodiments, the index may have a different name (e.g., different alphanumeric strings and/or characters may represent the name of the index) .

As discussed above, the value of an index (e.g., MtsIntraMode) may be determine based on the first flag and the second flat. For example, the index may have the value 0 when the (e.g., sps_mts_intra_enabled_flag) is not enabled (e.g., is equal to 0) and a second flag (e.g., sps_mts_intra_shape_adaptive_flag) is not enabled. In another example, the index may have the value 1 when the (e.g., sps_mts_intra_enabled_flag) is not enabled (e.g., is equal to 0) and a second flag (e.g., sps_mts_intra_shape_adaptive_flag) is enabled (e.g., is equal to 1) . In a further example, the index may have the value 2 when the (e.g., sps_mts_intra_enabled_flag) is enabled (e.g., is equal to 1) and a second flag (e.g., sps_mts_intra_shape_adaptive_flag) is not enabled (e.g., is equal to 0) . In some embodiments, determine the index may be equivalent to determine the first flag and the second flag. For example, where the present disclosure refers to determining whether the first flag is enabled and whether the second flag is enabled, the index may be used in place of the first flag and the second flag. For example, if the index has the value 1, the decoder 30 may use transforms determined based on the first flag not being enabled and the second flag being enabled, as discussed above. In another example, if the index has the value 0, the decoder 30 may use transforms determined based on the first flag not being enabled and the second flag not being enabled, as discussed above.

In one embodiment, if the (e.g., sps_mts_intra_enabled_flag) is enabled (e.g., is equal to 1) and a second flag (e.g., sps_mts_intra_shape_adaptive_flag) is not enabled (e.g., is equal to 0) , the decoder 30 may identify an index in the encoded picture data 21 (e.g., in the bitstream of the encoded picture data 21) . The index included in the bistream of the encoded picture data 21 may also be referred to as a flag. The location of the index within the encoded picture data 21 (e.g., within the NAL units 610) may be based on the syntax structure (e.g., syntax or format) of the encoded picture data 21. The decoder 30 may determine the horizontal transform and vertical transform to use for decoding a coding block 643 based the value of the index included in the bistream of the encoded picture data 21. If the value of the index is 0, DCT-VIII may be used for both the horizontal transform and the vertical transform (e.g., the horizontal and vertical transforms may be DCT-VIII) . If the value of the index is 1, DCT-VIII is used for the horizontal transform and DST-VII is used for the vertical transform (e.g., the horizontal transform is DCT-VIII and the vertical transform is DST-VII) . If the value of the index is 2, DST-VII is used for the horizontal transform and DCT-VIII is used for the vertical transform (e.g., the horizontal transform is DST-VII and the vertical transform is DCT-VIII) . If the value of the index is 3, DST-VII may be used for both the horizontal transform and the vertical transform (e.g., the horizontal and vertical transforms may be DST-VII) .

FIG. 7 is a flowchart illustrating an example process 700 for decoding a coding block (e.g., an intra luma coding block) , according to one embodiment. Process 700 may be performed by processing logic which may include software, hardware, or a combination thereof. Process 700 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, a processor, a processing device, a central processing unit (CPU) , a system-on-chip (SoC) , etc. ) , software (e.g., instructions running/executing on a processing device) , firmware (e.g., microcode) , or a combination thereof. In some embodiments, process 700 may be performed by a processing device, a decoder (e.g., decoder 30 illustrated in FIGS. 1-3) , portions and/or components of a decoder (e.g., entropy decoding unit 304, inverse transform processing unit 312, inverse transform processing unit 312, reconstruction unit 314 illustrated in FIG. 3) , etc.

At block 705, the process 700 may determine a set of transforms for decoding an intra luma coding block (e.g., a coding block) . As discussed above, the process 700 may determine the set of transforms based on a syntax structure associated with the intra luma coding block. The syntax structure may be used to obtain one or more flags and/or an index. The process 700 may determine a horizontal transform and/or a vertical transform for decoding the intra luma coding block, based on the one or more flags and/or the index.

At block 710 the process 700 may obtain an inverse transform block based on the horizontal transform and the horizontal transform. For example, the process 700 may apply an inverse transform on de-quantized coefficients of the intra luma coding block using the horizontal transform and the vertical transform. At block 715, the process 700 may obtain a reconstructed block based on the inverse transform block for the intra luma coding block. For example, the process 700 may obtain the may add the inverse transform block to a prediction block to obtain the reconstructed block. At block 720 the process 700 may obtain a decoded picture and/or a portion of a decoded picture based on the reconstructed block. For example, the process 700 may generate a decoded picture (e.g., a frame) based on the reconstructed block.

FIG. 8 is a flowchart illustrating an example process 800 for decoding a coding block (e.g., an intra luma coding block) , according to one embodiment. Process 800 may be performed by processing logic which may include software, hardware, or a combination thereof. Process 800 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, a processor, a processing device, a central processing unit (CPU) , a system-on-chip (SoC) , etc. ) , software (e.g., instructions running/executing on a processing device) , firmware (e.g., microcode) , or a combination thereof. In some embodiments, process 800 may be performed by a processing device, a decoder (e.g., decoder 30 illustrated in FIGS. 1-3) , portions and/or components of a decoder (e.g., entropy decoding unit 304, inverse transform processing unit 312, inverse transform processing unit 312, reconstruction unit 314 illustrated in FIG. 3) , etc. In one embodiment, the process 800 may correspond to block 705 illustrated in FIG. 7.

The process 800 begins at block 805 where the process 800 determines a first flag (e.g., the sps_mts_intra_enabled_flag) and a second flag (e.g., the sps_mts_intra_shape_adaptive_flag) . As discussed above, first flag and the second flag may be determined, identified, obtained, etc., based on a syntax structure associated with the coding block. For example, the syntax structure may indicate where the first flag and second flag are located within a SPS, PPS, header (e.g., slider header) , etc.

At block 810, the process 800 determines if the first flag is enabled. If the first flag is not enabled (e.g., equals 0) , the process 800 determines whether the second flag is enabled at block 815. If the second is not enabled, the process 800 determines that the horizontal and vertical transforms are DCT-II. If the second flag is enabled (e.g., equals 1) , the process 800 determines whether the width of the coding block is greater than less then, or equal to the height of the coding block at block 825. If the width is equal to the height, the process 800 determines that the horizontal and vertical transforms are DCT-II at block 830. If the width is greater than the height, the process 800 determines that the horizontal transform is DCT-II and the vertical transform is DST-VII at block 835. If the width is less than the height, the process 800 determines that the horizontal transform is DST-VII and the vertical transform is DCT-II at block 850.

If the first flag is enabled, the process 800 determines whether the second flag is enabled at block 845. If th second flag is not enabled, the process determines whether a third flag is enabled at block 850. If the third flag is enabled, the process 800 determines that the horizontal transform is DST-VII at block 860. If the third flag is not enabled the process 800 determines that the horizontal transform is DCT-VIII at block 855. At block 865, the process 800 determines whether a fourth flag is enabled. If the fourth flag is enabled, the process 800 determines that the horizontal transform is DST-VII at block 875. If the fourth flag is not enabled the process 800 determines that the horizontal transform is DCT-VIII at block 870.

FIG. 9 is a flowchart illustrating an example process 900 for decoding a coding block (e.g., an intra luma coding block) , according to one embodiment. Process 900 may be performed by processing logic which may include software, hardware, or a combination thereof. Process 900 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, a processor, a processing device, a central processing unit (CPU) , a system-on-chip (SoC) , etc. ) , software (e.g., instructions running/executing on a processing device) , firmware (e.g., microcode) , or a combination thereof. In some embodiments, process 900 may be performed by a processing device, a decoder (e.g., decoder 30 illustrated in FIGS. 1-3) , portions and/or components of a decoder (e.g., entropy decoding unit 304, inverse transform processing unit 312, inverse transform processing unit 312, reconstruction unit 314 illustrated in FIG. 3) , etc. In one embodiment, the process 900 may correspond to block 705 illustrated in FIG. 7.

The process 900 begins at block 905 where the process 900 determines a first flag (e.g., the sps_mts_intra_enabled_flag) and a second flag (e.g., the sps_mts_intra_shape_adaptive_flag) . As discussed above, first flag and the second flag may be determined, identified, obtained, etc., based on a syntax structure associated with the coding block. For example, the syntax structure may indicate where the first flag and second flag are located within a SPS, PPS, header (e.g., slider header) , etc.

At block 910, the process 900 determines if the first flag is enabled. If the first flag is not enabled (e.g., equals 0) , the process 900 determines whether the second flag is enabled at block 915. If the second is not enabled, the process 900 determines that the horizontal and vertical transforms are DCT-II. If the second flag is enabled (e.g., equals 1) , the process 900 determines whether the width of the coding block is greater than less then, or equal to the height of the coding block at block 925. If the width is equal to the height, the process 900 determines that the horizontal and vertical transforms are DCT-II at block 930. If the width is greater than the height, the process 900 determines whether the height is less than a threshold height. If the height is not less than the threshold height (e.g., greater than or equal to the threshold height) , the process 900 may determine that the horizontal and vertical transforms are DCT-II at block 936. If the height is less than the threshold height, the process 900 may determine that the horizontal transform is DCT-II and the vertical transform is DST-VII at block 937. If the width is less than the height, the process 900 determines whether the width is less than a threshold width at block 940. If the width is not less than the threshold width (e.g., greater than or equal to the threshold width) , the process 900 may determine that the horizontal and vertical transforms are DCT-II at block 941. If the width is less than the threshold width, the process 900 may determine that the horizontal transform is DST-VII and the vertical transform is DCT-II at block 942.

If the first flag is enabled, the process 900 determines whether the second flag is enabled at block 945. If th second flag is not enabled, the process determines whether a third flag is enabled at block 950. If the third flag is enabled, the process 900 determines that the horizontal transform is DST-VII at block 960. If the third flag is not enabled the process 900 determines that the horizontal transform is DCT-VIII at block 955. At block 965, the process 900 determines whether a fourth flag is enabled. If the fourth flag is enabled, the process 900 determines that the horizontal transform is DST-VII at block 975. If the fourth flag is not enabled the process 900 determines that the horizontal transform is DCT-VIII at block 970.

In one or more examples, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media, which corresponds to a tangible medium such as data storage media, or communication media including any medium that facilitates transfer of a computer program from one place to another, e.g., according to a communication protocol. In this manner, computer-readable media generally may correspond to (1) tangible computer-readable storage media which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code and/or data structures for implementation of the techniques described in this disclosure. A computer program product may include a computer-readable medium.

By way of example, and not limitation, such computer-readable storage media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) , or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transitory media, but are instead directed to non-transitory, tangible storage media. Disk and disc, as used herein, includes compact disc (CD) , laser disc, optical disc, digital versatile disc (DVD) , floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

Instructions may be executed by one or more processors, such as one or more digital signal processors (DSPs) , general purpose microprocessors, application specific integrated circuits (ASICs) , field programmable logic arrays (FPGAs) , or other equivalent integrated or discrete logic circuitry. Accordingly, the term “processor, ” as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. In addition, in some aspects, the functionality described herein may be provided within dedicated hardware and/or software modules configured for encoding and decoding, or incorporated in a combined codec. Also, the techniques could be fully implemented in one or more circuits or logic elements.

The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs (e.g., a chip set) . Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require realization by different hardware units. Rather, as described above, various units may be combined in a codec hardware unit or provided by a collection of interoperative hardware units, including one or more processors as described above, in conjunction with suitable software and/or firmware.

Claims

A method, comprising:

determining a set of transforms for decoding an intra luma coding block based on a syntax structure associated with the intra luma coding block, wherein the set of transforms comprise a horizontal transform and a vertical transform;

obtaining an inverse transform block for the intra luma coding block based on the horizontal transform and the vertical transform;

obtaining a reconstructed block based on the inverse transform block for the intra luma coding block; and

obtaining a decoded picture corresponding to the intra luma coding block based on the reconstructed block.
The method of claim 1, wherein obtaining the inverse transform block comprises:

applying an inverse transform on de-quantized coefficients of the intra luma coding block based on the determined horizontal transform and the determined vertical, so as to obtain an inverse transform block of the intra luma coding block.
The method of claim 1 or 2, wherein determining the set of transforms comprises:

deriving an index for indicating the horizontal transform and the vertical transform based on the syntax structure associated with the intra luma coding block;

determining the horizontal transform and the vertical transform based on the derived index.
The method of claim 1 or 2, wherein determining the set of transforms comprises:

determining a horizontal transform and a vertical transform based on a first flag and a second flag, wherein:

the first flag and the second flag are obtained based on the syntax structure;

the first flag indicates whether multiple transform selection is used; and

the second flag indicates whether adaptive transform selection is used.
The method of claim 4, wherein:

the first flag indicates that multiple transform selection is not used;

the second flag indicates that adaptive transform selection is not used; and

the horizontal transform and the vertical transform comprise a discrete cosine transform II (DCT-II transform) .
The method of claim 4, wherein:

the first flag indicates that multiple transform selection is not used;

the second flag indicates that adaptive transform selection is used;

the horizontal transform and the vertical transform comprise a discrete cosine transform II (DCT-II transform) when a width of the intra luma coding block is equal a height of the intra luma coding block;

the horizontal transform comprises a discrete sine transform VII (DST-VII transform) and the vertical transform comprises the DCT-II transform when the width of the intra luma coding block is less than the height of the intra luma coding block; or

the horizontal transform comprises the DCT-II transform and the vertical transform comprises the DST-VII transform when the width of the intra luma coding block is greater than the height of the intra luma coding block.
The method of claim 4, wherein:

the first flag indicates that multiple transform selection is not used;

the second flag indicates that adaptive transform selection is used;

the horizontal transform and the vertical transform comprise a discrete cosine transform II (DCT-II transform) when a width of the intra luma coding block is equal a height of the intra luma coding block;

the horizontal transform comprises a discrete sine transform VII (DST-VII transform) and the vertical transform comprises the DCT-II transform when the width of the intra luma coding block is less than the height of the intra luma coding block and when the width of the intra luma coding block is less than a threshold;

the horizontal transform and the vertical transform comprise a discrete cosine transform II (DCT-II transform) when the width of the intra luma coding block is less than the height of the intra luma coding block and when the width of the intra luma coding block greater than or equal to the threshold;

the horizontal transform comprises the DCT-II transform and the vertical transform comprises the DST-VII transform when the width of the intra luma coding block is greater than the height of the intra luma coding block and when the width of the intra luma coding block is less than the threshold; or

the horizontal transform and the vertical transform comprise a discrete cosine transform II (DCT-II transform) when the width of the intra luma coding block is greater than the height of the intra luma coding block and when the width of the intra luma coding block is greater than or equal to the threshold.
The method of claim 4, wherein:

the first flag indicates that multiple transform selection is used;

the second flag indicates that adaptive transform selection is not used;

the horizontal transform is determined further based on a third flag in a received bitstream and the vertical transform is determined further based on a fourth flag in the received bitstream.
The method of claim 8, wherein:

the horizontal transform comprises a discrete cosine transform VIII (DCT-VIII transform) when the third flag is 0;

the horizontal transform comprises a discrete sine transform VII (DST-VII transform) when the third flag is 1;

the vertical transform comprises a discrete cosine transform VIII (DCT-VIII transform) when the fourth flag is 0; or

the vertical transform comprises the DST-VII transform when the fourth flag is 1.
The method of claim 4, wherein:

the first flag indicates that multiple transform selection is used;

the second flag indicates that adaptive transform selection is not used;

the horizontal transform and the vertical transform are determined further based on an index in a received bitstream.
The method of claim 10, wherein:

the horizontal transform and the vertical transform comprise a discrete cosine transform VIII (DCT-VIII transform) when the index is 0;

the horizontal transform comprises the DCT-VIII transform and the vertical transform comprises a discrete sine transform VII (DST-VII transform) when the index is 1;

the horizontal transform comprises the DST-VII transform and the vertical transform comprises the DCT-VIII transform when the index is 2; or

the horizontal transform and the vertical transform comprise the DST-VII transform when the index is 3.
An apparatus, comprising:

a memory configured to store data;

a processor coupled to the memory, the processor to:

determine a set of transforms for decoding an intra luma coding block based on a syntax structure associated with the intra luma coding block, wherein the set of transforms comprise a horizontal transform and a vertical transform;

obtain an inverse transform block for the intra luma coding block based on the horizontal transform and the vertical transform;

obtain a reconstructed block based on the inverse transform block for the intra luma coding block; and

obtain a decoded picture corresponding to the intra luma coding block based on the reconstructed block.
The apparatus of claim 12, wherein to determine the set of transforms the processor is further to:

derive an index for indicating the horizontal transform and the vertical transform based on the syntax structure associated with the intra luma coding block;

determine the horizontal transform and the vertical transform based on the derived index.
The apparatus of claim 12, wherein to determine the set of transforms the processor is further to:

determine a horizontal transform and a vertical transform based on a first flag and a second flag, wherein:

the first flag and the second flag are obtained based on the syntax structure;

the first flag indicates whether multiple transform selection is used; and

the second flag indicates whether adaptive transform selection is used.
The apparatus of claim 14, wherein:

the first flag indicates that multiple transform selection is not used;

the second flag indicates that adaptive transform selection is not used; and

the horizontal transform and the vertical transform comprise a discrete cosine transform II (DCT-II transform) .
The apparatus of claim 14, wherein:

the first flag indicates that multiple transform selection is not used;

the second flag indicates that adaptive transform selection is used;

the horizontal transform and the vertical transform comprise a discrete cosine transform II (DCT-II transform) when a width of the intra luma coding block is equal a height of the intra luma coding block;

the horizontal transform comprises a discrete sine transform VII (DST-VII transform) and the vertical transform comprises the DCT-II transform when the width of the intra luma coding block is less than the height of the intra luma coding block; or

the horizontal transform comprises the DCT-II transform and the vertical transform comprises the DST-VII transform when the width of the intra luma coding block is greater than the height of the intra luma coding block;
The apparatus of claim 14, wherein:

the first flag indicates that multiple transform selection is not used;

the second flag indicates that adaptive transform selection is used;

the horizontal transform and the vertical transform comprise a discrete cosine transform II (DCT-II transform) when a width of the intra luma coding block is equal a height of the intra luma coding block;

the horizontal transform comprises a discrete sine transform VII (DST-VII transform) and the vertical transform comprises the DCT-II transform when the width of the intra luma coding block is less than the height of the intra luma coding block and when the width of the intra luma coding block is less than a threshold;

the horizontal transform and the vertical transform comprise a discrete cosine transform II (DCT-II transform) when the width of the intra luma coding block is less than the height of the intra luma coding block and when the width of the intra luma coding block greater than or equal to the threshold;

the horizontal transform comprises the DCT-II transform and the vertical transform comprises the DST-VII transform when the width of the intra luma coding block is greater than the height of the intra luma coding block and when the width of the intra luma coding block is less than the threshold; or

the horizontal transform and the vertical transform comprise a discrete cosine transform II (DCT-II transform) when the width of the intra luma coding block is greater than the height of the intra luma coding block and when the width of the intra luma coding block is greater than or equal to the threshold.
The apparatus of claim 14, wherein:

the first flag indicates that multiple transform selection is used;

the second flag indicates that adaptive transform selection is not used;

the horizontal transform is determined further based on a third flag in a received bitstream and the vertical transform is determined further based on a fourth flag in the received bitstream.
The method of claim 18, wherein:

the horizontal transform comprises a discrete cosine transform VIII (DCT-VIII transform) when the third flag is 0;

the horizontal transform comprises a discrete sine transform VII (DST-VII transform) when the third flag is 1;

the vertical transform comprises a discrete cosine transform VIII (DCT-VIII transform) when the fourth flag is 0; and

the vertical transform comprises the DST-VII transform when the fourth flag is 1.
A non-transitory machine-readable medium having instructions stored therein, which when executed by a processor, cause the processor to perform operations according to any one of claims 1 to 11.
A decoder (30) comprising processing circuitry for carrying out the method according to any one of claims 1 to 11.
A computer program product comprising a program code for performing the method according to any one of claims 1 to 11.