WO2020063929A1

WO2020063929A1 - Method and device for transmitting discovery reference signal

Info

Publication number: WO2020063929A1
Application number: PCT/CN2019/108769
Authority: WO
Inventors: 吴霁; 朱俊; 贾琼
Original assignee: 华为技术有限公司
Priority date: 2018-09-28
Filing date: 2019-09-27
Publication date: 2020-04-02
Also published as: CN110971362A; CN110971362B

Abstract

A method and device for transmitting a discovery reference signal, for use in solving the problem of a terminal being prone to generating a communication delay when receiving an RMSI CORESET and a corresponding SSB. The method comprises: a network device performs listen before talk and then accesses a channel. The network device transmits one or more discovery reference signals (DRS) to a terminal, where any of the DRS is carried on successive symbols.

Description

Method and device for sending discovery reference signal

This application claims the priority of a Chinese patent application filed on September 28, 2018 with the Chinese Patent Office, application number 201811142734.8, and application name "A Discovery Reference Signal Transmission Method and Device", the entire contents of which are incorporated herein by reference. Applying.

Technical field

The present application relates to the field of communication technologies, and in particular, to a method and a device for sending a discovery reference signal.

Background technique

A new wireless technology (new radio (NR)) standard defines a synchronization pulse sequence set (SS burst), which is mainly used by the UE for initial access / system message update / beam management. An SS burst consists of several synchronization signal blocks (synchronization signal / PBCH block, SS / PBCH block).

Each SS / PBCH block has 4 Orthogonal Frequency Division Multiplexing (OFDM) symbols, which correspond to the primary synchronization signal (PSS), physical broadcast signal (PBCH), and Synchronization signal (secondary synchronization signal, SSS), PBCH.

The NR system information is divided into a master system information block (master information block (MIB)) and remaining minimum system information (remaining system information) (RMSI). The MIB bearer is sent in the PBCH, and the MIB includes the basic information required to access the network, and the RMSI control resource set (CORESET), etc., where the RMSI CORESET is used to indicate the physical downlink shared channel carrying the RMSI downlink shared channel (PDSCH).

At present, discovery reference signals (DRS) in the NR system include at least SS / PBCH block, RMSI CORESET, and RMSI PDSCH. When sending a DRS, it is usually sent at a fixed symbol position. For example, when the subcarrier interval is 120 kHz, the first symbol position of the SS / PBCH block is {4,8,16,20} + 28 * n. As shown in Figure 1, the SS / PBCH block can be transmitted on symbols 4 to 7 of the first slot, or transmitted on symbols 8 to 11 of the first slot, or it can be carried on the second slot. Transmission is performed on symbols 2 to 5 of each slot, and transmission may also be carried on symbols 6 to 9 of the second slot. When the SS / PBCH block is transmitted on symbols 4 to 7 of the first slot, the corresponding RMSI CORESET is transmitted on

symbols

0 and 1 of the first slot. When the SS / PBCH block is transmitted on symbols 8 to 11 of the first slot, the corresponding RMSI CORESET is transmitted on

symbols

2 and 3 of the first slot. When the SS / PBCH block is transmitted on symbols 2 to 5 of the second slot, the corresponding RMSI CORESET is transmitted on

symbols

12 and 13 of the first slot. When the SS / PBCH block is transmitted on symbols 6 to 9 of the second slot, the corresponding RMSI CORESET is transmitted on

symbols

0 and 1 of the first slot.

However, it can be known from FIG. 1 that after the UE receives the RMSI CORESET carried on the first slot of symbol 0 and symbol 1, it receives the SS / PBCH block corresponding to the RMSI CORESET after multiple symbols are spaced, which results in communication. Delay.

Summary of the Invention

The present application provides a method and device for transmitting a discovery reference signal, which is used to solve the problem that a communication delay easily occurs when a terminal receives RMSI CORESET and a corresponding SSB.

In a first aspect, the present application provides a method for sending a discovery reference signal. The method includes: the network device listens to the LBT first and then accesses the channel. The network device sends one or more discovery reference signals DRS to the terminal, where any one of the DRSs is carried on consecutive symbols. In the embodiment of the present application, by sending DRS on consecutive symbols, the symbol interval between the RMSI CORESET and the SSB can be reduced, so that the terminal does not need to wait too long to receive the SSB after receiving the RMSI CORESET, thus It can reduce the communication delay to a certain extent, and by reducing the time interval between RMSI CORESET and SSB, it can also solve the problem of inaccurate DRS demodulation due to the long time interval between RMSI CORESET and SSB. .

In a possible design, the DRS includes at least a synchronization signal block and control information, where the control information is used to indicate a time-frequency resource in which the first system information is located, and the first system information is in the synchronization signal block. The system information indicated by the main system information, the synchronization signal block and the control information are carried at predetermined positions in the continuous symbols.

In a possible design, the any one DRS is sent using a first pattern, and in the first pattern, the N symbols occupied by the synchronization signal block are located behind the M symbols occupied by the control information. N and M are integers greater than 0. In the above design, when the network device sends the discovery reference signal, the control information can be sent in front of the synchronization signal, it can be sent after the synchronization signal, or it can be sent after the synchronization signal. Compared to the control information, it can only be synchronized. Signals are sent in front. In the above design, you can choose whether to send in front of the synchronization signal or after the synchronization signal according to the position of the symbol to be transmitted. This can improve the flexibility of sending control information and synchronization signals, and improve resource utilization. Can reduce the communication delay to a certain extent.

In a possible design, the any one DRS is transmitted using a first pattern, in which the N symbols occupied by the synchronization signal block are located before the M symbols occupied by the control information. In the above design, when the network device sends the discovery reference signal, the control information can be sent in front of the synchronization signal, it can be sent after the synchronization signal, or it can be sent after the synchronization signal. Compared to the control information, it can only be synchronized. Signals are sent in front. In the above design, you can choose whether to send in front of the synchronization signal or after the synchronization signal according to the position of the symbol to be transmitted. This can improve the flexibility of sending control information and synchronization signals, and improve resource utilization. Can reduce the communication delay to a certain extent.

In a possible design, the DRS includes a synchronization signal block, control information, and second system information, where the control information is used to indicate a time-frequency resource where the first system information is located, and the first system information is the The system information indicated by the main system information in the synchronization signal block, and the second system information includes at least the first system information.

In a possible design, the any DRS is sent using a second pattern, in which the N symbols occupied by the synchronization signal block are located behind the M symbols occupied by the control information, the The P symbols occupied by the second system information are located after the N symbols occupied by the synchronization signal block, and the N, M, and P are integers greater than 0. In the above design, when the network device sends the discovery reference signal, the control information may be sent in front of the synchronization signal, and the second system information may be sent after the synchronization signal block, thereby improving the flexibility of sending the second system information.

In a possible design, the any DRS is sent using a second pattern, in which the N symbols occupied by the synchronization signal block are located before the M symbols occupied by the control information, the The P symbols occupied by the second system information are located after the M symbols occupied by the control information, and P is an integer greater than 0. In the above design, when the network device sends the discovery reference signal, the control information may be sent after the synchronization signal, and the second system information may be sent after the control information, thereby improving the flexibility of sending the second system information.

In a possible design, if the number of symbols following the M symbols occupied by the control information is less than P in the same time slot, the second system information of any one DRS occupies multiple of the other time slots Consecutive symbols, multiple consecutive symbols occupied by the second system information of any one DRS are in the same time slot. Because the current control information may not support cross-slot scheduling system information, when the remaining symbols in the current slot are insufficient, the second system information is completely transmitted in other slots, which can solve the problem that the control information does not support cross-slot scheduling. Scheduling system information causes a problem that the second system information cannot be accurately demodulated.

In a second aspect, the present application provides a method for sending a discovery reference signal. The method includes: a terminal receiving one or more discovery reference signals DRS from a network device, wherein any one of the DRSs is carried on consecutive symbols. In the embodiment of the present application, by sending DRS on consecutive symbols, the symbol interval between the RMSI CORESET and the SSB can be reduced, so that the terminal does not need to wait too long to receive the SSB after receiving the RMSI CORESET. It can reduce the communication delay to a certain extent, and by reducing the time interval between RMSI CORESET and SSB, it can also solve the problem of inaccurate DRS demodulation due to the long time interval between RMSI CORESET and SSB. .

In a third aspect, the present application provides a method for sending a discovery reference signal. The method includes: a network device determines a discovery reference signal DRS, where the discovery reference signal includes at least a synchronization signal and control information, the control information includes information about time-frequency resources where first system information is located, and the first system information is the first system information The system information indicated by the main system information in the synchronization signal; the network device sends the one or more discovery reference signals to a terminal, wherein any one of the DRSs is carried on consecutive symbols. In the embodiment of the present application, by sending DRS on consecutive symbols, the symbol interval between the RMSI CORESET and the SSB can be reduced, so that the terminal does not need to wait too long to receive the SSB after receiving the RMSI CORESET, thus It can reduce the communication delay to a certain extent, and by reducing the time interval between RMSI CORESET and SSB, it can also solve the problem of inaccurate DRS demodulation due to the long time interval between RMSI CORESET and SSB. .

In a possible design, the control information is carried on N symbols in the consecutive symbols, the synchronization signal block is carried on M symbols in the consecutive symbols, and the N symbols The symbols are adjacent to the M symbols in the time domain, and N and M are integers greater than 0. In the above design, by reducing the symbol interval between the RMSI CORESET and the SSB, the terminal does not need to wait too long to receive the SSB after receiving the RMSI CORESET, thereby reducing the communication delay to a certain extent, and, By reducing the time interval between RMSI CORESET and SSB, the problem of inaccurate DRS demodulation due to the long time interval between RMSI CORESET and SSB can also be solved to a certain extent.

In a possible design, the discovery reference signal further includes second system information, the control information is carried on N symbols in the continuous symbols, and the synchronization signal block is carried in continuous symbols. On M symbols, the second system information is carried on n symbols other than the N symbols and the M symbols, and the control information and the second system information are adjacent in the time domain, The second system information and the synchronization signal block are adjacent in the time domain. In the above design, by carrying the second system information, control information, and the synchronization signal block on adjacent symbols, the terminal can schedule the second system information in time after receiving the control information, thereby reducing the communication delay, and Can improve resource utilization. In addition, currently the control information may not support scheduling system information across time slots. Therefore, by combining the second system information, the control information, and the synchronization signal block, the control information and the corresponding second system information can be in one time slot, thereby To some extent, control information can be avoided to schedule system information across time slots.

In a possible design, the discovery reference signal further includes second system information, the control information is carried on N symbols in the continuous symbols, and the synchronization signal block is carried in continuous symbols. On M symbols, the second system information is carried on the M symbols in a frequency division multiplexed manner, and the control information and the synchronization signal block are adjacent in the time domain. In the above design, the second system information is carried on the M symbols by means of frequency division multiplexing. After receiving the control information, the terminal can schedule the second system information in a timely manner, thereby reducing the communication delay, and Can improve resource utilization. In addition, currently the control information may not support scheduling system information across time slots. Therefore, by filling the second system information into the idle resource blocks of the M consecutive symbols, the control information and the corresponding second system information can be combined in one. In time slots, control information can be avoided to a certain extent to schedule system information across time slots.

In a possible design, the N symbols include t * (N + M) +1 symbols of a time slot to t * (N + M) + N symbols, and the M consecutive The symbols include the t * (N + M) + N + 1 symbols to the t * (N + M) + N + M symbols of the time slot, where t is an integer greater than or equal to 0.

In a possible design, the discovery reference signal further includes second system information, the control information occupies N consecutive symbols, and the synchronization signal block occupies M consecutive Symbols, the second system information is carried on the M symbols in a frequency division multiplexed manner. In the above design, by carrying the second system information on the M symbols in a frequency division multiplexed manner, the terminal can schedule the second system information in time after receiving the control information, thereby reducing the communication delay. It can also improve resource utilization. In addition, currently the control information may not support scheduling system information across time slots. Therefore, by filling the second system information into the idle resource blocks of the M consecutive symbols, the control information and the corresponding second system information can be combined in one. In time slots, control information can be avoided to a certain extent to schedule system information across time slots.

In a possible design, the synchronization signal carries the number of all symbols carrying the control information. In the above design, the terminal may determine the DRS transmission mode by the number of all symbols carrying the control information carried in the synchronization signal.

In a possible design, if the network device sends a discovery reference signal in a time slot, the second system information in the discovery reference signal is sent in one or more of the following ways: the second system Information is carried on the N consecutive symbols other than the symbols carrying the control information; the second system information is carried on the M consecutive symbols by means of frequency division multiplexing; The second system information is carried on a slot except for the N consecutive symbols and other symbols before the M consecutive symbols for transmission. When there are relatively few resource blocks in one time slot or the second system information data volume is large, the discovery reference signal can be sent in the above manner, so that the discovery reference signal can be completely transmitted in one time slot as far as possible, thereby providing reception Find the accuracy of the reference signal.

In a possible design, if the network device sends three discovery reference signals in two time slots, the second discovery reference signal is carried in the symbol of the first time slot, and the second discovery reference The synchronization signal in the signal is carried in the first M symbols of the second time slot. When there are many resource blocks included in one time slot, the above design can be used to send DRS, so that the number of discovery reference signals sent in one time slot can be increased, and resource utilization can be improved.

In a possible design, the idle resource blocks in the first M symbols of the second time slot are filled with downlink signals; or the idle resource blocks in the first M symbols of the second time slot The synchronization signal in the second discovery reference signal is used for padding.

In a fourth aspect, the present application provides a method for sending a discovery reference signal. The method includes: a network device determines a discovery reference signal, the discovery reference signal including at least a synchronization signal, control information, and second system information, the control information includes information about time-frequency resources where the first system information is located, and the first system The information is system information indicated by main system information in the synchronization signal, and the second system information includes at least the first system information; the network device starts to send the discovery reference signal to the terminal at a preset position, where The discovery reference signal lasts N symbols, and the synchronization signal, the control information, and the synchronization information are carried on the N symbols in a frequency division multiplexing manner, and N is an integer greater than 0. In the embodiment of the present application, by carrying a synchronization signal, the control information, and the synchronization information on the N symbols in a frequency division multiplexed manner, a relatively large number of discovery reference signals can be sent in one time slot. Taking a time slot including 14 symbols and N equal to 4 as an example, at present, a maximum of 2 discovery reference signals can be sent in a time slot. According to the embodiment of the present application, 4 discovery reference signals can be sent in a time slot.

In a possible design, the preset position is a t * N + 1th symbol in a time slot, where t is an integer greater than or equal to 0.

In a fifth aspect, the present application provides a device, which may be a terminal, a network device, or a chip. The device has a function of realizing any one of the designs of the first to sixth aspects. This function can be realized by hardware, and can also be implemented by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

According to a sixth aspect, an apparatus is provided, including: a processor, a communication interface, and a memory. The communication interface is used to transfer information, and / or messages, and / or data between the device and other devices. The memory is configured to store a computer execution instruction. When the device is running, the processor executes the computer execution instruction stored in the memory, so that the device executes the design described in any one of the first to fourth aspects. Discover the reference signal transmission method.

In a seventh aspect, the present application further provides a system including the network device in any one of the foregoing first aspect, the third aspect, and the fourth aspect, and any one of the foregoing second aspects. Terminal.

In an eighth aspect, the present application further provides a computer-readable storage medium, where the computer-readable storage medium stores instructions, and when the computer-readable storage medium runs on the computer, causes the computer to execute the methods described in the above aspects.

In a ninth aspect, the present application further provides a computer program product including instructions that, when run on a computer, causes the computer to execute the methods described in the above aspects.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic architecture diagram of a communication system provided by this application;

2 is a schematic diagram of resource allocation of a synchronization signal provided by the present application;

FIG. 3 is a schematic diagram of resource allocation of a discovery reference signal provided by the present application; FIG.

FIG. 4 is a schematic flowchart of a discovery reference signal sending method provided by the present application;

FIG. 5 is a schematic diagram of a first pattern provided by the present application; FIG.

6A is a schematic diagram of resource allocation of a discovery reference signal provided by the present application;

FIG. 6B is a schematic diagram of resource allocation of another discovery reference signal provided by the present application; FIG.

FIG. 6C is another schematic diagram of resource allocation for discovery reference signals provided by the present application; FIG.

FIG. 7A is a schematic diagram of a second pattern provided by the present application; FIG.

FIG. 7B is a schematic diagram of another second pattern provided by the present application; FIG.

FIG. 8A is a schematic diagram of resource allocation of another discovery reference signal provided by the present application; FIG.

FIG. 8B is a schematic diagram of resource allocation of another discovery reference signal provided by the present application; FIG.

FIG. 9A is a schematic diagram of a third pattern provided by the present application; FIG.

9B is a schematic diagram of another third pattern provided by the present application;

FIG. 9C is a schematic diagram of another third pattern provided by the present application; FIG.

9D is a schematic diagram of another third pattern provided by the present application;

10 is a schematic diagram of a fourth pattern provided by the present application;

11 is a schematic diagram of a fifth pattern provided by the present application;

FIG. 12 is a schematic flowchart of another discovery reference signal sending method provided by the present application; FIG.

FIG. 13A is a schematic diagram of a sixth pattern provided by the present application; FIG.

13B is a schematic diagram of another sixth pattern provided by the present application;

FIG. 14A is a schematic diagram of a seventh pattern provided by the present application; FIG.

14B is a schematic diagram of another seventh pattern provided by the present application;

FIG. 14C is a schematic diagram of another seventh pattern provided by the present application; FIG.

FIG. 15A is a schematic diagram of resource allocation of a discovery reference signal provided by the present application; FIG.

FIG. 15B is a schematic diagram of resource allocation of another discovery reference signal provided by this application; FIG.

FIG. 15C is a schematic diagram of resource allocation of another discovery reference signal provided by the present application; FIG.

16 is a schematic structural diagram of a communication device provided by the present application;

FIG. 17 is a schematic structural diagram of a communication device provided by the present application.

detailed description

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings.

The communication method provided in this application can be applied to various communication systems, for example, it can be the Internet of Things (IoT), narrowband Internet of Things (NB-IoT), long term evolution , LTE), it can also be the fifth generation (5G) communication system, it can also be a hybrid architecture of LTE and 5G, it can also be a 5G new radio (NR) system, a global mobile system (global system for mobile communication), (GSM), mobile communication system (universal mobile telecommunications system, UMTS), code division multiple access (code division multiple access, CDMA) system, and new communication systems emerging in the development of future communications. As long as the communication system needs to use multiple beams to send control information and / or data, the discovery reference signal sending method provided in the embodiment of the present application can be used.

The terminal involved in this embodiment of the present application is a user-side entity for receiving or transmitting signals. The terminal may be a device that provides voice and / or data connectivity to the user, such as a handheld device with a wireless connection function, a vehicle-mounted device, and the like. The terminal may also be another processing device connected to the wireless modem. The terminal may communicate with one or more core networks through a radio access network (radio access network, RAN). The terminal can also be called a wireless terminal, a subscriber unit, a subscriber station, a mobile station, a mobile station, a remote station, an access point, A remote terminal, an access terminal, a user terminal, a user agent, a user device, or a user equipment. Terminal devices can be mobile terminals, such as mobile phones (or "cellular" phones) and computers with mobile terminals. For example, they can be portable, pocket-sized, handheld, computer-built or vehicle-mounted mobile devices. The access network exchanges language and / or data. For example, the terminal device may also be a personal communication service (PCS) phone, a cordless phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, or a personal digital assistant. (personal digital assistant, PDA), and other devices. Common terminal devices include, for example, mobile phones, tablets, laptops, PDAs, mobile Internet devices (MID), wearable devices, such as smart watches, smart bracelets, pedometers, etc., but this application implements Examples are not limited to this.

The network equipment involved in the embodiments of the present application is an entity for transmitting or receiving signals on the network side, and can be used to convert the received air frames and network protocol (IP) packets to each other as A router between the terminal device and the rest of the access network, where the rest of the access network may include an IP network and the like. Network equipment can also coordinate the management of attributes of the air interface. For example, the network equipment may be a global mobile system (Global System for Mobile Communication, GSM) or a base station (BTS) in code division multiple access (CDMA), or a broadband code division multiple access (wideband code division multiple access, WCDMA) base station (NodeB), can also be an evolutionary base station (evolutionary NodeB, eNB or e-NodeB) in LTE, or a new wireless controller controller), which can be a gNodeB (gNB) in a 5G system, a centralized network unit, a new wireless base station, a radio remote module, a micro base station, or a relay ) May be a distributed network unit, a transmission point (TRP) or a transmission point (TP), or any other wireless access device, but the embodiment of the present application is not limited thereto. Network equipment can cover one or more cells.

Referring to FIG. 1, a communication system provided by an embodiment of the present application includes a network device and six terminal devices, that is, UE1 to UE6. In this communication system, UE1 to UE6 can send uplink data to the network device, and the network device can receive uplink data sent by UE1 to UE6. In addition, UE4 to UE6 may also form a sub-communication system. The network device can send downlink information to UE1, UE2, UE3, and UE5, and UE5 can send downlink information to UE4 and UE6 based on device-to-device (D2D) technology. FIG. 1 is only a schematic diagram, and does not specifically limit the type of the communication system, and the number and types of devices included in the communication system.

The network architecture and service scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those of ordinary skill in the art may know that with the network The evolution of the architecture and the emergence of new business scenarios. The technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

The NR standard defines a synchronization pulse sequence set (SS burst), which is mainly used by the UE for initial access / system message update / beam management. An SS burst consists of several synchronization signal blocks (synchronization signal / PBCH block, SS / PBCH block). Each SS / PBCH continues to have 4 orthogonal frequency division multiplexing (OFDM) symbols. These 4 OFDM symbols carry the primary synchronization signal (PSS) and physical broadcast signal in sequence. broadcast channel (PBCH), secondary synchronization signal (SSS), and PBCH, as shown in Figure 2.

In the NR system, the system information is divided into a master system information block (MIB), a remaining minimum system information (RMSI), and other system information (OSI). Among them, the MIB is carried in the PBCH of the SS / PBCH block, and the MIB carries basic information required for accessing the network. The RMSI mainly carries information related to cell access and cell selection, similar to SIB1 in LTE, and NR subframe configuration, scheduling and window information of other SIB blocks, and so on. RMSI includes RMSICORESET and RMSI physical downlink shared channel (PDSCH). In the NR system, in order to improve system scheduling flexibility, the position and size of the time-frequency resources of the RMSI PDSCH are variable, and the position and size of the time-frequency resources of the RMSI PDSCH are indicated by the RMSI CORESET. The instruction information for indicating RMSI CORESET is carried in the PBCH of the SS / PBCH block.

In an NR system based on unlicensed spectrum, in some embodiments, a discovery reference signal (DRS) includes SS / PBCH block, RMSI CORESET, and RMSI PDSCH. In other embodiments, the DRS may further include OSI, paging, channel state information-reference signal (CSI-RS), and the like.

Currently, when transmitting DRS in NR system. SS / PBCH blocks are usually sent at fixed symbol positions. The NR standard gives the specific time-frequency position of the SS / PBCH block at different subcarrier intervals, as follows:

When the subcarrier interval is 15KHz: the first symbol position of the SS / PBCH block is {2,8} + 14 * n. When the carrier frequency is less than 3GHz, n = 0,1; when the carrier frequency is greater than 3GHz and less than 6GHz, n = 0,1,2,3. Exemplarily, a slot includes 14 symbols.

When the subcarrier interval is 30KHz: the first symbol position of the SS / PBCH block is {4, 8, 16, 20} + 28 * n. When the carrier frequency is less than 3GHz, n = 0; when the carrier frequency is greater than 3GHz and less than 6GHz, n = 0, 1.

When the subcarrier interval is 30KHz: the first symbol position of the SS / PBCH block is {2,8} + 14 * n. When the carrier frequency is less than 3GHz, n = 0,1; when the carrier frequency is greater than 3GHz and less than 6GHz, n = 0,1,2,3.

When the subcarrier interval is 120KHz: the first symbol position of the SS / PBCH block is {4, 8, 16, 20} + 28 * n. When the carrier frequency is greater than 6 GHz, n = 0,1,2,3,5,6,7,8,10,11,12,13,15,16,17,18.

When the subcarrier interval is 240KHz: The first symbol position of the SS / PBCH block is {8, 12, 16, 20, 32, 36, 40, 44} + 56 * n. When the carrier frequency is greater than 6 GHz, n = 0,1,2,3,5,6,7,8.

Since the SS / PBCH block needs to last 4 symbols, based on the specific time-frequency position of the SS / PBCH block at different subcarrier intervals given by the NR standard, it is usually known that when sending DRS, two SS / PBCH blocks are sent in sequence RMSI CORESET. After sending the RMSI CORESET corresponding to the two SS / PBCH blocks, the two SS / PBCH blocks are sent in sequence. Taking the subcarrier interval as 120KHz as an example, as shown in FIG. 3,

symbols

0 and 1 occupying slot 0 send RMSI CORESET1 in the slot 0,

symbols

2 and 3 occupying slot 0 send RMSI CORESET2 in DRS2 and the slot 0 symbol 4-7 sends SS / PBCH block1 in DRS1, and the symbols 8-11 occupying slot 0 send SS / PBCH block2 in DRS2.

Symbols

12 and 13 occupying slot 0 send RMSI CORESET3 in slot 1 and

symbols

0 and 1 in slot 1 send RMSI CORESET4 in DRS4, symbols 2-5 occupying slot 1 send SS / PBCH block3 in DRS3 and occupy slot 1 The symbols 6-9 of SS / PBCH block4 in DRS4 are transmitted.

In this transmission mode, multiple symbols are separated between the SS / PBCH block and RMSI CORESET in the same DRS. Therefore, after receiving the RMSI CORESET, the UE needs to wait for multiple symbols before receiving the SS / PBCH block, as shown in the figure. As shown in 3, after receiving the RMSI CORESET1 at

symbols

0 and 1, the terminal needs to wait for two symbols (ie, symbols 2 and 3) before it can receive SS / PBCH block1 at symbols 4 to 6, resulting in communication delay. In addition, the SS / PBCH block cannot perform cross-slot scheduling, that is, the PBCH in the SS / PBCH block can only schedule RMSI CORESET in the slot where the SS / PBCH block is located. However, according to the sending method shown in Figure 3, SS / PBCH block 3 In the slot 0 of RMSI CORESET3, and SS / PBCH block3 in slot 1, the terminal may fail to receive DRS3 normally, and the terminal may not be able to synchronize with the cell.

Based on this, the embodiments of the present application provide a DRS transmission method and device, and propose a new type of DRS structure to avoid the problem that the terminal may not be able to synchronize with the cell due to the terminal's failure to receive DRS normally. Among them, the method and the device are based on the same inventive concept. Since the principle of the method and the device for solving the problem is similar, the implementation of the device and the method can refer to each other, and the duplicated parts will not be described again.

The network device uses a single beam to send DRS in a time slot. Therefore, the terminal can use a single beam to receive DRS in a time slot. In other implementations, the network device may repeatedly send the DRS by using a single beam in multiple consecutive time slots. Therefore, the terminal can repeatedly send DRS by using a single beam in multiple timeslots.

In still other implementation manners, the network device may use a DRS transmission method provided in the present application to transmit DRS in multiple beams in multiple consecutive time slots. For the mapping pattern of the DRS, refer to various patterns provided in this application. The terminal may receive the DRS through multiple beams by using the DRS transmission method provided in the present application in multiple consecutive time slots. Therefore, flexible configuration of DRS in a single-beam scenario or a multi-beam scenario is realized. It can be understood that when the terminal receives one DRS, it can perform corresponding decoding; when the terminal receives multiple DRS, the robustness can be enhanced.

In other embodiments, the network device may send one DRS in a time slot, or may send multiple DRSs. The multiple DRSs may be the same or different. In this one time slot, the network device may use a single beam to send one or more DRSs, or use multiple beams to send multiple DRSs. Optionally, the multiple DRSs may be DRSs carrying the same content, or DRSs carrying different content. Correspondingly, the terminal may receive one DRS or multiple DRSs in one slot, and the multiple DRSs may be the same or different. In this one time slot, the terminal may use a single beam to receive one or more DRSs, and may also use multiple beams to receive multiple DRSs. Of course, the multiple DRSs may be DRSs carrying the same content, or DRSs carrying different content.

In some other implementation manners, the network device may use a DRS-like transmission mode to transmit one DRS in multiple consecutive time slots, and may also transmit multiple DRS in multiple consecutive time slots. Optionally, the multiple DRSs may be DRSs carrying the same content, or DRSs carrying different content. Correspondingly, the terminal may use a transmission method similar to the DRS in one time slot to receive one DRS in multiple consecutive time slots, or may receive multiple DRS in multiple consecutive time slots. Of course, the multiple DRSs may be DRSs carrying the same content, or DRSs carrying different content.

For different beams, they can send the same DRS, or they can send different DRS. For the same beam, it can continuously send the same DRS, or it can continuously send different DRS.

The multiple involved in this application means two or more.

In addition, it should be understood that in the description of this application, the words "first" and "second" are used only for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor as indicating Or imply order.

The DRS transmission method provided in the embodiments of the present application will be specifically described below with reference to the accompanying drawings.

Referring to FIG. 4, a flowchart of a DRS sending method provided by the present application, the method includes:

S401. A network device determines a DRS, where the DRS includes at least a synchronization signal and control information, where the control information includes information about time-frequency resources where the first system information is located.

Among them, the synchronization signal may be SS / PBCH block. The first system information may carry information related to cell access and cell selection, as well as NR subframe configuration, scheduling and window information of other SIB blocks, and the like. The first system information is named differently in each access system. For example, in LTE, the first system information is SIB1. In the NR system, the first system information is RMSI PDSCH. In the future communication system, the first system information may be named other names, such as XX. It should be understood that if the XX can also implement the functions implemented by the first system information in the embodiments of the present application, the XX can also be understood as the first system information in the embodiments of the present application. For convenience of description, in the embodiment of the present application, the first system information is RMSI as an example for description. If the first system information is RMSI PDSCH, the control information may be RMSI CORESET.

In other embodiments, the DRS may further include second system information, and the second system information may include RMSI PDSCH, OSI, and the like. The DRS may also include other information, such as paging, CSI-RS, or other downlink signals.

In other embodiments, the DRS can be predefined. In other words, S401 is not a necessary step.

S402. The network device sends one or more discovery reference signals DRS to a terminal, where any one of the DRSs is carried on consecutive symbols.

S403. The terminal receives one or more of the DRSs sent by a network device. The terminal can receive the DRS at a preset position.

In a possible implementation manner, the DRS may be sent using the first pattern. In the first pattern, N symbols occupied by the synchronization signal block are located behind M symbols occupied by the control information, and N and M are integers greater than 0.

In an example, in the first pattern, N consecutive symbols and M consecutive symbols include a fixed number of symbols and a fixed position in the time domain. Exemplarily, the positions of the N consecutive symbols may be t * (N + M) +1 symbols to t * (N + M) + N symbols of a slot, and the positions of the M consecutive symbols may be T * (N + M) + N + 1 symbols to t * (N + M) + N + M symbols of a slot, where t is an integer greater than or equal to 0. Taking a slot including 14 symbols, N = 3, M = 4 as an example, the first pattern can be: the symbol position carrying the first RMSI CORESET is symbol 0 ~ 2, and the position carrying the first SS / PBCH block symbol It is the symbols 3 to 6, the symbol positions carrying the second RMSI CORESET are symbols 7 to 9, and the symbol positions carrying the second SS / PBCH block are symbols 10 to 13, as shown in FIG. 5.

Alternatively, in the first pattern, the number of symbols included in the M consecutive symbols is fixed and the position in the time domain is fixed. Exemplarily, the positions of M consecutive symbols may be t * (N + M) + N + 1 symbols of a slot to t * (N + M) + N + M symbols, and the M symbols It can carry SS / PBCH blocks, and N symbols located in front of the M symbols and adjacent to the M symbols in the time domain can carry RMSI CORESET. If two DRSs are sent in a slot, the first N consecutive symbols carrying RMSI CORESET precede the M consecutive symbols carrying SS / PBCH block and the second N consecutive CORESET carrying RMSI The symbols are between the first M consecutive symbols carrying the SS / PBCH block and the second M consecutive symbols carrying the SS / PBCH block. When there is an idle symbol between the RMSI CORESET and the corresponding SS / PBCH block, the second system information and other information in the DRS (such as paging, CSI-RS or other downlink signals, etc.) can be used for padding.

Exemplarily, the N consecutive symbols may be referred to as a first symbol group, and the M consecutive symbols may be referred to as a second symbol group.

In an implementation manner, when the network device sends the DRS to the terminal according to the first pattern, it may be implemented as follows:

A1, pad RMSI CORESET to N symbols, and SS / PBCH block to M symbols after N symbols.

A2, referring to FIG. 6A, if the RMSI CORESET occupies N symbols in a slot, the second system information and other information in the DRS and SS / PBCH block use frequency division multiplexing to occupy M symbols. 6B and 6C, if RMSI CORESET occupies n symbols in a slot, where n is an integer less than N, the second system information and other information in the DRS may be on one or more of the following resources Padding: Idle symbols in N symbols, that is, symbols that do not carry RMSI CORESET in N symbols, and idle resource blocks in M symbols, that is, resource blocks that do not carry SS / PBCH blocks in M symbols.

Taking the first pattern shown in FIG. 5 as an example, when a network device sends two DRSs to a terminal according to the first pattern, the two DRSs occupy 14 symbols of a slot, and the RMSI and CORESET in the first DRS occupy Symbols 0 to 2, the PSS, PBCH, SSS, and PBCH in the SS / PBCH block of the first DRS occupy symbols 3 to 6 in sequence. The second system information of the first DRS and other information included in the first DRS are filled in the idle resource blocks in symbols 0 to 2 and / or the idle resource blocks in symbols 3 to 6. The RMSI CORESET of the second DRS occupies symbols 7-9, and the PSS, PBCH, SSS, and PBCH in the SS / PBCH block of the second DRS occupies symbols 10-13 in turn. The second system information of the second DRS and other information included in the second DRS are filled in the idle resource blocks in symbols 7-9, and / or the idle resource blocks in symbols 10-13. RMSI CORESET lasts 3 symbols, that is, the first RMSI CORESET occupies all the symbols in symbols 0 to 2, and the second RMSI CORESET occupies all the symbols in symbols 7 to 9. The resource allocation of the two DRSs can be shown in FIG. RMSI CORESET lasts 2 symbols, that is, the first one is RMSI CORESET occupies symbol 0 and symbol 1 in symbols 0 to 2, the second RMSI CORESET occupies symbol 7 and symbol 8 in symbols 7 to 9, two DRS resources The allocation can be seen in Figure 6B. RMSI CORESET lasts 1 symbol, that is, the first RMSI CORESET occupies symbol 0 in symbols 0 to 2, and the second RMSI CORESET occupies symbol 7 in symbols 7 to 9. The resource allocation of the two DRSs can be shown in FIG. 6C .

The occupancy in the foregoing embodiment means that the corresponding symbol carries corresponding information. Taking the RMSI CORESET occupation symbols 0 to 2 in the first DRS as an example, it means that the symbols 0 to 2 carry the RMSI CORESET in the first DRS.

In the first pattern, when RMSI CORESET occupies all 3 symbols in the first symbol group, there are no idle symbols in the first symbol group to send the second system information and other information included in the DRS. Since the number of resource blocks contained in the 20 MHz bandwidth is greater at low subcarrier intervals, more second system information, and other information included in the DRS, and frequency division multiplexing with SS / PBCH blocks are used in the second symbol group. This approach can be applied to scenarios with low subcarrier spacing. When RMSI CORESET occupies all 1 symbols in the first symbol group, there are 2 free symbols in the first symbol group to send the second system information and other information included in the DRS, that is, symbol 1 and symbol 2, or Symbol 9 and symbol 9. When RMSI CORESET occupies all 1 symbols in the first symbol group, there is an idle symbol in the first symbol group that can send the second system information and other information included in the DRS, for example: symbol 2 in Figure 6B , Or the symbol 9.

The PBCH of the SS / PBCH block in the DRS can carry a time index to indicate the serial number of the current SS / PBCH block. In the above scenario, after detecting the SS / PBCH block, the terminal can obtain symbol-level time synchronization according to the time index it carries in the PBCH. Taking the first pattern shown in Figure 5 as an example, the time index carried in the SS / PBCH block is 0, then the SS / PBCH block is located at symbols 3-6, the PSS is located at symbol 3, and the time index carried in the SS / PBCH block is 1 The SS / PBCH block is located at symbols 10-13, and the PSS is located at symbol 10. Therefore, the terminal can perform cell synchronization according to the symbol position where the PSS is located.

In another possible implementation manner, when the network device sends the DRS to the terminal, the network device may also send the DRS according to the second pattern. In the second pattern, RMSI CORESET occupies N symbols, SS / PBCH block occupies M symbols, and the symbol occupied by SS / PBCH block is immediately after the symbol occupied by RMSI CORESET.

Take a slot consisting of 14 symbols, N is equal to 2, and M is equal to 4, for example, RMSI CORESET lasts 2 symbols, and SS / PBCH block lasts 4 symbols. Then the first RMSI CORESET occupies

symbols

0 and 1, the first SS / PBCH block occupies symbols 2 to 5, the second RMSI CORESET occupies

symbols

6 and 7, and the second SS / PBCH block occupies symbols 8 to 11. For a second pattern, please refer to FIG. 7A. If N is equal to 1, and M is equal to 4, that is, RMSI CORESET lasts for 1 symbol, and SS / PBCH blocks last for 4 symbols, then the first RMSI CORESET takes symbol 0, and the first SS / PBCH blocks take symbols 1 to 4. The two RMSI CORESET blocks occupy the symbol 5 and the second SS / PBCH block blocks occupy the symbols 6-9. The second pattern can be seen in FIG. 7B.

In an implementation manner, when the network device sends the DRS to the terminal according to the second pattern, the method may be implemented as follows:

B1, referring to FIG. 8A or FIG. 8B, RMSI CORESET occupies N symbols, and SS / PBCH block occupies M symbols after N symbols.

B2, the second system information and other information included in the DRS occupy M symbols in a frequency division multiplexing manner.

Taking the second pattern shown in FIG. 7A as an example, when a network device sends two DRSs to a terminal according to the second pattern, the two DRSs occupy 14 symbols of a time slot, and the RMSI and CORESET occupation symbols in the first DRS 0 and symbol 1. The PSS, PBCH, SSS, and PBCH in the SS / PBCH block of the first DRS occupy symbols 2 to 5 in sequence. The second system information of the first DRS and other information included in the first DRS may occupy symbols 2 to 5 in a frequency division multiplexing manner. The RMSI CORESET of the second DRS occupies symbol 6 and symbol 7, and the PSS, PBCH, SSS, and PBCH in the SS / PBCH block of the second DRS occupy symbols 8-11 in this order. The second system information of the second DRS and other information included in the second DRS may occupy symbols 8 to 11 in a frequency division multiplexing manner. For resource allocation of the two DRSs, refer to FIG. 8A.

Taking the second pattern shown in FIG. 7B as an example, when a network device sends two DRSs to a terminal according to the second pattern, the two DRSs occupy 14 symbols of a time slot, and the RMSI CORESET occupation symbol in the first DRS 0, the PSS, PBCH, SSS, and PBCH in the SS / PBCH block of the first DRS occupy symbols 1 to 4 in sequence. The second system information of the first DRS and other information included in the first DRS may occupy symbols 1 to 4 in a frequency division multiplexing manner. The RMSI CORESET of the second DRS occupies symbol 5, and the PSS, PBCH, SSS, and PBCH in the SS / PBCH block of the second DRS occupy symbols 6-9 in turn. The second system information of the second DRS and other information included in the second DRS may occupy symbols 6 to 9 in a frequency division multiplexing manner. For resource allocation of the two DRSs, refer to FIG. 8B.

As shown in Figures 8A and 8B, there will be 2-4 idle symbols in the slot at the end. These idle symbols can be used to send other information in the DRS, such as CSI-RS or other downlink reference signals / control signals / data, etc. .

In one implementation, the PBCH in the SS / PBCH block can carry the number of all symbols carrying RMSI CORESET. That is, the PBCH in the SS / PBCH block can carry the number of symbols occupied by RMSI CORESET. Therefore, the terminal can determine the number of continuous symbols of the RMSI and CORESET through the information carried by the PBCH, thereby determining which of the multiple patterns shown in FIG. 5, FIG. 7A, and FIG. 7B to use for the DRS for transmission.

When the symbol carrying RMSI CORESET and the symbol carrying corresponding SS / PBCH block are continuous in time and the duration of RMSI CORESET is less than 3 symbols, the next 2 to 4 symbols in the slot can be vacated to transmit other downlink signals / data, such as CSI- RS and so on. And the terminal can judge the actual symbol position where the SS / PBCH block is located according to the number of RMSI CORESET continuous symbols in the SS / PBCH block and obtain accurate time synchronization. The PBCH of the SS / PBCH block in the DRS can carry the time index to indicate the serial number of the current SS / PBCH block, so that the terminal can obtain the symbol-level time synchronization after detecting the SS / PBCH block according to the time index carried in the PBCH. For example, when the time index carried in the SS / PBCH block is 0 and the RMSI CORESE continues for 1 symbol, the terminal may determine that the network device uses the pattern shown in FIG. 7B. Therefore, the terminal can determine that the SS / PBCH block is located at symbols 1-4 and the PSS is located at symbol 3. When the time index in the SS / PBCH block is 1 and the RMSI CORESE continues for 1 symbol, the terminal can determine that the network device uses the pattern shown in FIG. 7B. Therefore, the terminal can determine that the SS / PBCH block is located at symbols 6-9, and the PSS is located at symbol 6. Therefore, the terminal can perform cell synchronization according to the symbol position where the PSS is located.

Further, the number of RMSI CORESET continuous symbols corresponding to two SS / PBCH blocks in a slot can be the same.

In another possible implementation manner, if the network device sends a DRS in a slot, when the network device sends the DRS to the terminal, the network device may send the DRS according to the third pattern. Among them, in the third pattern, the N symbols occupied by RMSI CORESET and the M symbols occupied by SS / PBCH block can be referred to FIG. 5, or FIG. 7A, or FIG. 7B. The symbol occupied by an SS / PBCH block is not repeated here. In the third pattern, the second system information and other information in the DRS can occupy other symbols in the slot except the symbol occupied by the RMSI CORESET and the symbol occupied by the SS / PBCH block. The second system information and other information in the DRS are also The M symbols carrying the SS / PBCH block can be occupied in a frequency division multiplexing manner.

In the third pattern, the N symbols occupied by RMSI CORESET and the M symbols occupied by SS / PBCH block are similar to the symbols occupied by the first RMSI CORESET and the symbol occupied by the first SS / PBCH block in the first pattern, that is, N Consecutive symbols and M consecutive symbols contain a fixed number of symbols and a fixed position in the time domain. Taking a slot including 14 symbols as an example, if N = 1, M = 4, the third pattern can be: RMSI CORESET occupies symbol 0. SS / PBCH blocks occupy symbols 3 to 6. The second system information and other information in the DRS occupy symbols 3 to 6 in a frequency division multiplexing manner, and the second system information and other information in the DRS occupy

symbols

1, 2 and 7 to 13, as shown in FIG. 9A. Show. If N = 2 and M = 4, the third pattern may be: RMSI CORESET occupies symbol 0 and symbol 1. SS / PBCH blocks occupy symbols 3 to 6. The second system information and other information in the DRS occupy symbols 3-6 using frequency division multiplexing, and the second system information and other information in the DRS occupy symbols 2 and 7-13, as shown in FIG. 9B. If N = 3 and M = 4, the third pattern may be: RMSI CORESET occupies symbols 0 ~ 2. SS / PBCH blocks occupy symbols 3 to 6. The second system information and other information in the DRS occupy symbols 3 to 6 in a frequency division multiplexing manner, and the second system information and other information in the DRS occupy symbols 7 to 13 as shown in FIG. 9C.

It should be noted that this is only an exemplary illustration. The time domain position of the symbols occupied by SS / PBCH and bloK may not be fixed to the symbols 3-6 in the slot, or may be fixed to 9-12. Therefore, when the CSI-RS or other downlink reference signals need to be transmitted at symbols 3-6, the SS / PBCH block can be transmitted at other positions in the slot, such as symbols 9-12. The starting position of RMSI CORESET can be fixed to the symbol 0, but the number of continuous symbols can be dynamically adjusted.

The N symbols occupied by RMSI CORESET and the M symbols occupied by SS / PBCH block in the third pattern are similar to the symbols occupied by the first RMSI CORESET and the symbol occupied by the first SS / PBCH block in the second pattern, that is, N Consecutive symbols and M consecutive symbols contain a fixed number of symbols and a fixed position in the time domain. Taking a slot including 14 symbols as an example, if N = 1, M = 4, the third pattern can be: RMSI CORESET occupies symbol 0. SS / PBCH blocks occupy symbols 1 to 4. The second system information and other information in the DRS occupy symbols 1 to 4 in a frequency division multiplexing manner, and the second system information and other information in the DRS occupy symbols 5 to 13, as shown in FIG. 9D.

In an implementation manner, when the network device sends the DRS to the terminal according to the third pattern, it may be implemented in the following manner, referring to FIGS. 9A to 9D:

D1, RMSI CORESET occupies N symbols, SS / PBCH block occupies M symbols.

D2, the second system information and other information occupy one or more of the following resources: idle symbols in time slots, that is, symbols that do not carry RMSI CORESET and SS / PBCH blocks in time slots, and M symbols that carry SS / PBCH blocks The idle resource block in is the resource block that does not carry the SS / PBCH block in the M symbols.

In one implementation, the PBCH in the SS / PBCH block can carry the number of all symbols carrying RMSI CORESET. That is, the PBCH in the SS / PBCH block can carry the number of symbols occupied by RMSI CORESET. Therefore, the terminal can determine the number of continuous symbols of the RMSI and CORESET through the information carried by the PBCH, thereby determining which of the multiple patterns shown in FIG. 9A to FIG. 9D is used by the DRS for transmission.

Since the number of RBs contained in the 20 MHz bandwidth is smaller at high subcarrier intervals, more symbols are needed to send the second system information and other information in the DRS. In the implementation of sending a DRS in a slot, when the RMSI CORESET continues for 3 symbols, the slot has 7 separate symbols that can send the second system information and other information in the DRS. When RMSI CORESET lasts 2 symbols, the slot has 8 separate symbols that can send the second system information and other information in the DRS. When the RMSI CORESET continues for 1 symbol, the slot has 9 separate symbols that can send the second system information and other information in the DRS. Therefore, this implementation can be applied to the scenario with large subcarrier spacing.

In the above implementation, when a network device sends multiple DRSs in multiple slots, the terminal can obtain the symbol-level time synchronization in the slot according to the time index carried in the PBCH after detecting the SS / PBCH block. For example, if the time domain position of the symbol occupied by SS / PBCH / blok is fixed at symbols 3-6, and the time index carried in the SS / PBCH block is 0, then the PSS of the SS / PBCH block is located at symbol 3 of slot 0. The time index in the SS / PBCH block is 1. The PSS of the SS / PBCH block is located at the symbol 3 of slot 1. Therefore, the terminal can perform cell synchronization according to the slot position of the SS / PBCH block and the symbol position where the PSS is located.

In another possible implementation manner, if the network device sends three DRS in two slots, when the network device sends the DRS to the terminal, the network device may send the DRS according to the fourth pattern. The fourth pattern can be in units of two time slots, where the second DRS can immediately follow the first DRS, the third DRS can immediately follow the second DRS, and when the second DRS When the occupied symbols span time slots, the second system information of the second DRS may all be in the same time slot. When the second system information of the second DRS and the SS / PBCH block of the second DRS are in two time slots, the other information in the second DRS can be used to fill the SS / PBCH block carrying the second DRS. Or, the SS / PBCH block can also be repeated to fill the M symbol bandwidth of the SS / PBCH block carrying the second DRS.

Take a slot including 14 symbols, N equals 3, and M equals 4 as an example. As shown in FIG. 10, the fourth pattern can be: the first DRS can occupy symbols 0 to 8 of slot 0, and the second DRS can occupy Symbols 9 to 13 of slot 0 and symbols 0 to 3 of slot 1, the third DRS can occupy symbols 4 to 12 of slot 1. Among the symbols 0 to 8 of slot 0, the RMSI CORESET of the first DRS occupies symbols 0 to 2 of slot 0, the SS / PBCH block of the first DRS occupies symbols 3 to 6 of slot 0, and the first DRS The second system information and other information of the first occupy the symbols 3 to 6 of the slot 0 in a frequency division multiplexing manner, and the second system information and other information of the first DRS also occupy the

symbols

7 and 8 of the slot 0. In symbols 9 to 13 of slot 0 and symbols 0 to 3 of slot 1, the RMSI CORESET of the second DRS occupies symbols 9 to 11 of slot 0, and the SS / PBCH block of the second DRS occupies symbols 0 to 1 of slot 1 3. The second system information of the second DRS occupies

symbols

12 and 13 of slot 0, and other information of the second DRS can occupy symbols 0 to 3 and / or slot 0 of slot 1 by using frequency division multiplexing.

Symbols

12 and 13.

In an implementation manner, when the network device sends the DRS to the terminal according to the fourth pattern, it may be implemented as follows, refer to FIG. 10:

E1, the first DRS occupies the first P symbols of the first slot, where P is an integer greater than or equal to N + M.

E2, the RMSI CORESET of the second DRS and the second system information occupy the idle symbols of the first time slot, that is, the symbols of the first DRS are not carried in the first time slot. The SS / PBCH block of the second DRS occupies the first M symbols of the second slot.

Among them, the first M symbols of slot 1 do not carry the SS / PBCH block free resource block of the second DRS, which can be filled with other information in the second DRS, or the SS / PBCH block can be repeated to fill. .

E3, the third DRS occupies the symbols following the first M symbols of the second slot.

In a possible implementation manner, the PBCH in the SS / PBCH block can indicate the number of continuous symbols of the RMSI CORESET and the slot in which it is located. Among them, the number of continuous symbols of the RMSI CORESET can be set to be optional. In this case, it is not necessary to indicate the number of continuous symbols of RMSI CORESET.

The second system information of the second DRS may also occupy the first M symbols of the second time slot in a frequency division multiplexing manner. In this case, RMSI CORESET can indicate whether there is second system information to perform frequency division multiplexing with the SS / PBCH block. When the second system information is frequency-division multiplexed with the SS / PBCH block, the modulation and coding strategy (MCS), modulation method, etc. of the second system information frequency-division multiplexed with the SS / PBCH block The transmission parameters can be the same as the full symbol RMSI PDSCH. Taking Figure 10 as an example, if the second system information of the second DRS occupies

symbols

12 and 13 of slot 0, and uses the SS / PBCH block multiplexing method to occupy symbols 0 to 3 of slot 1, RMSI CORESET may indicate that the second system information is frequency-division multiplexed with the SS / PBCH block. Therefore, when the terminal device demodulates the second system information carried on the symbols 0 to 3 of slot 1, transmission parameters such as MCS and modulation method used when demodulating the complete second system information can be adopted, thereby realizing time span. Slot scheduling second system information. The duration of the second system information that is frequency-division multiplexed with the SS / PBCH block can also be indicated in RMSI CORESET, such as lasting 1, 2 or 3 or 4 symbols. Within the continuous symbol, there may be only the second system information and the SS / PBCH block multiplexing, that is, the two occupy the entire bandwidth.

If the second system information is not frequency-division multiplexed with the SS / PBCH block, that is, when the second system information is all carried in

symbols

12 and 13 of slot0, other information in DRS can be used to fill the symbols 0 to 3 of slot1 Alternatively, the SS / PBCH block can also be repeated to fill the bandwidth of the symbols 0 to 3 of slot 1. As shown in FIG. 10, there will be one idle symbol at the end of the slot. This idle symbol can be used to send other information in the DRS, such as CSI-RS or other downlink reference signals / control signals / data and so on.

In another possible implementation manner, if the network device sends three DRSs in one slot, the DRS may be sent according to the fifth pattern. In the fifth pattern, the second DRS can be immediately after the first DRS, and the third DRS can be immediately after the second DRS. Each DRS occupies M symbols, and the SS / PBCH block, RMSI CORESET, and second system information of the DRS are carried on the M symbols in a frequency division multiplexed manner.

Take a slot consisting of 14 symbols, and M equals 4 as an example. As shown in Figure 11, the fifth pattern can be: the first DRS can occupy symbols 0 to 3, the second DRS can occupy symbols 4 to 7, and the third Each DRS can occupy symbols 8-11. Among them, the SS / PBCH block, RMSI CORESET, second system information, and other information of the first DRS occupy symbols 0 to 3 in a frequency division multiplexed manner. The SS / PBCH block, RMSI, CORESET, second system information, and other information of the second DRS occupy symbols 4 to 7 in a frequency division multiplexed manner. The SS / PBCH block, RMSI, CORESET, second system information, and other information of the third DRS occupy symbols 8-11 in a frequency division multiplexed manner.

In an implementation manner, when a network device sends a DRS to a terminal according to the fifth pattern, it may be implemented in the following manner, referring to FIG. 11:

F1, the SS / PBCH block, RMSI CORESET, the second system information, and other information of the first DRS occupy the first M symbols of the time slot in a frequency division multiplexing manner.

F2, the SS / PBCH block, RMSI, CORESET of the second DRS, and the second system information and other information occupy the M symbols following the first DRS in a frequency division multiplexed manner.

F3, the SS / PBCH block, RMSI, CORESET of the third DRS, and the second system information and other information occupy the M symbols behind the second DRS in a frequency division multiplexing manner.

In scenarios with large subcarrier spacing, such as 60kHz subcarrier spacing, the number of RBs contained in the 20MHz bandwidth is smaller, so there may be only RMSI CORESET and SS / PBCH block frequency division multiplexing. At this time, the corresponding second system information and Other information is sent in subsequent slots.

A terminal operating in an unlicensed frequency band (unlicensed band) can detect whether the channel is free and access the channel for work without authorization. In order to ensure coexistence with other terminals operating in unlicensed frequency bands, a listen-before-talk (LBT) channel contention access mechanism may be adopted. Before LBT, the terminal first determines the back-off priority based on the importance of the data to be sent and the data size, and randomly selects a back-off number based on the priority. The back-off number is the number of time slots that the terminal needs to wait when the listening channel is idle. For example, when the backoff number is 7, the terminal needs to continuously listen for 7 timeslots when the LBT is idle in order to send data. After the terminal performs LBT, it may not pass before the first symbol of a time slot, so a time offset may occur. If the terminal passes LBT and passes before the symbol 4 of the time slot, a symbol level of 4 symbols is generated. Offset. Based on this, the embodiment of the present application further provides another DRS sending method. Referring to FIG. 12, the method includes:

S1201, the network device listens to the LBT and then accesses the channel.

S1202. The network device sends one or more DRSs to the terminal, where any one of the DRSs is carried on consecutive symbols.

Exemplarily, the DRS may include a synchronization signal, control information, and the control information is used to indicate a time-frequency resource where the first system information is located, where the first system information is indicated by the main system information in the synchronization signal block. System information, the synchronization signal block and control information are carried at predetermined positions in the continuous symbols.

Among them, the synchronization signal may be SS / PBCH block. The first system information may be RMSI PDSCH. The control information can be RMSI CORESET.

In some other implementation manners, the DRS may further include second system information. The second system information may include RMSI PDSCH and OSI.

In other embodiments, the DRS may further include other information, such as paging, CSI-RS, or other downlink signals.

S1203: The terminal receives one or more of the DRSs sent by a network device. The terminal may receive the DRS at a preset position.

Manner 1: The DRS may be sent using a sixth pattern.

In one example, the sixth pattern may occupy M symbols in a frequency division multiplexing manner for the SS / PBCH block and RMSI CORESET. The second system information and other information occupy the symbols following the M symbols in a time division multiplexed manner. When the network device sends the DRS according to the sixth pattern, it can be implemented in the following manner: SS / PBCH block and RMSI CORESET use frequency division multiplexing to occupy M symbols starting from the symbols to be transmitted. The second system information and other information occupy the symbols following the M symbols in a time division multiplexed manner.

The symbol to be sent may be determined according to the LBT result, and there is a time offset between the symbol to be sent and the first symbol of the slot. For example, if the network device passes LBT before the symbol 4, the symbol to be sent may be the symbol 4. The time offset may be carried in the synchronization signal, or the time offset may also be carried in the control information.

SS / PBCH block and RMSI CORESET can use the frequency division multiplexing method to occupy the entire bandwidth of N symbols in the frequency domain, and SS / PBCH block and RMSI CORESET are located in the same time unit in the time domain and are continuous N symbols. The second system information can be sent in a time division multiplexed manner with SS / PBCH block and RMSI CORESET. Other information in the DRS can be sent in a frequency division multiplexed manner with SS / PBCH block and RMSI CORESET, or can be sent in frequency division multiplexed or time division multiplexed manner with the second system information.

Further, when the network device sends the second system information, if the number of symbols remaining in the slot after sending SS / PBCH block and RMSI CORESET is not less than T, the second system information occupies the M symbols T symbols. That is, if the network device has sufficient symbols remaining in the slot after sending SS / PBCH block and RMSI CORESET, the second system information may be sent after SS / PBCH block and RMSI CORESET, as shown in FIG. 13A. If after the SS / PBCH block and RMSI CORESET are sent, the number of symbols remaining in the slot is less than T, the second system information occupies P consecutive symbols at any position in other slots. It should be noted that P can be greater than T, smaller than T, or wait for T. The value of P can be determined according to parameters such as the resource configuration of other time slots and the time interval between other time slots and this time slot. That is, if the network device has insufficient symbols remaining in the slot after sending SS / PBCH block and RMSI CORESET, the second system information can be sent in other slots, such as four consecutive symbols in one slot, as shown in Figure 13B. Show.

In the first method above, RMSI CORESET and SS / PBCH block use the same time unit, and RMSI CORESET and SS / PBCH block also last N symbols. RMSI CORESET and SS / PBCH block can slide within the slot according to the LBT result. Compared with RMSI CORESET and SS / PBCH blocks can only be sent at fixed locations. Network devices need to wait for a fixed position to send RMSI CORESET and SS / PBCH blocks. Method 1 sends RMSI CORESET and SS / PBCH blocks in the time domain. More flexible, so that RMSI CORESET and SS / PBCH block can be sent when LBT passes, there is no need to wait to reach a fixed position, which can reduce communication delay to a certain extent. And, because the current RMSI CORESET may not support cross-slot scheduling system information, the first method is to send the second system information in the next slot completely when the remaining symbols in the current slot are insufficient. Time slot scheduling system information causes a problem that the second system information cannot be accurately demodulated.

Manner 2: The any DRS may be sent using a seventh pattern. In the seventh pattern, the N symbols occupied by the synchronization signal block are located behind the M symbols occupied by the control information, and N and M are integers greater than 0. Alternatively, in the seventh pattern, the N symbols occupied by the synchronization signal block are located before the M symbols occupied by the control information.

The DRS includes at least SS / PBCH block and RMSI CORESET, and the SS / PBCH block and RMSI CORESET cycle occupy the continuous symbols. In a slot, one or two DRSs can be sent (different according to the start symbol position when sending). Further, when the DRS is transmitted using the seventh pattern, the N symbols occupied by the SS / PBCH block of the DRS are located behind the M symbols occupied by the RMSI CORESET of the DRS. Alternatively, the N symbols occupied by the SS / PBCH block of the DRS are located before the M symbols occupied by the RMSI CORESET of the DRS.

In one example, the application also provides two seventh patterns. Referring to the pattern shown in FIG. 14A, in a slot, a maximum of two DRSs can be included according to the start position (possibly caused by LBT) when transmitting. The structure of the DRS that may be sent includes the following situations:

DRS 1: "Symbol 0-5", where RMSI CORESET occupies two symbols "0" and "1", SS / PBCH block occupies four symbols "2-5", or,

DRS 2: Symbol "2-7", where SS / PBCH block takes four symbols "2-5", RMSI CORESET takes two symbols "6" and "7", or,

DRS 3: symbol "6-11", where RMSI CORESET occupies two symbols "6" and "7", SS / PBCH block occupies symbol "8-11", or,

DRS 4: Symbol "8-13", of which SS / PBCH block takes four symbols "8-11" and RMSI CORESET takes two symbols "12" and "13".

Among them, the actual time domain position of RMSI CORESET can be indicated in the PBCH of the SS / PBCH block.

Referring to the pattern shown in FIG. 14B, in one slot, a maximum of two DRSs can be included according to the start position (possibly caused by LBT) when transmitting. The structure of the DRS that may be sent includes the following situations:

DRS 5: “Symbols 0-6”, where SS / PBCH blocks occupy four symbols “0-3” and RMSI CORESET occupy three symbols “4-6”; or,

DRS 6: "Symbols 4-10", where RMSI CORESET occupies three symbols "4-6", and SS / PBCH blocks occupies four symbols "7-10"; or,

DRS 7: "Symbol 7-13", of which SS / PBCH CORESET occupies four symbols "7-10", and SS / PBCH block occupies three symbols "11-13".

Referring to the pattern shown in FIG. 14C, in one slot, a maximum of two DRSs can be included according to the start position (possibly caused by LBT) when transmitting. The structure of the DRS that may be sent includes the following situations:

DRS 8: "Symbols 0-6", where SS / PBCH blocks occupy four symbols "3-6" and RMSI CORESET occupy three symbols "0-2"; or,

DRS 9: "Symbols 3-9", where RMSI CORESET occupies three symbols "3-6" and SS / PBCH blocks occupies four symbols "7-9"; or,

DRS 10: "Symbol 7-13", of which SS / PBCH CORESET occupies four symbols "10-13" and SS / PBCH block occupies three symbols "7-9".

Optionally, in the pattern of the same time slot, if there are remaining symbols after sending one or more DRSs according to the starting position, it can be used to send second system information and / or other information, etc., such as RMSI PDCCH . (See the description of FIGS. 15A to 15C).

An example is that the N symbols occupied by the synchronization signal block are located before the M symbols occupied by the control information, and the P symbols occupied by the second system information are located behind the M symbols occupied by the control information, The P is an integer greater than 0. See FIGS. 15A to 15C.

Further, if the number of symbols following the M symbols occupied by the control information is less than P, the second system information of the any one DRS occupies multiple consecutive symbols in other time slots, The multiple consecutive symbols occupied by the second system information are in the same time slot. See FIGS. 15A to 15C.

It should be noted that a general network device can send one or more DRSs in one time slot, for example, DRS1 and DRS3 in FIG. 14A are continuously sent before, or DRS2 and DRS4 are continuously sent. In some scenarios, the network device sends only one DRS in a time slot, and transmits other information when there are remaining symbols in the time slot. Depending on the moment when LBT is successful, the network device may transmit RMSI CORESET or SS / PBCH block first.

As shown in FIG. 15A, the network device uses the pattern shown in FIG. 14A. When LBT is successful before symbol 0, the network device transmits RMSI CORESET at symbols 0 to 1, and carries SS / PBCH blocks at symbols 2-5 (that is, sends DRS1). . Optionally, the network device may send the second system information, such as symbols 6-7, in the remaining symbols after the SS / PBCH block.

When LBT is successful before symbol 2 (preferably after symbol 0 and before symbol 2), the network device can transmit SS / PBCH blocks in symbols 2-5 and RMSI CORESET (that is, send DRS2) in symbols 6-7. Alternatively, the network device may send the second system information, such as symbols 8-13, at the symbol after RMSI CORESET.

When LBT succeeds before symbol 6 (preferably after symbol 2 and before symbol 6), the network device can transmit RMSI CORESET at symbols 6-7 and SS / PBCH block (that is, send DRS3) at symbols 8-11. Alternatively, the network device may send the second system information, such as symbols 12-13, at the symbol after the SS / PBCH block.

When LBT succeeds before symbol 8 (preferably after symbol 6 and before symbol 8), the network device can transmit SS / PBCH blocks at symbols 8-11 and RMSI CORESET (that is, send DRS3) at symbols 12-13. When there are no remaining symbols in the l slots, the network device can perform second system information transmission in other slots. When there are no remaining symbols in the same slot, the network device can transmit the second system information in any slot behind the slot. The second system information can occupy multiple consecutive symbols at any position in other time slots, such as the next time slot. The symbols 2 to 4. It should be noted that the symbols occupied by the second system information are in the same slot.

As shown in FIG. 15B, the network device adopts the pattern shown in FIG. 14B. When LBT is successful before symbol 0, the network device transmits SS / PBCH blocks at symbols 0 to 3, and carries RMSI CORESET at symbols 4-6 (that is, sends DRS5). . Optionally, the network device may send the second system information, such as symbols 7-8, in the remaining symbols after RMSI CORESET.

When LBT is successful before symbol 4 (preferably after symbol 0 and before symbol 4), the network device can transmit RMSI CORESET at symbols 4-6 and SS / PBCH block (that is, send DRS6) at symbols 7-10. Alternatively, the network device may send the second system information, such as symbols 11-12, at the symbol after the SS / PBCH block.

When LBT succeeds before symbol 7 (preferably after symbol 4 and before symbol 7), the network device can transmit SS / PBCH block in symbols 7-10 and RMSI CORESET (that is, send DRS7) in symbols 11-13. When there are no remaining symbols in the l slots, the network device can perform second system information transmission in other slots. When there are no remaining symbols in the same slot, the network device can transmit the second system information in any slot behind the slot. The second system information can occupy multiple consecutive symbols at any position in other time slots, such as the next time slot. The symbols 2 to 4. It should be noted that the symbols occupied by the second system information are in the same slot.

As shown in FIG. 15C, the network device adopts the pattern shown in FIG. 14C. When LBT is successful before symbol 0, the network device transmits RMSI CORESET at symbols 0 to 2, and carries SS / PBCH blocks at symbols 3-6, (that is, sends DRS8 ). Optionally, the network device may send the second system information, such as symbols 8-9, in the remaining symbols after the SS / PBCH block.

When LBT is successful before symbol 3 (preferably after symbol 2 and before symbol 6), the network device can transmit SS / PBCH block at symbol 3-6 and RMSI CORESET (that is, send DRS9) at symbol 7-9. Alternatively, the network device may send the second system information, such as symbols 10-11, at the symbol after RMSI CORESET.

When LBT is successful before symbol 7, the network device can transmit RMSI CORESET at symbols 7-9 and SS / PBCH block (that is, send DRS10) at symbols 10-13. At this time, there are no symbols left in the 1 slot. The second system information transmission is performed in other slots. When there are no remaining symbols in the same slot, the network device can transmit the second system information in any slot behind the slot. The second system information can occupy multiple consecutive symbols at any position in other time slots, such as the next time slot. The symbols 2 to 4. It should be noted that the symbols occupied by the second system information are in the same slot.

In the above second method, when sending a DRS, the network device may first determine the location of the SS / PBCH block, and when sending the RMSI CORESET, it may be sent in front of the SS / PBCH block, or it may be sent after the SS / PBCH block. Compared with RMSI, CORESET can only be sent in front of the SS / PBCH block. In the second method, you can choose to send in front of the SS / PBCH block or the SS / PBCH block according to the position of the symbol to be sent. CORESET and SS / PBCH block flexibility, and can provide resource utilization, can also reduce the communication delay to a certain extent. And, because the current RMSI CORESET may not support cross-slot scheduling system information, the first method is to send the second system information in the next slot completely when the remaining symbols in the current slot are insufficient. Time slot scheduling system information causes a problem that the second system information cannot be accurately demodulated.

In the first manner and the second manner, if the remaining resources in the current slot are insufficient, and the second system information is completely transmitted in the next slot, other downlink signals in the DRS may be used to fill up for carrying the synchronization. The bandwidth of the symbol of the signal, that is, other downlink signals in the DRS are filled into the idle resource blocks in the symbol used to carry the synchronization signal. Alternatively, the bandwidth of the symbol used to carry the synchronization signal may be filled in the repeated SS / PBCH block, that is, the repeated SS / PBCH block is filled into the idle resource block in the symbol used to carry the synchronization signal.

Based on the same inventive concept as the method embodiment, an embodiment of the present application provides a communication device. The structure of the communication device may be as shown in FIG. 16, and includes a processing unit 1601 and a transceiver unit 1602.

In an implementation manner, the apparatus may be specifically configured to implement the method performed by the network device in the embodiments described in FIG. 4 to FIG. 15C. The device may be the network device itself, or a chip or chipset in the network device or A part of a chip used to perform related method functions. Wherein, the processing unit may be configured to listen to the LBT first and then access the channel. The sending unit may be configured to send one or more discovery reference signals DRS to the terminal, where any one of the DRSs is carried on consecutive symbols.

The processing unit and the transceiver unit may also be used to perform other steps corresponding to the network devices in the foregoing method embodiments. For details, refer to the foregoing method embodiments, and details are not described herein again.

In another implementation manner, the device may be specifically configured to implement the method performed by the terminal in the embodiments described in FIG. 4 to FIG. 15C. The device may be the terminal itself, or a chip or chipset or chip in the terminal. Used to perform part of a related method function. The transceiver unit may be used to receive one or more discovery reference signals DRS from the network device under the control of the processing unit, and any one of the DRSs is carried on consecutive symbols.

The processing unit and the transceiver unit may also be used to perform other steps corresponding to the terminal in the foregoing method embodiments. For details, refer to the foregoing method embodiments, and details are not described herein again.

The division of the modules in the embodiments of the present application is schematic and is only a logical function division. In actual implementation, there may be another division manner. In addition, the functional modules in the embodiments of the present application may be integrated into one process. In the device, it can also exist separately physically, or two or more modules can be integrated into one module. The above integrated modules may be implemented in the form of hardware or software functional modules.

When the integrated module can be implemented in the form of hardware, the communication device may be as shown in FIG. 17, and the communication device may be a network device or a chip in the network device. The communication device may also be a terminal or a chip in the terminal. The communication device may include a processor 1701, a communication interface 1702, and a memory 1703. The processing unit 1601 may be a processor 1701. The sending unit 1602 may be a communication interface 1702.

The processor 1701 may be a central processing module (CPU), or a digital processing module. The communication interface 1702 may be a transceiver, an interface circuit such as a transceiver circuit, or a transceiver chip. The communication device further includes a memory 1703 for storing a program executed by the processor 1702. The memory 1703 may be a non-volatile memory, such as a hard disk (HDD) or a solid-state drive (SSD), etc., or a volatile memory, such as a random access memory (random -access memory, RAM). The memory 1703 is, but is not limited to, any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer.

The processor 1701 is configured to execute the program code stored in the memory 1703, and is specifically configured to perform an action of the processing unit 1601, which is not described herein again in this application.

The specific connection medium between the communication interface 1701, the processor 1702, and the memory 1703 is not limited in the embodiment of the present application. In the embodiment of the present application, the memory 1703, the processor 1702, and the communication interface 1701 are connected by a bus 1704 in FIG. 17. The bus is indicated by a thick line in FIG. 17. The connection modes between other components are only schematically illustrated. It is not limited. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is used in FIG. 17, but it does not mean that there is only one bus or one type of bus.

Those skilled in the art should understand that the embodiments of the present application may be provided as a method, a system, or a computer program product. Therefore, this application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, this application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

This application is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present application. It should be understood that each process and / or block in the flowcharts and / or block diagrams, and combinations of processes and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to produce a machine, so that the instructions generated by the processor of the computer or other programmable data processing device are used to generate instructions Means for implementing the functions specified in one or more flowcharts and / or one or more blocks of the block diagrams.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to work in a particular manner such that the instructions stored in the computer-readable memory produce a manufactured article including an instruction device, the instructions The device implements the functions specified in one or more flowcharts and / or one or more blocks of the block diagram.

These computer program instructions can also be loaded on a computer or other programmable data processing device, so that a series of steps can be performed on the computer or other programmable device to produce a computer-implemented process, which can be executed on the computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more flowcharts and / or one or more blocks of the block diagrams.

Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. In this way, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these changes and variations.

Claims

A method for transmitting a discovery reference signal, which comprises:

The network device listens to the LBT and then accesses the channel;

The network device sends one or more discovery reference signals DRS to the terminal, where any one of the DRSs is carried on consecutive symbols.
The method according to claim 1, wherein the DRS includes at least a synchronization signal block and control information, the control information is used to indicate a time-frequency resource where the first system information is located, and the first system information is all The system information indicated by the main system information in the synchronization signal block, and the synchronization signal block and the control information are carried at predetermined positions in the continuous symbols.
The method according to claim 2, wherein any one of the DRSs is transmitted using a first pattern, and in the first pattern, the N symbols occupied by the synchronization signal block are located in the M occupied by the control information. After the symbol, the N and M are integers greater than 0.
The method according to claim 2, wherein any one of the DRSs is transmitted using a first pattern, and in the first pattern, the N symbols occupied by the synchronization signal block are located in the M occupied by the control information. In front of the symbol.
The method according to claim 1, wherein the DRS comprises a synchronization signal block, control information, and second system information, and the control information is used to indicate a time-frequency resource where the first system information is located, and the first The system information is system information indicated by main system information in the synchronization signal block, and the second system information includes at least the first system information.
The method according to claim 5, wherein any one of the DRSs is transmitted by using a second pattern, and in the second pattern, the N symbols occupied by the synchronization signal block are located at M number occupied by the control information. After the symbols, the P symbols occupied by the second system information are located after the N symbols occupied by the synchronization signal block, and the N, M, and P are integers greater than 0.
The method according to claim 6, wherein any one of the DRSs is transmitted using a second pattern, and in the second pattern, the N symbols occupied by the synchronization signal block are located at M number occupied by the control information. In front of the symbols, the P symbols occupied by the second system information are located after the M symbols occupied by the control information, and P is an integer greater than 0.
The method according to claim 6 or 7, wherein if the number of symbols following M symbols occupied by the control information is less than P in the same time slot, the second system information of any one DRS Multiple consecutive symbols in other time slots are occupied, and multiple consecutive symbols occupied by the second system information of any one DRS are in the same time slot.
A method for transmitting a discovery reference signal, which comprises:

The terminal receives one or more discovery reference signals DRS from a network device, where any one of the DRSs is carried on consecutive symbols.
The method according to claim 9, wherein the DRS includes at least a synchronization signal block and control information, the control information is used to indicate a time-frequency resource where the first system information is located, and the first system information is all The system information indicated by the main system information in the synchronization signal block, and the synchronization signal block and the control information are carried at predetermined positions in the continuous symbols.
The method according to claim 10, wherein any one of the DRSs is transmitted using a first pattern, and the N symbols occupied by the synchronization signal block in the first pattern are located in M number occupied by the control information After the symbol, the N and M are integers greater than 0.
The method according to claim 10, wherein any one of the DRSs is transmitted using a first pattern, and the N symbols occupied by the synchronization signal block in the first pattern are located in M number occupied by the control information In front of the symbol.
The method according to claim 9, wherein the DRS comprises a synchronization signal block, control information, and second system information, and the control information is used to indicate a time-frequency resource where the first system information is located, and the first The system information is system information indicated by main system information in the synchronization signal block, and the second system information includes at least the first system information.
The method according to claim 13, wherein any one of the DRSs is transmitted using a second pattern, and in the second pattern, the N symbols occupied by the synchronization signal block are located at M number occupied by the control information. After the symbols, the P symbols occupied by the second system information are located after the N symbols occupied by the synchronization signal block, and the N, M, and P are integers greater than 0.
The method according to claim 14, wherein any one of the DRSs is transmitted by using a second pattern, and in the second pattern, the N symbols occupied by the synchronization signal block are located at M number occupied by the control information. In front of the symbols, the P symbols occupied by the second system information are located after the M symbols occupied by the control information, and P is an integer greater than 0.
The method according to claim 14 or 15, wherein if the number of symbols following the M symbols occupied by the control information is less than P in the same time slot, the second system information of any one DRS Multiple consecutive symbols in other time slots are occupied, and multiple consecutive symbols occupied by the second system information of any one DRS are in the same time slot.
A device for transmitting a discovery reference signal, comprising:

A processing unit, configured to listen to the LBT first and then access the channel;

The transceiver unit is configured to send one or more discovery reference signals DRS to the terminal, where any one of the DRSs is carried on consecutive symbols.
The apparatus according to claim 17, wherein the DRS includes at least a synchronization signal block and control information, the control information is used to indicate a time-frequency resource where the first system information is located, and the first system information is all The system information indicated by the main system information in the synchronization signal block, and the synchronization signal block and the control information are carried at predetermined positions in the continuous symbols.
The apparatus according to claim 18, wherein any one of the DRSs is transmitted using a first pattern, and in the first pattern, N symbols occupied by the synchronization signal block are located in M numbers occupied by the control information. After the symbol, the N and M are integers greater than 0.
The apparatus according to claim 18, wherein any one of the DRSs is transmitted using a first pattern, and in the first pattern, N symbols occupied by the synchronization signal block are located in M numbers occupied by the control information. In front of the symbol.
The apparatus according to claim 17, wherein the DRS includes a synchronization signal block, control information, and second system information, and the control information is used to indicate a time-frequency resource where the first system information is located, and the first The system information is system information indicated by main system information in the synchronization signal block, and the second system information includes at least the first system information.
The apparatus according to claim 21, wherein the any one DRS is transmitted by using a second pattern, and in the second pattern, the N symbols occupied by the synchronization signal block are located at M number occupied by the control information. After the symbols, the P symbols occupied by the second system information are located after the N symbols occupied by the synchronization signal block, and the N, M, and P are integers greater than 0.
The device according to claim 22, wherein any one of the DRSs is transmitted using a second pattern, and in the second pattern, the N symbols occupied by the synchronization signal block are located at M number occupied by the control information. In front of the symbols, the P symbols occupied by the second system information are located after the M symbols occupied by the control information, and P is an integer greater than 0.
The device according to claim 22 or 23, wherein if the number of symbols following M symbols occupied by the control information is less than P in the same time slot, the second system information of any one DRS Multiple consecutive symbols in other time slots are occupied, and multiple consecutive symbols occupied by the second system information of any one DRS are in the same time slot.
A discovery reference signal transmitting device, comprising: a processing unit and a transceiver unit;

The transceiver unit is configured to receive one or more discovery reference signals DRS from a network device under the control of the processing unit, where any one of the DRSs is carried on consecutive symbols.
The apparatus according to claim 25, wherein the DRS includes at least a synchronization signal block and control information, the control information is used to indicate a time-frequency resource where the first system information is located, and the first system information is all The system information indicated by the main system information in the synchronization signal block, and the synchronization signal block and the control information are carried at predetermined positions in the continuous symbols.
The apparatus according to claim 26, wherein the any one DRS is transmitted using a first pattern, and in the first pattern, N symbols occupied by the synchronization signal block are located in M numbers occupied by the control information. After the symbol, the N and M are integers greater than 0.
The apparatus according to claim 26, wherein the any one DRS is transmitted using a first pattern, and in the first pattern, N symbols occupied by the synchronization signal block are located in M numbers occupied by the control information. In front of the symbol.
The apparatus according to claim 25, wherein the DRS includes a synchronization signal block, control information, and second system information, and the control information is used to indicate a time-frequency resource where the first system information is located, and the first The system information is system information indicated by main system information in the synchronization signal block, and the second system information includes at least the first system information.
The apparatus according to claim 29, wherein any one of the DRSs is transmitted by using a second pattern, and the N symbols occupied by the synchronization signal block in the second pattern are located at M number occupied by the control information After the symbols, the P symbols occupied by the second system information are located after the N symbols occupied by the synchronization signal block, and the N, M, and P are integers greater than 0.
The device according to claim 30, wherein any one of the DRSs is transmitted by using a second pattern, and the N symbols occupied by the synchronization signal block in the second pattern are located at M number occupied by the control information In front of the symbols, the P symbols occupied by the second system information are located after the M symbols occupied by the control information, and P is an integer greater than 0.
The device according to claim 30 or 31, wherein if the number of symbols after M symbols occupied by the control information is less than P in the same time slot, the second system information of any one DRS Multiple consecutive symbols in other time slots are occupied, and multiple consecutive symbols occupied by the second system information of any one DRS are in the same time slot.
A computer-readable storage medium, characterized in that a program is stored in the computer-readable storage medium, and when read and executed by one or more processors, the program according to any one of claims 1 to 8 can be implemented. The method described above; or, when the program is read and executed by one or more processors, the method according to any one of claims 9 to 16 can be implemented.
A computer program product containing instructions, wherein when the computer program product is run on a computer, the computer is caused to execute the method according to any one of claims 1-8, or the computer is caused to execute the method according to claim 9- The method of any one of 16.