WO2020056622A1

WO2020056622A1 - Method for reading image check coefficient, flash memory controller, system and storage medium

Info

Publication number: WO2020056622A1
Application number: PCT/CN2018/106472
Authority: WO
Inventors: 周俊; 陈德坤
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2018-09-19
Filing date: 2018-09-19
Publication date: 2020-03-26
Also published as: CN109313608A; CN109313608B

Abstract

Provided by the present application are a method for reading an image check coefficient, a flash memory controller, a system and a storage medium, the method comprising: a flash memory controller acquiring an interruption request sent by a cache; according to the interruption request, the flash memory controller reading from a flash memory an image check coefficient subset which currently needs to be cached; and the flash memory controller storing the image check coefficient subset which currently needs to be cached in the cache. Thus, it is possible to prevent an interruption request from taking up the time of a CPU so that the CPU is able to process other tasks, thereby increasing the task processing efficiency of the CPU.

Description

Method for reading image check coefficient, flash memory controller, system and storage medium

Technical field

The present application relates to the technical field of data processing, and in particular, to a method for reading an image check coefficient, a flash memory controller, a system, and a storage medium.

Background technique

In a 3D or 2D imaging system, an image signal processor (ISP) receives an image collected from an image sensor, and performs processing such as noise reduction and verification on the image. The ISP needs to perform noise reduction and verification on the image through the image verification coefficient.

In the prior art, the process by which an ISP obtains an image check coefficient includes: usually the ISP reads the image check coefficient from a buffer (Buffer), and when the image check coefficient in the buffer has been read, the buffer generates an interrupt request. And sends the interrupt request to a central processing unit (CPU), and after receiving the interrupt request, the CPU controls the flash controller (Flash Controller) to read the next image check coefficient from the flash (Flash), The read image check coefficient is stored in the buffer.

However, because the cache memory is limited, the internal image check coefficient can be easily read. Based on this, the cache generates interrupt requests very frequently. The CPU needs to process these interrupt requests in real time in order to control the flash memory controller to read the image check coefficient from the flash memory. This will consume a lot of time of the CPU and affect the CPU to process other transactions, that is, the transaction processing efficiency of the CPU.

Summary of the Invention

The application provides a method for reading an image check coefficient, a flash memory controller, a system, and a storage medium.

In a first aspect, the present application provides a method for reading an image check coefficient, comprising: a flash memory controller obtaining an interrupt request sent by a cache; the flash memory controller reading a subset of image check coefficients currently required to be cached from the flash memory according to the interrupt request ; The flash controller stores a subset of the image check coefficients that currently need to be cached into the cache.

On the one hand, it can prevent the interrupt request from occupying the CPU time, so that the CPU can process other transactions, which improves the transaction efficiency of the CPU. On the other hand, since the embodiment of the present application does not need the CPU to receive an interrupt request every time, the CPU controls the flash memory controller to read the image verification coefficient from the flash memory, but the memory controller can directly read the current cache required according to the interrupt request. A subset of the image check coefficient, thereby improving the reading efficiency of the image check coefficient.

Optionally, before the flash memory controller obtains the interrupt request sent by the cache, the flash memory controller further includes: the flash memory controller receives the instruction information sent by the central processing unit; correspondingly, the flash memory controller reads the current cached image check from the flash memory according to the interrupt request The subset of coefficients includes: the flash memory controller reads a subset of image check coefficients that need to be buffered from the flash memory according to the interrupt request and the instruction information.

That is, the CPU sends only one instruction message to the flash memory controller, and subsequent flash memory controllers only need to read a subset of the image check coefficients that need to be cached from the flash memory according to the interrupt request and the instruction information. On the one hand, the interrupt request can be prevented. The CPU time is occupied so that the CPU can process other transactions, that is, the transaction processing efficiency of the CPU is improved. On the other hand, since the embodiment of the present application does not need the CPU to receive an interrupt request every time, the CPU controls the flash memory controller to read the image verification coefficient from the flash memory, but the memory controller can directly read the current cache required according to the interrupt request. A subset of the image check coefficient, thereby improving the reading efficiency of the image check coefficient.

Optionally, the indication information includes: a start address of the image check coefficient set in the flash memory, an end address of the image check coefficient set in the flash memory, and an image check included in the image check coefficient subset that needs to be cached each time. The total length of the factor.

Optionally, the indication information further includes: a start address of each image check coefficient subset.

Optionally, the flash memory controller reads the current subset of image check coefficients to be cached from the flash memory according to the interrupt request and the instruction information, including: the flash memory controller determines, based on the instruction information, that the current image buffer needs to be cached according to the instruction request. The start address of the subset of verification coefficients and the total length of the image verification coefficients included in the subset of image verification coefficients that currently need to be cached; the flash memory controller starts from the flash memory, starting from the subset of image verification coefficients that currently needs to be cached The start address starts to read the data of the total length.

Optionally, the interrupt request includes: a start address of a subset of image check coefficients that currently needs to be cached and a total length of image check coefficients included in the subset of image check coefficients that currently need to be cached; a subset of image check coefficients It is a subset of the image check coefficient set. The image check coefficient set is composed of all the image check coefficients required in the image processing process. Correspondingly, the flash memory controller reads the currently checked cached image check from the flash memory according to the interrupt request. The coefficient subset includes: the flash memory controller reads data of the total length from the flash memory, starting from the start address of the image verification coefficient subset that currently needs to be buffered.

Optionally, before the flash memory controller reads the total length of data from the flash memory, starting from the start address of the subset of image check coefficients that currently needs to be buffered, the flash memory controller further includes: the flash memory controller determines the image check coefficients that currently need to be buffered. Whether the start address of the subset is smaller than the end address of the image check coefficient set in the flash memory; correspondingly, the flash memory controller reads from the flash memory the starting address of the subset of the image check coefficient that currently needs to be cached The total length of data includes: If the start address of the subset of image check coefficients currently required to be cached is less than the end address of the image check coefficient set in the flash memory, the flash memory controller The start address of the subset of test coefficients starts to read the data of the total length. If the start address of the image check coefficient subset that needs to be cached is greater than or equal to the end address of the image check coefficient set in the flash memory, the flash memory controller determines that the start address of the image check coefficient subset that needs to be cached is The starting address of the image check coefficient set in the flash memory. The total length of the image check coefficient included in the image check coefficient subset that needs to be cached is the first image check coefficient subset included in the image check coefficient set. The total length of the image check coefficients in the flash memory controller; starting from the flash memory, the data of the total length of the image check coefficient subsets that need to be buffered is read from the start address of the subset of the image check coefficients that currently need to be buffered. This ensures that when the image check coefficients required for a frame of image have been transmitted, the flash memory controller can still accurately obtain a subset of the image check coefficients that currently need to be cached, thereby improving the reliability of the flash memory controller.

The following describes the flash memory controller, system, storage medium, and computer program products. For the effects, refer to the effects in the method section.

In a second aspect, the present application provides a flash memory controller, including: the flash memory controller is configured to: obtain an interrupt request sent by a cache; read a subset of image check coefficients that currently need to be cached from the flash memory according to the interrupt request; A subset of the image check coefficients is stored in the cache.

Optionally, the flash memory controller is further configured to: receive instruction information sent by the central processing unit; correspondingly, the flash memory controller is specifically configured to: read the subset of image check coefficients currently required to be cached from the flash memory according to the interrupt request and the instruction information .

Optionally, the indication information includes: a start address of the image check coefficient set in the flash memory, an end address of the image check coefficient set in the flash memory, and an image check included in the image check coefficient subset that needs to be cached each time. The total length of the coefficients; among them, the image check coefficient set is composed of all the image check coefficients required in the image processing process, and the image check coefficient subset is a subset of the image check coefficient set.

Optionally, the flash memory controller is specifically configured to: under the trigger of the interrupt request, determine the start address of the image check coefficient subset that needs to be cached currently and the image check coefficient subset that needs to be cached according to the instruction information. The total length of the image check coefficient; from the flash memory, the data of the total length is read from the start address of the subset of the image check coefficient that currently needs to be cached.

Optionally, the start address of the subset of image check coefficients that currently needs to be cached and the total length of the image check coefficients included in the subset of image check coefficients that currently need to be cached; the subset of image check coefficients is image verification A subset of the coefficient set. The image check coefficient set is composed of all the image check coefficients required in the image processing process. Correspondingly, the flash memory controller is specifically used to: from the flash memory, the image check coefficients that are currently buffered. The start address of the set starts to read the total length of data.

Optionally, the flash memory controller is further configured to: determine whether a start address of a subset of image check coefficients currently required to be cached is smaller than an end address of the image check coefficient set in the flash memory; accordingly, the flash memory controller is specifically configured to: If the start address of the image check coefficient subset that needs to be cached is less than the end address of the image check coefficient set in the flash memory, then read from the flash memory starting from the start address of the image check coefficient subset that currently needs to be cached. Take the total length of the data.

Optionally, the flash memory controller is further configured to: if the start address of the subset of image check coefficients currently required to be cached is greater than or equal to the end address of the set of image check coefficients in the flash memory, determine the currently required cached image check The starting address of the coefficient subset is the starting address of the image verification coefficient set in the flash memory. The total length of the image verification coefficient included in the image verification coefficient subset that needs to be cached is the first in the image verification coefficient set. The total length of the image check coefficients included in the image check coefficient subset; from the flash memory, the data of the total length is read from the start address of the image check coefficient subset that currently needs to be buffered.

In a third aspect, the present application provides an image check coefficient reading system, including a cache, a flash memory, a central processing unit, and an optional flash memory controller for implementing the first aspect or the first aspect.

Optionally, the system further includes: an image sensor and an image signal processor; the image sensor is configured to acquire an image; the image signal processor is configured to acquire an image acquired by the image sensor, and obtain a current subset of image check coefficients to be cached from the cache. , Processing the images acquired by the image sensor according to the current subset of image check coefficients to be buffered.

According to a fourth aspect, the present application provides a computer storage medium, where the storage medium includes computer instructions, and when the instructions are executed by a computer, the computer implements the first aspect or the method of the first aspect.

In a fifth aspect, the present application provides a computer program product, including computer instructions, which, when executed by a computer, cause the computer to implement the first aspect or the method of the first aspect.

The application provides a method for reading an image check coefficient, a flash memory controller, a system, and a storage medium, including: the flash memory controller obtains an interrupt request sent by a cache; the flash memory controller reads an image that needs to be cached from the flash memory according to the interrupt request Check coefficient subset; the flash memory controller stores a subset of image check coefficients that currently need to be buffered into the cache. On the one hand, it can prevent the interrupt request from occupying the CPU time, so that the CPU can process other transactions, which improves the transaction efficiency of the CPU. On the other hand, since the embodiment of the present application does not need the CPU to receive an interrupt request every time, the CPU controls the flash memory controller to read the image verification coefficient from the flash memory, but the memory controller can directly read the current cache required according to the interrupt request. A subset of the image check coefficient, thereby improving the reading efficiency of the image check coefficient.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to explain the technical solutions in the embodiments of the present application or the prior art more clearly, the drawings used in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without paying creative labor.

FIG. 1 is a schematic application scenario diagram of the technical solution of the present application;

2 is a flowchart of a method for reading an image check coefficient provided by an embodiment of the present application;

3 is a flowchart of a method for reading an image check coefficient provided by another embodiment of the present application;

4 is a flowchart of a method for reading an image check coefficient provided by another embodiment of the present application;

5 is a flowchart of a method for reading an image check coefficient according to another embodiment of the present application;

6 is a flowchart of a method for reading an image check coefficient according to another embodiment of the present application;

FIG. 7 is a schematic diagram of an image check coefficient reading system 70 according to an embodiment of the present application.

detailed description

In order to make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments These are part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

The terms "first", "second", "third", "fourth", and the like (if present) in the description and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used For describing a particular order or sequence. It should be understood that the data used in this way are interchangeable under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. Furthermore, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or device that includes a series of steps or units need not be limited to those explicitly listed Those steps or units may instead include other steps or units not explicitly listed or inherent to these processes, methods, products or equipment.

As mentioned above, on the one hand, because the cache memory is limited, its internal image check coefficient can be easily read. Based on this, the cache generates interrupt requests very frequently. The CPU needs to process these interrupt requests in real time in order to control the flash memory controller to read the image check coefficient from the flash memory. This will consume a lot of time of the CPU and affect the CPU to process other transactions, that is, the transaction processing efficiency of the CPU. On the other hand, in the prior art, each time the CPU receives an interrupt request, the CPU must control the flash memory controller to read the image verification coefficient from the flash memory, which will inevitably cause a problem that the reading efficiency of the image verification coefficient is low. . In order to solve these technical problems, embodiments of the present application provide a method for reading an image check coefficient, a flash memory controller, a system, and a storage medium.

Before introducing the embodiments of the present invention, the following describes the related concepts:

The image check coefficient set is composed of all the image check coefficients required in the image processing process.

The image check coefficient subset is composed of at least one image check coefficient to be buffered into the cache each time, and the subset is a subset of the image check coefficient set.

Specifically, FIG. 1 is an application scenario diagram of the technical solution of the present application. As shown in FIG. 1, for a frame image, the flash memory 11 stores an image check coefficient set corresponding to the frame image, and the flash memory controller 12 may The image check coefficient subset that needs to be cached is read each time. The flash memory controller 12 stores the read image check coefficient subset into the cache 13. Further, the ISP 14 reads the currently cached image correction coefficient in the cache 13. Check the subset of coefficients, and obtain image data through the image sensor 15, and process the image data through the read subset of the image check coefficients, such as noise reduction, verification and other processing. After the current cached image check coefficient subset in the cache 13 is read, the cache 13 generates an interrupt request and sends the interrupt request to the flash controller 12, so that the flash controller 12 reads from the flash 11 the next time it needs Cached image check coefficient subset, and store the read image check coefficient subset into cache 13 so that ISP 14 reads the cached image check coefficient subset cached in cache 13 and acquires the image through image sensor 15 Data, the image data is processed again through the read image check coefficient subset.

Based on the above application scenarios, the technical solution of this application is described in detail below:

Example one

FIG. 2 is a flowchart of a method for reading an image verification coefficient according to an embodiment of the present application. As shown in FIG. 2, the method includes the following steps:

Step S21: The flash memory controller obtains an interrupt request sent by the cache.

Step S22: The flash memory controller reads from the flash memory a subset of image check coefficients that currently needs to be buffered according to the interrupt request.

Step S23: The flash memory controller stores a subset of image check coefficients that currently needs to be buffered into the buffer.

The description of step S21:

An optional method: The interrupt request is used to trigger the flash memory controller to read from the flash memory a subset of image check coefficients that currently need to be buffered.

Another optional method: the interrupt request includes: a start address of a subset of image check coefficients that currently needs to be buffered and a total length of the image check coefficients included in the subset of image check coefficients that currently need to be buffered.

In step S21, after a subset of the image check coefficients currently cached in the cache 13 is read, the cache 13 generates an interrupt request and sends an interrupt request to the flash memory controller 12.

The description of step S22:

First, the flash memory controller determines, based on the interrupt request, the start address of the image check coefficient subset that currently needs to be cached and the total length of the image check coefficient included in the image check coefficient subset that currently needs to be buffered. The start address of the image check coefficient subset that currently needs to be buffered refers to the start address of the first image check coefficient included in the image check coefficient subset. Generally, the cache stores image check coefficients corresponding to one row of pixels in a frame of image, and each pixel corresponds to an image check coefficient. Assume that the image check coefficients corresponding to the pixels in the first row are currently stored in the cache. In this case, the starting address of the subset of the image check coefficients refers to the starting address of the pixels in the first row and the first column in the flash memory. Further, the subset of image check coefficients that currently needs to be buffered includes at least one image check coefficient. When the subset of image check coefficients that currently need to be buffered includes one image check coefficient, the subset of image check coefficients that currently need to be buffered. The total length of the included image check coefficient refers to the length of the one image check coefficient. When the subset of image check coefficients that currently needs to be cached includes multiple image check coefficients, the total length of the image check coefficients included in the subset of image check coefficients that currently need to be cached refers to the multiple image check coefficients Total length. Assume that the image check coefficients corresponding to the pixels in the first line are currently stored in the cache. In this case, the total length of the image check coefficient subset refers to the total length of the image check coefficients corresponding to all pixels in the first line.

Secondly, the flash memory controller reads the data of the total length from the flash memory, starting from the start address of the subset of image check coefficients that currently needs to be buffered.

Wherein, if the interrupt request is the above-mentioned first optional way, the flash memory controller also receives instruction information sent by the CPU before step S21, and the instruction information is used to determine a start address of a subset of image check coefficients that currently needs to be buffered. And the total length of image check coefficients included in the subset of image check coefficients that need to be cached.

If the interrupt request is the second optional method described above, the flash memory controller may directly determine the start address of the image check coefficient subset that needs to be cached and the image check coefficient subset that currently needs to be cached according to the interrupt request. The total length of the image check coefficient.

Optionally, after step S23, the ISP reads from the cache the subset of image check coefficients that currently needs to be cached, and performs image processing through the subset of image check coefficients that currently need to be cached. Specifically, it can be based on the current needs The buffered image check coefficient subset processes the image information obtained from the image sensor. The embodiment of the present application does not limit how to perform image processing by using the image check coefficient.

In the embodiment of the present application, the cache does not need to send an interrupt request to the CPU, but directly sends an interrupt request to the flash memory controller, so that the flash memory controller reads from the flash memory a subset of image check coefficients that currently need to be cached according to the interrupt request, and Store a subset of image check coefficients that currently need to be cached into the cache. On the one hand, it can prevent the interrupt request from occupying the CPU time, so that the CPU can process other transactions, which improves the transaction efficiency of the CPU. On the other hand, since the embodiment of the present application does not need the CPU to receive an interrupt request every time, the CPU controls the flash memory controller to read the image verification coefficient from the flash memory, but the memory controller can directly read the current cache required according to the interrupt request. A subset of the image check coefficient, thereby improving the reading efficiency of the image check coefficient.

Example two

Step S22 is described with reference to the first optional way of step S21: Specifically, FIG. 3 is a flowchart of a method for reading an image check coefficient provided by another embodiment of the present application. As shown in FIG. 3, the method It includes the following steps:

Step S31: The flash memory controller receives instruction information sent by the CPU.

Step S32: The flash memory controller obtains an interrupt request sent by the cache.

Step S33: The flash memory controller reads from the flash memory a subset of image check coefficients that currently needs to be buffered according to the interrupt request and the instruction information.

Step S34: The flash memory controller stores a subset of image check coefficients that currently needs to be buffered into the buffer.

Among them, step S32 is the same as step S21, and step S34 is the same as step S23, which is not repeated in the embodiment of the present application.

The following describes step S31:

An optional method: The indication information includes: a start address of the image check coefficient set in the flash memory, an end address of the image check coefficient set in the flash memory, and an image check coefficient that needs to be cached each time. The total length of the image check coefficients included in the subset.

Another optional method: The indication information includes: a start address of the image check coefficient set in the flash memory, an end address of the image check coefficient set in the flash memory, and an image check that needs to be cached each time. The total length of the image check coefficients included in the coefficient subsets, and the start address of each of the image check coefficient subsets.

Optionally, the total length of the image check coefficients included in the image check coefficient subsets that need to be cached each time may be the same or different.

The storage area between the start address of the image check coefficient set in the flash memory and the end address of the image check coefficient set in the flash memory is a continuous storage area.

The termination address of the image check coefficient set in the flash memory refers to the termination address of the last image check coefficient set in the image check coefficient set in the flash memory.

The following describes step S33:

FIG. 4 is a flowchart of a method for reading an image verification coefficient according to another embodiment of the present application. As shown in FIG. 4, the above step S33 includes:

Step S331: The flash memory controller determines, based on the instruction information, the start address of the image check coefficient subset that needs to be cached and the image check coefficient included in the image check coefficient subset that currently needs to be cached according to the instruction information. Total length.

Step S332: The flash memory controller reads the data of the total length from the flash memory, starting from the start address of the image check coefficient subset that currently needs to be buffered.

Specifically, with regard to the first optional manner of the indication information, if the currently required subset of image check coefficients to be cached is the first subset of image check coefficients in the image check coefficient set, since the indication information includes: the first The initial address of each image check coefficient subset and the length of the first image check coefficient subset. Based on this, the flash memory controller directly determines the initial address of the first image check coefficient subset as the image that needs to be cached currently. The initial address of the check coefficient subset, and determines the total length of the image check coefficients included in the first image check coefficient subset as the image check coefficients included in the image check coefficient subset that currently needs to be cached. Total length. If the current subset of image check coefficients to be cached is not the first subset of image check coefficients in the image check coefficient set, because the indication information does not include: the initial address of the subset of image check coefficients that currently need to be cached, based on Therefore, the flash memory controller first determines the initial address of the image check coefficient subset that was successfully read last time, and the total length of the image check coefficient included in the image check coefficient, and calculates the last successfully read The sum of the initial address of the image check coefficient subset and the total length of the image check coefficient included in the image check coefficient subset, to obtain the initial address of the image check coefficient subset that needs to be buffered. And because the total length of the image check coefficient included in the image check coefficient subset that needs to be cached is carried in the instruction information, the flash memory controller can directly determine the current image check coefficient subset that needs to be cached in the instruction information. The total length of the image check coefficients included.

The second optional manner for the indication information is that the indication information includes: a start address of the image check coefficient set in the flash memory, an end address of the image check coefficient set in the flash memory, The total length of the image check coefficient subset included in the cached image check coefficient subset, and the start address of each of the image check coefficient subsets. Based on this, the flash memory controller can directly determine the current through the instruction information. The initial address of the subset of image check coefficients to be cached and the total length of the image check coefficients it contains.

In the embodiment of the present application, the CPU sends only one instruction message to the flash memory controller, and subsequent flash memory controllers only need to read a subset of image check coefficients that need to be cached from the flash memory according to the interrupt request and the instruction information. On the one hand, it can prevent the interrupt request from occupying the CPU time, so that the CPU can process other transactions, which improves the transaction efficiency of the CPU. On the other hand, since the embodiment of the present application does not need the CPU to receive an interrupt request every time, the CPU controls the flash memory controller to read the image verification coefficient from the flash memory, but the memory controller can directly read the current cache required according to the interrupt request. A subset of the image check coefficient, thereby improving the reading efficiency of the image check coefficient.

Example three

Step S22 is described with reference to the second optional method of step S21: Specifically, FIG. 5 is a flowchart of a method for reading an image verification coefficient according to another embodiment of the present application. As shown in FIG. 5, the method include:

Step S51: The flash memory controller obtains an interrupt request sent by the cache.

Step S52: The flash memory controller reads, from the flash memory, the data of the total length of the image check coefficients included in the image check coefficient subset starting from the start address of the image check coefficient subset that currently needs to be buffered.

Step S53: The flash memory controller stores a subset of image check coefficients that currently needs to be buffered into the buffer.

Among them, step S52 is the same as step S21, and step S53 is the same as step S33, which is not repeated in the embodiment of the present application.

The following describes step S52:

Because the interrupt request includes the starting address of the image check coefficient subset that needs to be cached and the total length of the image check coefficient included in the image check coefficient subset that needs to be cached, the image check coefficient subset is A subset of the image check coefficient set, which is composed of all the image check coefficients required in the image processing process. Therefore, the flash memory controller reads the data of the total length from the flash memory, starting from the start address of the subset of image check coefficients that currently needs to be buffered.

Embodiment 4

For step S332 or step S52, the method for reading image verification coefficients further includes: optionally, the flash memory controller determines whether the start address of the subset of image verification coefficients that currently needs to be buffered is smaller than the image verification The termination address of the coefficient set in the flash memory. If the start address of the image check coefficient subset that currently needs to be buffered is smaller than the end address of the image check coefficient set in the flash memory, step S332 or step S52 is performed. If the start address of the subset of image check coefficients that currently needs to be buffered is greater than or equal to the end address of the set of image check coefficients in the flash memory, the flash memory controller determines the currently needed buffered image check The starting address of the coefficient subset is the starting address of the image verification coefficient set in the flash memory, and the total length of the image verification coefficient included in the image verification coefficient subset that needs to be buffered is the image calibration. The total length of the image check coefficient included in the first image check coefficient subset in the test coefficient set, and then the flash memory controller reads from the flash memory, starting from the start address of the image check coefficient subset that currently needs to be buffered Take the data of the total length.

Specifically, the above content is described in detail with reference to the second embodiment:

FIG. 6 is a flowchart of a method for reading an image check coefficient according to another embodiment of the present application. As shown in FIG. 6, the method includes the following steps:

Step S61: The flash memory controller receives instruction information sent by the CPU.

Step S62: The flash memory controller obtains an interrupt request sent by the cache.

Step S63: The flash memory controller determines, based on the instruction information, the start address of the image check coefficient subset that needs to be cached and the image check coefficient included in the image check coefficient subset that needs to be cached according to the instruction information. Total length.

Step S64: The flash memory controller judges whether the start address of the subset of image check coefficients currently required to be buffered is smaller than the end address of the image check coefficient set in the flash memory; if it is less than step S65, otherwise, then Steps S66 to S67 are performed.

Step S65: The flash memory controller reads the data of the total length from the flash memory, starting from the start address of the subset of image check coefficients that currently needs to be buffered.

Step S66: The flash memory controller determines that the start address of the subset of image check coefficients that needs to be cached is the start address of the set of image check coefficients in the flash memory. The total length of the test coefficients is the total length of the image check coefficients included in the first image check coefficient subset in the image check coefficient set.

Step S67: The flash memory controller reads the data of the total length from the flash memory, starting from the start address of the subset of image check coefficients that currently needs to be buffered.

Step S68: The flash memory controller stores a subset of image check coefficients that need to be buffered into the buffer.

Among them, step S61 is the same as step S31, step S62 is the same as step S32, step S63 is the same as step S331, and step S68 is the same as step S34, which is not described in this embodiment of the present application.

Description is made with reference to steps S64 to S67:

When the flash controller receives the interrupt request for the first time, the flash controller sets the start address req_address of the subset of image check coefficients that need to be cached to the start address of the image check coefficient set in memory, and reads from req_address. Take the data of the total length of the image check coefficients included in the image check coefficient subset that needs to be buffered into the buffer; then the flash controller adds req_address to req_len; that is, req_address = req_address + req_len. Next, each time the flash memory controller receives an interrupt request, it first determines whether req_address is less than the end address of the image verification coefficient set in memory. If so, the flash memory controller reads the currently verified image verification from req_address. Data of the total length of the image check coefficients included in the coefficient subset are buffered; then the flash memory controller adds req_address to req_len; that is, req_address = req_address + req_len. If req_address is greater than or equal to end_address, it means that the image check coefficient required for one frame of image has been transferred, and the flash controller resets req_address to start_address.

In the embodiment of the present application, before the flash memory controller reads a subset of image check coefficients that currently needs to be cached, the flash memory controller needs to determine whether the start address of the subset of image check coefficients that currently need to be cached is smaller than the image check coefficient Start address set in flash memory; if the start address of the subset of image check coefficients currently needed to be cached is smaller than the start address of the image check coefficient set in flash, the flash memory controller reads the currently calibrated image Check coefficient subset, otherwise, the flash memory controller reads the first subset of image check coefficients in the image check coefficient set. This ensures that when the image check coefficients required for a frame of image have been transmitted, the flash memory controller can still accurately obtain a subset of the image check coefficients that currently need to be cached, thereby improving the reliability of the flash memory controller.

Example 5

An embodiment of the present application further provides a flash memory controller, where the flash memory controller is configured to: obtain an interrupt request sent by a cache; read a subset of image check coefficients that currently need to be cached from the flash memory according to the interrupt request; A subset of the test coefficients is stored in the cache.

Optionally,

The start address of the image check coefficient subset that needs to be cached and the total length of the image check coefficient included in the image check coefficient subset that needs to be cached; the image check coefficient subset is a subset of the image check coefficient set Set, the image check coefficient set is composed of all the image check coefficients required in the image processing process; correspondingly, the flash memory controller is specifically used to: from the flash memory, from the beginning of the current subset of image check coefficients to be cached The address starts to read the total length of data.

The flash memory controller provided in the embodiment of the present application may be used to execute the above-mentioned method for reading the image verification coefficient. For the content and effect, refer to the method section, which is not limited in the embodiment of the present application.

Example Six

FIG. 7 is a schematic diagram of an image check coefficient reading system 70 according to an embodiment of the present application. As shown in FIG. 7, the system includes: a cache 71, a flash memory 72, a CPU 73, and an image check coefficient. Read method of flash controller 74.

Optionally, the system 70 further includes: an image sensor 75 and an ISP 76.

Among them, the image sensor 75 is used to collect images; the ISP 76 is used to acquire the images collected by the image sensor 75, and from the cache 71, to obtain a subset of the image check coefficients that need to be cached, and to process according to the subset of the image check coefficients that are currently cached. An image captured by the image sensor 75.

The flash memory controller in the image check coefficient reading system provided by the embodiment of the present application can be used to execute the above-mentioned method for reading the image check coefficient. For the content and effect, refer to the method part, which is not done in the embodiment of the present application. limit.

Example Seven

An embodiment of the present application further provides a computer storage medium. The storage medium includes computer instructions. When the instructions are executed by a computer, the computer enables the computer to implement the method for reading the image check coefficient as described above.

Example eight

An embodiment of the present application further provides a computer program product, including: computer instructions that, when executed by a computer, cause the computer to implement the method for reading an image check coefficient as described above.

A person of ordinary skill in the art may understand that all or part of the steps of implementing the foregoing method embodiments may be implemented by a program instructing related hardware. The aforementioned program may be stored in a computer-readable storage medium. When the program is executed, the steps including the foregoing method embodiments are executed; and the foregoing storage medium includes: various media that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disc.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention, but not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or to replace some or all of the technical features equivalently; and these modifications or replacements do not depart from the essence of the corresponding technical solutions of the technical solutions of the embodiments of the present invention. range.

Claims

A method for reading an image check coefficient is characterized in that it includes:

The flash controller obtains the interrupt request sent by the cache;

Reading, by the flash memory controller, a subset of image check coefficients that currently need to be buffered from the flash memory according to the interrupt request;

The flash memory controller stores a subset of image check coefficients that currently need to be buffered into the buffer.
The method according to claim 1, before the flash memory controller obtaining the interrupt request sent by the cache, further comprising:

Receiving, by the flash memory controller, instruction information sent by a central processing unit;

Correspondingly, the flash memory controller reading the current subset of image check coefficients to be cached from the flash memory according to the interrupt request includes:

The flash memory controller reads, from the flash memory, a subset of image check coefficients that currently need to be buffered according to the interrupt request and the instruction information.
The method according to claim 2, wherein the indication information comprises: a start address of the image check coefficient set in the flash memory, an end address of the image check coefficient set in the flash memory, The total length of the image check coefficients included in the subset of image check coefficients to be cached each time;

The image check coefficient set is composed of all the image check coefficients required in the image processing process, and the image check coefficient subset is a subset of the image check coefficient set.
The method according to claim 3, wherein the indication information further comprises: a start address of each of the image check coefficient subsets.
The method according to claim 3 or 4, wherein the flash memory controller reading the subset of image check coefficients that currently needs to be cached from the flash memory according to the interrupt request and the instruction information, comprises:

When triggered by the interrupt request, the flash memory controller determines, according to the instruction information, a start address of a subset of image check coefficients that currently needs to be cached and an image calibration included in the subset of image check coefficients that currently needs to be cached. Total length of the test coefficient;

The flash memory controller reads the data of the total length from the flash memory, starting from a start address of a subset of image check coefficients that currently needs to be buffered.
The method according to claim 1, wherein the interrupt request comprises: a start address of a subset of image check coefficients that currently needs to be buffered and an image check included in the subset of image check coefficients that currently need to be buffered The total length of the coefficients; the image check coefficient subset is a subset of the image check coefficient set, and the image check coefficient set is composed of all the image check coefficients required in the image processing process;

Correspondingly, the flash memory controller reading the current subset of image check coefficients to be cached from the flash memory according to the interrupt request includes:

The flash memory controller reads the data of the total length from the flash memory, starting from a start address of a subset of image check coefficients that currently needs to be buffered.
The method according to claim 5 or 6, wherein the flash memory controller reads the data of the total length from the flash memory, starting from a start address of a subset of image check coefficients that currently needs to be buffered. Before, it also included:

The flash memory controller determining whether a start address of a subset of image check coefficients that currently needs to be buffered is smaller than an end address of the image check coefficient set in the flash memory;

Correspondingly, the flash memory controller reads the data of the total length from the flash memory, starting from a start address of a subset of image check coefficients that currently needs to be buffered, including:

If the start address of the subset of image check coefficients that currently needs to be cached is smaller than the end address of the image check coefficient set in the flash memory, the flash memory controller will cache the current set of cache memory coefficients from the flash memory. The start address of the subset of image check coefficients starts to read the data of the total length.
The method according to claim 7, further comprising:

If the start address of the subset of image check coefficients that currently needs to be buffered is greater than or equal to the end address of the set of image check coefficients in the flash memory, the flash memory controller determines the currently needed buffered image check The starting address of the coefficient subset is the starting address of the image verification coefficient set in the flash memory, and the total length of the image verification coefficient included in the image verification coefficient subset that needs to be buffered is the image calibration. The total length of the image check coefficients included in the first image check coefficient subset of the test coefficient set;

The flash memory controller reads the data of the total length from the flash memory, starting from a start address of a subset of image check coefficients that currently needs to be buffered.
A flash memory controller, comprising: the flash memory controller is used for:

Get the interrupt request sent by the cache;

Reading a subset of image check coefficients that currently need to be cached from the flash memory according to the interrupt request;

A subset of image check coefficients that currently need to be cached is stored in the cache.
The flash memory controller according to claim 9, wherein the flash memory controller is further configured to:

Receiving instruction information sent by the central processing unit;

Accordingly, the flash memory controller is specifically configured to:

And reading a subset of image check coefficients that currently need to be buffered from the flash memory according to the interrupt request and the instruction information.
The flash memory controller according to claim 10, wherein the indication information comprises: a start address of an image check coefficient set in the flash memory, and an end of the image check coefficient set in the flash memory Address, total length of image check coefficients included in the subset of image check coefficients to be cached each time;

The image check coefficient set is composed of all the image check coefficients required in the image processing process, and the image check coefficient subset is a subset of the image check coefficient set.
The flash memory controller according to claim 11, wherein the indication information further comprises: a start address of each of the image check coefficient subsets.
The flash memory controller according to claim 11 or 12, wherein the flash memory controller is specifically configured to:

Triggered by the interrupt request, determining a start address of a subset of image check coefficients that currently needs to be cached and a total length of image check coefficients included in the subset of image check coefficients that currently need to be cached according to the instruction information ;

The total length of data is read from the flash memory starting from the start address of the subset of image check coefficients that currently needs to be cached.
The flash memory controller according to claim 9, wherein the start address of the subset of image check coefficients that currently needs to be buffered and the total length of the image check coefficients included in the subset of image check coefficients that need to be currently buffered The image check coefficient subset is a subset of the image check coefficient set, and the image check coefficient set is composed of all the image check coefficients required in the image processing process;

Accordingly, the flash memory controller is specifically configured to:

The total length of data is read from the flash memory starting from the start address of the subset of image check coefficients that currently needs to be cached.
The flash memory controller according to claim 13 or 14, wherein the flash memory controller is further configured to:

Determining whether a start address of a subset of image check coefficients that needs to be buffered currently is less than an end address of the image check coefficient set in the flash memory;

Accordingly, the flash memory controller is specifically configured to:

If the start address of the subset of image check coefficients that currently needs to be cached is less than the end address of the image check coefficient set in the flash memory, The start address of the subset begins to read the data of the total length.
The flash memory controller according to claim 15, wherein the flash memory controller is further configured to:

If the start address of the subset of image check coefficients that currently needs to be cached is greater than or equal to the end address of the set of image check coefficients in the flash memory, determine the start of the subset of image check coefficients that currently need to be cached The start address is the start address of the image check coefficient set in the flash memory, and the total length of the image check coefficient included in the image check coefficient subset that needs to be cached is the first in the image check coefficient set. The total length of the image check coefficients included in the image check coefficient subsets;

The total length of data is read from the flash memory starting from the start address of the subset of image check coefficients that currently needs to be cached.
A system for reading image check coefficients, comprising: a cache, a flash memory, a central processing unit, and a flash memory controller for implementing the method according to any one of claims 1-8.
The system according to claim 17, further comprising: an image sensor and an image signal processor;

The image sensor is used to acquire an image;

The image signal processor is configured to obtain an image collected by the image sensor, and obtain the subset of image check coefficients that currently needs to be cached from the cache, and process according to the subset of image check coefficients that currently need to be cached. An image acquired by the image sensor.
A computer storage medium, wherein the storage medium comprises computer instructions, and when the instructions are executed by a computer, the computer is caused to implement the method according to any one of claims 1 to 8.