WO2020052754A1

WO2020052754A1 - Simplified check node processing for ldpc decoding

Info

Publication number: WO2020052754A1
Application number: PCT/EP2018/074667
Authority: WO
Inventors: Wei Zhou; Michael Lentmaier; Sergei Semenov; Wenquan HU; Bengt Lindoff
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2018-09-12
Filing date: 2018-09-12
Publication date: 2020-03-19

Abstract

Low-density parity-check, LDPC, codes may be used to transmit and/or store information in environments, where the information may be corrupted due to, for example, noise. The originally transmitted/stored information may be retrieved using an LDPC decoder. According to an embodiment, a decoder for decoding LDPC codes is configured to receive L-values to a check node, CN, from neighbouring variable nodes, VNs, process a first subset of L-values in the CN to produce a first L-value, and process a second subset of L-values in the CN to produce a second L-value. The first L-value may be passed to a neighbouring VN corresponding to a smallest L-value magnitude, and the second L-value may be passed to other neighbouring VNs.

Description

SIMPLIFIED CHECK NODE PROCESSING FOR LDPC DECODING

TECHNICAL FIELD

The disclosure relates to a field of error correction, and more particularly to a decoder and a procedure for decoding low-density parity-check codes. Furthermore, the disclosure relates to a corresponding method and a computer program.

BACKGROUND

Low-density parity-check, LDPC, codes can be used widely, for example, in digital communications and storage systems. Data transmitted in communication systems or stored in storage systems can be corrupted by noise, and LDPC codes may be used to correct errors caused by this corruption. LDPC codes may achieve this by storing/transmitting parity check bits in addition to the original data bits. An objective of decoding LDPC codes is to reconstruct the original data from the corrupted noisy data.

The 3rd Generation Partnership Project, 3GPP, has finalized the design of fifth generation, 5G, new radio, NR, LDPC codes for enhanced mobile broadband, eMBB, services. To support a broad range of code lengths and rates, two base graphs, BGs, BG1 and BG2 are considered in the NR eMBB implementation. Both BG1 and BG2 consist of two parts, a core graph representing the high rate codes, as well as an extension graph which includes more parity bits for lower rate codes.

SUMMARY

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

It is an object to provide a decoder for decoding LDPC codes. The object is achieved by the features of the independent claims. Further implementation forms are provided in the dependent claims, the description and the figures. According to a first aspect, a decoder for decoding low-density parity-check codes is configured to: receive L-values to a check node, CN, from neighbouring variable nodes, VNs; select a first subset of L-values from the received L-values comprising s’-1 received L-values with smallest magnitudes excluding a received L-value with a smallest magnitude, Lmin; process the first subset of L-values in the CN to produce a first extrinsic L-value; pass the first extrinsic L-value to a neighbouring VN corresponding to Lmin; select a second subset of L-values from the received L-values comprising s received L-values with smallest magnitudes; process the second subset of L-values in the CN to produce a second L-value; and pass the second L-value to the neighbouring VNs excluding the VN corresponding to Lmin. With these configurations, the decoder can, for example, decode LDPC codes with a reduced number of operations.

In an implementation form of the first aspect, the decoder is further configured to: initialise L-values in the VNs according to received channel outputs; and transmit the initialised L-values from the VNs to the CN. With these configurations, the decoder can, for example, use the channel outputs as a starting point for the decoding iteration.

In a further implementation form of the first aspect, the decoder is further configured to: calculate outgoing L-values from each VN to the CN by summing all L-values received to the VN excluding an L-value received from the CN. With these configurations, the decoder can, for example, efficiently calculate the outgoing L-values in the VNs from the L-value received from the CNs.

In a further implementation form of the first aspect, s’-1 and/or s are preconfigured integer values. With these configurations, the decoder can, for example, select the first and second subset of L-values using the preconfigured integer values.

In a further implementation form of the first aspect, an outgoing L-value of a VN is set to zero, if a sign of the outgoing L-value changes between two consecutive iterations. With these configurations, the decoder can, for example, perform self-correction so that unreliable L-values are removed from the iteration. This may improve performance of the decoder.

In a further implementation form of the first aspect, s’-1 and/or s are configured according to a threshold, Lth, so that a magnitude of each L-value in the first subset and in the second subset is less or equal to Lth. With these configurations, the decoder can, for example, select the first and second subset so that the sizes of the subsets scale according to the L-value magnitudes.

In a further implementation form of the first aspect, Lth is determined by Lmin and a factor b, wherein b indicates a proportion between Lth and Lmin. With these configurations, the decoder can, for example, efficiently determine the value of Lth.

In a further implementation form of the first aspect, With these

configurations, the decoder can, for example, efficiently compute the value of Lth.

In a further implementation form of the first aspect, s’-1 and/or s are configured according to the number of L-values received to the CN, d_c, and a factor l, wherein l indicates a proportion between d_cand s or between d_cand s’-1. With these configurations, the decoder can, for example, select the first and second subset so that the sizes of the subsets scale according to the number of L-values received to the CN.

In a further implementation form of the first aspect, s=ceil(kd_c). With these configurations, the decoder can, for example, efficiently compute the value of s.

In a further implementation form of the first aspect, the decoder is further configured to: rescale the L-values received to the CN by multiplying each received L-value by a factor. With these configurations, the decoder can, for example, improve performance in the case of LLR mismatch.

According to a second aspect, a method comprises: receiving L-values to a check node, CN, from neighbouring variable nodes, VNs; selecting a first subset of L-values from the received L-values comprising s’-1 received L-values with smallest magnitudes excluding a received L-value with a smallest magnitude, Lmin; processing the first subset of L-values in the CN to produce a first extrinsic L-value; passing the first extrinsic L-value to a neighbouring VN corresponding to Lmin; selecting a second subset of L-values from the received L-values comprising s received L-values with smallest magnitudes; processing the second subset of L- values in the CN to produce a second L-value; and passing the second L-value to the neighbouring VNs excluding the VN corresponding to Lmin.

In an implementation form of the second aspect, the method further comprises initialising L-values in the VNs according to received channel outputs; and transmitting the initialised L-values from the VNs to the CN. In a further implementation form of the second aspect, the method further comprises calculating outgoing L-values from each VN to the CN by summing all L-values received to the VN excluding an L-value received from the CN.

In a further implementation form of the second aspect, s’-1 and/or s are preconfigured integer values.

In a further implementation form of the second aspect, the method further comprises setting an outgoing L-value of a VN to zero, if a sign of the outgoing L- value changes between two consecutive iterations.

In a further implementation form of the second aspect, the method further comprises configuring s’-1 and/or s according to a threshold, Lth, so that a magnitude of each L-value in the first subset and in the second subset is less or equal to Lth.

In a further implementation form of the second aspect, the method further comprises determining Lth by Lmin and a factor b, wherein b indicates a proportion between Lth and Lmin.

In a further implementation form of the second aspect,

In a further implementation form of the second aspect, the method further comprises configuring s’-1 and/or s according to the number of L-values received to the CN, d_c, and a factor l, wherein l indicates a proportion between d_cand s or between d_cand s’-1.

In a further implementation form of the second aspect, s=eeil(ld_c).

In a further implementation form of the second aspect, the method further comprises rescaling the L-values received to the CN by multiplying each received L-value by a factor.

According to a third aspect, a computer program is provided, comprising program code configured to perform a method according to the second aspect when the computer program is executed on a computer.

Many of the attendant features will be more readily appreciated as they become better understood by reference to the following detailed description considered in connection with the accompanying drawings. DESCRIPTION OF THE DRAWINGS

The present description will be better understood from the following detailed description read in light of the accompanying drawings, wherein:

FIG. 1 illustrates a schematic representation of a decoder according to an embodiment;

FIG. 2 illustrates a schematic representation of a Tanner graph according to an embodiment;

FIG. 3 illustrates a schematic representation of Tanner graphs for check node and a variable node according to an embodiment;

FIG. 4 illustrates a schematic representation of a Tanner graph of critical value processing according to an embodiment;

FIG. 5 illustrates a schematic representation of a Tanner graph of non- critical value processing according to an embodiment;

FIG. 6 illustrates a schematic representation of simulation results according to an embodiment;

FIG. 7 illustrates a schematic representation of simulation results according to another embodiment;

FIG. 8 illustrates a schematic representation of simulation results according to another embodiment;

FIG. 9 illustrates a schematic representation of simulation results according to another embodiment;

FIG. 10 illustrates a schematic representation of a table according to an embodiment; and

FIG. 11 illustrates a flow diagram of a method according to an embodiment.

Fike references are used to designate like parts in the accompanying drawings.

DETAIFED DESCRIPTION

The detailed description provided below in connection with the appended drawings is intended as a description of the embodiments and is not intended to represent the only forms in which the embodiment may be constructed or utilized. However, the same or equivalent functions and structures may be accomplished by different embodiments. FIG. 1 illustrates a schematic representation of a decoder 100 according to an embodiment. The decoder 100 may comprise a processor 101 and a memory 102. The decoder 100 may be a device or it may be part of a device. For example, the decoder 100 may be a mobile phone, or the decoder 100 may refer to a part of the mobile phone that implements decoding. The decoder 100 may be implemented, for example, in software or in hardware.

According to an embodiment, the decoder 100 is configured to receive L- values to a check node, CN, from neighbouring variable nodes, VNs. As a person skilled in the art can appreciate, VNs and CNs may be implemented in software and may not respond to any physical components in the decoder 100. The decoder 100 may be further configured to select a first subset of L-values from the received L- values comprising s’-1 received L-values with smallest magnitudes excluding a received L-value with a smallest magnitude, Lmin. The decoder may then process the first subset of L-values in the CN to produce a first extrinsic L-value. This L- value may be referred to as a critical L-value. The decoder 100 may then pass the first extrinsic L-value to a neighbouring VN corresponding to Lmin. The decoder 100 may be further configured to select a second subset of L-values from the received L-values comprising s received L-values with smallest magnitudes. The decoder 100 may be further configured to process the second subset of L-values in the CN to produce a second L-value. This L-value may be referred to as non-critical L-value. The decoder 100 may be further configured to pass the second L-value to the neighbouring VNs excluding the VN corresponding to Lmin. Each VN may calculate a new L-value, and these L-values may be passed back to the CNs. This process may be iterated until a stopping criterion is met.

The decoder 100 may be part of, for example, a client device or a network access device in a wireless communication system. The decoder 100 may be configured to perform the functionalities and operations relating to it as described in the embodiments. For example, a client device may transmit a message to a network access device using wireless communication and code the message using LDPC coding. The network access device may use the decoder 100 to decode such message.

A client device may be any of a User Equipment (UE) in Long Term Evolution (LTE) or 5G new radio (NR), mobile station (MS), wireless terminal, or mobile terminal which is enabled to communicate wirelessly in a wireless communication system, sometimes also referred to as a cellular radio system. The client device may further be referred to as a mobile telephone, a cellular telephone, a computer tablet or a laptop with wireless capability. The client device in the present context may be, for example, a portable, pocket-storable, hand-held, computer-comprised, or vehicle-mounted mobile device, enabled to communicate voice or data, via a radio access network, with another entity, such as another receiver or a server. The client device 100 can be a Station (STA) which is any device that contains an IEEE 802.11 -conformant Media Access Control (MAC) and Physical Layer (PHY) interface to the Wireless Medium (WM).

A network access device may be a transmission or reception point, TRP, or a NR 5G base station, gNB. The network access device may be a base station, a (radio) network node or an access node or an access point or a base station, e.g., a Radio Base Station (RBS), which in some networks may be referred to as a transmitter, “eNB”, “eNodeB”, “gNB”, “gNodeB”, “NodeB”, or “B node”, depending on the technology and terminology used. The radio network nodes may be of different classes such as, e.g., macro eNodeB, home eNodeB or pico base station, based on transmission power and thereby also cell size. The radio network node can be a Station (STA) which is any device that contains an IEEE 802.11- conformant Media Access Control (MAC) and Physical Layer (PHY) interface to the Wireless Medium (WM).

An LDPC code can be described by a sparse parity-check matrix H. The codewords v of the LDPC code is a set of vectors, the null space of which is H, i.e., vH^T = 0, where H^T is the transpose of H. LDPC codes can also be represented by so called Tanner graphs. A Tanner graph is a bipartite graph which consists of variable nodes, VNs, and check nodes, CNs. VNs may also be referred to as digit nodes or bit nodes, and CNs may also be referred to as subcode nodes or parity nodes. An example of a parity-check matrix may be

A Tanner graph corresponding to the matrix H above is presented in FIG. 2 according to an embodiment. As can be seen from FIG. 2, columns of H corresponds to connections of each VN 201, and rows of H correspond to connections of each CN 202. For example, in the first column of H, three first entries are ones. Thus, the first VN 201, counting from the left, is connected to the three first CNs 202. Generally, if the entry in the ith row and yth column of H is one, then in the corresponding Tanner graph, the ith CN 202 and yth VN 201 are connected. When a VN 201 and a CN 202 are connected in a Tanner graph, they may be referred to as neighbouring nodes. For example, in FIG. 2, the first VN 201 is a neighbouring VN to the first, second, and third CNs 202. The number of VNs 201 in the Tanner graph is the length N of the code, and the number of CNs M is number of parity bits of the code. If H has full rank, then the rank of the code R can be defined as R = (N— M)/N. For example, in NR eMBB, BG1 may be used for codes of lengths N = 512 to 8448 and of rates R = 8/9 to 1/3, while BG2 may be used for codes of lengths N = 40 to 2560 and of rates R = 2/3 to 1/5.

An LDPC codeword at the receiver can be decoded into a reconstructed copy of transmitted codeword v. For a binary case, the codeword bits v_n, for n = 1,2, ... N, can take one of two values of 0 or 1 with some probabilities P(v_n = 1) and P(v_n = 0) . It may be convenient to define a so-called log-likelihood ratio, LLR, or L-value. L-value may be defined as

Here, log refers to the natural logarithm. As can be seen from the definition of the L-value, a large L-value may imply that the corresponding bit v_n is likely to be a zero, while a low value may imply that the corresponding bit is likely to be a one. Since log 1 = 0, low L-value magnitude, i.e. a L-value close to zero, may imply that there is a large uncertainty in the value of the bit. A set of L-values or a single L-value may be referred to as a message. In addition, a channel can also output codeword L-values. This may be denoted by based on the received vector r.

In LDPC decoding, such as in the sum product, SP, decoding of LDPC codes, the CNs 202 and VNs 201 work in an iterative way, which can be illustrated in the Tanner graph representation of FIG. 3. A so-called flooding schedule may be used. All VNs 201 process their input L-value and pass the extrinsic L-values to their neighbouring CNs 202. The CNs 202 then process their input L-value and output extrinsic L-values to their neighbouring VNs 201. The term“extrinsic” may indicate that the L-value is transmitted to another node. The procedure may repeat until a pre-set maximum number of iterations is reached or some stopping criterion is satisfied. The decoder can then estimate the L-value for each bit v_n, from which the more probable bit value may be deduced.

A so-called box-plus operation can be used by the VNs 201 and the CNs

202 to process the L-values. For two input L-values L₁ and L₂ , the box-plus operation can be defined as

In wireless communication, due to possible noise estimation mismatch in the detector, automatic gain control, AGC, and other front-end components, the L- values fed into an LDPC decoder can be modelled as a scaled version of the true received L-values. This may be referred to LLR mismatch and may cause performance degradation in LDPC decoding.

The computational complexity of LDPC decoding may be reduced using a so-called approximate min*, a-min*, algorithm. Unlike the SP decoding where the CNs compute a unique L-value for every neighbouring VN 201, the a-min* algorithm computes only two magnitudes of L-values per CN 202. The Self- corrected Min-Sum (SCMS) algorithm performs the same CN processing as that of the MS algorithm and differs only in the VN processing.

CN processing for the ga-min* decoder is presented below according to an embodiment. This processing may be implemented by the decoder 100. This CN processing may be combined with some other processing steps performed, for example, in the VNs 201. For example, the CNs 202 may perform processing according to the steps presented below and then pass L-values produced in the processing to VNs 201. The VNs 201 may perform other processing and pass new L-values to the CNs. These steps may be iterated, for example, until a stopping criterion is met.

It should be appreciated that the number of incoming L-values, s'— 1 and s, to the CN for computing critical and non-critical L-values, respectively, is not equal to 1 and d_c. According to an embodiment, s'— 1 and/or s are preconfigured integer values.

According to an embodiment, among all neighbouring VNs of a CN m, VN n_t indicates the VN whose L-value magnitude is the least out of L-values passed to CN m. One of the L-values computed at CN processor is specially send to VN n₁ and the other L-value is sent to the rest of neighbouring VNs of CN m. The L- values corresponding to these two magnitudes may be referred to as critical and non-critical L-values, respectively.

According to an embodiment, the decoder 100 may be configured to initialise L-values in the VNs according to received channel outputs and transmit the initialised L-values from the VNs to the CN. L-values of each VN may be initialised according to the channel outputs

, where n = 0,1, , N— 1. For simplicity, L_ch (v_n \ r) may be denoted by L_n . The outgoing L-values from a VN to its neighbouring CNs may be set as the channel L-values This may

be used as a starting point for the iterative LDPC decoding. The VNs may pass the L-values received from the channel to the CNs, and the CNs may process the L- values.

According to an embodiment, the ga-min* algorithm may be described using the following steps:

1. At a CN m with d_c VN neighbours, sort the magnitude of incoming in an ascending order. Denote the VN with i th smallest

magnitude In the following, L_n. denotes L-values

from VN n_L to CN m instead of

for simplicity. Let

be the resulting two subsets which contain the sorted VN L-values with

where refer to the

number of elements in the subsets S_m and S_m' , respectively. S_m' may be referred to as a first subset, and S_m may be referred to as a second subset.

2. The magnitude of critical CN L-value to VN % may be computed by applying the box-plus operator to VNs in S’_m with an extrinsic sign that is the product of signs

where N(m ) denotes the neighbours of CN m. These may also be referred to as VNs in the neighbourhood of CN m. Herein, notation such as N(m )— n₁ denotes the set N ( m ) excluding the element n₁. Alternatively, this could be notated as

3. For the other VNs in the neighbourhood of CN m, the magnitude of non-critical L-values to may be computed by applying the box-

plus operator to L-values in S_m with an extrinsic sign that is the product of signs of

According to an embodiment, the decoder 100 may be configured to calculate outgoing L-values from each VN to the CN by summing all L-values received to the VN excluding an L-value received from the CN. For example, the extrinsic L-values from VN n to CN M_i are the sum of all L-values that VN n receives from neighboring CNs m₁, m₂, ..., excluding

plus the L-values from channel L_ch, as described by the following equation:

where N(ri) denotes CNs in the neighbourhood of VN n.

For each VN, the total LLR can be computed using the following equation:

Thus, the total LLR may be computed by summing the L-value received from the channel L_n and L-values received from neighbouring CNs N(ri).

The aforementioned steps may be iterated multiple times. In each iteration,

VNs may pass L-values to CNs and vice versa. The iteration may be stopped, when a stopping criterion is met. An estimate of the bit value v_n may be deduced from

The stopping criterion may be, for example or the number of iterations

equals a preconfigured maximum limit.

FIG. 4 illustrates a schematic representation of a Tanner graph of the ga- min* algorithm for a critical L-value according to an embodiment. FIG. 4 illustrates the procedure only for one CN 202 with five neighbouring VNs 201, V₁, V₂ ... V₅. In practice, there may be significantly more CNs 202 in an LDPC code, and this procedure may be used for each such CN 202.

Before the L-values are processed by the CN 202, the magnitudes of L- values may enter a sorting block 203 where the L-values are sorted according their magnitudes. The sorting block 203 may be implemented in software. The sorting may be needed so that L-values with smallest magnitudes can be used for the processing in the CN 202. Alternatively, the L-values with the least magnitude may be found using some procedure other than sorting. A magnitude of an L-value may also be referred to as an absolute value or a modulus.

After the sorting block 203, the VNs 201 may be denoted so that V_n denotes the VN 201’ with the smallest L-value magnitude, and V_n2 201 denotes the VN 201 with the second smallest L-value magnitude, and so on. In the embodiment presented in FIG. 4, s' = 4. The subset S' 401 comprises L-values corresponding to VNs V_n2, V_n3, and V_n4. Therefore, only L-values from V_n,2, V_n3, F„₄ need to be passed into the CN 202, and the CN 202 may calculate an extrinsic L-value based on these three L-values and pass the extrinsic L-value 402 to the VN corresponding to the smallest L-value magnitude V_ni 201

FIG. 5 illustrates a schematic representation of a Tanner graph of the ga min* algorithm for a non-critical L-value according to an embodiment. Similarly to the embodiment of FIG. 4, the magnitudes of L-values may enter a sorting block 203 where the L-values are sorted according their magnitudes so that s smallest L- value magnitudes can be found. Other procedures may also be used to find the smallest magnitudes. In this embodiment, s = 3. Thus, the subset S 501 comprises L-values corresponding to VNs V_ni, V_n2, and V_nr Therefore, only L-values from V_ni, V_n2, V_n3 need to be passed into the CN 202, and the CN may calculate an L- value 502 based on these three L-values. The CN 202 may then pass the L-value 502 to VNs 201 other than the VN 201’ corresponding to the smallest L-value magnitude, i.e. V_n2, V_n3, V_n4, and V_n5.

It should be appreciated that for the embodiments of FIG. 4 and FIG. 5, the L-values need to be sorted only once, and this sorted list may be used for the processing presented in FIG. 4 and FIG. 5. A maximum of s' or s magnitudes need to be sorted, depending on which parameter is greater. For example, in the embodiments presented above, if the L-values are sorted to find s' = 4 smallest L- value magnitudes, the same sorted list may be used to find the s = 3 smallest L- vable magnitudes.

With s' = 4, L-values only from need to be processed by the

CN 202 to calculate the critical L-value 402, and the CN 202 can send the critical L-value 402 to V_n . Similarly, with s = 3, L-values only from need to

be processed by the CN 202 to calculate the non-critical L-value 502, and the CN 202 can send the non-critical L-value 502 to VNs 201 other than This way, the

two magnitudes of L-values in CNs 202 are computed and sent to all neighbouring with ^a reduced number of L-values processed.

The ga-min* procedure has been described above with two parameters s and s'. Since s and s' represent the number of input L-values needed to be sorted, greater s or s' may make the sorting hardware more complex, meanwhile the resulting output may be more accurate. The value of s and s' should be chosen to have a good performance-complexity trade-off. Several embodiments for choosing the value of these two parameters and variants of the ga-min* procedure are given below. As a person skilled in the art can appreciate, configuring s' also configures s'— 1. Thus, these two terms may be used interchangeably.

According to an embodiment, s = 2 or 3 for generating non-critical L- values and s' = 3 or 4 for critical L-values, where s = 2 or 3 and s' = 3 or 4 are chosen to achieve a good complexity and performance trade -off.

According to an embodiment, s'— 1 and/or s are configured according to a threshold, Lth, so that a magnitude of each L-value in the first subset and in the second subset is less or equal to Lth. For example, s and/or s' can be dynamically determined by a threshold L_th such that

According to another embodiment, Lth is determined by Lmin in and a factor b, wherein b indicates a proportion between Lth and Lmin. For example, L_th can be determined using the factor b so that or Like

above, denotes L-values with the smallest magnitude. For example, if

The number of incoming L-

values processed by CN m , s or s’, comprises all i e {1, 2, ... , d_c} such that

According to an embodiment, s’-1 and/or s are configured according to the number of L-values received to the CN, d_c, and a factor l, wherein l indicates a proportion between d_c and s or between d_c and s’-1. For example, s or s' can be based on the factor l and the degree d_c of the CN m. Degree refers to the number of neighbours connected to the CN m. For example, s = ceil(ld_c), where ceil is the ceiling function. Thus, a predetermined proportion of all L-values d_c transmitted to the CN may be used for the processing in the CN. For example, if d_c = 15 and l = 0.2, s =ceil(15 x 0.2) = 3.

According to an embodiment, the decoder 100 may be configured to rescale the L-values received to the CN 202 by multiplying each received L-value by a factor. For example, in the absence of LLR mismatch, the input L-values may be rescaled by multiplying them by a factor m. For example, m = 2 may be used for the ga-min* with s = 2 and s' = 3 to possibly achieve better performance.

According to an embodiment, an outgoing L-value of a VN 201 is set to zero, if a sign of the outgoing L-value changes between two consecutive iterations. In some embodiments, VNs 201 may utilise so-called self-corrected, SC, processing. The SC processing may be combined with any embodiment described herein. In the SC processing, VN n may first compute a temporary L-value

to CN m. The temporary L-value may get erased, i.e if there is a sign

change of the L-values between the current iteration i and previous iteration i— 1. Otherwise, the extrinsic L-value of the VN 201 is set to be equal to the temporary L-value l^(L) _{n m}. This way, unreliable L-values can be detected by sign fluctuation. By erasing these unreliable L-values, improved decoding performance may be achieved, and decoding may be robust even in noisy conditions.

FIG. 6 and FIG. 7 illustrate schematic representations of simulation results according to an embodiment. In the simulation presented in FIG. 6, information length K = 4224 and code rate R = 1/3, while in the simulation of FIG. 7 , K = 960 and R = 1/5. In these simulations, additive white Gaussian noise, AWGN, channel with binary phase-shift keying, BPSK, modulated transmission was used. The block error rate, BLER, was simulated down to approximately 10^-2 , since this may be the primary target rate in NR eMBB. An LDPC code in each BG was selected with the lowest rate. For simplicity, in the simulation, s = s'— 1 in the (sc)ga-min*, and s = 2 or 3. scga-min* refers to the ga-min* algorithm with SC processing. Other simulated algorithms were, sum product, SP, approximate min*, a-min*, self-correcting a-min*, sca-min*, self-correcting minimum sum, SCMS, and normalised minimum sum, NMS.

Given information length K, the lowest rate, i.e. 1/3 in BG1 and 1/5 in BG2, seems to lead biggest performance gaps between SP algorithm and other iterative decoding algorithms. With s = 2, the ga-min*, illustrated by curves 601 and 701, has 0.3dB and 0.2dB loss to the SP algorithm in these two codes, respectively. With s = 3, the gap reduces to O.ldB. The performance gap is less than 0.05dB in the first code and almost overlapped with the a-min* in the second. Meaning that with s = 3 , the CN processing of both critical and non-critical L-values are good approximations of those in the a-min*.

The performance of the sca-min* and the a-min* is fairly close. Under this condition, SC technique seems to have no prominent effect in improving the performance. Similar condition can account for the close performance between the scga-min*, illustrated by curves 604 and 704, and the ga-min*, illustrated by curves 602 and 702, with s = 3, where the CN L-value is close enough to that of the a- min*, as mentioned above.

However, with s = 2, scga-min*, illustrated by curves 603 and 703, seems to outperform ga-min* by 0.2dB and also slightly better than the performance of a- min*. This may indicate that the SC technique can achieve a performance boost when the critical L-value in the CN of the ga-min* is over-estimated. An even bigger performance gain of 0.4dB, can be observed between the SCMS and the NMS. In this case, the SC technique seems to also be powerful in improving the performance.

FIG. 8 and FIG. 9 illustrate schematic representations of simulation results according to an embodiment. In both simulations, K = 4224 and R = 1/3, and L- values fed into the decoder were scaled by a constant r?. If h > 1, this may be referred to as LLR over estimation. If h < 1, this may be referred to as LLR under estimation. FIG. 8 illustrates simulation results when h = 1/2 , and FIG. 9 illustrates simulation results when h = 2.

The ga-min*, illustrated by curves 801 and 901, and scga-min*, illustrated by curves 803 and 903, seem to show superiority in performance compared to other iterative algorithms for both h values. The SP and a-min* decoder seem to be very sensitive to both SNR underestimation (h = 1/2) in FIG. 8 and over-estimation (h = 2) in FIG. 9. There can be at least ldB loss to the performance compared to the absence of LLR mismatch as presented in FIG. 6. The SCMS and scga-min* with s = 2 show signs of robustness in both LLR under-estimation and over-estimation scenarios. Specifically, the performance of the SCMS is similar in both cases, whereas only 0.2dB and O.ldB degradation for LLR underestimate and overestimate, respectively, can be observed in the scga-min* with s = 2. For LLR under-estimation, the ga-min* even outperforms the one in the absence of LLR mismatch by O.ldB, but it degrades drastically for LLR over-estimation. When SC is applied to the ga-min* with s = 2, the robustness of the performance can be enhanced against LLR mismatch.

FIG. 10 illustrates a schematic representation of a table 1000 comparing a number of box-plus operations between ga-min* and a-min* according to an embodiment. In ga-min*, the box-plus operator may be used only s times per CN, compared to d_c— 1 times in a-min*. The saving in the box-plus operations may be at the cost of sorting incoming L-values of size s + 1, which may be relatively inexpensive to implement in hardware for the cases of s = 2 or s = 3. Table of FIG. 10 illustrates a complexity comparison with respect to box-plus operation savings for various code rates of NR LDPC codes. The highest rate has the highest average row weight d_c due to the high CN degree in the core graph, resulting in greatest savings, namely 86% for s = 2 and 80% for s = 3 in BG1, and 69% for s = 2 and 53% for s = 3 in BG2. For lower rates, more CNs are included in the extension graph, which lowers d_c, and the complexity saving is 66% for s = 2 and 49% for s = 3 in BG1, and 46% for s = 2 and 19% for s = 3 in BG2.

FIG. 11 illustrates a flow diagram of a method according to an embodiment.

At 1100 L-values are received to a check node, CN, from neighbouring variable nodes, VNs.

At 1102 a first subset of L-values is selected from the received L-values comprising .s’- 1 received L-values with smallest magnitudes excluding a received L-value with a smallest magnitude, Lmin.

At 1104 processing the first subset of L-values is processed in the CN to produce a first extrinsic L-value. At 1106 the first extrinsic L-value is passed to a neighbouring VN corresponding to Lmin.

At 1108 a second subset of L-values is selected from the received L-values comprising s received L-values with smallest magnitudes.

At 1110 the second subset of L-values is processed in the CN to produce a second L-value.

At 1112 the second L-value is passed to the neighbouring VNs excluding the VN corresponding to Lmin.

The steps 1 100-1112 may be implemented by the decoder 100 discussed in relation to FIG. 1.

The functionality described herein can be performed, at least in part, by one or more computer program product components such as software components. According to an embodiment, the decoder 100 comprises the processor 101 configured by the program code when executed to execute the embodiments of the operations and functionality described. Alternatively, or in addition, the functionality described herein can be performed, at least in part, by one or more hardware logic components. For example, and without limitation, illustrative types of hardware logic components that can be used include Field-programmable Gate Arrays (FPGAs), Program-specific Integrated Circuits (ASICs), Program-specific Standard Products (ASSPs), System-on-a-chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), Graphics Processing Units (GPUs).

Any range or device value given herein may be extended or altered without losing the effect sought. Also any embodiment may be combined with another embodiment unless explicitly disallowed.

Although the subject matter has been described in language specific to structural features and/or acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as embodiments of implementing the claims and other equivalent features and acts are intended to be within the scope of the claims.

It will be understood that the benefits and advantages described above may relate to one embodiment or may relate to several embodiments. The embodiments are not limited to those that solve any or all of the stated problems or those that have any or all of the stated benefits and advantages. It will further be understood that reference to 'an' item may refer to one or more of those items. The term‘and/or’ may be used to indicate that one or more of the cases it connects may occur. Both, or more, connected cases may occur, or only either one of the connected cases may occur.

The operations of the methods described herein may be carried out in any suitable order, or simultaneously where appropriate. Additionally, individual blocks may be deleted from any of the methods without departing from the spirit and scope of the subject matter described herein. Aspects of any of the embodiments described above may be combined with aspects of any of the other embodiments described to form further embodiments without losing the effect sought.

The term 'comprising' is used herein to mean including the method, blocks or elements identified, but that such blocks or elements do not comprise an exclusive list and a method or apparatus may contain additional blocks or elements.

It will be understood that the above description is given by way of example only and that various modifications may be made by those skilled in the art. The above specification, embodiments and data provide a complete description of the structure and use of exemplary embodiments. Although various embodiments have been described above with a certain degree of particularity, or with reference to one or more individual embodiments, those skilled in the art could make numerous alterations to the disclosed embodiments without departing from the spirit or scope of this specification.

Claims

1. A decoder (100) for decoding low-density parity-check codes, configured to:

receive L-values to a check node (202), CN, from neighbouring variable nodes (201), VNs;

select a first subset (401) of L-values from the received L-values comprisings ' - 1 received L-values with smallest magnitudes excluding a received L-value with a smallest magnitude, Lmin;

process the first subset of L-values in the CN to produce a first extrinsic L- value (402);

pass the first extrinsic L-value to a neighbouring VN (201’) corresponding to Lmin;

select a second subset (501) of L-values from the received L-values comprising s received L-values with smallest magnitudes;

process the second subset of L-values in the CN to produce a second L-value (502); and

pass the second L-value to the neighbouring VNs excluding the VN corresponding to Lmin.

2. The decoder (100) of claim 1, further configured to:

initialise L-values in the VNs according to received channel outputs; and transmit the initialised L-values from the VNs to the CN.

3. The decoder (100) of any preceding claim, further configured to:

calculate outgoing L-values from each VN to the CN by summing all L- values received to the VN excluding an L-value received from the CN.

4. The decoder (100) of any preceding claim, wherein s’ - 1 and/or s are preconfigured integer values.

5. The decoder (100) of any preceding claim, wherein an outgoing L-value of a VN is set to zero, if a sign of the outgoing L-value changes between two consecutive iterations.

6. The decoder (100) of any preceding claim, wherein s’ - 1 and/or s are configured according to a threshold, Lth, so that a magnitude of each L-value in the first subset and in the second subset is less or equal to Lth.

7. The decoder (100) of claim 6, wherein Lth is determined by Lmin and a factor b, wherein b indicates a proportion between Lth and Lmin.

8. The decoder (100) of claim 7, wherein

9. The decoder (100) of any of claims 1 - 5, wherein s’-1 and/or s are configured according to the number of L-values received to the CN, d_c, and a factor l, wherein l indicates a proportion between d_cand s or between d_c and s’-1.

10. The decoder (100) of claim 9, wherein

11. The decoder (100) of any preceding claim, further configured to:

rescale the L-values received to the CN by multiplying each received L- value by a factor.

12. A method, comprising:

receiving (1100) L-values to a check node, CN, from neighbouring variable nodes, VNs;

selecting (1102) a first subset of L-values from the received L-values comprising .s’- 1 received L-values with smallest magnitudes excluding a received L-value with a smallest magnitude, Lmin;

processing (1104) the first subset of L-values in the CN to produce a first extrinsic L-value;

passing (1106) the first extrinsic L-value to a neighbouring VN corresponding to Lmin;

selecting (1108) a second subset of L-values from the received L-values comprising s received L-values with smallest magnitudes;

processing (1100) the second subset of L-values in the CN to produce a second L-value; and passing (1102) the second L-value to the neighbouring VNs excluding the VN corresponding to Lmin.

13. A computer program comprising program code configured to perform a method according to claim 12 when the computer program is executed on a computer.