WO2020042888A1

WO2020042888A1 - Method and apparatus for digitizing scintillation pulse

Info

Publication number: WO2020042888A1
Application number: PCT/CN2019/099904
Authority: WO
Inventors: 陈瑞; 奚道明; 刘苇; 曾晨
Original assignee: 苏州瑞迈斯医疗科技有限公司
Priority date: 2018-08-29
Filing date: 2019-08-09
Publication date: 2020-03-05
Also published as: CN109274369B; CN109274369A

Abstract

A method and apparatus for digitizing a scintillation pulse. The method comprises: step S1: setting n theoretical threshold voltages according to a multiple-voltage threshold sampling requirement; step S2: calculating pulse width modulation characteristics according to the value of the theoretical threshold voltages, and using an I/O port of an FPGA to respectively generate, according to the pulse width modulation characteristics, n paths of pulse width modulation signals corresponding to different theoretical threshold voltages; step S3: inputting the n paths of pulse width modulation signals to filtering circuits, and generating n corresponding threshold voltage signals; step S4: respectively inputting a scintillation pulse signal to be sampled and n threshold voltage signals into n comparators of the FPGA and performing voltage comparison; and step S5: using a time-to-digital conversion unit inside the FPGA to collect threshold voltage-time pairs according to the comparison results of the n comparators. A filtering circuit constructed by resistors and capacitors is used to replace a DAC to complete MVT sampling, and the structure is simple, so that costs can be reduced greatly and system power consumption and the area of a PCB circuit can be reduced.

Description

Method and device for digitizing flicker pulse

Technical field

The present application relates to the field of signal processing, and more particularly, to a method and a device for digitizing a flicker pulse.

Background technique

MVT (Multi-Voltage Threshold, multi-threshold voltage) sampling method is a method of digitizing flicker pulses that is different from time interval sampling. It sets n threshold voltages Vth according to the characteristics of flicker pulses. It uses n low-voltage differential signal receiving ports. Voltage comparator, when the flicker pulse to be sampled crosses any threshold voltage Vth, the voltage comparator outputs a state transition and the threshold voltage Vth corresponding to the state transition; and then uses a time-to-digital converter (ie, TDC) to check the state The transition time is digitally sampled; at the same time, the threshold voltage Vth corresponding to the state transition is identified, and the flicker pulse voltage time pair is obtained to complete the digital sampling of the flicker pulse.

In a traditional MVT sampling application circuit, a field programmable gate array (ie, FPGA) is used to generate control signals to configure a digital analog converter (DAC) chip to generate a DC threshold voltage signal. Generally, in order to ensure the performance of the DAC chip, it is necessary to provide a reference voltage for the DAC chip through an external highly stable voltage reference source; and then input the flicker pulse and the threshold voltage signal to the low-voltage differential signal port of the FPGA at the same time, that is, LVDS port), the LVDS port acts as a voltage comparator, and uses the FPGA internal resources to build a TDC to record the state transition time of the LVDS port. The threshold voltage time pair is obtained through the above steps, and the digital sampling of the flicker pulse is completed. The overall structure is shown in FIG. 1.

As can be seen from Figure 1, the overall structure of the traditional MVT sampling application circuit includes at least important components such as DAC chips and peripheral configuration circuits, voltage reference sources, FPGAs, etc. There are many components in the system, and analog circuits and digital circuits are intermixed, and the overall circuit structure is complex . At the same time, taking the PET system detector module as an example, the channel of a single 6 × 6 probe module is usually 36, and the number of flicker pulse signals generated is 36. In order to ensure the sampling performance, each threshold of the flicker pulse signal is set to correspond to 4 thresholds. Voltage, so the total number of output channels of the DAC chip is required to be 36 × 4 = 144. However, in the prior art, the number of output channels of DAC chips with a general accuracy of more than 12 bits is mostly 8 channels. Therefore, the number of 8-channel DAC chips required to complete the 36-channel flicker pulse digital sampling is 144 ÷ 8 = 18. The official selling price of a single 12-bit 8-channel DAC chip usually requires a minimum of $ 4.75, so the cost of the circuit that generates only the voltage threshold is at least $ 4.75 x 18 = $ 85.5, and the average cost of each channel is $ 2.375. In addition, plus the cost of external voltage reference and FPGA, the cost of the entire MVT sampling circuit will be extremely high. At the same time, as the accuracy of the DAC chip increases and the number of integrated channels increases, the cost of the DAC chip part will also rise sharply. For a PET system, the number of signal channels usually reaches tens of thousands, so this will make the cost of the PET system increase sharply.

Application content

The purpose of this application is to provide a method and a device for digitizing a flicker pulse, thereby solving the problem that the cost of flicker pulse signal sampling in the prior art is too high.

In order to solve the above technical problem, the technical solution of the present application is to provide a method for digitizing a flicker pulse, which includes the following steps:

Step S1: Set n theoretical threshold voltages according to the requirements of multi-threshold voltage sampling, where n is a natural number;

Step S2: Calculate a pulse width modulation characteristic according to the value of the theoretical threshold voltage, and use an input / output port of the FPGA to generate n pulse width modulation signals corresponding to the theoretical threshold voltage according to the pulse width modulation characteristic;

Step S3: input n pulse-width modulation signals into a filter circuit to generate corresponding n threshold voltages;

Step S4: input the flicker pulse signal to be sampled and n threshold voltage signals into n comparators of the FPGA and perform voltage comparison;

Step S5: Use a time-to-digital conversion unit inside the FPGA to collect threshold voltage-time pairs according to the comparison results of n comparators.

According to an embodiment of the present application, the multi-threshold voltage sampling requirement includes one and / or several of spatial resolution, temporal resolution, and energy resolution.

According to an embodiment of the present application, the multi-threshold voltage sampling requirement is obtained by the following method: establishing a database according to the acquired threshold voltage-time pairs, and performing waveform reconstruction to extract the spatial resolution, temporal resolution, and Energy resolution.

According to an embodiment of the present application, the setting of the theoretical threshold voltage may be performed by the following method: determining a voltage amplitude range of the flicker pulse signal to be sampled, and at least one of the theoretical threshold voltages is located in the flicker pulse to be sampled Within the voltage amplitude of the signal.

According to an embodiment of the present application, a specific method for calculating the pulse width modulation characteristic includes:

Step S21: Determine the level of the output port corresponding to the pulse width modulation signal to be generated according to the theoretical threshold voltage;

Step S22: Calculate the duty cycle D of the pulse width modulation signal according to the following formula.

D = theoretical threshold voltage / level of the corresponding output port,

Wherein, the duty ratio D represents the percentage of the duration of the high level of the pulse width modulation signal output by the output port in a period to the entire signal time;

In step S23, it is determined that the pulse width modulation characteristic of the pulse width modulation signal to be generated is: the duty ratio D, and the maximum amplitude value is the level of the corresponding output port.

According to an embodiment of the present application, the specific method for the FPGA to generate a pulse width modulation signal is: according to the duty ratio D, using a timer unit inside the FPGA to control the period and high level of a single pulse width modulation signal duration.

According to an embodiment of the present application, a specific method for inputting n channels of the pulse width modulation signal into a filter circuit is: directly accessing the filter circuit at the back end of the pulse width modulation signal, or in the pulse width modulation signal After filtering, the filter circuit is connected.

According to an embodiment of the present application, the filter circuit is a 4-order filter circuit.

According to an embodiment of the present application, the fourth-order filter circuit includes four resistors R1, R2, R3, and R4 connected in series, and the pulse width modulation signal generated is connected to the filter circuit through the resistor R1, where The resistor R1 and the resistor R2 are connected to the ground through a capacitor C1, the resistor R2 and the resistor R3 are connected to the ground through a capacitor C2, and the resistor R3 and the resistor R4 are connected to each other through a capacitor C3. The terminal of the resistor R4 is connected to the ground through a capacitor C4, and the terminal of the resistor R4 is also responsible for outputting the filtered threshold voltage.

According to an embodiment of the present application, in the step S4, a voltage comparison is performed between the flicker pulse signals to be sampled and n threshold voltage signals through a low-voltage differential signal comparator.

According to an embodiment of the present application, the time-to-digital conversion unit includes a first counter and a second counter, and the first time value output by the first counter and the second time value output by the second counter are combined to The edge arrival time of the flicker pulse signal is obtained. The time-digital conversion unit compares the edge arrival time of the flicker pulse signal with the threshold voltage signal, and records the time information corresponding to the high and low level state transitions and the time information. Threshold voltage information.

According to an embodiment of the present application, the method further includes step S6: repeating the above steps S1 to S5 to obtain threshold voltage time pairs of multiple sets of flicker pulse signals, and digitize the flicker pulse signals.

According to an embodiment of the present application, the threshold voltage time pair includes a threshold voltage and time corresponding to a flicker pulse signal at each sampling point, or a threshold voltage and time corresponding to each sampling point after several samplings. average value.

The present application also provides a device for digitizing a flicker pulse according to the above method. The device includes: an FPGA configured to set n theoretical threshold voltages according to a multi-threshold voltage sampling requirement. The FPGA has input / output. Port, the input / output port is configured to generate a pulse width modulation signal according to the theoretical threshold voltage; a filter circuit is configured to convert the pulse width modulation signal to a threshold voltage signal; the FPGA also The comparator includes a comparator and a time-to-digital conversion unit. The comparator is configured to receive a flicker pulse signal to be sampled and compare with the threshold voltage signal. The time-to-digital conversion unit is configured to be based on a comparison result of the comparator. Acquisition threshold voltage-time pairs.

According to an embodiment of the present application, at least one of the theoretical threshold voltages is within a voltage amplitude range of the flicker pulse signal to be sampled.

According to an embodiment of the present application, the input / output port of the FPGA is a low-voltage differential signal port.

According to an embodiment of the present application, the fourth-order filter circuit includes four resistors R1, R2, R3, and R4 connected in series, wherein the resistor R1 and the resistor R2 are connected to each other through a capacitor C1 and grounded. The resistor R2 and the resistor R3 are connected to the ground through a capacitor C2, the resistor R3 and the resistor R4 are connected to the ground through a capacitor C3, and the end of the resistor R4 is connected to the ground through the capacitor C4. The pulse width modulation signal is connected to a filter circuit through the resistor R1, and the filtered threshold voltage is output through an end of the resistor R4.

According to an embodiment of the present application, the comparator is a low-voltage differential signal comparator.

The method and device for digitizing the flicker pulse provided in the present application generate a PWM signal through an FPGA and generate a DC threshold voltage signal after a multi-stage RC filter circuit constructed by a resistor and a capacitor, thereby replacing the circuit function of the DAC part and completing the MVT sampling. Compared with the traditional MVT sampling circuit, because the multi-stage RC filter circuit is built by the back-end FPGA and a small number of resistors and capacitors to generate the threshold voltage signal, the DAC and voltage reference circuit are eliminated, and the flicker pulse can be digitized by using the FPGA alone Sampling makes the whole circuit structure simple. At the same time, in terms of performance, the quality of the DC threshold voltage signal generated by the PWM signal through a 4th-order RC low-pass filter circuit (which is composed of 4 resistors and 4 capacitors) is equivalent to the output of a 12-bit precision DAC. Capacitors are very common basic electronic components and are inexpensive. Usually a resistor or capacitor is priced at about 0.001 USD, so its single channel cost is about 0.001 * 8 * 4 = 0.032 USD, which is relative to the cost of a single channel DAC. Can greatly reduce costs, while reducing system power consumption and PCB circuit area.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to explain the technical solutions in the embodiments of the present application or the prior art more clearly, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without paying creative labor.

1 is a schematic structural diagram of a multi-threshold voltage sampling application circuit according to the prior art;

2 is a schematic diagram of steps of a method for digitizing a flicker pulse according to a preferred embodiment of the present application;

3 is a schematic diagram of a fourth-order RC filter circuit used in a device for digitizing a flicker pulse according to an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a device for digitizing a flicker pulse according to FIG. 2.

detailed description

The following further describes this application with reference to specific embodiments. It should be understood that the following examples are only used to illustrate the present application and not to limit the scope of the present application.

It should be noted that when an element is referred to as being “disposed on” another element, it may be directly disposed on another element or a centered element may exist. When an element is referred to as being "connected / coupled" to another element, it can be directly connected / coupled to the other element or intervening elements may be concurrently present. The term "connected / coupled" as used herein may include electrical and / or mechanical physical connections / couplings. The term "including / comprising" as used herein refers to the presence of a feature, step, or element, but does not exclude the presence or addition of one or more other features, steps, or elements. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application.

It should be noted that, in this application, the terms “input terminal” and “output terminal” may also be referred to as “input interface” and “output interface”, respectively.

FIG. 2 is a schematic diagram of steps of a method for digitizing a flicker pulse according to a preferred embodiment of the present application. As can be seen from FIG. 2, the method for digitizing a flicker pulse provided by the present application includes the following steps:

Step S1: Set n theoretical threshold voltages according to the MVT sampling requirements, and record the n theoretical threshold voltages as V1, V2, V3, ..., Vn, where n is a natural number;

In step S1, the MVT sampling requirement generally refers to one and / or several requirements for achieving spatial resolution, temporal resolution, and energy resolution. For different MVT sampling requirements, you can set them during MVT sampling. Different theoretical threshold voltage size, theoretical threshold voltage number, sampling time and other parameters are implemented.

Further, those skilled in the art may establish a database based on data of a large number of threshold voltage-time pairs that have been collected, and perform waveform reconstruction based on the collected data of the threshold voltage-time pairs, to obtain a reconstructed waveform, thereby extracting the spatial resolution of the flicker pulse, Information such as time resolution and energy resolution. On the basis of the database, in order to obtain more accurate information, those skilled in the art can reasonably set the theoretical threshold voltage and theoretical threshold voltage of MVT sampling based on the empirical information obtained from the database. , Sampling time and other parameters to meet different energy, time resolution and energy resolution requirements.

In step S1, the setting of the theoretical threshold voltage may be completed by determining the voltage amplitude range of the flicker pulse signal to be sampled, and selecting a theoretical threshold voltage of different amplitude according to the voltage amplitude of the flicker pulse signal to be sampled, so that All theoretical threshold voltages are within the amplitude range of the flicker pulse signal to be sampled; or different theoretical threshold voltages of different amplitudes are selected according to the voltage amplitude of the flicker pulse signal to be sampled, so that at least one of the set theoretical threshold voltages is set Within the amplitude range of the flicker pulse signal to be sampled.

Step S2: Calculate the pulse width modulation (PWM) characteristics according to the theoretical threshold voltage value set in step S1, and use the input / output ports (also known as I / O ports) of the FPGA according to the PWM characteristics. Generate n PWM signals corresponding to the theoretical threshold voltage, and record them as P1, P2, P3, ..., Pn, respectively;

In step S2, the specific method for calculating the PWM characteristic according to the value of the theoretical threshold voltage set in step S1 includes:

Step S21: Determine the level Vpwm of the output port corresponding to the PWM signal to be generated according to the theoretical threshold voltage;

Step S22: Calculate the duty cycle D of the PWM signal according to the following formula.

D = Vn / Vpwm,

The duty ratio D indicates the duration of the high level of the signal output by the output port in one cycle as a percentage of the total signal time;

In step S23, it is determined that the PWM characteristics of the PWM signal to be generated are: the duty ratio D and the maximum amplitude Vpwm (that is, the level of the output port).

Further, the following illustrates the calculation method of the PWM characteristics. If the theoretical threshold voltage set in step S1 is 1.65V, that is, the theoretical threshold voltage generated by the FPGA in step S2 is 1.65V. According to the characteristics of the FPGA, the I of the FPGA can be known. The level of the / O port is 3.3V, that is, the level of the output port corresponding to the PWM signal to be generated is 3.3V, then the calculated duty cycle D = 1.65V / 3.3V = 50%, at this time the 1.65V The PWM characteristics of the PWM signal corresponding to the theoretical threshold voltage are: a duty cycle of 50% and a maximum amplitude of 3.3V.

In step S2, a specific method for generating a PWM signal by using the I / O port of the FPGA is: According to the level Vpwm of the output port of the FPGA, the theoretical threshold voltage Vn, the calculated duty cycle D of the PWM signal is used. The timer unit controls the period and high-level duration of a single signal. At this time, the output signal is a PWM signal that meets the duty cycle requirements.

Further, the following example illustrates the method of generating a PWM signal: assuming that 12-bit timer units are used internally in FPGAN, and the period of each timer unit is T, then the period of a PWM signal is 212 × T = 4096T, which generates a high level The time is set to TH = 4096T × D, and the time to generate a low level is TL = 4096T × (1-D).

Step S3: input the n PWM signals generated in step S2 to the n filter circuits, generate corresponding n threshold voltage signals and record them as Vt1, Vt2, Vt3, ..., Vtn;

In the above step S3, the specific method for inputting the n-channel PWM signals generated in step S2 into the m-order filter circuit may be directly connected to the filter circuit at the back end of the PWM signal, or after the PWM signal is passed through other filtering processes. Then access the filter circuit.

FIG. 3 is a schematic diagram of an m-order filter circuit according to an embodiment of the present application, where m = 4. As can be seen from FIG. 3, the 4-order filter circuit includes four resistors R1, R2, R3, and R4 connected in series. The PWM signal is connected to the filter circuit through the resistor R1. Among them, the resistor R1 and the resistor R2 are connected to the ground through the capacitor C1, the resistor R2 and the resistor R3 are connected to the ground through the capacitor C2, and the resistor R3 and the resistor R4 are connected through the capacitor C3. After connecting, it is grounded. The end of resistor R4 is connected to ground through capacitor C4. The end of resistor R4 is also responsible for outputting the filtered threshold voltage. The filter circuit filters the PWM signal and filters the high-frequency signal in the PWM signal to make the ripple smaller and the output smooth.

Step S4: input the flicker pulse signal to be sampled and the n threshold voltage signals Vt1, Vt2, Vt3, ..., Vtn to the n comparators of the FPGA respectively for voltage comparison;

In step S4, the comparator can be any voltage comparator that meets the requirements, preferably an LVDS comparator. Compared with a conventional voltage comparator chip, the LVDS comparator has the advantages of low cost, high integration, and low power consumption. For example, conventional FPGA chips have LVDS ports, and the number is large.

Step S5: use a time-to-digital conversion unit inside the FPGA to collect threshold voltage-time pairs according to the comparison results of the n comparators;

In step S5, the time-to-digital conversion unit may be formed by a logic unit inside the FPGA. The function of the time-to-digital conversion unit is to measure the edge arrival time (including rising and falling edges) of the flicker pulse signal and determine when the flicker pulse signal is high. Level and when it is low to control the collected data. The time-to-digital conversion unit may include a coarse counter (first counter) and a fine counter (second counter). The coarse time value (first time value) output by the coarse counter and the fine time value (second time value) output by the fine counter. ) According to a certain relationship, the edge arrival time of the flicker pulse signal can be obtained. The time-digital conversion unit compares the edge arrival time of the flicker pulse signal with the threshold voltage signal, and records the corresponding response when the high and low state transitions. The time information and the threshold voltage information corresponding to the time information form a threshold voltage-time pair of the flicker pulse signal.

Specifically, the coarse counter is driven by a clock signal, and after each clock cycle, the count value output by the coarse counter is increased by 1, and the current coarse value is obtained by multiplying the current count value by one clock cycle. When the edge of the trigger signal s comes, the time-to-digital converter records the count value of the coarse counter output at this moment, and records it as N. If the clock period is recorded as Tc, the coarse time of the edge arrival of the trigger signal s can be expressed as N * Tc. The time measurement accuracy of the coarse counter is based on the clock cycle, but for FPGAs, the frequency of the clock signal cannot be increased without limit. To further improve the time measurement accuracy, a fine counter needs to be introduced. The implementation of the fine counter is based on a delay line that outputs a temperature code. The temperature code includes several 0s and 1. The temperature code on the delay line is characterized by all 0s on one side and 1,0 and 1 on the other side. The relationship between the elimination of each other, and the sum of the number of 0s and the number of 1s is equal to the total length of the temperature code. For example, 1110000 is a piece of temperature code composed of 3 1s and 5 0s. By counting the number of 0 or 1, and multiplying the length of time represented by each 0 or 1, the fine time of the edge of the signal to be measured on the delay line can be calculated. Therefore, the edge arrival time of the trigger signal s is equal to the sum of the coarse time and the fine time. With the help of a delay line, the time measurement accuracy of the time-to-digital converter can be improved to better than 100 picoseconds.

More specifically, the clock distribution device uses logic units on the FPGA to form a delay line. The essence of a delay line is a serial adder composed of several full adders. Each full adder has ports for carry inputs and outputs. These The ports are connected end to end, and the carry output of the full adder in the upper stage is connected to the carry input of the full adder in the next stage. For convenience of description, for example, the bit width of the serial adder is 8 bits. The serial adder has two inputs, one of which is set to an 8-bit binary constant 11111111, and the other is a digitized signal to be tested ( For example, the trigger signal s), the part less than 8 bits is filled with 0. When the rising edge of the signal to be measured arrives, the digital level of the signal to be measured changes from 0 to 1, the calculation result of the serial adder does not immediately become all 0, the calculation of the full adder closest to the signal to be measured first The result becomes 0, and then the carry signal of this full adder changes from 0 to 1 and is passed to the next stage; the calculation result of the full adder in the second stage then becomes 0, and its carry signal changes from 0 to 1. Then pass to the next level, and so on. The transfer of the carry signal takes time. The time from the n-th full adder to the carry signal to the n + 1 th full adder to generate the carry signal is usually less than 100 picoseconds, and the temperature code contains 0 for each level of the carry signal. Add 1 to the number.

Similarly, when the digital level of the signal to be measured changes from 1 to 0, the calculation result of the serial adder does not immediately become all 1, the calculation result of the full adder closest to the signal to be measured first becomes 1, Its carry signal is changed from 1 to 0 and passed to the next stage until the calculation result of all full adders becomes 1.

The time-to-digital conversion unit uses a clock signal (same as the clock signal of the coarse counter) to sample the temperature code output from the delay line. When the most significant bit (MSB) side of the temperature code is 1 and the least significant bit (LSB) side is 0, it indicates that the rising edge of the signal is detected, and the number of 0 in the temperature code output on the delay line is counted. The value as a fine count. When the most significant bit (MSB) side of the temperature code is 0 and the least significant bit (LSB) side is 1, it indicates that the falling edge of the signal is detected, and the number of 1 in the temperature code output on the delay line is counted. As a fine count. For an 8-bit temperature code, the number of 1 or 0 contained in the temperature code is 0 to 8, which can be represented by a 4-bit binary number, but in the actual implementation process of this application, the time-to-digital converter uses a 128-bit temperature Code, the temperature code contains 1 or 0, the number is 0 to 128, expressed by an 8-bit binary number. The above conversion process of temperature code to fine count is completed by the encoder.

For each edge of the trigger signal s, the time-to-digital conversion unit will give a coarse count and a fine count. The edge arrival time of the trigger signal s is T = Tc × N-To × M, where the coarse time is Tc × N and the fine time is To × M; Tc is one clock cycle, which is a known value; N is the count of the coarse count Value; To is the average time of each temperature code carry on the delay line; M is the count value of the fine count.

Step S6: Repeat the above steps S1-S5 to obtain the threshold voltage time pair of the flicker pulse signal, and complete the digitization of the flicker pulse signal.

In step S6, the threshold voltage time pair of the flicker pulse may include the threshold voltage and time corresponding to the flicker pulse signal at each sampling point, and may also include the threshold voltage and time corresponding to each sampling point after several samplings. average of.

FIG. 4 is a schematic structural diagram of a device for digitizing a flicker pulse using the above method. As can be seen from FIG. 4, the device includes FPGA 10, and the FPGA 10 has a comparator 11 and a time-to-digital conversion unit 12 formed by using its own logic unit. The comparator 11 and time The digital conversion unit 12 is communicatively connected. The flicker pulse signal to be sampled externally is input to the comparator 11 through the interface. The FPGA 10 sends a PWM signal to the filter circuit 20 connected to the FPGA 11 through the I / O port 13. The filter circuit 20 and the other of the comparator 11 are PWM signals. The port is communicatively connected and sends a threshold voltage signal to the comparator 11.

Specifically, according to an embodiment of the present application, the FPGA 10 is configured to set n theoretical threshold voltages according to MVT sampling requirements, and the n theoretical threshold voltages are respectively denoted as V1, V2, V3, ..., Vn, where: n is a natural number.

MVT sampling requirements generally refer to one and / or several of the requirements of spatial resolution, time resolution, and energy resolution. For different MVT sampling requirements, different theoretical threshold voltages can be set during MVT sampling Size, theoretical threshold voltage, sampling time and other parameters.

Further, a person skilled in the art may establish a database based on data of a large number of threshold voltage time pairs that have been collected, and perform waveform reconstruction based on the collected data of the threshold voltage time pairs, to obtain a reconstructed waveform, thereby extracting the spatial resolution and time of the flicker pulse. Information such as resolution and energy resolution. On the basis of the database, in order to obtain more accurate information, those skilled in the art can reasonably set the theoretical threshold voltage magnitude, theoretical threshold voltage number, Sampling time and other parameters to meet different energy, time resolution and energy resolution requirements.

The determination of the theoretical threshold voltage can be accomplished by: determining the voltage amplitude range of the flicker pulse signal to be sampled, and selecting the theoretical threshold voltage of different amplitudes according to the voltage amplitude of the flicker pulse signal to be sampled, so that all the theoretical threshold voltages are equal; Is located within the amplitude range of the flicker pulse signal to be sampled; or a theoretical threshold voltage of different amplitude is selected according to the voltage amplitude of the flicker pulse signal to be sampled, so that at least one of the set theoretical threshold voltages is located in the flicker to be sampled Within the amplitude of the pulse signal.

According to an embodiment of the present application, the performance parameters of the FPGA 10 can be configured to have 114480 logic units, the number of user-available I / O ports is 528, and the number of LVDS ports is up to 230 pairs.

According to an embodiment of the present application, the FPGA 10 may be configured to calculate a PWM characteristic of a pulse signal according to the value of the theoretical threshold voltage Vn, and the I / O port 13 of the FPGA 10 is configured to generate a signal corresponding to a different theoretical threshold voltage. The n-channel PWM signals are denoted as P1, P2, P3, ..., Pn, respectively, and the I / O port 13 sends a PWM signal to the filter circuit 20.

The specific process of calculating the PWM characteristics is: Calculate the duty cycle D of the PWM signal according to the formula D = Vn / Vpwm. The duty cycle D indicates that the duration of the high level of the signal output by the output port in a period accounts for the entire signal. The percentage of time; thereby determining the PWM characteristics of the PWM signal to be generated: the duty cycle D, the maximum amplitude Vpwm (that is, the level of the output port).

The specific process of the FPGA I / O port generating a PWM signal is: According to the calculated duty cycle D of the PWM signal, the FPGA uses the internal timer unit to control the period and high-level duration of a single signal. The signal output from the O port is a PWM signal that meets the duty cycle requirements.

According to an embodiment of the present application, the filter circuit 20 is configured to generate corresponding n DC-shaped threshold voltages Vt1, Vt2, Vt3,..., Vtn according to n PWM signals, and the filter circuit 20 sends the threshold to the comparator 11 at the same time. Voltage signal.

According to an embodiment of the present application, the filter circuit 20 uses RC filter circuits (resistance-capacitance circuits) constructed by fourth-order resistors and capacitors. As shown in FIG. 3, the fourth-order filter circuit includes four resistors R1, R2, which are connected in series in order. R3 and R4. The generated PWM signal is connected to the filter circuit through resistor R1. Among them, resistor R1 and resistor R2 are connected to ground through capacitor C1, and resistor R2 and resistor R3 are connected to ground through capacitor C2. Resistor R3 and resistor R4 is connected to ground through capacitor C3, and the end of resistor R4 is connected to ground through capacitor C4. The end of resistor R4 is also responsible for outputting the filtered threshold voltage. The filter circuit filters the PWM signal and filters the high-frequency signal in the PWM signal to make the ripple smaller and the output smooth. In addition, the RC filter circuit also has many advantages such as simple structure, low price, excellent performance and easy implementation.

Those skilled in the art should understand that the FPGA 10 can input n-channel PWM signals to the m-order filter circuit through the port 13 or use other filtering processing between the port 13 and the filter circuit 20 and then access the filter circuit 20. This will not be repeated here.

The comparator 11 in the FPGA 10 can use any voltage comparator that meets the requirements, preferably an LVDS comparator. Compared with a conventional voltage comparator chip, the LVDS comparator has the advantages of low cost, high integration, and low power consumption. For example, conventional FPGA chips have LVDS ports, and the number is large.

The time-to-digital conversion unit 12 in FGPA can be formed by a logic unit inside the FPGA. The time-to-digital conversion unit 12 is configured to measure the edge arrival time (including rising and falling edges) of the flicker pulse signal and determine when the flicker pulse signal is high. Level and when it is low to control the collected data. The time-to-digital conversion unit 12 may include a coarse counter (first counter, not shown in the figure) and a fine counter (second counter, not shown in the figure). The coarse time value (first time value) and fine The fine time value (second time value) output by the counter is combined according to a certain relationship to obtain the edge arrival time of the flicker pulse signal. The time-digital conversion unit compares the edge arrival time of the flicker pulse signal with the threshold voltage signal and records it. The time information corresponding to the high and low state transitions and the threshold voltage information corresponding to the time information form a threshold voltage-time pair of the flicker pulse signal.

Specifically, the coarse counter is driven by a clock signal, and after each clock cycle, the count value output by the coarse counter is increased by 1, and the current coarse value is obtained by multiplying the current count value by one clock cycle. When the edge of the trigger signal s comes, the time-to-digital converter records the count value of the coarse counter output at this moment, and records it as N. If the clock period is recorded as Tc, the coarse time of the edge arrival of the trigger signal s can be expressed as N * Tc. The time measurement accuracy of the coarse counter is based on the clock cycle, but for FPGAs, the frequency of the clock signal cannot be increased without limit. To further improve the time measurement accuracy, a fine counter needs to be introduced. The implementation of the fine counter is based on a delay line that outputs a temperature code. The temperature code includes several 0s and 1. The temperature code on the delay line is characterized by all 0s on one side and 1,0 and 1 on the other side. The relationship between the elimination of each other, and the sum of the number of 0 and the number of 1 is equal to the total length of the temperature code. For example, 1110000 is a piece of temperature code composed of 3 1s and 5 0s. The boundary between 0 and 1 represents the signal to be measured. By counting the number of 0 or 1, and multiplying the length of time represented by each 0 or 1, the fine time of the edge of the signal to be measured on the delay line can be calculated. Therefore, the edge arrival time of the trigger signal s is equal to the sum of the coarse time and the fine time. With the help of a delay line, the time measurement accuracy of the time-to-digital converter can be improved to better than 100 picoseconds.

The threshold voltage-time pair of the flicker pulse may include the threshold voltage information and time information corresponding to the flicker pulse signal at each sampling point, and may also include the threshold voltage information and time information corresponding to each sampling point after several samplings. average of.

The method and device for digitizing the flicker pulse provided in the present application generate a PWM signal through an FPGA and generate a DC threshold voltage signal after a filter circuit constructed by a resistor and a capacitor, thereby replacing the circuit function of the DAC part and completing the MVT sampling. Compared with the traditional MVT sampling circuit, because the multi-stage RC filter circuit is built by the back-end FPGA and a small number of resistors and capacitors to generate the threshold voltage signal, the DAC and voltage reference circuit are eliminated, and the flicker pulse can be digitized by using the FPGA alone Sampling makes the whole circuit structure simple. At the same time, in terms of performance, the quality of the DC threshold voltage signal generated by the PWM signal through the filter circuit is equivalent to the output of a 12-bit precision DAC, and the resistance and capacitance are very common basic electronic components and the price is low, usually 1 resistor or The price of a capacitor is about 0.001 USD, so its single-channel cost is about 0.001 * 8 * 4 = 0.032 USD. Compared with a single-channel DAC, the cost can greatly reduce the cost, reduce system power consumption and PCB circuit area.

The above are only preferred embodiments of the present application, and are not intended to limit the scope of the present application. The above embodiments of the present application can also make various changes. That is, any simple and equivalent changes and modifications made based on the content of the claims and the description of the present application shall fall into the protection scope of the claims of the present patent. What is not described in detail in this application is conventional technical content.

Claims

A method for digitizing a scintillation pulse, wherein the method includes the following steps:

Step S1: Set n theoretical threshold voltages according to the requirements of multi-threshold voltage sampling, where n is a natural number;

Step S2: Calculate a pulse width modulation characteristic according to the theoretical threshold voltage, and use an input / output port of the FPGA to generate n pulse width modulation signals corresponding to the theoretical threshold voltage according to the pulse width modulation characteristic;

Step S3: input n pulse-width modulation signals into a filter circuit to generate corresponding n threshold voltage signals;

Step S4: input the flicker pulse signal to be sampled and n threshold voltage signals into n comparators of the FPGA and perform voltage comparison;

Step S5: Use a time-to-digital conversion unit inside the FPGA to collect threshold voltage-time pairs according to the comparison results of n comparators.
The method of digitizing a scintillation pulse according to claim 1, wherein the requirement of multi-threshold voltage sampling includes one or more of spatial resolution, temporal resolution, and energy resolution.
The method for digitizing a flicker pulse according to claim 1, wherein the demand for multi-threshold voltage sampling is obtained by the following method: establishing a database according to the threshold voltage-time pair that has been collected, and performing waveform reconstruction to extract flicker The spatial, temporal, and energy resolution of the pulse signal.
The method for digitizing a flicker pulse according to claim 1, wherein the setting of the theoretical threshold voltage is performed by the following method: determining a voltage amplitude range of the flicker pulse signal to be sampled, and at least one of the theoretical threshold voltages is set. One is within the voltage amplitude range of the blinking pulse signal to be sampled.
The method of digitizing a flicker pulse according to claim 1, wherein a specific method of calculating the pulse width modulation characteristic comprises:

Step S21: Determine the level of the output port corresponding to the pulse width modulation signal to be generated according to the theoretical threshold voltage;

Step S22: Calculate the duty cycle D of the pulse width modulation signal according to the following formula:

D = theoretical threshold voltage / level of the corresponding output port,

Wherein, the duty ratio D represents the duration of the high level of the pulse width modulation signal output by the output port in a period as a percentage of the entire signal time;

In step S23, it is determined that the pulse width modulation characteristic of the pulse width modulation signal to be generated is: the duty ratio D, and the maximum amplitude value is the level of the corresponding output port.
The method for digitizing a flicker pulse according to claim 5, wherein a specific method for generating a pulse width modulated signal by the FPGA is: using a timer unit inside the FPGA to control a single pulse according to the duty cycle D Period and high-level duration of the width-modulated signal.
The method for digitizing a flicker pulse according to claim 1, wherein a specific method of inputting n channels of the pulse width modulation signal to a filter circuit is: directly connecting the filter circuit at a back end of the pulse width modulation signal Or after filtering the pulse width modulated signal, the filtering circuit is connected to the filtering circuit.
The method for digitizing a flicker pulse according to claim 7, wherein the filter circuit is a fourth-order filter circuit.
The method for digitizing a scintillation pulse according to claim 8, wherein the fourth-order filter circuit includes four resistors R1, R2, R3, and R4 connected in series, and the pulse width modulation signal generated by the resistor passes through the resistor R1 is connected to a filter circuit, wherein the resistor R1 and the resistor R2 are connected to each other through a capacitor C1 and grounded, and the resistor R2 and the resistor R3 are connected to each other through a capacitor C2 to be grounded, and the resistor R3 and all The resistors R4 are connected to ground through a capacitor C3, the ends of the resistors R4 are connected to ground through a capacitor C4, and the ends of the resistors R4 are also responsible for outputting the filtered threshold voltage.
The method for digitizing a flicker pulse according to claim 1, wherein in the step S4, a voltage comparison is performed between the flicker pulse signal to be sampled and n threshold voltage signals through a low-voltage differential signal comparator.
The method for digitizing a flicker pulse according to claim 1, wherein the time-to-digital conversion unit comprises a first counter and a second counter, and the first time value output by the first counter and the second counter The second time values output by the counters are combined to obtain the edge arrival time of the flicker pulse signal. The time-to-digital conversion unit compares the edge arrival time of the flicker pulse signal with the threshold voltage signal, and records the high and low level state transitions. The corresponding time information and the threshold voltage information corresponding to the time information.
The method of digitizing a flicker pulse according to claim 1, further comprising:

Step S6: Repeat the above steps S1-S5 to obtain the threshold voltage-time pairs of multiple sets of flicker pulse signals, and complete the digitization of the flicker pulse signals.
The method of digitizing a flicker pulse according to claim 12, wherein the threshold voltage-time pair includes threshold voltage and time corresponding to the flicker pulse signal at each sampling point, or comprises The average of the corresponding threshold voltage and time at the sampling point.
A device for digitizing a flicker pulse is characterized in that the device comprises:

FPGA, the FPGA is configured to set n theoretical threshold voltages according to the requirements of multi-threshold voltage sampling, the FPGA has input / output ports, and the input / output ports are configured to generate pulse widths based on the theoretical threshold voltages Modulated signal;

A filtering circuit configured to convert the pulse width modulation signal into a threshold voltage signal;

The FPGA further includes a comparator and a time-to-digital conversion unit. The comparator is configured to receive a flicker pulse signal to be sampled and compare the threshold voltage signal with each other; and the time-to-digital conversion unit is configured to perform a comparison based on the comparison. The result of the comparison is collected by the threshold voltage-time pair.
The device for digitizing a flicker pulse according to claim 14, wherein at least one of the theoretical threshold voltages is within a voltage amplitude range of the flicker pulse signal to be sampled.
The device for digitizing a flicker pulse according to claim 14, wherein the input / output port of the FPGA is a low-voltage differential signal port.
The device for digitizing a flicker pulse according to claim 14, wherein the filter circuit is a fourth-order filter circuit.
The device for digitizing a flicker pulse according to claim 17, wherein the fourth-order filter circuit includes four resistors R1, R2, R3, and R4 connected in series, wherein one of the resistor R1 and the resistor R2 Between the resistor R2 and the resistor R3 through a capacitor C2, and then between the resistor R3 and the resistor R4 through a capacitor C3, the resistor R4 ends. The capacitor C4 is connected to ground, the generated pulse width modulation signal is connected to a filter circuit through the resistor R1, and the filtered threshold voltage is output through an end of the resistor R4.
The device for digitizing a flicker pulse according to claim 14, wherein the comparator is a low-voltage differential signal comparator.
The device for digitizing a flicker pulse according to claim 14, wherein the time-to-digital conversion unit includes a coarse counter and a fine counter, and the coarse time value output by the coarse counter and the fine time output by the fine counter The values are combined to obtain the edge arrival time of the flicker pulse signal. The time-digital conversion unit compares the edge arrival time of the flicker pulse signal with the threshold voltage signal, and records the time information corresponding to the high and low level state transitions and the Threshold voltage information corresponding to time information.