WO2019239602A1 - Memory history management system - Google Patents

Memory history management system Download PDF

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Publication number
WO2019239602A1
WO2019239602A1 PCT/JP2018/023015 JP2018023015W WO2019239602A1 WO 2019239602 A1 WO2019239602 A1 WO 2019239602A1 JP 2018023015 W JP2018023015 W JP 2018023015W WO 2019239602 A1 WO2019239602 A1 WO 2019239602A1
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memory
history
data
write
data value
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PCT/JP2018/023015
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French (fr)
Japanese (ja)
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亜希子 米田
治 遠山
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三菱電機株式会社
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Priority to PCT/JP2018/023015 priority Critical patent/WO2019239602A1/en
Priority to TW107128443A priority patent/TW202001562A/en
Publication of WO2019239602A1 publication Critical patent/WO2019239602A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment

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  • the present invention relates to a memory history management system.
  • a history of memory accessed by the processor may be recorded to investigate the cause of failure.
  • a method of recording the memory reference history there are a hardware method and a software method.
  • Patent Document 1 discloses a method of compressing a memory address using entry information of a cache memory and storing it in a history buffer when a reference to the cache memory occurs.
  • Patent Document 2 As a method using software, in Patent Document 2, a memory area to be traced is protected by a program, a segmentation fault that occurs when the processor accesses the protected memory area, and addressing is performed by exception processing. It shows how to output a trace.
  • the object of the present invention is to leave history information of data values with a small capacity without affecting the processing time of software.
  • a memory history management system includes: A history memory for recording a history for restoring the data value of the main memory at the first time point from the data value of the main memory at the second time point; A pre-write data memory that stores a data value stored in the main memory in an area corresponding to a write destination address when data is stored in a write-back cache memory in response to a write request to the main memory When, When a write back to the main memory occurs, a write back destination address and a data value stored in an area corresponding to the write back destination address of the pre-write data memory are recorded in the history memory.
  • a write-back monitoring unit to be added to the history;
  • the data value stored in the cache memory is compared with the data value stored in the pre-write data memory, and if there is a difference, the corresponding address in the main memory and the pre-write
  • a difference information extraction unit that adds a data value stored in an area corresponding to the corresponding address of the data memory to a history recorded in the history memory.
  • FIG. 1 is a block diagram showing a configuration of a memory history management system according to Embodiment 1.
  • FIG. The figure which shows the state of the main memory at the time of the start of 1st period process execution based on Embodiment 1, a cache memory, and the data memory before write.
  • 4 is a table showing a write history of first cycle processing according to the first embodiment.
  • surface which shows the content of the history memory at the time of the 2nd period process execution start based on Embodiment 1.
  • FIG. The figure which shows the state of the main memory after execution of a 2nd period process, cache memory, and the data memory before write based on Embodiment 1.
  • FIG. The table
  • FIG. 4 is a block diagram showing a configuration of a memory history management system according to a second embodiment.
  • Embodiment 1 FIG. This embodiment will be described with reference to FIGS.
  • the memory history management system 10 is a computer.
  • the memory history management system 10 includes a processor 11 and a main memory 12, and a memory history collection circuit 20 between the processor 11 and the main memory 12.
  • the processor 11 is, for example, a CPU.
  • CPU Central Processing Unit
  • the main memory 12 is, for example, a RAM. “RAM” is an abbreviation for Random Access Memory.
  • the memory history collection circuit 20 includes a cache memory 21, a pre-write data memory 22, a history memory 23, a write back monitoring unit 24, a difference information extraction unit 25, and a memory value reproduction unit 26.
  • the cache memory 21 is a memory having a smaller capacity than the main memory 12 that temporarily stores data of the main memory 12 accessed from the processor 11.
  • the cache memory 21 is a write-back method, and when a write from the processor 11 occurs, the write data is not immediately reflected in the main memory 12, but when the data is evicted from the cache memory 21. Is written back to the main memory 12.
  • the pre-write data memory 22 is a memory for storing data values read from the main memory 12 when storing the data of the main memory 12 in the cache memory 21, and stores data corresponding to each entry of the cache memory 21. Store.
  • the history memory 23 is a memory for storing history information of data values of the main memory 12, and records addresses and data values of the main memory 12.
  • the write-back monitoring unit 24 detects a write-back from the cache memory 21
  • the history memory 23 displays the write-back destination address and the data value stored in the pre-write data memory 22 corresponding to the write-back destination address. It is the control circuit which stores in.
  • the difference information extraction unit 25 is a control circuit that compares the data value stored in the cache memory 21 with the corresponding data value in the pre-write data memory 22 for all entries in the cache memory 21. If there is a difference, the difference information extraction unit 25 stores the memory address and the pre-write data value in the history memory 23, and then updates the data value of the pre-write data memory 22 to the current data value.
  • the memory value reproduction unit 26 is a circuit that reproduces past data in the main memory 12 from the current data value stored in the main memory 12 and the history information stored in the history memory 23.
  • This embodiment is intended for a system that performs periodic processing.
  • the same program is executed at regular intervals. Therefore, if the data value at the start of periodic processing is clear and the data value is not changed by anyone other than the periodic processing program during execution of the periodic processing, the operation of the program within that cycle can be reproduced. It becomes.
  • the processor 11 checks whether data is stored in the cache memory 21. When data is not stored in the cache memory 21, the processor 11 reads a data value from the main memory 12 and stores the data in the cache memory 21. At this time, the processor 11 stores the data value read from the main memory 12 in the pre-write data memory 22.
  • the processor 11 When a read or write access to data stored in the cache memory 21 from the processor 11 occurs, the processor 11 performs a data read or write access to the cache memory 21.
  • the processor 11 accesses data not stored in the cache memory 21 and stores the data in the main memory 12 in the cache memory 21, the data stored in the area where the data is newly stored is transferred from the cache memory 21. Get kicked out. At this time, if the processor 11 has written the evicted data, there is a possibility that the value does not match that of the main memory 12, so a write back from the cache memory 21 to the main memory 12 occurs. When a write back occurs, the write back monitoring unit 24 determines whether there is a difference between the data value of the write back generated from the cache memory 21 and the data value of the pre-write data memory 22 corresponding to the written back data. judge.
  • the write-back monitoring unit 24 stores the history number in the history memory 23 as the history information, the cycle number indicating the current cycle, the address of the main memory 12 having a difference in value, and the pre-write data corresponding to the address.
  • the data value of the memory 22 is stored.
  • the processing is instructed to the difference information extraction unit 25 by the processor 11 or an external signal.
  • the difference information extraction unit 25 compares all the data values in the cache memory 21 with the data values in the pre-write data memory 22. If the data value in the cache memory 21 and the data value in the pre-write data memory 22 do not match, the difference information extraction unit 25 stores the history information in the history memory 23 and caches the data value in the pre-write data memory 22. The data value in the memory 21 is updated.
  • the history information is information indicating a cycle number, an address of the main memory 12 having a difference in value, and a data value of the pre-write data memory 22 corresponding to the address.
  • the above operation is performed every time the periodic process is executed.
  • the history memory 23 When the history memory 23 is full and the history information cannot be stored, it can be executed continuously by overwriting the top data of the history memory 23.
  • the history memory 23 and the data value of the main memory 12 or the cache memory 21 are used to restore the data value of the main memory 12. For example, when the execution of the i-th cycle process is completed, the data value of the main memory 12 at the completion of the execution of the i-th cycle process is stored in the main memory 12 or the cache memory 21. Reads out the data from the main memory 12 via the cache memory 21, so that the data value can be reproduced.
  • the execution of the i-1th cycle process which is the cycle process of the previous cycle
  • the main memory 12 and the cache memory 21 at the completion of the ith cycle process Are reproduced from the data value of the data and the information in the history memory 23.
  • the data value in the history memory 23 is set to the data value at the completion of the execution of the i-th cycle process, that is, before the execution of the i-th cycle process is started. Data value.
  • the data value at the completion of the execution of the i-th cycle process is the data value at the completion of the execution of the i-1th cycle process, that is, the i-th cycle The data value before the start of processing execution.
  • FIG. 2 shows the states of the main memory 12, the cache memory 21, and the pre-write data memory 22 at the start of execution of the first cycle process.
  • the pre-write data memory 22 has a pre-write data storage area corresponding to each entry of the cache memory 21. When reading from the main memory 12 occurs in the cache memory 21, the data value read from the main memory 12 is stored in the corresponding storage area.
  • FIG. 3 shows a write address and a write value generated during the execution of the first cycle process.
  • FIG. 4 shows the main memory 12 and the cache memory 21 when the write shown in FIG. 3 occurs from the state of the main memory 12, the cache memory 21 and the pre-write data memory 22 in FIG. The state of the pre-write data memory 22 is shown.
  • the difference information extraction unit 25 stores the history information in the history memory 23. Specifically, the difference information extraction unit 25 compares the data value of each entry in the cache memory 21 with the pre-write data value, and if the values are different, the cycle number, the address, and the pre-write data value And store. In FIG. 4, since the data values of entry 0, entry 1 and entry 2 are different from the pre-write data value, the pre-write data memory 22 corresponding to the addresses “0x100”, “0x110” and “0x120” is written. The data value is stored in the history memory 23. The contents of the history memory 23 from which the difference information extraction unit 25 outputs the history information are shown in FIG.
  • the difference information extraction unit 25 updates the pre-write data value of the pre-write data memory 22 to the data value of the cache memory 21.
  • the states of the main memory 12, the cache memory 21 and the pre-write data memory 22 after the history information is stored by the difference information extraction unit 25 are shown in FIG.
  • the second cycle process is executed.
  • FIG. 7 shows the address and write value of a write that occurred during the execution of the second cycle process.
  • FIG. 8 shows the main memory 12 and the cache memory 21 when the write shown in FIG. 7 occurs from the state of the main memory 12, the cache memory 21 and the pre-write data memory 22 in FIG. The state of the pre-write data memory 22 is shown.
  • the write-back destination address “0x110” and the value “0x3333” of the pre-write data memory 22 corresponding to the address together with the cycle number “2” are stored in the history memory. 23.
  • the address “0x210” and the data value “0x8888” of # 3 are stored in the entry 1 of the cache memory 21.
  • the data value “0xeeee” read from the main memory 12 is stored in entry 1 of the pre-write data memory 22.
  • FIG. 9 shows the contents of the history memory 23 before the execution of the second cycle process is completed and the difference information extraction unit 25 stores the history information in the history memory 23.
  • the difference information extraction unit 25 stores the history information in the history memory 23 in the same manner as after the completion of the execution of the first cycle process.
  • FIG. 10 shows the contents of the history memory 23 from which the difference information extraction unit 25 outputs the history information after the execution of the second cycle process is completed.
  • the difference information extraction unit 25 updates the pre-write data value of the pre-write data memory 22 to the data value of the cache memory 21.
  • FIG. 11 shows the states of the main memory 12, the cache memory 21, and the pre-write data memory 22 after the history information is stored by the difference information extraction unit 25.
  • the data value read from the main memory 12 is the main memory 12 before the start of the execution of the third cycle process. It becomes the value of.
  • FIG. 12 shows the state of the main memory 12 before the start of execution of the third cycle process.
  • the value before the start of the execution of the second cycle process is restored from the value of the main memory 12 and the entry of the cycle number “2” in the history memory 23 before the start of the execution of the third cycle process.
  • the memory value reproduction unit 26 looks at the data in the history memory 23 from the latest entry, and sets the data value of the entry with the cycle number “2” as the data value of the cycle. When there are a plurality of entries with the same cycle number as in # 4 and # 7 in FIG. 10, the memory value reproduction unit 26 uses the data value of the oldest entry as the data value at the start of execution of that cycle. To do.
  • FIG. 13 shows the state of the main memory 12 before the restored second cycle process is started.
  • the value before the start of the execution of the first cycle process is restored from the value of the main memory 12 and the entry of the cycle number “1” in the history memory 23 before the start of the execution of the second cycle process.
  • the memory value reproduction unit 26 looks at the data in the history memory 23 from the latest entry, and the data value of the entry whose cycle number is “1”, as in the method of restoring the value before the execution of the second cycle process. Data value.
  • FIG. 14 shows the state of the main memory 12 before the restored first cycle process is started.
  • the history memory 23 records a history for restoring the data value of the main memory 12 at the first time point from the data value of the main memory 12 at the second time point.
  • the data value stored in the main memory 12 is an area corresponding to the write destination address of the pre-write data memory 22.
  • the write back monitoring unit 24 displays the write back destination address and the data value stored in the area corresponding to the write back destination address of the pre-write data memory 22 in the history memory. 23 is added to the history recorded in 23.
  • the difference information extraction unit 25 compares the data value stored in the cache memory 21 with the data value stored in the pre-write data memory 22 at the second time point. When there is a difference, the difference information extraction unit 25 stores the corresponding address in the main memory 12 and the data value stored in the area corresponding to the corresponding address in the pre-write data memory 22 in the history recorded in the history memory 23. to add.
  • the difference information extraction unit 25 updates the data value stored in the pre-write data memory 22 to the data value stored in the cache memory 21 after addition to the history.
  • the first time point and the second time point are the start time point and the end time point of each of the plurality of processes.
  • the address and data value added to the history are recorded in the history memory 23 together with information for identifying the corresponding process among the plurality of processes.
  • the cycle number “1” is a history as information for identifying the first cycle process. Recorded in the memory 23.
  • the cycle number “2” is a history as information for identifying the second cycle process. Recorded in the memory 23.
  • the write-back monitoring unit 24 overwrites the oldest data in order when the data amount of the address and data value to be added to the history exceeds the capacity of the history memory 23. Go.
  • the difference information extraction unit 25 also overwrites the old data in order when the data amount of the address and data value to be added to the history exceeds the capacity of the history memory 23.
  • the memory value reproduction unit 26 restores the data value of the main memory 12 at the first time point from the data value of the main memory 12 at the second time point, using the history recorded in the history memory 23.
  • the memory value reproduction unit 26 converts the data value stored in the main memory 12 to the second value when the data value stored in the cache memory 21 at the second time point is reflected in the main memory 12. Used as the data value of the main memory 12 at the time. In addition, the memory value reproduction unit 26 uses the data value stored in the main memory 12 when the data value stored in the cache memory 21 at the first time point is reflected in the main memory 12 as the main memory value at the first time point. Restored as 12 data values.
  • the memory value reproduction unit 26 shows the data values stored in the main memory 12 when the data values stored in the cache memory 21 in FIG. It is used as the data value of the main memory 12 at the end of execution of the first cycle process.
  • the memory value reproduction unit 26 displays the data value stored in the main memory 12 when the data value stored in the cache memory 21 is reflected in the main memory 12 at the start of execution of the first periodic process. 14 is restored as the data value of the main memory 12 at the start of execution of the first periodic process as shown in FIG.
  • the memory value reproduction unit 26 shows the data values stored in the main memory 12 when the data values stored in the cache memory 21 in FIG. It is used as the data value of the main memory 12 at the end of execution of the second cycle processing.
  • the memory value reproducing unit 26 displays the data value stored in the main memory 12 when the data value stored in the cache memory 21 is reflected in the main memory 12 at the start of execution of the second cycle processing. 13 is restored as the data value of the main memory 12 at the start of execution of the second cycle processing as shown in FIG.
  • the present embodiment can be applied to an embedded system that performs periodic processing.
  • the history of the memory value of the main memory 12 can be acquired and reproduced for debugging or investigating a failure.
  • the data value at the start of the periodic process can be reproduced with a small history capacity.
  • the data in the main memory 12 is restored by tracing back from the latest history information. Therefore, when the capacity of the history memory 23 becomes full, it is possible to continue storing the history by sequentially overwriting old entries. Furthermore, since tracing is performed in order from the latest entry, data can be restored as long as the history information in the history memory 23 of the cycle to be restored remains.
  • the amount of data required for restoration is small compared with the method of leaving only the access history. Further, unlike the method of storing the initial value data and the difference information, the data restoration is performed from the current value of the main memory 12 and the value of the history memory 23. Therefore, the data amount necessary for the data restoration is the initial value. Less because there is no data.
  • the restored data value is output to the main memory 12 or another memory (not shown).
  • the restoration data is output to an unused area of the main memory 12 or another memory
  • the past periodic processing is performed while holding the data value of the main memory 12 at the completion of execution of the i-th periodic processing which is the current periodic processing. It is possible to reproduce the data value at the start of execution of the k-th cycle process.
  • i and k are integers satisfying k ⁇ i.
  • the memory value reproduction unit 26 may be realized as a program executed on the processor 11 or an external processor.
  • the history memory 23 may be a part of the main memory 12. That is, a part of the main memory 12 may be used for the history memory 23. In this case, the history memory 23 is not subject to history recording. That is, by making the area corresponding to the history memory 23 out of the collection target of the history information, it is possible to prevent the storage history in the area of the history memory 23 from being stored in the area of the history memory 23.
  • Embodiment 2 FIG. The difference between the present embodiment and the first embodiment will be mainly described with reference to FIG.
  • the memory history management system 10 includes a memory history collection system 13 and a data value restoration system 14.
  • the memory history collection system 13 and the data value restoration system 14 are connected by a network 40 such as a LAN or the Internet.
  • a network 40 such as a LAN or the Internet.
  • LAN is an abbreviation for Local Area Network.
  • the memory history collection system 13 is configured by removing the memory value reproduction unit 26 from the memory history management system 10 of the first embodiment shown in FIG. Since the functions and operations other than the data restoration processing are the same, the description thereof is omitted.
  • the data value restoration system 14 is a computer.
  • the data value restoration system 14 includes a processor 31 and a memory 32.
  • the memory value reproduction unit 26 of the first embodiment is realized as a memory value reproduction program 33 that is a program executed on the processor 31 of the data value restoration system 14.
  • the history information 34 indicating the memory value of the history memory 23 acquired by the memory history collection system 13 and the main memory data value 35 indicating the value of the main memory 12 are transmitted via the network 40. It is transferred to the memory 32 of the value restoration system 14. Based on the history information 34 and the main memory data value 35 transferred to the memory 32, the memory value reproduction program 33 restores the value of the main memory 12 at the start of execution of each periodic process.
  • the memory value is reproduced by a system different from the memory history collection, so that it is not necessary to provide an area for storing the reproduced data in an embedded system that performs periodic processing, so that the memory capacity is reduced. There is an effect that can be.
  • 10 memory history management system 11 processor, 12 main memory, 13 memory history collection system, 14 data value restoration system, 20 memory history collection circuit, 21 cache memory, 22 pre-write data memory, 23 history memory, 24 write back monitoring unit 25, difference information extraction unit, 26 memory value reproduction unit, 31 processor, 32 memory, 33 memory value reproduction program, 34 history information, 35 main memory data value, 40 network.

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Abstract

In the present invention, a history for restoring a data value of a main memory (12) is recorded in a history memory (23). When data is stored in a write-back cache memory (21) in accordance with a request to write to the main memory (12), the data value stored in the main memory (12) is stored in a corresponding region of a pre-write data memory (22). When a write-back has occurred, a write-back monitoring unit (24) adds, to the history, a write-back destination address and the data value stored in the corresponding region of the pre-write data memory (22). A differential information extraction unit (25) compares the data value stored in the cache memory (21) and the data value stored in the pre-write data memory (22), and if a difference exists, the differential information extraction unit adds, to the history, the address of the main memory (12) and the data value stored in the corresponding region of the pre-write data memory (22).

Description

メモリ履歴管理システムMemory history management system
　本発明は、メモリ履歴管理システムに関するものである。 The present invention relates to a memory history management system.
　障害発生要因調査のために、プロセッサがアクセスしたメモリの履歴を記録しておくことがある。メモリの参照履歴を記録しておく方法には、ハードウェアによる方法とソフトウェアによる方法とがある。 ∙ A history of memory accessed by the processor may be recorded to investigate the cause of failure. As a method of recording the memory reference history, there are a hardware method and a software method.
　ハードウェアによる方法として、特許文献１では、キャッシュメモリへの参照が発生した場合に、キャッシュメモリのエントリ情報を用いてメモリアドレスを圧縮して履歴バッファに記憶する方法が示されている。 As a method using hardware, Patent Document 1 discloses a method of compressing a memory address using entry information of a cache memory and storing it in a history buffer when a reference to the cache memory occurs.
　ソフトウェアによる方法として、特許文献２では、プログラムによって、トレースの採取対象のメモリ領域をプロテクトしておき、プロセッサがプロテクトされたメモリ領域へアクセスする際に発生するセグメンテーションフォールトを捕捉し、例外処理によってアドレストレースを出力する方法が示されている。 As a method using software, in Patent Document 2, a memory area to be traced is protected by a program, a segmentation fault that occurs when the processor accesses the protected memory area, and addressing is performed by exception processing. It shows how to output a trace.
特開２００２－２０７６１３号公報JP 2002-207613 A 特開２００７－１４０８３７号公報JP 2007-140837 A
　特許文献１に示されている方法では、アクセスが発生する度に履歴を残すため、参照回数が多いほど、履歴バッファへの格納容量が増えてしまう。また、記録対象がメモリアドレスであり、データ値を圧縮する方法については示されていないため、データ値の履歴容量は圧縮できない。 In the method disclosed in Patent Document 1, since a history is left every time an access occurs, the storage capacity in the history buffer increases as the number of references increases. Further, since the recording target is a memory address and the method for compressing the data value is not shown, the history capacity of the data value cannot be compressed.
　特許文献２に示されている方法では、履歴情報をプログラムの例外処理にて取得するため、履歴情報を収集する時間および処理時間が増加してしまう。 In the method shown in Patent Document 2, since history information is acquired by exception processing of a program, the time for collecting history information and the processing time increase.
　本発明は、ソフトウェアの処理時間に影響を与えず、かつ、少ない容量でデータ値の履歴情報を残すことを目的とする。 The object of the present invention is to leave history information of data values with a small capacity without affecting the processing time of software.
　本発明の一態様に係るメモリ履歴管理システムは、
　第１時点におけるメインメモリのデータ値を第２時点における前記メインメモリのデータ値から復元するための履歴を記録する履歴メモリと、
　前記メインメモリへのライト要求に応じてライトバック方式のキャッシュメモリにデータが格納されるときに、前記メインメモリに格納されているデータ値をライト先アドレスに対応する領域に格納するライト前データメモリと、
　前記メインメモリへのライトバックが発生したときに、ライトバック先アドレスと前記ライト前データメモリの前記ライトバック先アドレスに対応する領域に格納されているデータ値とを前記履歴メモリに記録されている履歴に追加するライトバック監視部と、
　前記第２時点において、前記キャッシュメモリに格納されているデータ値と前記ライト前データメモリに格納されているデータ値とを比較し、差分がある場合は、前記メインメモリの該当アドレスと前記ライト前データメモリの前記該当アドレスに対応する領域に格納されているデータ値とを前記履歴メモリに記録されている履歴に追加する差分情報抽出部と
を備える。 A memory history management system according to an aspect of the present invention includes:
A history memory for recording a history for restoring the data value of the main memory at the first time point from the data value of the main memory at the second time point;
A pre-write data memory that stores a data value stored in the main memory in an area corresponding to a write destination address when data is stored in a write-back cache memory in response to a write request to the main memory When,
When a write back to the main memory occurs, a write back destination address and a data value stored in an area corresponding to the write back destination address of the pre-write data memory are recorded in the history memory. A write-back monitoring unit to be added to the history;
At the second time point, the data value stored in the cache memory is compared with the data value stored in the pre-write data memory, and if there is a difference, the corresponding address in the main memory and the pre-write A difference information extraction unit that adds a data value stored in an area corresponding to the corresponding address of the data memory to a history recorded in the history memory.
　本発明によれば、ソフトウェアの処理時間に影響を与えず、かつ、少ない容量でデータ値の履歴情報を残すことができる。 According to the present invention, it is possible to leave history information of data values with a small capacity without affecting the processing time of software.
実施の形態１に係るメモリ履歴管理システムの構成を示すブロック図。1 is a block diagram showing a configuration of a memory history management system according to Embodiment 1. FIG. 実施の形態１に係る、第１周期処理実行開始時のメインメモリ、キャッシュメモリおよびライト前データメモリの状態を示す図。The figure which shows the state of the main memory at the time of the start of 1st period process execution based on Embodiment 1, a cache memory, and the data memory before write. 実施の形態１に係る第１周期処理のライト履歴を示す表。4 is a table showing a write history of first cycle processing according to the first embodiment. 実施の形態１に係る、第１周期処理実行後のメインメモリ、キャッシュメモリおよびライト前データメモリの状態を示す図。The figure which shows the state of the main memory after 1st period process execution based on Embodiment 1, a cache memory, and the data memory before write. 実施の形態１に係る、第２周期処理実行開始時の履歴メモリの内容を示す表。The table | surface which shows the content of the history memory at the time of the 2nd period process execution start based on Embodiment 1. FIG. 実施の形態１に係る、第２周期処理実行開始時のメインメモリ、キャッシュメモリおよびライト前データメモリの状態を示す図。The figure which shows the state of the main memory at the time of the start of 2nd period process execution based on Embodiment 1, a cache memory, and the data memory before writing. 実施の形態１に係る第２周期処理のライト履歴を示す表。The table | surface which shows the write history of the 2nd period process which concerns on Embodiment 1. FIG. 実施の形態１に係る、第２周期処理実行後のメインメモリ、キャッシュメモリおよびライト前データメモリの状態を示す図。The figure which shows the state of the main memory after execution of a 2nd period process, cache memory, and the data memory before write based on Embodiment 1. FIG. 実施の形態１に係る、第２周期処理実行後の履歴メモリの内容を示す表。The table | surface which shows the content of the log | history memory after execution of a 2nd period process based on Embodiment 1. FIG. 実施の形態１に係る、第３周期処理実行開始時の履歴メモリの内容を示す表。The table | surface which shows the content of the history memory at the time of the start of 3rd period process execution based on Embodiment 1. FIG. 実施の形態１に係る、第３周期処理実行開始時のメインメモリ、キャッシュメモリおよびライト前データメモリの状態を示す図。The figure which shows the state of the main memory at the time of the start of 3rd period process execution based on Embodiment 1, a cache memory, and the data memory before writing. 実施の形態１に係る、第３周期処理実行開始前のメインメモリの状態を示す表。The table | surface which shows the state of the main memory before the start of 3rd period process execution based on Embodiment 1. FIG. 実施の形態１に係る、第２周期処理実行開始前のメインメモリの状態を示す表。The table | surface which shows the state of the main memory before the start of 2nd period process execution based on Embodiment 1. FIG. 実施の形態１に係る、第１周期処理実行開始前のメインメモリの状態を示す表。The table | surface which shows the state of the main memory before the start of 1st period process execution based on Embodiment 1. FIG. 実施の形態２に係るメモリ履歴管理システムの構成を示すブロック図。FIG. 4 is a block diagram showing a configuration of a memory history management system according to a second embodiment.
　以下、本発明の実施の形態について、図を用いて説明する。各図中、同一または相当する部分には、同一符号を付している。実施の形態の説明において、同一または相当する部分については、説明を適宜省略または簡略化する。なお、本発明は、以下に説明する実施の形態に限定されるものではなく、必要に応じて種々の変更が可能である。例えば、以下に説明する実施の形態のうち、２つ以上の実施の形態が組み合わせられて実施されても構わない。あるいは、以下に説明する実施の形態のうち、１つの実施の形態または２つ以上の実施の形態の組み合わせが部分的に実施されても構わない。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals. In the description of the embodiments, the description of the same or corresponding parts will be omitted or simplified as appropriate. The present invention is not limited to the embodiments described below, and various modifications can be made as necessary. For example, two or more embodiments among the embodiments described below may be combined and executed. Alternatively, among the embodiments described below, one embodiment or a combination of two or more embodiments may be partially implemented.
　実施の形態１．
　本実施の形態について、図１から図１４を用いて説明する。 Embodiment 1 FIG.
This embodiment will be described with reference to FIGS.
　＊＊＊構成の説明＊＊＊
　図１を参照して、本実施の形態に係るメモリ履歴管理システム１０の構成を説明する。 *** Explanation of configuration ***
With reference to FIG. 1, the configuration of a memory history management system 10 according to the present embodiment will be described.
　メモリ履歴管理システム１０は、コンピュータである。メモリ履歴管理システム１０は、プロセッサ１１とメインメモリ１２とを備えるとともに、プロセッサ１１とメインメモリ１２との間にメモリ履歴収集回路２０を備える。 The memory history management system 10 is a computer. The memory history management system 10 includes a processor 11 and a main memory 12, and a memory history collection circuit 20 between the processor 11 and the main memory 12.
　プロセッサ１１は、例えば、ＣＰＵである。「ＣＰＵ」は、Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔの略語である。 The processor 11 is, for example, a CPU. “CPU” is an abbreviation for Central Processing Unit.
　メインメモリ１２は、例えば、ＲＡＭである。「ＲＡＭ」は、Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙの略語である。 The main memory 12 is, for example, a RAM. “RAM” is an abbreviation for Random Access Memory.
　メモリ履歴収集回路２０は、キャッシュメモリ２１と、ライト前データメモリ２２と、履歴メモリ２３と、ライトバック監視部２４と、差分情報抽出部２５と、メモリ値再現部２６とを備える。 The memory history collection circuit 20 includes a cache memory 21, a pre-write data memory 22, a history memory 23, a write back monitoring unit 24, a difference information extraction unit 25, and a memory value reproduction unit 26.
　キャッシュメモリ２１は、プロセッサ１１からアクセスするメインメモリ１２のデータを一時的に格納する、メインメモリ１２よりも小容量のメモリである。本実施の形態では、キャッシュメモリ２１は、ライトバック方式であり、プロセッサ１１からのライトが発生した場合、ライトデータはメインメモリ１２にはすぐに反映されず、キャッシュメモリ２１からデータが追い出される際にメインメモリ１２に書き戻される。 The cache memory 21 is a memory having a smaller capacity than the main memory 12 that temporarily stores data of the main memory 12 accessed from the processor 11. In the present embodiment, the cache memory 21 is a write-back method, and when a write from the processor 11 occurs, the write data is not immediately reflected in the main memory 12, but when the data is evicted from the cache memory 21. Is written back to the main memory 12.
　ライト前データメモリ２２は、キャッシュメモリ２１にメインメモリ１２のデータを格納する際に、メインメモリ１２から読み出したデータ値を格納しておくメモリであり、キャッシュメモリ２１のエントリごとに対応するデータを格納する。 The pre-write data memory 22 is a memory for storing data values read from the main memory 12 when storing the data of the main memory 12 in the cache memory 21, and stores data corresponding to each entry of the cache memory 21. Store.
　履歴メモリ２３は、メインメモリ１２のデータ値の履歴情報を格納するメモリであり、メインメモリ１２のアドレスとデータ値とを記録しておく。 The history memory 23 is a memory for storing history information of data values of the main memory 12, and records addresses and data values of the main memory 12.
　ライトバック監視部２４は、キャッシュメモリ２１からのライトバックを検出すると、ライトバック先のアドレスと、ライトバック先のアドレスに対応したライト前データメモリ２２に格納されているデータ値とを履歴メモリ２３に格納する制御回路である。 When the write-back monitoring unit 24 detects a write-back from the cache memory 21, the history memory 23 displays the write-back destination address and the data value stored in the pre-write data memory 22 corresponding to the write-back destination address. It is the control circuit which stores in.
　差分情報抽出部２５は、キャッシュメモリ２１のすべてのエントリに対し、キャッシュメモリ２１に格納されているデータ値と、対応するライト前データメモリ２２のデータ値とを比較する制御回路である。差分情報抽出部２５は、差分がある場合はメモリアドレスとライト前データ値とを履歴メモリ２３に格納し、その後、ライト前データメモリ２２のデータ値を現在のデータ値に更新する。 The difference information extraction unit 25 is a control circuit that compares the data value stored in the cache memory 21 with the corresponding data value in the pre-write data memory 22 for all entries in the cache memory 21. If there is a difference, the difference information extraction unit 25 stores the memory address and the pre-write data value in the history memory 23, and then updates the data value of the pre-write data memory 22 to the current data value.
　メモリ値再現部２６は、メインメモリ１２に格納されている現在のデータ値と履歴メモリ２３に格納されている履歴情報から、メインメモリ１２の過去のデータを再現する回路である。 The memory value reproduction unit 26 is a circuit that reproduces past data in the main memory 12 from the current data value stored in the main memory 12 and the history information stored in the history memory 23.
　＊＊＊動作の説明＊＊＊
　図１を参照して、本実施の形態に係るメモリ履歴管理システム１０の動作を説明する。メモリ履歴管理システム１０の動作は、本実施の形態に係るメモリ履歴管理方法に相当する。 *** Explanation of operation ***
The operation of the memory history management system 10 according to the present embodiment will be described with reference to FIG. The operation of the memory history management system 10 corresponds to the memory history management method according to the present embodiment.
　本実施の形態は、周期処理を行うシステムを対象とする。周期処理を行うシステムでは、一定の周期ごとに同じプログラムを実行する。そのため、周期処理開始時のデータの値が明らかであり、かつ、周期処理実行中は周期処理プログラム以外がデータ値を変更することがなければ、その周期内のプログラムの動作を再現することが可能となる。 This embodiment is intended for a system that performs periodic processing. In a system that performs periodic processing, the same program is executed at regular intervals. Therefore, if the data value at the start of periodic processing is clear and the data value is not changed by anyone other than the periodic processing program during execution of the periodic processing, the operation of the program within that cycle can be reproduced. It becomes.
　周期処理が開始し、プロセッサ１１からメインメモリ１２へのリードまたはライトアクセスが発生すると、プロセッサ１１は、キャッシュメモリ２１にデータが格納されているかをチェックする。キャッシュメモリ２１にデータが格納されていない場合、プロセッサ１１は、メインメモリ１２からデータ値を読み出して、キャッシュメモリ２１にデータを格納する。このとき、プロセッサ１１は、ライト前データメモリ２２にメインメモリ１２から読み出したデータ値を格納する。 When the periodic processing starts and a read or write access from the processor 11 to the main memory 12 occurs, the processor 11 checks whether data is stored in the cache memory 21. When data is not stored in the cache memory 21, the processor 11 reads a data value from the main memory 12 and stores the data in the cache memory 21. At this time, the processor 11 stores the data value read from the main memory 12 in the pre-write data memory 22.
　プロセッサ１１からキャッシュメモリ２１に格納されているデータへのリードまたはライトアクセスが発生した場合は、プロセッサ１１は、キャッシュメモリ２１に対してデータのリードまたはライトアクセスを行う。 When a read or write access to data stored in the cache memory 21 from the processor 11 occurs, the processor 11 performs a data read or write access to the cache memory 21.
　プロセッサ１１がキャッシュメモリ２１に格納されていないデータへのアクセスを行い、メインメモリ１２のデータをキャッシュメモリ２１に格納した場合、新たにデータを格納した領域に格納されていたデータはキャッシュメモリ２１から追い出される。このとき、追い出されたデータをプロセッサ１１がライトしていた場合は、メインメモリ１２と値が一致していない可能性があるため、キャッシュメモリ２１からメインメモリ１２へのライトバックが発生する。ライトバックが発生した場合、ライトバック監視部２４は、キャッシュメモリ２１から発生したライトバックのデータ値と、ライトバックしたデータに対応するライト前データメモリ２２のデータ値とに差があるかどうかを判定する。差がある場合、ライトバック監視部２４は、履歴メモリ２３に履歴情報として、現在の周期を示す周期番号と、値に差のあったメインメモリ１２のアドレスと、そのアドレスに対応するライト前データメモリ２２のデータ値とを格納する。 When the processor 11 accesses data not stored in the cache memory 21 and stores the data in the main memory 12 in the cache memory 21, the data stored in the area where the data is newly stored is transferred from the cache memory 21. Get kicked out. At this time, if the processor 11 has written the evicted data, there is a possibility that the value does not match that of the main memory 12, so a write back from the cache memory 21 to the main memory 12 occurs. When a write back occurs, the write back monitoring unit 24 determines whether there is a difference between the data value of the write back generated from the cache memory 21 and the data value of the pre-write data memory 22 corresponding to the written back data. judge. If there is a difference, the write-back monitoring unit 24 stores the history number in the history memory 23 as the history information, the cycle number indicating the current cycle, the address of the main memory 12 having a difference in value, and the pre-write data corresponding to the address. The data value of the memory 22 is stored.
　周期処理が終了すると、プロセッサ１１または外部の信号にて差分情報抽出部２５へ処理が指示される。 When the periodic processing is completed, the processing is instructed to the difference information extraction unit 25 by the processor 11 or an external signal.
　差分情報抽出部２５は、キャッシュメモリ２１内のすべてのデータ値と、ライト前データメモリ２２のデータ値とを比較する。キャッシュメモリ２１内のデータ値とライト前データメモリ２２のデータ値とが不一致であれば、差分情報抽出部２５は、履歴メモリ２３に履歴情報を格納し、ライト前データメモリ２２のデータ値をキャッシュメモリ２１のデータ値に更新する。履歴情報は、周期番号と、値に差のあったメインメモリ１２のアドレスと、そのアドレスに対応するライト前データメモリ２２のデータ値とを示す情報である。 The difference information extraction unit 25 compares all the data values in the cache memory 21 with the data values in the pre-write data memory 22. If the data value in the cache memory 21 and the data value in the pre-write data memory 22 do not match, the difference information extraction unit 25 stores the history information in the history memory 23 and caches the data value in the pre-write data memory 22. The data value in the memory 21 is updated. The history information is information indicating a cycle number, an address of the main memory 12 having a difference in value, and a data value of the pre-write data memory 22 corresponding to the address.
　上記動作が周期処理の実行の都度行われる。 The above operation is performed every time the periodic process is executed.
　履歴メモリ２３の容量がいっぱいになり、履歴情報が格納できなくなった場合は、履歴メモリ２３の先頭のデータを上書きすることで、継続して実行可能となる。 When the history memory 23 is full and the history information cannot be stored, it can be executed continuously by overwriting the top data of the history memory 23.
　メインメモリ１２のデータ値の復元には、履歴メモリ２３と、メインメモリ１２またはキャッシュメモリ２１のデータ値とが利用される。例えば、第ｉ周期処理の実行が完了した時点では、第ｉ周期処理の実行完了時のメインメモリ１２のデータ値は、メインメモリ１２またはキャッシュメモリ２１に格納されているため、メモリ値再現部２６がキャッシュメモリ２１を経由してメインメモリ１２からデータを読み出すことで、データ値を再現することができる。１周期前の周期処理である第ｉ－１周期処理の実行完了時、すなわち、第ｉ周期処理の実行開始前のデータ値は、第ｉ周期処理の実行完了時のメインメモリ１２及びキャッシュメモリ２１のデータ値と、履歴メモリ２３の情報とから再現される。履歴メモリ２３に第ｉ周期処理の履歴情報が格納されている場合は、履歴メモリ２３のデータ値を第ｉ－１周期処理の実行完了時のデータ値、すなわち、第ｉ周期処理の実行開始前のデータ値とする。履歴メモリ２３に第ｉ周期処理の履歴情報が格納されていない場合は、第ｉ周期処理の実行完了時のデータ値を第ｉ－１周期処理の実行完了時のデータ値、すなわち、第ｉ周期処理の実行開始前のデータ値とする。 The history memory 23 and the data value of the main memory 12 or the cache memory 21 are used to restore the data value of the main memory 12. For example, when the execution of the i-th cycle process is completed, the data value of the main memory 12 at the completion of the execution of the i-th cycle process is stored in the main memory 12 or the cache memory 21. Reads out the data from the main memory 12 via the cache memory 21, so that the data value can be reproduced. When the execution of the i-1th cycle process, which is the cycle process of the previous cycle, is completed, that is, the data value before the execution of the ith cycle process is started, the main memory 12 and the cache memory 21 at the completion of the ith cycle process Are reproduced from the data value of the data and the information in the history memory 23. When the history information of the i-th cycle process is stored in the history memory 23, the data value in the history memory 23 is set to the data value at the completion of the execution of the i-th cycle process, that is, before the execution of the i-th cycle process is started. Data value. When the history information of the i-th cycle process is not stored in the history memory 23, the data value at the completion of the execution of the i-th cycle process is the data value at the completion of the execution of the i-1th cycle process, that is, the i-th cycle The data value before the start of processing execution.
　図２から図１１を参照して、履歴メモリ２３への履歴の格納およびその履歴を用いたメインメモリ１２のデータ値の復元の具体例を説明する。 A specific example of storing the history in the history memory 23 and restoring the data value of the main memory 12 using the history will be described with reference to FIGS.
　図２は、第１周期処理実行開始時のメインメモリ１２、キャッシュメモリ２１およびライト前データメモリ２２の状態を示している。 FIG. 2 shows the states of the main memory 12, the cache memory 21, and the pre-write data memory 22 at the start of execution of the first cycle process.
　メインメモリ１２にはアドレス「０ｘ１００」、「０ｘ１１０」、「０ｘ１２０」、「０ｘ１３０」および「０ｘ２１０」にそれぞれ「０ｘａａａａ」、「０ｘｂｂｂｂ」、「０ｘｃｃｃｃ」、「０ｘｄｄｄｄ」および「０ｘｅｅｅｅ」のデータが格納されている。キャッシュメモリ２１には何のデータも格納されていない。 In the main memory 12, data of addresses “0x100”, “0x110”, “0x120”, “0x130”, and “0x210” is stored with “0xaaaa”, “0xbbbb”, “0xcccc”, “0xdddd”, and “0xeeee”, respectively. Has been. No data is stored in the cache memory 21.
　プロセッサ１１からメインメモリ１２へのアクセスが発生すると、キャッシュメモリ２１のエントリ０にはメインメモリ１２のアドレス「０ｘ１００」のデータが格納される。エントリ１にはメインメモリ１２のアドレス「０ｘ１１０」または「０ｘ２１０」のデータが格納される。エントリ２にはメインメモリ１２のアドレス「０ｘ１２０」のデータが格納される。エントリ３にはメインメモリ１２のアドレス「０ｘ１３０」のデータが格納される。ライト前データメモリ２２には、キャッシュメモリ２１の各エントリに対応したライト前データの格納領域がある。キャッシュメモリ２１にメインメモリ１２からの読み出しが発生すると、対応する格納領域にメインメモリ１２から読み出されたデータ値が格納される。 When an access from the processor 11 to the main memory 12 occurs, data of the address “0x100” of the main memory 12 is stored in the entry 0 of the cache memory 21. The entry 1 stores data of the address “0x110” or “0x210” of the main memory 12. The entry 2 stores data of the address “0x120” of the main memory 12. The entry 3 stores data of the address “0x130” of the main memory 12. The pre-write data memory 22 has a pre-write data storage area corresponding to each entry of the cache memory 21. When reading from the main memory 12 occurs in the cache memory 21, the data value read from the main memory 12 is stored in the corresponding storage area.
　図３は、第１周期処理の実行中に発生したライトのアドレスとライト値とを示している。 FIG. 3 shows a write address and a write value generated during the execution of the first cycle process.
　図４は、図２のメインメモリ１２、キャッシュメモリ２１およびライト前データメモリ２２の状態から図３に示すライトが発生し、第１周期処理の実行が完了したときのメインメモリ１２、キャッシュメモリ２１およびライト前データメモリ２２の状態を示している。 4 shows the main memory 12 and the cache memory 21 when the write shown in FIG. 3 occurs from the state of the main memory 12, the cache memory 21 and the pre-write data memory 22 in FIG. The state of the pre-write data memory 22 is shown.
　第１周期処理では、アドレス「０ｘ１００」、「０ｘ１１０」、「０ｘ１２０」および「０ｘ１３０」へのライトが発生するため、キャッシュメモリ２１のエントリ０からエントリ３にそれぞれ、ライトが発生したアドレスとライトデータとが格納される。ライト前データメモリ２２には、キャッシュメモリ２１へのデータ格納時にメインメモリ１２から読み出されたデータ「０ｘａａａａ」、「０ｘｂｂｂｂ」、「０ｘｃｃｃｃ」および「０ｘｄｄｄｄ」が格納される。第１周期処理では「０ｘ１００」と「０ｘ１３０」にはライトが２回発生するが、ライト前データメモリ２２のライト前データは、最初にメインメモリ１２から読み出されたデータ値「０ｘａａａａ」および「０ｘｄｄｄｄ」のままとする。 In the first cycle process, since writing to addresses “0x100”, “0x110”, “0x120”, and “0x130” occurs, the address and write data where the write occurred from entry 0 to entry 3 in the cache memory 21 respectively. And are stored. Data “0xaaaa”, “0xbbbb”, “0xcccc”, and “0xdddd” read from the main memory 12 when data is stored in the cache memory 21 are stored in the pre-write data memory 22. In the first cycle process, “0x100” and “0x130” are written twice, but the pre-write data in the pre-write data memory 22 has the data values “0xaaa” and “0xaaa” read from the main memory 12 first. It remains “0xdddd”.
　第１周期処理の実行が完了すると、差分情報抽出部２５が履歴メモリ２３に履歴情報を格納する。具体的には、差分情報抽出部２５は、キャッシュメモリ２１の各エントリのデータ値と、ライト前データ値とを比較し、値が異なっていれば、周期番号と、アドレスと、ライト前データ値とを格納する。図４では、エントリ０、エントリ１およびエントリ２のデータ値とライト前データ値とが異なっているため、アドレス「０ｘ１００」、「０ｘ１１０」および「０ｘ１２０」と対応するライト前データメモリ２２のライト前データ値が履歴メモリ２３に格納される。差分情報抽出部２５が履歴情報を出力した履歴メモリ２３の内容を図５に示す。 When the execution of the first cycle process is completed, the difference information extraction unit 25 stores the history information in the history memory 23. Specifically, the difference information extraction unit 25 compares the data value of each entry in the cache memory 21 with the pre-write data value, and if the values are different, the cycle number, the address, and the pre-write data value And store. In FIG. 4, since the data values of entry 0, entry 1 and entry 2 are different from the pre-write data value, the pre-write data memory 22 corresponding to the addresses “0x100”, “0x110” and “0x120” is written. The data value is stored in the history memory 23. The contents of the history memory 23 from which the difference information extraction unit 25 outputs the history information are shown in FIG.
　その後、差分情報抽出部２５は、ライト前データメモリ２２のライト前データ値を、キャッシュメモリ２１のデータ値に更新する。差分情報抽出部２５による履歴情報の格納後のメインメモリ１２、キャッシュメモリ２１およびライト前データメモリ２２の状態を図６に示す。 Thereafter, the difference information extraction unit 25 updates the pre-write data value of the pre-write data memory 22 to the data value of the cache memory 21. The states of the main memory 12, the cache memory 21 and the pre-write data memory 22 after the history information is stored by the difference information extraction unit 25 are shown in FIG.
　差分情報抽出部２５による履歴情報の格納及び、ライト前データメモリ２２のライト前データ値の更新後、第２周期処理が実行される。 After the history information is stored by the difference information extraction unit 25 and the pre-write data value in the pre-write data memory 22 is updated, the second cycle process is executed.
　図７は、第２周期処理の実行中に発生したライトのアドレスとライト値とを示している。 FIG. 7 shows the address and write value of a write that occurred during the execution of the second cycle process.
　図８は、図６のメインメモリ１２、キャッシュメモリ２１およびライト前データメモリ２２の状態から図７に示すライトが発生し、第２周期処理の実行が完了したときのメインメモリ１２、キャッシュメモリ２１およびライト前データメモリ２２の状態を示している。 FIG. 8 shows the main memory 12 and the cache memory 21 when the write shown in FIG. 7 occurs from the state of the main memory 12, the cache memory 21 and the pre-write data memory 22 in FIG. The state of the pre-write data memory 22 is shown.
　第２周期処理の＃１で「０ｘ１００」へのライトが発生すると、キャッシュメモリ２１のエントリ０にアドレス「０ｘ１００」のデータが格納されているため、キャッシュメモリ２１のライトデータが「０ｘ６６６６」に更新される。 When a write to “0x100” occurs in # 1 of the second cycle process, the data at the address “0x100” is stored in entry 0 of the cache memory 21, so the write data in the cache memory 21 is updated to “0x6666” Is done.
　第２周期処理の＃２で「０ｘ１１０」へのライトが発生すると、キャッシュメモリ２１のエントリ１にアドレス「０ｘ１１０」のデータが格納されているため、キャッシュメモリ２１のライトデータが「０ｘ７７７７」に更新される。 When a write to “0x110” occurs in # 2 of the second cycle process, the write data in the cache memory 21 is updated to “0x7777” because the data of the address “0x110” is stored in the entry 1 of the cache memory 21 Is done.
　第２周期処理の＃３で「０ｘ２１０」へのライトが発生すると、キャッシュメモリ２１の、アドレス「０ｘ２１０」のデータを格納する領域であるエントリ１にすでにアドレス「０ｘ１１０」のデータが格納されているため、キャッシュメモリ２１からアドレス「０ｘ１１０」のデータが追い出される。アドレス「０ｘ１１０」にはプロセッサ１１からライトが行われているため、メインメモリ１２のメモリ値とキャッシュメモリ２１のデータ値が異なっていることから、キャッシュメモリ２１からメインメモリ１２に対してデータを書き戻すライトバック処理が発生する。ライトバック監視部２４は、このライトバック処理を検知すると、ライトバック先のアドレス「０ｘ１１０」と、そのアドレスに対応するライト前データメモリ２２の値「０ｘ３３３３」とを周期番号「２」とともに履歴メモリ２３に格納する。キャッシュメモリ２１からのライトバックとライトバック監視部２４による履歴メモリ２３への履歴の格納の後、キャッシュメモリ２１のエントリ１に＃３のアドレス「０ｘ２１０」とデータ値「０ｘ８８８８」とが格納される。ライト前データメモリ２２のエントリ１にはメインメモリ１２から読み出されたデータ値「０ｘｅｅｅｅ」が格納される。 When a write to “0x210” occurs in # 3 of the second cycle process, the data of the address “0x110” is already stored in the entry 1 which is the area for storing the data of the address “0x210” in the cache memory 21. Therefore, the data at the address “0x110” is evicted from the cache memory 21. Since the address “0x110” is written from the processor 11, the memory value of the main memory 12 and the data value of the cache memory 21 are different, so that data is written from the cache memory 21 to the main memory 12. Write back processing occurs. When the write-back monitoring unit 24 detects this write-back process, the write-back destination address “0x110” and the value “0x3333” of the pre-write data memory 22 corresponding to the address together with the cycle number “2” are stored in the history memory. 23. After write back from the cache memory 21 and storage of the history in the history memory 23 by the write back monitoring unit 24, the address “0x210” and the data value “0x8888” of # 3 are stored in the entry 1 of the cache memory 21. . The data value “0xeeee” read from the main memory 12 is stored in entry 1 of the pre-write data memory 22.
　その後、第２周期処理の＃４で再度「０ｘ１１０」へのライトが発生すると、キャッシュメモリ２１の、アドレス「０ｘ１１０」のデータを格納する領域であるエントリ１にアドレス「０ｘ２１０」のデータが格納されているため、アドレス「０ｘ２１０」のデータ「０ｘ８８８８」がメインメモリ１２に書き戻される。ライトバック監視部２４は、アドレス「０ｘ２１０」とライト前データ値「０ｘｅｅｅｅ」とを履歴メモリ２３に格納する。その後、キャッシュメモリ２１のエントリ１に＃４のアドレス「０ｘ１１０」とデータ値「０ｘ９９９９」とが格納される。ライト前データメモリ２２のエントリ１にはメインメモリ１２から読み出されたデータ値「０ｘ７７７７」が格納される。第２周期処理の実行が完了し、差分情報抽出部２５が履歴メモリ２３に履歴情報を格納する前の履歴メモリ２３の内容を図９に示す。 Thereafter, when the write to “0x110” occurs again in # 4 of the second cycle process, the data of the address “0x210” is stored in the entry 1 which is the area for storing the data of the address “0x110” in the cache memory 21. Therefore, the data “0x8888” at the address “0x210” is written back to the main memory 12. The write back monitoring unit 24 stores the address “0x210” and the pre-write data value “0xeeee” in the history memory 23. Thereafter, the address “0x110” and the data value “0x9999” of # 4 are stored in the entry 1 of the cache memory 21. The data value “0x7777” read from the main memory 12 is stored in entry 1 of the pre-write data memory 22. FIG. 9 shows the contents of the history memory 23 before the execution of the second cycle process is completed and the difference information extraction unit 25 stores the history information in the history memory 23.
　第２周期処理の実行が完了すると、差分情報抽出部２５が第１周期処理の実行完了後と同じように、履歴メモリ２３に履歴情報を格納する。第２周期処理の実行完了後に差分情報抽出部２５が履歴情報を出力した履歴メモリ２３の内容を図１０に示す。 When the execution of the second cycle process is completed, the difference information extraction unit 25 stores the history information in the history memory 23 in the same manner as after the completion of the execution of the first cycle process. FIG. 10 shows the contents of the history memory 23 from which the difference information extraction unit 25 outputs the history information after the execution of the second cycle process is completed.
　その後、差分情報抽出部２５は、ライト前データメモリ２２のライト前データ値を、キャッシュメモリ２１のデータ値に更新する。差分情報抽出部２５による履歴情報の格納後のメインメモリ１２、キャッシュメモリ２１およびライト前データメモリ２２の状態を図１１に示す。 Thereafter, the difference information extraction unit 25 updates the pre-write data value of the pre-write data memory 22 to the data value of the cache memory 21. FIG. 11 shows the states of the main memory 12, the cache memory 21, and the pre-write data memory 22 after the history information is stored by the difference information extraction unit 25.
　差分情報抽出部２５による履歴情報の格納後、第３周期処理が実行される。 After the history information is stored by the difference information extraction unit 25, the third period process is executed.
　このように、周期処理が順次実行される。 In this way, periodic processing is executed sequentially.
　図１２から図１４を参照して、図１１のメインメモリ１２およびキャッシュメモリ２１の状態と、図１０の履歴メモリ２３の内容とから、第３周期処理の実行開始前と、第２周期処理の実行開始前と、第１周期処理の実行開始前とのそれぞれにおけるメインメモリ１２の値を復元する例を説明する。 Referring to FIG. 12 to FIG. 14, from the state of the main memory 12 and the cache memory 21 in FIG. 11 and the contents of the history memory 23 in FIG. An example of restoring the value of the main memory 12 before the start of execution and before the start of execution of the first periodic process will be described.
　第３周期処理の実行開始前の値は、現在のメインメモリ１２またはキャッシュメモリ２１の値と等しいため、メインメモリ１２から読み出されたデータ値が第３周期処理の実行開始前のメインメモリ１２の値となる。第３周期処理の実行開始前のメインメモリ１２の状態を図１２に示す。 Since the value before the execution of the third cycle process is equal to the current value of the main memory 12 or the cache memory 21, the data value read from the main memory 12 is the main memory 12 before the start of the execution of the third cycle process. It becomes the value of. FIG. 12 shows the state of the main memory 12 before the start of execution of the third cycle process.
　第２周期処理の実行開始前の値は、第３周期処理の実行開始前のメインメモリ１２の値と履歴メモリ２３の周期番号「２」のエントリとから復元される。メモリ値再現部２６は、履歴メモリ２３のデータを最新のエントリからみていき、周期番号が「２」のエントリのデータ値をその周期のデータ値とする。図１０の＃４および＃７のように、同じ周期番号で、複数のエントリがある場合は、メモリ値再現部２６は、最も古いエントリのデータ値を、その周期の実行開始時のデータ値とする。復元された第２周期処理の実行開始前のメインメモリ１２の状態を図１３に示す。 The value before the start of the execution of the second cycle process is restored from the value of the main memory 12 and the entry of the cycle number “2” in the history memory 23 before the start of the execution of the third cycle process. The memory value reproduction unit 26 looks at the data in the history memory 23 from the latest entry, and sets the data value of the entry with the cycle number “2” as the data value of the cycle. When there are a plurality of entries with the same cycle number as in # 4 and # 7 in FIG. 10, the memory value reproduction unit 26 uses the data value of the oldest entry as the data value at the start of execution of that cycle. To do. FIG. 13 shows the state of the main memory 12 before the restored second cycle process is started.
　第１周期処理の実行開始前の値は、第２周期処理の実行開始前のメインメモリ１２の値と履歴メモリ２３の周期番号「１」のエントリから復元される。メモリ値再現部２６は、第２周期処理の実行開始前の値の復元方法と同様、履歴メモリ２３のデータを最新のエントリからみていき、周期番号が「１」のエントリのデータ値をその周期のデータ値とする。復元された第１周期処理の実行開始前のメインメモリ１２の状態を図１４に示す。 The value before the start of the execution of the first cycle process is restored from the value of the main memory 12 and the entry of the cycle number “1” in the history memory 23 before the start of the execution of the second cycle process. The memory value reproduction unit 26 looks at the data in the history memory 23 from the latest entry, and the data value of the entry whose cycle number is “1”, as in the method of restoring the value before the execution of the second cycle process. Data value. FIG. 14 shows the state of the main memory 12 before the restored first cycle process is started.
　以上説明したように、履歴メモリ２３には、第１時点におけるメインメモリ１２のデータ値を第２時点におけるメインメモリ１２のデータ値から復元するための履歴が記録される。メインメモリ１２へのライト要求に応じてライトバック方式のキャッシュメモリ２１にデータが格納されるときには、メインメモリ１２に格納されているデータ値がライト前データメモリ２２の、ライト先アドレスに対応する領域に格納される。ライトバック監視部２４は、メインメモリ１２へのライトバックが発生したときに、ライトバック先アドレスとライト前データメモリ２２のライトバック先アドレスに対応する領域に格納されているデータ値とを履歴メモリ２３に記録されている履歴に追加する。差分情報抽出部２５は、第２時点において、キャッシュメモリ２１に格納されているデータ値とライト前データメモリ２２に格納されているデータ値とを比較する。差分がある場合、差分情報抽出部２５は、メインメモリ１２の該当アドレスとライト前データメモリ２２の該当アドレスに対応する領域に格納されているデータ値とを履歴メモリ２３に記録されている履歴に追加する。 As described above, the history memory 23 records a history for restoring the data value of the main memory 12 at the first time point from the data value of the main memory 12 at the second time point. When data is stored in the write-back cache memory 21 in response to a write request to the main memory 12, the data value stored in the main memory 12 is an area corresponding to the write destination address of the pre-write data memory 22. Stored in When the write back to the main memory 12 occurs, the write back monitoring unit 24 displays the write back destination address and the data value stored in the area corresponding to the write back destination address of the pre-write data memory 22 in the history memory. 23 is added to the history recorded in 23. The difference information extraction unit 25 compares the data value stored in the cache memory 21 with the data value stored in the pre-write data memory 22 at the second time point. When there is a difference, the difference information extraction unit 25 stores the corresponding address in the main memory 12 and the data value stored in the area corresponding to the corresponding address in the pre-write data memory 22 in the history recorded in the history memory 23. to add.
　差分情報抽出部２５は、差分がある場合は、履歴への追加後に、ライト前データメモリ２２に格納されているデータ値をキャッシュメモリ２１に格納されているデータ値に更新する。 When there is a difference, the difference information extraction unit 25 updates the data value stored in the pre-write data memory 22 to the data value stored in the cache memory 21 after addition to the history.
　本実施の形態では、第１時点および第２時点は、複数の処理それぞれの開始時点および終了時点である。履歴に追加されるアドレスおよびデータ値は、複数の処理のうち、該当する処理を識別する情報とともに履歴メモリ２３に記録される。 In the present embodiment, the first time point and the second time point are the start time point and the end time point of each of the plurality of processes. The address and data value added to the history are recorded in the history memory 23 together with information for identifying the corresponding process among the plurality of processes.
　前述した例において、第１周期処理の実行開始時点を第１時点、第１周期処理の実行終了時点を第２時点とすると、第１周期処理を識別する情報として、周期番号「１」が履歴メモリ２３に記録される。 In the example described above, if the execution start time of the first cycle process is the first time point and the execution end time of the first cycle process is the second time point, the cycle number “1” is a history as information for identifying the first cycle process. Recorded in the memory 23.
　前述した例において、第２周期処理の実行開始時点を第１時点、第２周期処理の実行終了時点を第２時点とすると、第２周期処理を識別する情報として、周期番号「２」が履歴メモリ２３に記録される。 In the example described above, when the execution start time of the second cycle process is the first time point and the execution end time of the second cycle process is the second time point, the cycle number “2” is a history as information for identifying the second cycle process. Recorded in the memory 23.
　なお、後述するように、本実施の形態では、ライトバック監視部２４は、履歴に追加するアドレスおよびデータ値のデータ量が履歴メモリ２３の容量を超える場合は、古いデータから順番に上書きしていく。差分情報抽出部２５も、履歴に追加するアドレスおよびデータ値のデータ量が履歴メモリ２３の容量を超える場合は、古いデータから順番に上書きしていく。 As will be described later, in this embodiment, the write-back monitoring unit 24 overwrites the oldest data in order when the data amount of the address and data value to be added to the history exceeds the capacity of the history memory 23. Go. The difference information extraction unit 25 also overwrites the old data in order when the data amount of the address and data value to be added to the history exceeds the capacity of the history memory 23.
　メモリ値再現部２６は、履歴メモリ２３に記録されている履歴を用いて、第２時点におけるメインメモリ１２のデータ値から第１時点におけるメインメモリ１２のデータ値を復元する。 The memory value reproduction unit 26 restores the data value of the main memory 12 at the first time point from the data value of the main memory 12 at the second time point, using the history recorded in the history memory 23.
　本実施の形態では、メモリ値再現部２６は、第２時点においてキャッシュメモリ２１に格納されているデータ値がメインメモリ１２に反映された場合にメインメモリ１２に格納されるデータ値を、第２時点におけるメインメモリ１２のデータ値として用いる。また、メモリ値再現部２６は、第１時点においてキャッシュメモリ２１に格納されているデータ値がメインメモリ１２に反映された場合にメインメモリ１２に格納されるデータ値を、第１時点におけるメインメモリ１２のデータ値として復元する。 In the present embodiment, the memory value reproduction unit 26 converts the data value stored in the main memory 12 to the second value when the data value stored in the cache memory 21 at the second time point is reflected in the main memory 12. Used as the data value of the main memory 12 at the time. In addition, the memory value reproduction unit 26 uses the data value stored in the main memory 12 when the data value stored in the cache memory 21 at the first time point is reflected in the main memory 12 as the main memory value at the first time point. Restored as 12 data values.
　前述した例において、メモリ値再現部２６は、図４においてキャッシュメモリ２１に格納されているデータ値がメインメモリ１２に反映された場合にメインメモリ１２に格納されるデータ値を、図１３に示したような第１周期処理の実行終了時点におけるメインメモリ１２のデータ値として用いる。また、メモリ値再現部２６は、第１周期処理の実行開始時点においてキャッシュメモリ２１に格納されているデータ値がメインメモリ１２に反映された場合にメインメモリ１２に格納されるデータ値を、図１４に示したような第１周期処理の実行開始時点におけるメインメモリ１２のデータ値として復元する。 In the example described above, the memory value reproduction unit 26 shows the data values stored in the main memory 12 when the data values stored in the cache memory 21 in FIG. It is used as the data value of the main memory 12 at the end of execution of the first cycle process. In addition, the memory value reproduction unit 26 displays the data value stored in the main memory 12 when the data value stored in the cache memory 21 is reflected in the main memory 12 at the start of execution of the first periodic process. 14 is restored as the data value of the main memory 12 at the start of execution of the first periodic process as shown in FIG.
　前述した例において、メモリ値再現部２６は、図８においてキャッシュメモリ２１に格納されているデータ値がメインメモリ１２に反映された場合にメインメモリ１２に格納されるデータ値を、図１２に示したような第２周期処理の実行終了時点におけるメインメモリ１２のデータ値として用いる。また、メモリ値再現部２６は、第２周期処理の実行開始時点においてキャッシュメモリ２１に格納されているデータ値がメインメモリ１２に反映された場合にメインメモリ１２に格納されるデータ値を、図１３に示したような第２周期処理の実行開始時点におけるメインメモリ１２のデータ値として復元する。 In the example described above, the memory value reproduction unit 26 shows the data values stored in the main memory 12 when the data values stored in the cache memory 21 in FIG. It is used as the data value of the main memory 12 at the end of execution of the second cycle processing. In addition, the memory value reproducing unit 26 displays the data value stored in the main memory 12 when the data value stored in the cache memory 21 is reflected in the main memory 12 at the start of execution of the second cycle processing. 13 is restored as the data value of the main memory 12 at the start of execution of the second cycle processing as shown in FIG.
　＊＊＊実施の形態の効果の説明＊＊＊
　本実施の形態によれば、ソフトウェアの処理時間に影響を与えず、かつ、少ない容量でデータ値の履歴情報を残すことができる。 *** Explanation of the effect of the embodiment ***
According to the present embodiment, it is possible to leave history information of data values with a small capacity without affecting the processing time of software.
　本実施の形態は、周期処理を行う組込みシステムに適用することができ、そのようなシステムにおいて、デバッグまたは障害調査のためにメインメモリ１２のメモリ値の履歴の取得および再現を行うことができる。 The present embodiment can be applied to an embedded system that performs periodic processing. In such a system, the history of the memory value of the main memory 12 can be acquired and reproduced for debugging or investigating a failure.
　周期処理開始時のすべてのデータ値を記録しておくと、再現したい周期の数に比例して履歴データの量が増えてしまう。本実施の形態によれば、周期処理開始時のデータ値を少ない履歴容量で再現することができる。 If you record all the data values at the start of the cycle process, the amount of history data will increase in proportion to the number of cycles you want to reproduce. According to the present embodiment, the data value at the start of the periodic process can be reproduced with a small history capacity.
　本実施の形態では、メインメモリ１２のデータを最新の履歴情報から逆に辿って復元していく。そのため、履歴メモリ２３の容量がいっぱいになった場合は古いエントリを順次上書きしていくことで、履歴の格納を継続することが可能となる。さらに、最新のエントリから順番に辿るため、復元したい周期の履歴メモリ２３の履歴情報が残っている限り、データの復元が可能となる。 In this embodiment, the data in the main memory 12 is restored by tracing back from the latest history information. Therefore, when the capacity of the history memory 23 becomes full, it is possible to continue storing the history by sequentially overwriting old entries. Furthermore, since tracing is performed in order from the latest entry, data can be restored as long as the history information in the history memory 23 of the cycle to be restored remains.
　本実施の形態では、周期処理の実行中の変化値のみ履歴情報として記録していくため、アクセスの履歴のみを残す方法と比較しても復元に必要なデータ量は少ない。また、初期値データと差分情報とを格納する方式と異なり、データの復元は現在のメインメモリ１２の値と、履歴メモリ２３の値とから行うため、データの復元に必要なデータ量は初期値データがない分、少なくなる。 In the present embodiment, since only the change value during the execution of the periodic process is recorded as history information, the amount of data required for restoration is small compared with the method of leaving only the access history. Further, unlike the method of storing the initial value data and the difference information, the data restoration is performed from the current value of the main memory 12 and the value of the history memory 23. Therefore, the data amount necessary for the data restoration is the initial value. Less because there is no data.
　本実施の形態では、復元したデータ値はメインメモリ１２あるいは図示しない別のメモリに出力する。メインメモリ１２の未使用領域または別のメモリに復元データを出力した場合は、現在の周期処理である第ｉ周期処理の実行完了時のメインメモリ１２のデータ値を保持しつつ、過去の周期処理である第ｋ周期処理の実行開始時のデータ値を再現することが可能となる。ｉおよびｋは、ｋ≦ｉを満たす整数である。復元したデータ値を、復元したデータのアドレスに出力して上書きした場合は、メインメモリ１２の値を第ｋ周期処理の実行開始時の状態にロールバックすることが可能になる。 In this embodiment, the restored data value is output to the main memory 12 or another memory (not shown). When the restoration data is output to an unused area of the main memory 12 or another memory, the past periodic processing is performed while holding the data value of the main memory 12 at the completion of execution of the i-th periodic processing which is the current periodic processing. It is possible to reproduce the data value at the start of execution of the k-th cycle process. i and k are integers satisfying k ≦ i. When the restored data value is output to the restored data address and overwritten, the value of the main memory 12 can be rolled back to the state at the start of execution of the k-th cycle process.
　＊＊＊他の構成＊＊＊
　本実施の形態の変形例として、メモリ値再現部２６は、プロセッサ１１または外部のプロセッサ上で実行するプログラムとして実現してもよい。 *** Other configurations ***
As a modification of the present embodiment, the memory value reproduction unit 26 may be realized as a program executed on the processor 11 or an external processor.
　履歴メモリ２３は、メインメモリ１２の一部であってもよい。すなわち、履歴メモリ２３にメインメモリ１２の一部を利用してもよい。この場合は、履歴メモリ２３は、履歴の記録の対象外である。すなわち、履歴メモリ２３に相当する領域を履歴情報の収集対象外とすることにより、履歴メモリ２３の領域への格納履歴を履歴メモリ２３の領域に格納することを防ぐことができる。 The history memory 23 may be a part of the main memory 12. That is, a part of the main memory 12 may be used for the history memory 23. In this case, the history memory 23 is not subject to history recording. That is, by making the area corresponding to the history memory 23 out of the collection target of the history information, it is possible to prevent the storage history in the area of the history memory 23 from being stored in the area of the history memory 23.
　実施の形態２．
　本実施の形態について、主に実施の形態１との差異を、図１５を用いて説明する。 Embodiment 2. FIG.
The difference between the present embodiment and the first embodiment will be mainly described with reference to FIG.
　本実施の形態では、メモリ履歴管理システム１０は、メモリ履歴収集システム１３と、データ値復元システム１４とを備える。 In the present embodiment, the memory history management system 10 includes a memory history collection system 13 and a data value restoration system 14.
　メモリ履歴収集システム１３とデータ値復元システム１４は、ＬＡＮまたはインターネット等のネットワーク４０で接続されている。「ＬＡＮ」は、Ｌｏｃａｌ　Ａｒｅａ　Ｎｅｔｗｏｒｋの略語である。 The memory history collection system 13 and the data value restoration system 14 are connected by a network 40 such as a LAN or the Internet. “LAN” is an abbreviation for Local Area Network.
　メモリ履歴収集システム１３は、図１に示した実施の形態１のメモリ履歴管理システム１０からメモリ値再現部２６を除いて構成されている。データの復元処理以外の機能および動作は同じであるため、説明を省略する。 The memory history collection system 13 is configured by removing the memory value reproduction unit 26 from the memory history management system 10 of the first embodiment shown in FIG. Since the functions and operations other than the data restoration processing are the same, the description thereof is omitted.
　データ値復元システム１４は、コンピュータである。データ値復元システム１４は、プロセッサ３１とメモリ３２とを備える。 The data value restoration system 14 is a computer. The data value restoration system 14 includes a processor 31 and a memory 32.
　本実施の形態では、実施の形態１のメモリ値再現部２６をデータ値復元システム１４のプロセッサ３１上で実行するプログラムであるメモリ値再現プログラム３３として実現している。 In the present embodiment, the memory value reproduction unit 26 of the first embodiment is realized as a memory value reproduction program 33 that is a program executed on the processor 31 of the data value restoration system 14.
　本実施の形態では、メモリ履歴収集システム１３にて取得した履歴メモリ２３のメモリ値を示す履歴情報３４と、メインメモリ１２の値を示すメインメモリデータ値３５とが、ネットワーク４０を経由してデータ値復元システム１４のメモリ３２に転送される。メモリ値再現プログラム３３は、メモリ３２に転送された履歴情報３４とメインメモリデータ値３５とをもとに、各周期処理の実行開始時のメインメモリ１２の値の復元を行う。 In the present embodiment, the history information 34 indicating the memory value of the history memory 23 acquired by the memory history collection system 13 and the main memory data value 35 indicating the value of the main memory 12 are transmitted via the network 40. It is transferred to the memory 32 of the value restoration system 14. Based on the history information 34 and the main memory data value 35 transferred to the memory 32, the memory value reproduction program 33 restores the value of the main memory 12 at the start of execution of each periodic process.
　本実施の形態では、メモリ値の再現をメモリ履歴の収集と異なるシステムにて行うことで、周期処理を行う組込みシステムに再現されたデータを格納する領域を備える必要がないため、メモリ容量を抑えることができるという効果がある。 In this embodiment, the memory value is reproduced by a system different from the memory history collection, so that it is not necessary to provide an area for storing the reproduced data in an embedded system that performs periodic processing, so that the memory capacity is reduced. There is an effect that can be.
　１０　メモリ履歴管理システム、１１　プロセッサ、１２　メインメモリ、１３　メモリ履歴収集システム、１４　データ値復元システム、２０　メモリ履歴収集回路、２１　キャッシュメモリ、２２　ライト前データメモリ、２３　履歴メモリ、２４　ライトバック監視部、２５　差分情報抽出部、２６　メモリ値再現部、３１　プロセッサ、３２　メモリ、３３　メモリ値再現プログラム、３４　履歴情報、３５　メインメモリデータ値、４０　ネットワーク。 10 memory history management system, 11 processor, 12 main memory, 13 memory history collection system, 14 data value restoration system, 20 memory history collection circuit, 21 cache memory, 22 pre-write data memory, 23 history memory, 24 write back monitoring unit 25, difference information extraction unit, 26 memory value reproduction unit, 31 processor, 32 memory, 33 memory value reproduction program, 34 history information, 35 main memory data value, 40 network.

Claims (8)

  1. 　第１時点におけるメインメモリのデータ値を第２時点における前記メインメモリのデータ値から復元するための履歴を記録する履歴メモリと、
    　前記メインメモリへのライト要求に応じてライトバック方式のキャッシュメモリにデータが格納されるときに、前記メインメモリに格納されているデータ値をライト先アドレスに対応する領域に格納するライト前データメモリと、
    　前記メインメモリへのライトバックが発生したときに、ライトバック先アドレスと前記ライト前データメモリの前記ライトバック先アドレスに対応する領域に格納されているデータ値とを前記履歴メモリに記録されている履歴に追加するライトバック監視部と、
    　前記第２時点において、前記キャッシュメモリに格納されているデータ値と前記ライト前データメモリに格納されているデータ値とを比較し、差分がある場合は、前記メインメモリの該当アドレスと前記ライト前データメモリの前記該当アドレスに対応する領域に格納されているデータ値とを前記履歴メモリに記録されている履歴に追加する差分情報抽出部と
    を備えるメモリ履歴管理システム。     A history memory for recording a history for restoring the data value of the main memory at the first time point from the data value of the main memory at the second time point;
    A pre-write data memory that stores a data value stored in the main memory in an area corresponding to a write destination address when data is stored in a write-back cache memory in response to a write request to the main memory When,
    When a write back to the main memory occurs, a write back destination address and a data value stored in an area corresponding to the write back destination address of the pre-write data memory are recorded in the history memory. A write-back monitoring unit to be added to the history;
    At the second time point, the data value stored in the cache memory is compared with the data value stored in the pre-write data memory, and if there is a difference, the corresponding address in the main memory and the pre-write A memory history management system comprising: a difference information extraction unit that adds a data value stored in an area corresponding to the corresponding address of a data memory to a history recorded in the history memory.
  2. 　前記差分情報抽出部は、前記差分がある場合は、前記履歴への追加後に、前記ライト前データメモリに格納されているデータ値を前記キャッシュメモリに格納されているデータ値に更新する請求項１に記載のメモリ履歴管理システム。 The difference information extraction unit updates the data value stored in the pre-write data memory to the data value stored in the cache memory after addition to the history when there is the difference. Memory history management system described in 1.
  3. 　前記第１時点および前記第２時点は、複数の処理それぞれの開始時点および終了時点であり、
    　前記履歴に追加されるアドレスおよびデータ値は、前記複数の処理のうち、該当する処理を識別する情報とともに前記履歴メモリに記録される請求項１または２に記載のメモリ履歴管理システム。     The first time point and the second time point are start time points and end time points of a plurality of processes,
    The memory history management system according to claim 1, wherein the address and the data value added to the history are recorded in the history memory together with information for identifying a corresponding process among the plurality of processes.
  4. 　前記履歴メモリに記録されている履歴を用いて、前記第２時点における前記メインメモリのデータ値から前記第１時点における前記メインメモリのデータ値を復元するメモリ値再現部をさらに備える請求項１から３のいずれか１項に記載のメモリ履歴管理システム。 The apparatus further comprises a memory value reproduction unit that restores the data value of the main memory at the first time point from the data value of the main memory at the second time point using the history recorded in the history memory. 4. The memory history management system according to any one of items 3.
  5. 　前記メモリ値再現部は、前記第２時点において前記キャッシュメモリに格納されているデータ値が前記メインメモリに反映された場合に前記メインメモリに格納されるデータ値を、前記第２時点における前記メインメモリのデータ値として用いる請求項４に記載のメモリ履歴管理システム。 The memory value reproduction unit converts the data value stored in the main memory when the data value stored in the cache memory at the second time point is reflected in the main memory, to the main value at the second time point. The memory history management system according to claim 4, wherein the memory history management system is used as a data value of a memory.
  6. 　前記メモリ値再現部は、前記第１時点において前記キャッシュメモリに格納されているデータ値が前記メインメモリに反映された場合に前記メインメモリに格納されるデータ値を、前記第１時点における前記メインメモリのデータ値として復元する請求項４または５に記載のメモリ履歴管理システム。 The memory value reproduction unit converts the data value stored in the main memory when the data value stored in the cache memory at the first time point is reflected in the main memory, to the main value at the first time point. 6. The memory history management system according to claim 4, wherein the memory history management system is restored as a data value of the memory.
  7. 　前記履歴メモリは、前記メインメモリの一部であり、前記履歴の記録の対象外である請求項１から６のいずれか１項に記載のメモリ履歴管理システム。 The memory history management system according to any one of claims 1 to 6, wherein the history memory is a part of the main memory and is not subject to recording of the history.
  8. 　前記ライトバック監視部または前記差分情報抽出部は、前記履歴に追加するアドレスおよびデータ値のデータ量が前記履歴メモリの容量を超える場合は、古いデータから順番に上書きしていく請求項１から７のいずれか１項に記載のメモリ履歴管理システム。 The write-back monitoring unit or the difference information extracting unit overwrites data in order from the oldest data when the data amount of the address and data value to be added to the history exceeds the capacity of the history memory. The memory history management system according to any one of the above.
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