WO2019238443A1

WO2019238443A1 - Voltage source converter generating at least two pulse trains using at least three voltage levels

Info

Publication number: WO2019238443A1
Application number: PCT/EP2019/064299
Authority: WO
Inventors: Antonios ANTONOPOULOS; Jan Svensson; Malaya SAHU; Anshuman Shukla
Original assignee: Abb Schweiz Ag
Priority date: 2018-06-12
Filing date: 2019-06-03
Publication date: 2019-12-19
Also published as: SE1850720A1; SE542022C2

Abstract

A voltage source converter configured to generate at least two pulse trains using at least three voltage levels comprises a first arm (ua) between a junction (j) and a first DC terminal (DC₁) having a first voltage level (Vdc/2), a second arm (la) between the first junction and a second DC terminal (DC₂) having a second voltage level (-Vdc/2) and a third arm (na) between the junction (j) and a neutral point (np) having a third voltage level (0) between the first and second voltage levels, wherein at least one of the arms (ua, la) comprises cells (Cua1, Cua2, Cua₃, Cua₄, Cla1, Cla2, Cla₃, Cla₄), each cell comprising a main switch, a first auxiliary switch and a snubber capacitor, where the main switches switch between two of the voltage levels and the auxiliary switches introduce a slope in the transition between the two levels; and the other arms (na) only comprise switches (S1, S2) for connecting the junction to a corresponding voltage level.

Description

VOLTAGE SOURCE CONVERTER GENERATING AT LEAST TWO PULSE TRAINS USING AT LEAST THREE VOLTAGE LEVELS

FIELD OF INVENTION

The present invention generally relates to a voltage source converter. More particularly the present invention relates to a voltage source converter configured to generate at least two pulse trains using at least three voltage levels.

BACKGROUND

The Modular Multilevel Converter (MMC) is frequently used in different high voltage applications. The MMC employs submodules in phase arms between two Direct Current (DC) terminals for forming a sinusoidal waveform, such as an Alternating Current (AC) waveform. Such

submodules comprise a pair of switches in parallel with a capacitor. There are also different variations of such a converter, where one variation disclosed in US 4670828 has the midpoint between two such phase arms connected to a neutral point via two bidirectional switches.

The Quasi-Two Level (Q2L) conversion technique has recently become interesting to use in various high-voltage applications, such as in power transmission and distribution systems. The Q2L conversion technique uses cells that resemble the submodules of the MMC. These cells comprise a main switch in parallel with an auxiliary switch and a snubber capacitor However, in the Q2L technique a single pulse train with pulses between two voltage levels is generated using the cells. This type of technique is for instance described by Gowaid et al in“Quasi Two-Level Operation of Modular Multilevel Converter for Use in a High-Power DC Transformer With DC Fault Isolation Capability”, IEEE Transactions On Power

Electronics, Vol. 30, No. 1, January 2015. It is also described by Mertens and Kucka in“Quasi Two-Level PWM Operation of an MMC Phase Leg With Reduced Module Capacitance”, IEEE Transactions On Power

Electronics, Vol. 31, No. 10, October 2016.

The Q2L converter can be considered to be an intermediate step between a standard two-level (2L) converter and a MMC. It makes steps with a dwell time of t_D during the transition between the two voltage levels present in the phase voltage waveform of a 2L converter. This is done in order to limit the dv/dt produced by the converter during this transition. Higher values of dv/dt can result in increased electromagnetic interference (EMI) and insulation stress on reactors connected to the converter. Moreover, in Q2L there are no advanced requirements on gate units as the series connection relies on active snubber and not on advanced gate unit.

The Q2L converter has an advantage compared to the MMC in that the required capacitance per cell is much lower than the corresponding capacitance per submodule. This reduction in capacitance occurs because each cell capacitance only charges or discharges during the time when transition between the upper and lower arms of one phase leg occurs. This is a significantly smaller charging/discharging time than what is seen by the submodule capacitors in an MMC.

The Q2L converter is a voltage source converter, which needs a

capacitance on the DC side and an inductance on the AC side terminals. A discrete DC-link capacitor will be required to filter the ripple in current. Hence, although the cell capacitor size is reduced because of the Q2L operation, a large size of capacitor requirement on the DC side does not necessarily result in a compact converter system. Moreover, the converter output voltage waveform is essentially of the 2L shape. This will

necessarily pose a significant amount of Alternating Current (AC) filters requirements. It is thus of interest to obtain an improvement of the Q2L technique with regard to one or more of the above mentioned problems and especially one that reduces the filtering requirements.

SUMMARY OF THE INVENTION

The present invention is directed towards reducing the filtering

requirements in relation to the use of the Quasi-Two Level conversion technique.

This object is according to a first aspect achieved through a voltage source converter configured to generate at least two pulse trains using at least three voltage levels, which converter comprises a first converter arm connected between a junction and a first DC terminal having a first voltage level, a second converter arm connected between the first junction and a second DC terminal having a second voltage level and a third converter arm connected between the junction and a neutral point having a third voltage level between the first and second voltage levels, wherein at least one of the arms comprises cells, each cell comprising a first main switch, a first auxiliary switch and snubber capacitor, wherein the first main switches of the cells are configured to switch between two of the voltage levels and the first auxiliary switches of the cells are configured to connect snubber capacitors to introduce a slope in the transition between the two levels; and the other or remaining arms only comprise switches for connecting the junction to a corresponding voltage level.

The at least one arm comprising cells may be the first and the second arms, in which case the other arm only comprising switches is the third arm. In this case the corresponding voltage level of the third arm is a neutral voltage, for instance zero or ground. In this case it is also possible that the cells have a unipolar voltage contribution capability, which may be realized through the cells having a half-bridge structure. The at least one arm comprising cells may be the neutral arm, in which case the other or remaining arms only comprising switches are the first and second arms. In this case the corresponding voltage level of the first arm is the voltage level of the first DC terminal and the corresponding voltage level of the second arm is the voltage level of the second DC terminal. In this case the third arm may also comprise cells with a bipolar voltage contribution capability, for instance realized as full-bridge cells, i.e. cells having a full-bridge structure. The third arm can also comprise cells with a unipolar voltage contribution capability, such as half-bridge cells. The third arm may thus have a mix of half- and full -bridge cells. Other similar cell structures may also be used, which can produce uni- and/or bi polar voltages.

The sum of cells of an arm may be rated for the full converter voltage, i.e. the difference between the first and the second voltage. Thereby these cells combinedly are dimensioned for handling the full converter voltage.

It is furthermore possible that the at least one arm comprising cells also comprises switches. In this case these are configured to be turned on when the cells of the arm are being operated for switching between two of the voltage levels.

The cells of an arm may be rated for the difference between the third voltage level and one of the first or the second voltage levels. In this case the switches of the arm are rated for the voltage difference between the third voltage level and the other of the first or second voltage levels in order for the arm to be rated for the full converter voltage. If for instance the first arm comprises both cells and switches, then the cells of this first arm would be rated for the difference between the first and the third voltage levels, while the switches would be rated for the difference between the third and second voltage levels. If the second arm comprises both cells and switches, then the cells of this second arm would be rated for the difference between the third and second voltage levels, while the switches would be rated for the difference between the first and third voltage levels.

If an arm comprises cells with bipolar voltage contribution capability, then each cell with bipolar voltage contribution capability may comprise a second main switch and a second auxiliary switch, where the second main switches of these cells are configured to switch between two voltage levels, one of which is another than those of the first main switches, and the second auxiliary switches of the cells are configured to connect the snubber capacitors to introduce a slope in the transition between the two levels operated by the second auxiliary switches.

The cells may comprise a first damping resistor between the first auxiliary switch and the snubber capacitor and a first diode between a first and a second junction, where the first junction is a junction between the first auxiliary switch and the first main switch and the second junction is a junction between the first damping resistor and the snubber capacitor.

In case the cells have a bipolar voltage contribution capability, then these cells may comprise a second damping resistor between the second auxiliary switch and the snubber capacitor and a second diode between a third and the second junction. In this case the second damping resistor may be connected to the second junction. The third junction may be a junction between the second main switch and second auxiliary switch.

If other cell structures than half-bridge and full-bridge cell structures are used in the converter, then the switches of these other cell structures may in a analogous manner be provided with snubber diodes and damping resistors.

The neutral point may be a midpoint of a capacitor string connected between the first and second DC terminals. The capacitor string may comprise two or more capacitors between the midpoint and a corresponding DC terminal. There may thus be two or more capacitors between the first DC terminal and the neutral point as well as two or more capacitors between the second DC terminal and the neutral point. There may also be a number of branches with the same realization as the third arm, where each such branch between the first DC terminal and the neutral point is at one end connected between two capacitors and at the other end connected to a corresponding point in the first arm and each such branch between the second DC terminal and the neutral point is at one end connected between two capacitors and at the other end connected to a corresponding point in the second arm, where such a corresponding point in the first and the second arms is a point between two identical strings with components and where two identical strings in the first arm are connected in series with each other between the first DC terminal and the junction, while two identical strings in the second arm are connected in series with each other between the second DC terminal and the junction.

The point in the first and second arm may be a point between two identical strings with cells, a point between two identical strings with switches or a point between two identical strings of cells and switches.

The switches of the cells may be Metal Oxide Semiconductor Field Effect Transistor (MOSFET) switches or similar switches or a combination of switches having bi-directional current handling capability. They may also be Silicon Carbide (SiC) switches, i.e. switches on SiC substrates or other wide-band gap devices.

The switches of arms only comprising switches may in turn comprise Insulated Gate Bipolar Transistors (IGBTs). These switches may

furthermore be Silicon (Si) switches, i.e. switches on Si substrates.

The pulse trains may have a periodicity by which they occur allowing filtering equipment to form a sine wave and the slope of a pulse in a pulse train may be a fraction of such a periodicity of the pulse train, such as i/ioo. The periodicity of the pulse train may furthermore be half the period of the sine wave. Each cell may also have a dwell time, i.e. a time at which it dwells at a voltage provided by the snubber capacitor. The dwell time may be in the range of tens to hundreds of nano seconds for a fundamental frequency of the line of 50 or 60Hz , i.e. for a period of 0.02 - 0.017 seconds. The period may therefore be 104 - 10⁶ times longer than the dwell time.

The invention has a number of advantages. It uses an improved Quasi-Two Level (Q2L) conversion technique. Thereby it is possible to the use increased switching frequencies and reduce the cell capacitor size. The improve technique also leads to reduced requirements of active/passive filters and passive components size.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will in the following be described with reference being made to the accompanying drawings, where fig. 1 schematically shows a first cell-based voltage source converter, fig. 2 schematically shows a half-bridge cell for use in the converter of fig.

1,

fig. 3 schematically shows the how cells and switches of the converter in fig. 1 generate different voltage levels,

fig. 4 schematically shows the generation of a first and second pulse train using the converter of fig. 1,

fig. 5 schematically shows a second cell-based voltage source converter, fig. 6 schematically shows a full bridge cell for use in the converter in fig. 5, fig. 7 shows the generation of positive pulses in the converter of fig. 5, fig. 8 shows active and inactive parts of the full-bridge cell for forming the positive pulses,

fig. 9 shows the generation of negative pulses in the converter of fig. 5, fig. 10 shows active and inactive parts of the full-bridge cell for forming the negative pulses, fig. li schematically shows a third cell-based voltage source converter, fig. 12 schematically shows a fourth cell-based voltage source converter that is a development of the converter in fig. t,

fig. 13 schematically shows a fifth cell-based voltage source converter that is a development of the converter in fig. 5,

fig. 14 schematically shows a sixth cell-based voltage source converter, that is a development of the converter in fig. 11,

fig. 15 schematically shows a seventh cell-based voltage source converter, fig. 16 schematically shows an eighth cell-based voltage source converter together with voltages generated therein,

fig. 17 schematically shows how cells and switches of the converter in fig.

15 generate different voltage levels,

fig. 18 schematically shows the generation of a first and second pulse train using the converter of fig. 15, and

fig. 19 shows a ninth cell-based voltage source converter together with a pulse train generated using an arm with cells.

DETAILED DESCRIPTION OF THE INVENTION

In the following, a detailed description of preferred embodiments of the invention will be given.

Fig. 1 shows one variation of a converter in the form of a cell based voltage source converter 10. The converter operates to convert between alternating current (AC) and direct current (DC). The converter 10 in fig. 1 is shown as comprising three arms, which three arms are all related to a single AC phase. It should however be realized that there may be three different phases and thus a totality of nine different arms, with three arms for each phase.

As can be seen in the figure there is a first upper converter arm ua connected between a first DC terminal DCi and a first junction j, a second lower converter arm la connected between the junction j and a second DC terminal DC2. There is also a string of capacitors Cl and C2 connected between the first and second DC terminals DCi and DC2 and the midpoint of this string is a neutral point np or grounding point. A third neutral converter arm na is connected between the junction j and the neutral point. Via the junction j there is also provided a first AC terminal ACi on which an output voltage is provided.

In a three-phase case there would be three groups of arms, where each group comprises an upper arm, a lower arms and a neutral arm connected to a corresponding AC terminal, with the first arms of all groups being connected to the first DC terminal, all lower arms connected to the second DC terminal and all neutral arms connected to the capacitor string midpoint. The capacitor string midpoint is thereby common to all neutral arms.

The first DC terminal DCi may be connected to a first pole of a DC power transmission system, such as a High Voltage Direct Current (HVDC) power transmission system and the second DC terminal DC2 may be connected to a second pole of the same system.

The first DC terminal DCi furthermore has a first potential or voltage level Vdc/2 that may be positive. The first pole may therefore also be termed a positive pole. The second DC terminal DC2 has a second potential or voltage level -Vdc/2 and the second pole may therefore be termed a negative pole. The neutral point has a third potential or voltage level that is a level between the voltage levels of the two DC terminals DCi and DC2. It may for instance be a zero voltage level. The AC terminal ACi may be connected to an AC system, for instance via a transformer.

As mentioned above, the type of voltage source converter shown in fig. l is only one example of a converter where the invention may be used. It is for instance possible to use the converter as a reactive compensating device, such as a Static Compensator. The voltage source converter depicted in fig. 1 has a symmetric monopole configuration. It is thus connected between a positive and negative potential. As an alternative it may be connected in an asymmetric monopole configuration or a symmetric bipole configuration.

At least one of the arms comprises cells and any arm that lacks cells only comprises switches for connecting the junction to a corresponding voltage level. In the first converter to, the upper and lower arms ua and la comprise cells, which cells are with advantage connected in series or in cascade in an arm, and thereby the neutral arm comprises switches.

In the example given in fig. t there are four series-connected or cascaded cells in the upper and lower arms ua and la. Thus, the upper arm ua includes four cells Cuai, Cua2, Cua3 and Cua4, while the lower arm la includes four cells Clai, Cla2, Cla3 and Cla4. Across each cell there is a voltage of Vdc/n, where n is the sum of cells in the upper or lower arms, which means that the sum of cells in an arm provides the voltage of Vdc. However, the rating of the cells in the arm in the converter in fig. l is typically Vdc/n.

The neutral arm na, which only comprises switches, i.e. it lacks cells, comprises a first and a second switch Si and S2, with opposite orientation, where each switch is realized as a combination of a transistor, such as an Insulated Gate Bipolar Transistor (IGBT) with anti-parallel diode on a suitable substrate, such as Silicon (S) or Silicon Carbide (Si). The switch is thereby an Si switch or an SiC switch. Through providing two oppositely oriented switches, the junction j may be connected with and disconnected from the neutral point np independently of the direction of current through the neutral arm. An SiC switch is an example of one type of wide band gap device. It should be realized that it is possible to also user other types of band gap devices. The number of cells provided in fig. l is only an example. It therefore has to be stressed that the number of cells in an arm may vary, where the number typically depends on the shape that is to be created in the AC terminal ACi and the magnitude of the voltages involved.

There is also a control unit 12 provided for controlling all the arms of the converter 10. However, in order to simplify the figure only the control of the cells Cuai, Cua2, Cua3 and Cua4 in the upper arm ua and the switches Si and S2 in the neutral arm na are indicated with dashed arrows in fig. 1. The control unit 12 may be implemented through a computer or processor with associated program memory. Other types of realizations such as using Field- Programmable Gate Arrays (FPGAs) are also possible.

As was mentioned above, the upper and lower arms ua and la of the voltage source converter 10 in the example in fig. 1 comprise cells. A cell is a unit that may be switched when transitioning between two voltage levels at the junction j. It is more particularly provided for giving the edges of pulses generated at the junction j a slope. A cell with unipolar voltage contribution capability, such as a cell having a half-bridge structure, is suitable for use in the upper and lower arms ua and la. An example of such a cell is schematically shown in fig. 2.

The cell Cuai comprises a first main switch MSW and in parallel with this first main switch MSW there is a branch comprising a snubber capacitor Csn in series with a second auxiliary switch ASW. In the cell Cuai shown in fig. 2 there is also an optional damping resistor Rd connected in the branch between the auxiliary switch ASW and the snubber capacitor Csn as well as an optional snubber diode Dsn connected between a first and a second junction, where the first junction is a junction between the two switches ASW and MSW and the second junction is a junction between the damping resistor Rd and the snubber capacitor Csn. The diode Dsn conducts current towards the snubber capacitor Csn. A first connection terminal of the cell Cuai is in this case provided at the first junction between the two switches MSW and ASW and a second connection terminal is provided at a junction between the main switch and the snubber capacitor. The cell Cuai may be switched to provide a voltage contribution corresponding to the voltage of the snubber capacitor Csn or a zero voltage contribution. When providing a voltage corresponding to the voltage of the snubber capacitor Csn, the cell Cuai inserts the voltage of the snubber capacitor Csn in the arm in which it is included. When no voltage or a zero voltage is provided by the cell Cuai, then the snubber capacitor Csn is bypassed. In the example realization of fig. 2, the switches are realized as Metal Oxide Semiconductor Field Effect Transistor

(MOSFET) switches on a suitable substrate such as Si or SiC, where SiC is preferred. However, it should be realized that other types of realizations may be used such as IGBT and anti-parallel diode on suitable substrate such as Si or SiC. These cells are also in the following termed light half bridge cells (LHBCs). As was mentioned above it is also possible to omit the damping resistor Rd and the snubber diode Dsn.

The operation of the converter 10, which is performed under the control of the control unit 12, will now be described with reference also being made to fig 3 and 4, where fig. 3 shows how the cells and switches of the converter in fig. 1 generate different voltage levels and fig. 4 schematically shows the generation of a first and second pulse train using the converter of fig. 1.

The converter generates at least two pulses using at least three voltage levels.

The converter operation is shown in Fig. 3. In the example given in fig. 1 there are four“LHBCs” on both the upper as well as lower arm. The LHBC can be a cell of the type disclosed in fig. 2 and the switching of the cell switches is performed in the manner shown in Fig. 3. For simplicity, it is assumed that only two pulses per half cycle is produced in an output voltage Uva at the AC terminal ACi of the converter. In Fig. 3, the level“o” of a positive pulse indicates that none of the LHBCs in the upper arm ua are inserted, i.e., all the cell capacitors are bypassed. Hence the resulting voltage generated will be Vdc/2 (half of the net DC link voltage). After a sufficient time interval, which will depend on the desired output voltage magnitude, device switching frequency, maximum allowable capacitor size, current flowing through the cells and also on the inherent passive elements, one of the cells in the upper arm ua is inserted (represented in Fig. 3 as number“t”). This will result in the value of Uva to decrease from Vdc/2 to (Vdc/2-Vdc/n), where Vdc/n is the capacitor voltage of the cell. This type of switching of the cells in the upper arm ua will be continued in consecutive manner till a time when all the cells in the upper arm ua are inserted and hence Uva reaches a zero voltage level. At this instant, the switches Si and S2 are turned on and the current commutates from the LHBCs to the switches Si and S2. This will clamp the output voltage to zero and the voltage will remain clamped for a desired period of time.

Similar switching sequence is followed for generating a negative half cycle by using the lower arm LHBCs and the lower capacitor C2 on the DC side. These type of switching transients can be generated for sufficiently large number of times in each half cycle without forcing the LHBC capacitor to carry current for a large duration of time. Hence the capacitance of a cell remains limited to minimum.

The additional switches Si and S2 are thus turned on every time when all the upper arm LHBCs are inserted in the positive half cycle of the fundamental output voltage so that the output voltage is clamped to zero.

Similarly, in the negative half cycle of the output voltage, the Si switches Si and S2 are turned on every time when all the LHBCs of the lower arm la are inserted in the negative half cycle so that the output voltage is clamped to zero again.

The step made by a cell is made with a dwell time of t_D during the transition between the two voltage levels of zero and Vdc/2 or -Vdc/2.

This is done in order to give the pulse edge a slope in order to limit the dv/dt produced by the converter during this transition. Higher values of dv/dt can result in increased electromagnetic interference (EMI) and insulation stress on reactors connected to the converter. The dwell time, which is a time at which a cell“dwells” at a voltage level provided by the snubber capacitors may be in the range of tens to hundreds of nano seconds. The sum of dwell times used in the forming of a slope may then be considered to be a dwell period.

It can thus be seen that the main switches of the cells in an arm are provided for switching between two voltage levels, while the auxiliary switches are configured to connect the snubber capacitors to introduce a slope in the transitions between the two levels.

If the switches used in LHBCs are capable of switching very fast then many narrow pulses can be generated so that there is a first pulse train PTi between the first voltage level Vdc/2 and the third voltage level o and a second pulse train PT2 between the third voltage level o and the second voltage level PT2 and the resulting voltage waveform will be like the sum of the pulse trains PTi and PT2 shown in Fig. 4. It is clear from Figs. 3 & 4 that the converter output phase voltage is of three levels as opposed to the two levels voltage waveform obtained using Q2L converter.

The pulse trains can then be used for forming a sine waveform of an AC system by using necessary filters, where one of the pulse trains is used for a first section of the period of the wave and the other for a second section of the period of the wave, where a section in this case may be a half-period. It can be seen that the dwell time of a pulse in a pulse train is a fraction of such a section. Commonly used frequencies for such waves are 50 or 60 Hz, which means that the period may as an example be io4 - 10⁶ times longer than the dwell time.

Hence a significant reduction in the filter sizes can be expected. Moreover, all the LHBC capacitors remain inserted for very short duration and hence the net DC capacitor size is expected to be similar to the size of DC capacitor required in a Q2L converter. The transition time of Uva to change its value from o to Vdc/2 is very small (assuming that very fast devices, like SiC are used) and hence the LHBC capacitors size will be dictated only by the duration for which all the LHBCs are inserted. An extra voltage level may be introduced at the cost of additional switches though.

The snubber capacitor thus inserts a voltage that is used to adjust the pulse edge. The damping resistor in this case dampens the current through the snubber capacitor. The snubber diode Dsn in turn reduces the losses in the resistor Rd.

A second converter that is able to achieve the same type of pulses is shown in fig. 5.

In this converter three cells Cnai, Cna2 and Cna3 are as an example placed in the neutral arm na and rated for a voltage of Vdc/2, while the upper arm ua comprises n switches Suai, ... , Suan. Thereby the junction j may be connected with and disconnected from the first DC terminal DCi independently of the direction of current through the upper arm ua.

Moreover, each switch may be realized as a combination of a transistor, such as an IGBT with anti-parallel diode or MOSFET, on a substrate such as Si or SiC. In a similar manner the lower arm la comprises n switches Slat , ..., Sian. Thereby the junction j may be connected with and

disconnected from the second DC terminal DC2 independently of the direction of current through the lower arm la. The switches Slat and Sla2 in the lower arm may have the same realization as the switches in the upper armSui, ... ,Sun. The number n is typically selected in order to meet the desired voltage rating of an arm.

The cells Cnai, Cna2 and Cna3 used in the neutral arm na are in this case bipolar cells, i.e. cells having bipolar voltage contribution capability, and have as an example a full-bridge structure and are therefore full-bridge cells or light full-bridge cells (LFBCs). One realization of such a cell is shown in fig. 6. The cell Cnai comprises a first main switch MSWi. A first end of this first main switch MSWi is connected to a first end of a snubber capacitor Csn via a series connection of a first auxiliary switch ASWi and a first optional damping resistor Rdi. There is also a second main switch MSW2 having a first end connected to the same first end of the snubber capacitor Csn via a series connection of a second auxiliary switch ASW2 and an optional second damping resistor Rd2. In this case there is also an optional first snubber diode Dsni connected between a first and a second junction, where the first junction is a junction between the two switches ASW12 and MSWi and the second junction is a junction between the first damping resistor Rdi, the second damping resistor Rd2 and the snubber capacitor Csn. There is also an optional second snubber diode Dsn2 connected between a third and the second junction, where the third junction is a junction between the two switches ASW2 and MSW2. Both diodes Dsni and Dsn2 conduct current towards the snubber capacitor Csn. Finally second ends of the first and second main switches MSWi and MSW2 are also connected to a second end of the snubber capacitor Csn. A first connection terminal of the cell Cnai is provided at the first junction, while a second connection terminal of the cell is provided at the third junction. The cell Cnai may be switched to provide a voltage contribution corresponding to the positive voltage of the snubber capacitor Csn, to the negative voltage of the snubber capacitor Csn or a zero voltage. When providing a voltage corresponding to the voltage of the snubber capacitor

Csn the cell inserts the voltage of the snubber capacitor Csn. When no voltage or a zero voltage is provided by the cell Cnai then the snubber capacitor Csn is bypassed. In the example realization of fig. 6, the switches are realized as MOSFET switches on SiC. However it should be realized that other types of realizations and substrates may be used such as IGBT and anti-parallel diode on Si. It should be realized that it is possible that the neutral arm also comprises unipolar cells, such as half-bridge cells.

The operation of the converter in fig. 5 for forming positive pulses will now be described with reference also being made to fig. 7 and 8, where fig. 7 shows the generation of positive pulses and fig. 8 shows active and inactive parts of the full-bridge cell Cnai.

When the converter is producing positive pulses as shown in Fig. 7, the second main switch, MSW2 is permanently turned ON and the second auxiliary switch ASW2 is permanently turned OFF. Then the cell Cnai can be presented as shown in fig. 8, where the second main switch MSW2 is represented by a short-circuit or a direct connection between the second connection terminal or third junction and the second end of the snubber capacitor Csn, while the second auxiliary switch ASW2, second snubber diode Dsn2 and second damping resistor Rd2 are indicated through dashed symbols. With this configuration the cell is operated as a half bridge cell having a positive voltage contribution. The forming of positive pulses when going from Vdc/2 to zero has three stages. In a first stage, the switches Suai to Suan in the upper arm are On and the first auxiliary switches ASWi are on in the cells Cnia (the first main switches MSWi are off). In this first stage the output voltage is at a maximum, Vdc/2. During the first stage also the snubber capacitors Csn are clamped to Vdc/2. In the second stage, the switches Suai - Suan in the upper arm are turned off while the first auxiliary switches ASWi are still on. Thereby the output voltage is still Vdc/2, but there is no longer any clamping. In going from the second stage to the third stage, the first main switches MSWi in the cells are turned on (and the first auxiliary switches ASWi are simultaneously turned off) gradually one by one. This is the dwelling period. Once all the cells Cna have their first main switch MSWi On then the output voltage reaches zero. The reverse process is followed while going from the third to the first stage. The operation of the converter in fig. 5 for forming negative pulses will now be described with reference also being made to fig. 9 and 10, where fig. 9 shows the generation of negative pulses and fig. 10 shows active and inactive parts of the full-bridge cell.

When the converter is generating negative pulses as shown in fig. 9 then the first main switch MSWi is permanently turned ON and the first auxiliary switch ASWi is permanently turned OFF. Then the cell Cnai is represented as shown in fig. 10, where the first main switch MSWi is represented by a short-circuit or a direct connection between the first connection terminal or the first junction and the second end of the snubber capacitor, while the first auxiliary switch ASWi, first snubber diode Dsni and first damping resistor Rdi are indicated through dashed symbols. With this configuration the cell is operated as a half- bridge cell having a negative voltage contribution.

The forming of negative pulses when going from -Vdc/2 to zero has three stages similar to the positive pulses. In the first stage the switches Slat to Sian in the lower arm are On and the second Auxiliary switches ASW2 are on in the cells Cna (second main switches MSW2 are off). The output voltage is negative maximum, -Vdc/2. During the first stage also the cell capacitors are clamped to Vdc/2. In the second stage, the switches Slat to Sian in the lower arm are turned off while the second auxiliary switches ASW2 are still on. Thereby the output voltage is still -Vdc/2, but there is no longer any clamping. In going from the second stage to the third stage the second main switches MSW2 in the cells are turned on (and second auxiliary switches ASW2 are simultaneously turned off) gradually one by one. This is the dwelling period. Once all the cells have their second main switch MSW2 On then the output voltage reaches zero. The reverse process is followed while going from third to the first stage. This type of converter has the advantage compared with the first converter in that the number of snubber capacitors is reduced. They may be halved.

A third converter to is shown in fig. n. This converter to is in many ways similar to the converter in fig. l having a neutral arm with Si, ... Sn switches of opposite directions. However, in this converter 10 the upper arm ua and lower arm la comprise switches Suai , ..., Suan and Slat, ..., Sian in addition to cells Cuai, Cua2, ..., Cuan and Clai, Cla2, ..., Clan. Thereby the at least one arm comprising cells also comprises switches and these switches are configured to be turned on when the cells of the same arm are being operated for switching between generating third and first or second voltage levels. The number of cells in each branch is here as an example n as are the switches. The cells of an arm here have a rating of Vdc/2 as have the switches of the branch. Thereby the arm has the rating of the full voltage Vdc, which is shared equally by the switches and the cells. This means that the cells are rated for the difference between the third voltage level and one of the first or the second voltage level, while the switches of the same arm are rated for the difference between the third voltage level and the other of the first or the second voltage level. Each cell will therefore have a rating of Vdc/(2n) as will each switch.

The operation of this type of converter will now be described with reference again being made to fig. 7 and 9. When the converter is producing positive pulses as shown in fig. 7, Slat—

Sian are permanently off. Also the main switches of Clai to Clan in the lower arm are normally off and their auxiliary switches can be made ON or OFF. During the dwelling period while going from positive value (Vdc/2) to zero, the main switches in Cua 1 to Cuan in the upper arm gradually one by one will be turned-off and their corresponding auxiliary switches will be turned-on. When the voltage level reaches zero, Si-Sn in the neutral branch nb will be turned-on. This time the cell voltages are clamped to Vdc/2. The reverse process is followed when going from zero to Vdc/2.

Similarly during negative pulse generation as shown in fig. 9, Suai to Suan are permanently off. Also the main switches of Cuai to Cuan in the upper arm are normally off and their auxiliary switches in Cua can be made ON or OFF.

During the dwelling period while going from negative value (-Vdc/2) to zero, the main switches in Clai to Clan gradually one by one will be turned- off and its corresponding auxiliary switches will be turned-on. When the voltage level reaches zero, Si-Sn will be turned-on. This time the lower arm cells are clamped to Vdc/2. The transition from lower arm to upper arm or upper arm to lower arm is done when the converter is at zero voltage output. While selecting the incoming arm, the Sai-San switches in the outgoing arm is turned off and in the incoming arm Sai-san arm is turned on. This type of converter has the advantage of handling the full voltage without the use of excessive cells.

It may here be mentioned that additional switches may also be added to the neutral branch comprising cells depicted in fig. 5.

Another variation of the converter in fig. 1 can be seen in fig. 12. In this converter there is an upper arm with n LHBC cells Cuai, Cua2, Cua3, ..., Cua(n-3), Cua(n-2), Cua(n-i) and Cuan and a lower arm with n LHBC cells Clai, Cla2, Cla3, · · ·, Cla(n-3), Cla(n-2), Cla(n-i) and Clan. There is also a neutral arm na with the first and second switches Si and S2 connecting the junction between the upper and lower arms with a neutral point of a series-connection or string of DC link capacitors C. In this case there are more than three capacitors in the string and the number is denoted n. However, there is here a number of branches brut, bru(n/2-2), bru(n/2-i), brli, brl(n/2-2) and brl(n/2-i) with the same realization as the neutral arm, i.e. with switches interconnecting points of the capacitor string with the upper and lower arms, which switches may have opposite orientations in relation to each other. It can more particularly be seen that there are n/2-1 such branches interconnecting the upper half of the capacitor string with the upper arm and n/2 -1 branches interconnecting the lower half of thee capacitor string with the lower arm. A capacitor in the string is thereby connected in parallel with a number of cells in an arm via one or two such branches with switches, where the number of cells in the given example is two.

It can be seen that each branch between the first DC terminal and the neutral point is connected between two capacitors and a corresponding point in the upper arm and that each branch between the second DC terminal and the neutral point is connected between two capacitors and a corresponding point in the lower arm, where the associated point in question is a point or junction between two identical strings with components, where the strings in these case are strings with cells, as an example a string with two cells. It can also be seen that two identical strings in the upper arm are connected in series with each other between the first DC terminal DCi and the junction j, while two identical strings in the lower arm are connected in series with each other between the second DC terminal DC2 and the junction j . A branch more particularly interconnects such a point in an arm with a junction between two capacitors in the capacitor string.

Thereby it is possible to introduce even further number of levels in the converter compared with the converter of fig. 1. In this case, a number of

DC-link capacitors would be required and a number of switches will be required as well. Nonetheless, the multilevel waveshape can be produced without enhancing the capacitance of cells. The number of branches discussed above was only an example. It should be realized that the number being introduced depends on the number of levels that is desired.

The above-mentioned principle can also be applied on the topologies of fig. 5 and n, which is shown in fig. 13 and 14, respectively.

It can be seen in fig. 13 that branches with cells are connected between two capacitors C located between the first DC terminal DCi and the neutral point, and a corresponding point in the upper arm as well as between two capacitors C located between the second DC terminal DC2 and the neutral point and a corresponding point in the lower arm, where the

corresponding points in the upper and lower arms are points between identical strings with switches SSu(n/2-i) and SSu(n/2), SSl(n/2-i) and SSl(n/2).

It can be seen in fig. 14 that branches with switches are connected between two capacitors C located between the first DC terminal DCi and the neutral point, and a corresponding point in the upper arm as well as between two capacitors located between the second DC terminal Dc2 and the neutral point and a corresponding point in the lower arm, where the

corresponding points in the upper and lower arms are points between identical strings with both cells and switches Su(n/2-i) and Su(n/2), Sl(n/2-i) and Sl(n/2). Fig. 15 shows another variation of a converter for handling a phase. There is here an arm with cells HC connected to an H bridge switching

arrangement via an inductor, where the cells may be LHBCs comprising SiC switches. The arm with cells HC may be seen as being a waveshaper circuit. The H bridge comprises a first and third switch Si and S3 connected in parallel with the inductor and string of cells and a second and fourth switch S2 and S4 also connected in parallel with the inductor and string of cells. The switches in the H bridge may be Si switches formed as IGBTs with anti-parallel diodes. An output voltage Ua of the phase is obtained from a first terminal at the junction between the first and third switches Si and S3 and from a second terminal at the junction between the second and fourth terminal S2 and S4. This converter reduces the DC side capacitor (capacitor Cl and C2 in Fig.

1) and also improves the converter output voltage profile.

A corresponding three-phase structure is shown in Fig. 16. On the AC side, the AC terminals of three phases connect with AC system separately through three single-phase transformers. The secondary electrical circuits of the transformers are isolated with each other. On the DC side, the total DC voltage is superimposed by the three-phase HC stacks.

A major advantage of this circuit is that only three chain-links of cells are required and these are outside the main current path. Therefore the number of half-bridge cells required for this converter is only a fraction (-25%) of those needed for three parallel branches of cells and the value of the capacitance used in each cell may be substantially reduced. A further benefit of this arrangement is the voltage imposed on the series

IGBTs forming the H-bridge is directly controlled by the attached wave shaping circuit. In steady state operation, the series IGBTs are switched at zero voltage giving zero switching losses and simple dynamic voltage sharing.

The converter of fig. 15 uses the cells of fig. 2 and the arm with cells generates pulses in the way of the cells in the upper arm of fig. 1. However, the forming of two different pulses is done in a different way. It is assumed that, as an example, there are four“light” half bridge cells (LHBC) on the DC side of each full bridge. The switches used in the full bridge circuit (Si-

S4) may be a Si-switch as they are required to be switched at the fundamental frequency, in the similar way as explained above with reference to Fig. 15. However, these switches (S1-S4) may also be realized by using series connection of SiC devices. In that case the high voltage blocking capability and low conduction loss features of these devices can be exploited. Moreover, it is also not a definite requirement to switch S1-S4 at the fundamental frequency. They may be controlled in a way, even with non- fundamental switching, to result in a better harmonic performance or to serve other important requirements. The switchings of LHBCs are done in the manner as shown in Fig. 17. For simplicity, it is assumed that only two pulses per half cycle is produced as an output voltage Ua at the AC output terminal of the converter. The voltage generated on the DC side of the single-phase converter is illustrated as the waveform of Udca in Fig. 17. The number“o”indicates that none of the LHBCs are inserted, i.e., all the cells capacitors are bypassed. Hence the resulting voltage generated will be o. After a sufficient time interval, which will depend on the device switching frequency, maximum allowable capacitor size, current flowing through the cells and also on the inherent passive elements, one of the cells is inserted

(represented in Fig. 17 as number“1”). This will result in the value of Udca to jump from o to Vdc. This type of switching will be continued in consecutive manner till the time when all the cells are inserted and hence Udca reaches 4Vdc (represented in Fig. 17 as number“4”). The downward movement profile of Udca is generated in the similar manner. Then the full-bridge switches (S1-S4) are used to generate the AC voltage (Ua) in the manner shown in Fig. 17.

If the switches used in the LHBCs are capable of switching very fast then many narrow pulses can be generated and the resulting voltage waveforms will be like the ones shown in Fig. 18. It is clear from Fig. 18 that the converter output phase voltage is of three levels as opposed to the two levels voltage waveform obtained using Q2L converter. Hence a significant reduction in the filter sizes can be expected. Moreover, all the LHBC capacitors remain inserted for very short duration (equivalent to t4, as shown in Fig. 17) and hence the net DC capacitor size is expected to be smaller than the size of DC capacitor required in a Q2L converter. It is to be noted that LHBCs are used to create the slopy voltage transition, with lower dv/dt, from one to another extreme voltage values (o to nVdc in Fig. 18). Then, once the transition is over, if the DC voltage stays at nVdc for t4 (Fig. 17) then the nVdc voltage is supported by the combined capacitance of all the LHBCs as all of them remain inserted for t4 time. On the other hand, if the DC voltage stays at o level following a complete voltage transition, for the duration of to as shown on Fig. 17, then all the LHBCs are bypassed for this duration. Hence, all the LHBCs are supposed to support the nVdc voltage for a maximum duration of t4, which will be having a maximum value depending on the converter output voltage magnitude and harmonic performance requirements. On the other hand, in Q2L, the DC side capacitor C is supposed to support both the extreme voltage levels (+Vdc/2 and - Vdc/2). Therefore, for the same current handling requirements, the combined capacitance of LHBCs in the proposed circuit of Fig. 15 will be much smaller than the DC side capacitor C of the Q2L converter.

The capacitance of LHBC capacitors will be decided by the maximum allowable value of t4 and the current flowing through the capacitors The transition time of Udca to change its value from o to nVdc is very small (assuming that very fast devices, like SiC are used) and hence the LHBC capacitors size will be dictated only by the duration for which all the

LHBCs are inserted (t4 in Fig. 17). Therefore, the net overall capacitor requirement in converter will be much lower than that required in the Q2L circuit and also in a sine waveshaping converter having the same structure as the structure in Fig. 15.

It is also to be noted that in such a chain-link circuit, a large DC side inductor is required to filter out the 6th order harmonic. However, in the proposed converter of Fig. 15, the DC side inductor can be significantly reduced/ eliminated because very high frequency pulse width modulated voltage waveform is generated on the DC side of each full bridge (Fig. 18).

It is further to be noted that the converter of Fig. 15 can be used not only in the stacked series form for three-phase configuration (as shown in Fig. 16), but it can also be used in the parallel configuration. A possible

arrangement for the parallel circuit is shown in Fig. 19. An advantage of this converter when compared with the series circuit of Fig. 16 is that a single chain link of LHBCs would be required. Then the three phase outputs can be obtained by three separate full bridge circuits (shown in Fig. 19 as FB-a, FB-b and FB-c), which are switched in a manner that three-phase output voltages are obtained with a phase displacement of 120⁰ among themselves. This circuit can be operated in different ways so that the desired three phase outputs can be obtained. One of the ways is to generate a DC voltage (Udc) with a train of pulses of constant width. By doing this, the rms value of the fundamental component of the three phase voltages generated will be equal using the circuit shown in Fig. 19. If the voltage rms value is required to be changed, then the widths of all the pulses can be varied. The harmonic performance with this type of modulation will not be as good as the case when the pulse widths are not kept constant and varied in accordance with the desired voltage magnitude and harmonic performance. However, with very high switching operation, the harmonic performance using the scheme with constant pulse widths will not be bad either. Moreover, the number of LHBCs required is reduced to one third. However, the DC side filtering requirement will be increased with the converter shown in Fig. 19 as the DC link voltage is of high frequency pulse pattern. However, it is to be however noted that the zero voltage switching of the director switches (S1-S4) may not be guaranteed in this converter configuration with parallel H-bridge circuits.

The structure and switching scheme of the previously described converters have the following benefits: Significant reduction in the stored capacitor energy as compared to the Q2L converter.

Improved voltage profile compared to the Q2L converter.

Light half bridge cells with very small capacitors and utilizing SiC devices can be used. Hence a compact converter structure and reduction in losses are expected.

There is no advance requirements on the gate units for

LHBCs.

The structure and switching scheme of the parallel hybrid converters shown in fig. 15 - 19 have the following further benefits:

The director switches are switched at the fundamental frequency and the zero voltage switching can also be achieved. Hence the switching losses are expected to be minimal. Si IGBT can be used as the director switches.

The SCFM requirements for the LHBCs are

relaxed/eliminated. However, the director switches (S1-S4) will be requiring Short-Circuit Failure mode (SCFM) capability at the position level.

The number of LHBCs and hence the semiconductors and capacitors, can be reduced to one third by using the series circuit configuration of Fig. 19.

It should be realized that it is possible to perform further variations in addition to those already described. The switches are not limited to employing IGBTs and MOSFETs. A switch may for instance be based on a Junction Field Effect Transistor (JFET) instead. Also Integrated Gate- Commutated Thyristors (IGCTs) may be used. From the foregoing discussion it is evident that the present invention can be varied in a multitude of ways. It shall consequently be realized that the present invention is only to be limited by the following claims.

Claims

1. A voltage source converter (to) configured to generate at least two pulse trains (PTi, PT2) using at least three voltage levels (+Vdc/2, o, -Vdc/2), said converter comprising a first converter arm (ua) connected between a junction (j) and a first DC terminal (DCi) having a first voltage level (Vdc/2), a second converter arm (la) connected between the first junction and a second DC terminal (DC2) having a second voltage level (-Vdc/2) and a third converter arm (na) connected between the junction (j) and a neutral point (np) having a third voltage level (o) between the first and second voltage levels, wherein at least one of the arms (ua, la; na) comprises cells (Cuai, Cua2, Cua3, Cua4, Clai, Cla2, Cla3, Cla4; Cnai, Cna2, Cna3), each cell comprising a first main switch (MSW; MSWi), a first auxiliary switch (ASW; ASWi) and a snubber capacitor (Csn), wherein the first main switches (MSW; MSWi) of the cells are configured to switch between two of the voltage levels and the first auxiliary switches (ASW; ASWi) of the cells are configured to connect snubber capacitors (Csn) to introduce a slope in the transition between the two levels; and

the other arms only comprise switches (Si, S2; Suai, Suan, Slat, Sian) for connecting the junction (j) to a corresponding voltage level.

2. The voltage source converter (10) according to claim 1, wherein said at least one arm comprising cells also comprise switches (Suai, Suan, Slat, Sian) configured to be turned on when the cells of the arm are being operated for switching between two of the voltage levels.

3. The voltage source converter (10) according to claim 2, wherein the cells are rated for the difference between the third voltage level and one of the first or the second voltage levels and the switches are rated for the voltage difference between the third voltage level and the other of the first or second voltage levels.

4. The voltage source converter (10) according to any previous claim, wherein the first and second arms comprise cells, while the third arm only comprises switches.

5. The voltage source converter (10) according to claim 4, wherein the cells have a unipolar voltage contribution capabilitiy.

6. The voltage source converter (10) according to any of claims 1 - 3, wherein the first and second arms only comprise switches and the third arm comprises cells having a bipolar voltage contribution capability with a second main switch (MSW2) and a second auxiliary switch (ASW2), wherein said cells with bipolar voltage contribution capability are configured to switch between two voltage levels, one of which is another than those of the first main switch, and the second auxiliary switches (ASW2) of these cells are configured to connect snubber capacitors (Csn) to introduce a slope in the transition between the two levels operated by the second auxiliary switches.

7. The voltage source converter (10) according to any previous claim, wherein the neutral point is a midpoint of a capacitor string connected between the first and second DC terminals.

8. The voltage source converter (10) according to claim 7, wherein the capacitor string comprises two or more capacitors (C) between the midpoint and a corresponding DC terminal and a number of branches (brut, bru(n/2-2), bru(n/2-i), brl, brl(n/2-2), brl(n/2-i)) with the same realization as the third arm, where each such branch between the first DC terminal (DCi) and the neutral point is at one end connected between two capacitors (C) and at the other end connected to a corresponding point in the first arm and each such branch between the second DC terminal (DC2) and the neutral point is at one end connected between two capacitors (C) and at the other end connected to a corresponding point in the second arm between two identical strings with components (Cua(n-3), Cua(n-2), Cua(n-i), Cuan; SSu(n/2-i), SSu(n/2); Su(n/2-i), Su(n/2)).

9. The voltage source converter (10) according to any previous claim, wherein the cells comprise a first damping resistor (Rd; Rdi) between the first auxiliary switch (ASW; ASWi,) and the snubber capacitor (Csn) and a first diode (Dsn; Dsni ) between a first and a second junction, where the first junction is a junction between the first main switch (MSW; MSWi) and the first auxiliary switch (MSW, ASW; MSWi, ASWi) and the second junction is a junction between the first damping resistor (Rd; Rdi) and the snubber capacitor (Csn).

10. The voltage source converter (10) according to claim 9 when depending on claim 6, wherein the cells comprise a second damping resistor (Rd2) between the second auxiliary switch (ASW2) and the snubber capacitor

(Csn) and a second diode (Dsn2) between a third and the second junction, where the third junction is a junction between the second main switch and the second auxiliary switch (MSW2, ASW2).

11. The voltage source converter (10) according to any previous claim, wherein the switches of at least some cells are Metal Oxide

Semiconductor Field Effect Transistor switches.

12. The voltage source converter (10) according to any previous claim, wherein the switches of at least some cells are Silicon Carbide switches or a combination of Silicon and Silicon Carbide switches.

13. The voltage source converter according to any previous claim, wherein the switches of arms only comprising switches comprise Insulated Gate Bipolar Transistors or any similar semiconductor switch.

14. The voltage source converter according to any previous claim, wherein the switches of arms only comprising switches comprise Silicon switches and/or Silicon Carbide switches.

15. The voltage source converter according to any previous claim, wherein the pulse trains have a periodicity by which they occur used for forming a sine wave and the slope of a pulse in a pulse train is a fraction of the periodicity.