WO2019193834A1 - Semiconductor driving device and power conversion device - Google Patents

Abstract

According to the present invention, on/off determination units 23H, 23L output on/off determination signals SonH, SonL which indicate on/off states of switching elements M1, M2. Abnormality detection units 24H, 24L output abnormality detection signals SfaH, SfaL which indicate the presence or absence of abnormality of the switching elements M1, M2. State signal generation units 21H, 21L output state signals SstH, SstL on the basis of the on/off determination signals SonH, SonL and the abnormality detection signals SfaH, SfaL. Insulating communication units 20H, 20L transmit state signals output from the state signal generation units 21H, 21L while securing insulation between the state signal generation units 21H, 21L and a control unit 10. The control unit 10 generates on/off command signals SctlH, SctlL for driving the switching elements M1, M2, respectively.

Description

Semiconductor drive device and power conversion device

The present invention relates to a semiconductor drive device that drives a plurality of semiconductor switching elements connected in series, and a power conversion device using the same.

The power conversion device including the inverter device realizes the power conversion by the on / off operation of the semiconductor switching element. As semiconductor switching elements, there are voltage-driven switching elements represented by MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor). Hereinafter, the semiconductor switching element is simply referred to as a switching element.

Recently, for the purpose of increasing the power density of power converters, capacitors and inductors and the like tend to be miniaturized and on / off switching of switching elements tends to be performed at higher frequencies. In a power converter, an arm short circuit occurs when a plurality of switching elements connected in series are simultaneously turned on. In order to prevent the occurrence of such an arm short circuit, a period (dead time) in which a plurality of switching elements are simultaneously turned off is provided. Usually, the dead time is set to a fixed time. For this reason, as the on / off switching frequency increases, the time ratio of the dead time in the carrier cycle becomes relatively large. When a MOSFET is used as the switching element, a conduction loss of the built-in diode occurs during the dead time. When the time ratio of dead time increases, such conduction loss is likely to occur. As a result, power conversion efficiency is reduced. Further, when the power conversion device is, for example, a boost converter, the effective on-duty is reduced by increasing the time ratio of dead time. As a result, the boostable range is reduced. Furthermore, when a SiC (Silicon Carbide) -MOSFET including a wide band gap semiconductor is used as a switching element and a built-in diode of the MOSFET is used, current deterioration due to SiC crystal defects occurs.

JP2015-154524A JP 2007-185024 A

In response to the above problem, for example, Patent Document 1 discloses a method for reducing dead time by utilizing a sense transistor. Specifically, when the synchronous rectification is started, the detection diode becomes lower than the reference voltage by energizing the parasitic diode of the sense transistor. In response to this, the main transistor is turned on. In this case, even if the command signal to the main transistor is at a low level, the main transistor is turned on, so that the dead time at the start of synchronous rectification is shortened. However, with this method, even if the dead time at the start of synchronous rectification can be shortened, the dead time at the end of synchronous rectification cannot be shortened. Therefore, even if the dead time at the start of synchronous rectification is reduced by 90%, the overall reduction rate is 50% × 90% = 45%, and a sufficient reduction effect cannot be obtained.

In order to shorten the dead time at the end of synchronous rectification, it is necessary to turn on the other switching element in accordance with the timing when one of the pair of switching elements is turned off. For example, in Patent Document 2, on / off information is transmitted between a pair of drive devices that respectively drive a pair of switching elements, and the pair of switching elements are prevented from being simultaneously turned on based on the on / off signal. However, this system requires a new insulating circuit for transmitting on / off information. This increases the size of the drive device and increases the cost.

The present invention has been made to solve the above-described problems, and an object thereof is to provide a semiconductor drive device and a power conversion device capable of reducing dead time while suppressing increase in size and cost. And

A semiconductor drive device according to the present invention includes a control unit that generates a plurality of on / off command signals for driving a plurality of semiconductor switching elements connected in series, and one semiconductor switching element among the plurality of semiconductor switching elements. An on / off determination unit that detects an on / off state and outputs an on / off determination signal that indicates the detected on / off state, and detects whether there is an abnormality in one semiconductor switching element and outputs an abnormality detection signal that indicates the presence / absence of the detected abnormality An abnormality detection unit that outputs a state signal based on the on / off determination signal output from the on / off determination unit and the abnormality detection signal output from the abnormality detection unit, and the control unit and the one switching element. Drive one semiconductor switching element generated by the controller while ensuring insulation between the two An insulation communication unit that transmits a first on / off command signal and transmits a state signal output from the state signal generation unit while ensuring insulation between the state signal generation unit and the control unit, and a control unit Generates another on / off command signal for driving another semiconductor switching element among the plurality of semiconductor switching elements based on the state signal transmitted by the insulating communication unit.

According to the present invention, it is possible to reduce dead time while suppressing increase in size and cost.

It is a block diagram which shows the basic composition of the semiconductor drive device which concerns on Embodiment 1 and Embodiment 2 of this invention. It is a circuit diagram which shows the specific structural example of the state signal generation part of the semiconductor drive device concerning Embodiment 1 of this invention, a gate drive part, an on-off determination part, and an abnormality detection part. It is a circuit diagram which shows the specific structural example of the control part of the semiconductor drive device which concerns on Embodiment 1 of this invention. It is a timing chart which shows an example of the change of the various signals in Embodiment 1 of this invention, and the change of the gate-source voltage of a switching element. It is a timing chart which shows an example of a change of a status signal, a clear signal, an abnormal signal, and an abnormal hold signal in Embodiment 1 of the present invention. It is a timing chart for demonstrating the change of the various signals when a switching element is hard-cut in Embodiment 1 of this invention. 5 is a timing chart for explaining changes in various signals when the ON determination time is set to be relatively long in Embodiment 1 of the present invention. It is a circuit diagram which shows the specific structural example of the state signal generation part of the semiconductor drive device concerning Embodiment 2 of this invention, a gate drive part, an on-off determination part, and an abnormality detection part. It is a circuit diagram which shows the specific structural example of the control part of the semiconductor drive device in Embodiment 2 of this invention. It is a time chart which shows an example of the change of the various signals in Embodiment 2 of this invention, and the change of the gate-source voltage of a switching element. It is a timing chart which shows an example of the change of the command signal in Embodiment 2 of this invention, an on-off command signal, a status signal, a difference determination signal, and an abnormal signal. It is a block diagram which shows the basic composition of the semiconductor drive device which concerns on Embodiment 3 of this invention. It is a circuit diagram which shows the specific structural example of the state signal generation part of the semiconductor drive device concerning Embodiment 3 of this invention, a gate drive part, an on-off determination part, and an abnormality detection part. It is a block diagram which shows the basic composition of the semiconductor drive device which concerns on Embodiment 4 of this invention. It is a circuit diagram which shows the specific structural example of the state signal generation part of the semiconductor drive device concerning Embodiment 4 of this invention, a gate drive part, an on-off determination part, and an abnormality detection part. It is a circuit diagram which shows the basic composition of the power converter device which concerns on Embodiment 5 of this invention. It is a circuit diagram which shows the basic composition of the power converter device which concerns on Embodiment 6 of this invention. It is a circuit diagram which shows the specific structural example of the control part of the semiconductor drive device used for the power converter device which concerns on Embodiment 6 of this invention. It is a time chart for demonstrating the relationship between the abnormal signal and other various signals in Embodiment 6 of this invention. It is a circuit diagram which shows the basic composition of the power converter device which concerns on Embodiment 7 of this invention. It is a figure which shows the example by which each function of a control part is implement | achieved by software.

[Embodiment 1]
FIG. 1 is a block diagram showing a basic configuration of a semiconductor drive device according to Embodiment 1 of the present invention. The semiconductor drive device 1 according to the first embodiment includes a pair of semiconductor switching elements (hereinafter abbreviated as switching elements) M1 and M2 connected in series between a positive terminal TP and a negative terminal TN of a DC power supply. Each is driven by pulse width modulation. In this example, the switching elements M1 and M2 are power MOSFETs. A parasitic diode is provided in each of the switching elements M1 and M2. The semiconductor drive device 1 has a function of detecting an arm short circuit based on a voltage between the drain terminal DrainH and the source terminal SourceH of the switching element M1 and a voltage between the drain terminal DrainL and the source terminal SourceL of the switching element M2. Prepare. The arm short circuit is a short circuit that occurs between the positive terminal TP and the negative terminal TN when the switching elements M1 and M2 are simultaneously turned on.

The semiconductor drive device 1 includes a control unit 10, gate drive units 22H and 22L, on / off determination units 23H and 23L, and abnormality detection units 24H and 24L. The control unit 10 generates an on / off command signal SctlH for driving the switching element M1 and an on / off command signal SctlL for driving the switching element M2. The on / off command signals SctlH and SctlL are at a high level when the switching elements M1 and M2 are to be turned on, and are at a low level when the switching elements M1 and M2 are to be turned off. The on / off command signal SctlH is given to the gate drive unit 22H and the on / off determination unit 23H as an on / off command signal SgdH through an insulating communication unit 20H described later. The on / off command signal SctlL is given to the gate drive unit 22L and the on / off determination unit 23L as the on / off command signal SgdL via the insulation communication unit 20L described later.

The on / off command signal SgdH transmitted by the insulated communication unit 20H is input to the gate drive unit 22H. The gate drive unit 22H drives the switching element M1 based on the input on / off command signal SgdH. An ON / OFF command signal SgdL transmitted by the insulated communication unit 20L is input to the gate drive unit 22L. The gate drive unit 22L drives the switching element M2 based on the input on / off command signal SgdL. In this example, the gate drive units 22H and 22L drive the switching elements M1 and M2 by applying a voltage to the gate terminals GateH and GateL of the switching elements M1 and M2. The gate drive units 22H and 22L may drive the switching elements M1 and M2 by applying a current to the gate terminals GateH and GateL of the switching elements M1 and M2. For example, when a current drive type semiconductor such as a bipolar transistor is used as the switching elements M1 and M2, the switching elements M1 and M2 are driven by the current.

The on / off determination unit 23H is supplied with the on / off command signal SgdH transmitted by the insulated communication unit 20H and the voltage of the gate terminal GateH of the switching element M1. The on / off determination unit 23H determines the on / off state of the switching element M1 based on the voltage of the gate terminal GateH of the switching element M1, and outputs an on / off determination signal SonH indicating the determined on / off state. The on / off determination unit 23L receives the on / off command signal SgdL transmitted by the insulating communication unit 20L and is given the voltage of the gate terminal GateL of the switching element M2. The on / off determination unit 23L determines the on / off state of the switching element M2 based on the voltage of the gate terminal GateL of the switching element M2, and outputs an on / off determination signal SonL indicating the determined on / off state. When the switching elements M1 and M2 are on, the on / off determination units 23H and 23L output high-level on / off determination signals SonH and SonL, and when the switching elements M1 and M2 are off, the on / off determination units 23H and 23L. Outputs low-level on / off determination signals SonH and SonL. Note that the on / off determination units 23H and 23L may determine the on / off states of the switching elements M1 and M2 based on the current applied to the gate terminals GateH and GateL of the switching elements M1 and M2.

The abnormality detection unit 24H receives the on / off determination signal SonH output from the on / off determination unit 23H and the voltage of the drain terminal DrainH of the switching element M1. The abnormality detection unit 24H detects whether or not the switching element M1 is abnormal, and outputs an abnormality detection signal SfaH that indicates the presence or absence of the detected abnormality. The abnormality detection unit 24L receives the on / off determination signal SonL output from the on / off determination unit 23L and is given the voltage of the drain terminal DrainL of the switching element M2. The abnormality detection unit 24L detects whether or not the switching element M2 is abnormal and outputs an abnormality detection signal SfaL that indicates the presence or absence of the detected abnormality. The high level abnormality detection signals SfaH and SfaL indicate that the switching elements M1 and M2 are abnormal, and the low level abnormality detection signals SfaH and SfaL indicate that the switching elements M1 and M2 are not abnormal. In this example, the abnormality detection units 24H and 24L detect an arm short circuit as an abnormality of the switching elements M1 and M2, respectively.

The semiconductor drive device 1 further includes state signal generation units 21H and 21L and insulating communication units 20H and 20L. The state signal generation unit 21H receives the on / off determination signal SonH output from the on / off determination unit 23H and the abnormality detection signal SfaH output from the abnormality detection unit 24H. The state signal generation unit 21H generates a state signal SstH based on the on / off determination signal SonH and the abnormality detection signal SfaH, and outputs the generated state signal SstH. The state signal generation unit 21H receives the on / off determination signal SonL output from the on / off determination unit 23L and the abnormality detection signal SfaL output from the abnormality detection unit 24L. The state signal generation unit 21L generates a state signal SstL based on the on / off determination signal SonL and the abnormality detection signal SfaL, and outputs the generated state signal SstL.

The insulated communication unit 20H includes channels Ch1 and Ch2, and the insulated communication unit 20L includes channels Ch3 and Ch4. For the channels Ch1 to Ch4, for example, an insulating element such as a photocoupler or a pulse transformer is used. An optical fiber formed of an insulating material (for example, resin) may be used for the channels Ch1 to Ch4. Further, the channels Ch1 to Ch4 may be insulated such as a pulse transformer formed in an integrated circuit (IC).

The insulation communication unit 20H transmits an on / off command signal from the control unit 10 to the gate drive unit 22H while ensuring insulation between the control unit 10 and the gate drive unit 22H, and the state signal generation unit 21H and the control unit 10 The state signal is transmitted from the state signal generation unit 21H to the control unit 10 while ensuring the insulation between them. Specifically, the on / off command signal SctlH output from the control unit 10 is input to the channel Ch1, and the on / off command signal SgdH output from the channel Ch1 is supplied to the gate drive unit 22H. The state signal SstH output from the state signal generation unit 21H is input to the channel Ch2, and the state signal SfbH output from the channel Ch2 is provided to the control unit 10.

The insulation communication unit 20L transmits an on / off command signal from the control unit 10 to the gate drive unit 22L while ensuring insulation between the control unit 10 and the gate drive unit 22L, and the state signal generation unit 21L and the control unit 10 A state signal is transmitted from the state signal generation unit 21L to the control unit 10 while ensuring insulation between the two. Specifically, the on / off command signal SctlL output from the control unit 10 is input to the channel Ch3, and the on / off command signal SgdL output from the channel Ch3 is supplied to the gate drive unit 22L. The state signal SstL output from the state signal generation unit 21L is input to the channel Ch4, and the state signal SfbL output from the channel Ch4 is provided to the control unit 10.

There is a slight delay between the time when signals are input to the insulated communication units 20H and 20L and the time when signals are output from the insulated communication units 20H and 20L. Therefore, the on / off command signal SgdH changes with a slight delay from the on / off command signal SctlH, and the state signal SfbH changes with a slight delay from the state signal SstH. Similarly, the on / off command signal SgdL changes with a slight delay from the on / off command signal SctlL, and the state signal SfbL changes with a slight delay from the state signal SstL.

Signals input / output to / from each of the gate drive unit 22H, the on / off determination unit 23H, the abnormality detection unit 24H and the state signal generation unit 21H are based on the potential of the source terminal SourceH of the switching element M1. In addition, signals input / output to / from each of the gate drive unit 22L, the on / off determination unit 23L, the abnormality detection unit 24L, and the state signal generation unit 21L are based on the potential of the source terminal SourceH of the switching element M2. The potentials of the source terminals SourceH and SourceL vary depending on the switching operation of the switching elements M1 and M2. On the other hand, signals input to and output from the control unit 10 are preferably based on a certain potential. Therefore, it is necessary to transmit a signal via insulation between the control unit 10 and the gate driving units 22H and 22H and between the control unit 10 and the state signal generation units 21H and 21L. In the present embodiment, by providing insulation communication units 20H and 20L, insulation is provided between control unit 10 and gate drive units 22H and 22H and between control unit 10 and state signal generation units 21H and 21L. The transmitted signal can be transmitted.

The control unit 10 includes an on command generation unit 11 and dead time generation units 12H and 12L. The on-command generating unit 11 receives the status signal SfbH transmitted by the insulated communication unit 20H and the status signal SfbL transmitted by the insulated communication unit 20L. The on command generation unit 11 generates on signals SinH and SinL based on the state signals SfbH and SfbL. The dead time generating unit 12H receives the state signal SfbL transmitted from the insulating communication unit 20L and the on signal SinH output from the on command generating unit 11. The dead time generation unit 12H generates the on / off command signal SctlH based on the state signal SfbL and the on signal SinH so that the dead time is suitably secured. The dead time generating unit 12L receives the state signal SfbH transmitted from the insulated communication unit 20H and the on signal SinL output from the on command generating unit 11. The dead time generation unit 12L generates an on / off command signal SctlL based on the state signal SfbL and the on signal SinL so that the dead time is suitably secured.

In the present embodiment, the on / off determination signal SonH is not transmitted via the dedicated channel of the isolated communication unit 20H, but the state signal SstH is generated from the on / off determination signal SonH and the abnormality detection signal SfaH, and the state signal SstH Is transmitted through one channel Ch2 of the insulated communication unit 20H. In addition, the on / off determination signal SonL is not transmitted via the dedicated channel of the isolated communication unit 20L, but the state signal SstL is generated from the on / off determination signal SonL and the abnormality detection signal SfaL, and the state signal SstL is generated by the isolated communication unit. It is transmitted through one channel Ch4 of 20H. Thus, the on / off states of the switching elements M1, M2 can be transmitted to the control unit 10 without providing a new channel in the insulated communication units 20H, 20L in order to transmit the on / off determination signals SonH, SonL.

FIG. 2 is a schematic circuit diagram showing a specific configuration example of the state signal generation unit 21H, the gate drive unit 22H, the on / off determination unit 23H, and the abnormality detection unit 24H of FIG. The state signal generation unit 21L, the gate drive unit 22L, the on / off determination unit 23L, and the abnormality detection unit 24L in FIG. 1 are the same as the state signal generation unit 21H, the gate drive unit 22H, the on / off determination unit 23H, and the abnormality detection unit 24H. Has configuration and function.

The gate driver 22H includes a buffer circuit BF1, resistors R1 to R10, speed-up capacitors C1 and C2, and transistors Tr1 to Tr3. The on / off command signal SgdH output from the insulated communication unit 20H is amplified by the buffer circuit BF1, and is turned on by the gate resistors R6 and R8 and the speed-up capacitor C2, or is turned off by the gate resistors R7 and R8 and the speed-up capacitor C1. To the gate terminal GateH of the switching element M1. The voltage VccH is applied to the positive terminal of the buffer circuit BF1, and the voltage VeeH is applied to the negative terminal. The voltages VccH and VeeH are set with reference to the potential FgH of the source terminal SourceH. The voltage VeeH may be set to 0 so that the potential of the negative terminal of the buffer circuit BF1 becomes FgH. In order to prevent false firing, the voltage VeeH may be set to a negative voltage so that the potential of the negative terminal of the buffer circuit BF1 is lower than FgH. In the example of FIG. 2, the speed-up capacitors C1 and C2 are provided in order to shorten the dead time, but a configuration other than the speed-up capacitors C1 and C2 may be used. Furthermore, in the example of FIG. 2, the gate driving method is constant voltage driving, but the gate driving method may be constant current driving or active gate driving. Active gate driving is a driving method that dynamically changes the impedance of a gate driving circuit.

When an arm short-circuit occurs, if the switching element M1 is cut off (so-called hard cut-off), an excessive surge voltage may be generated due to a large current cut-off. In this example, such an excessive surge voltage is prevented by the buffer circuit BF1 and the transistor Tr3. Specifically, when the abnormality detection signal SfaH output from the abnormality detection unit 24H by detecting an arm short circuit becomes a high level, the buffer circuit BF1 is held in a high impedance state, whereby the output of the buffer circuit BF1 is Stopped. When the transistor Tr3 is turned on in this state, the switching element M1 is cut off at low speed by the gate resistor R10 (so-called soft cutoff). The value of the gate resistor R10 is larger than the sum of the value of the gate resistor R7 and the value of the gate resistor R8, for example, about 10 times the sum of the value of the gate resistor R7 and the value of the gate resistor R8.

The on / off determination unit 23H includes a comparator CP1, resistors R11 to R15, a diode D1, and a capacitor C3. The gate-source voltage of the switching element M1 (the voltage between the gate terminal GateH and the source terminal SourceH) is applied to the positive side input terminal of the comparator CP1 via the resistor R11. The comparator CP1 compares the gate-source voltage of the switching element M1 with the comparison reference voltage. The comparison reference voltage depends on the values of the resistors R13 to R15. In this example, the on / off command signal SgdH is given to the negative input terminal of the comparator CP1 via the resistor R15. Therefore, the comparison reference voltage is changed between when the on / off command signal SgdH is at a high level and when the on / off command signal SgdH is at a low level. Further, the resistors R11 and R12 and the capacitor C3 constitute a low-pass filter. As will be described later, the time from when the switching element M1 is turned on until the on / off determination signal SonH becomes high level (hereinafter referred to as the on determination time) is equal to the on / off determination signal SonH after the switching element M1 is turned off. The low pass filter may be set so as to be longer than the time until the low level (hereinafter referred to as the off determination time). The on determination time is an example of the second time, and the off determination time is an example of the first time. Note that when there is no need to provide a difference between the on determination time and the off determination time, the resistor R12 and the diode D1 may not be provided.

The abnormality detection unit 24H includes a comparator CP2, resistors R16 to R20, diodes D2 and D3, a capacitor C4, a transistor Tr5, a constant current source Idc1, and a signal width expansion circuit MM1. When the voltage of the drain terminal DrainH rises due to the arm short circuit, the current from the constant current source Idc1 does not flow to the drain terminal DrainH. As a result, the voltage at the positive input terminal of the comparator CP2 rises, and the output signal of the comparator CP2 becomes high level. Thereby, the occurrence of an arm short circuit is detected. The on / off determination signal SonH output from the on / off determination unit 23H is applied to the base of the transistor Tr5. The transistor Tr5 is a pnp type. When the on / off determination signal SonH is at a low level (when the switching element M1 is off), the transistor Tr5 is kept on, so that the current from the constant current source Idc1 flows to the negative terminal via the transistor Tr5. As a result, when the switching element M1 is normally turned off, the voltage at the positive input terminal of the comparator CP2 does not increase even if the voltage at the drain terminal DrainH increases. As a result, erroneous detection of an arm short circuit is prevented. The output signal of the comparator CP2 is expanded in the time axis direction by the signal width expansion circuit MM1, and is output as the abnormality detection signal SfaH.

The state signal generation unit 21H includes a pulse signal generation source CLK1, an inverter circuit INV1, OR circuits B1 and B2, and an AND circuit A1. The pulse signal generation source CLK1 generates an abnormal pulse signal Sfp consisting of continuous pulses, and supplies the abnormal pulse signal Sfp to one input terminal of the OR circuit B1. In this example, the pulse period Tf (FIG. 5 described later) in the abnormal pulse signal SfP is shorter than the carrier period of pulse width modulation. An abnormality detection signal SfaH from the abnormality detection unit 24H is applied to the other input terminal of the OR circuit B1 via the inverter circuit INV1. The abnormality detection signal SfaH from the abnormality detection unit 24H is given to one input terminal of the OR circuit B2. An ON / OFF determination signal SonH from the ON / OFF determination unit 23H is supplied to the other input terminal of the OR circuit B2. The output signal of the OR circuit B1 is given to one input terminal of the AND circuit A1, and the output signal of the OR circuit B2 is given to the other input terminal of the AND circuit A1. The AND circuit A1 outputs a state signal SstH.

When the abnormality detection signal SfaH is at the low level, the on / off determination signal SonH is output as the state signal SstH, and when the abnormality detection signal SfaH is at the high level, the abnormal pulse signal Sfp generated by the pulse signal generation source CLK1 is the state signal. Output as SstH. That is, when an abnormality is not detected, the state signal SstH represents the on / off state of the switching element M1 by a signal level. When an abnormality is detected, the state signal SstH indicates that the switching element M1 has an abnormality. Is represented by Thereby, it is possible to determine the on / off state of the switching element M1 and the presence / absence of an abnormality from the state signal SstH.

As described above, when the abnormality detection signal SfaH becomes a high level, the gate drive unit 22H turns off the switching element M1. Thereby, an arm short circuit is eliminated. However, when an arm short circuit occurs due to a failure of the switching element M2, even if the arm short circuit is temporarily eliminated by turning off the switching element M1, the arm short circuit is repeated when the switching element M1 is subsequently turned on. . Therefore, the abnormality detection signal SfaH is held at the high level even after the arm short circuit is eliminated by the signal width expansion circuit MM1. As a result, the switching element M1 is kept off for a predetermined time or more, and the repetition of the arm short circuit is prevented.

FIG. 3 is a schematic circuit diagram showing a specific configuration example of the control unit 10 of FIG. As shown in FIG. 3, the ON command generation unit 11 includes counter circuits CN1 and CN2, an OR circuit B3, a signal holding circuit FF1, a signal generation unit PG1, AND circuits A11 and A12, and inverter circuits INV2 and INV11. The status signal SfbH is provided from the insulated communication unit 20L in FIG. 1 to the counter circuit CN1, and the status signal SfbH is provided from the insulated communication unit 20H in FIG. 1 to the counter circuit CN2. The counter circuit CN1 counts the number of pulses of the status signal SfbL. The counter circuit CN2 counts the number of pulses of the status signal SfbH. Each of the counter circuits CN1 and CN2 is supplied with a clear signal CLR at a predetermined count reset period Tr (FIG. 5 described later). When the clear signal CLR is given, the counter circuits CN1 and CN2 reset the count value. When a predetermined number of pulses are counted within the count reset period Tr by at least one of the counter circuits CN1 and CN2, it is determined that an abnormality has occurred.

The count reset period Tr is set larger than the pulse period Tf of the abnormal pulse signal Sfp. Thereby, when an abnormality occurs, each of the counter circuits CN1 and CN2 counts at least one pulse of the abnormal pulse signal Sfp. The pulse period Tf of the abnormal pulse signal Sfp is set to be smaller than the carrier period Tc of pulse width modulation (FIG. 5 described later). Accordingly, it is possible to accurately distinguish the pulses of the on / off determination signals SonH and SonL included in the normal state signals SfbH and SfbL from the pulses of the abnormal pulse signal Sfp included in the state signals SfbH and SfbL when the abnormality occurs. it can. Details of the status signals SfbH and SfbL will be described later. The signal holding circuit FF1 generates the abnormality holding signal SfbFF by holding the abnormality signal ScnH or the abnormality signal ScnL. The abnormality holding signal SfbFF output from the signal holding circuit FF1 is inverted by the inverter circuit INV11 and applied to one input terminal of the AND circuit A11 and one input terminal of the AND circuit A12.

The signal generation unit PG1 is supplied with a control signal Sdrv for realizing a switching operation by pulse width modulation from an arithmetic processing unit (not shown) (for example, a microcomputer). The signal generator PG1 outputs a command signal Scom based on the control signal Sdrv. The command signal Scom is at a high level during a period during which the switching element M1 is to be turned on, and is at a low level during a period during which the switching element M2 is to be turned on. Command signal Scom is applied to the other input terminal of AND circuit A12, inverted by inverter circuit INV2, and applied to the other input terminal of AND circuit A11 as command signal Scom '. The AND circuit A11 outputs an on signal SinH. The AND circuit A12 outputs an on signal SinL.

When normal, the abnormality holding signal SfbFF output from the signal holding circuit FF1 is at a low level. Therefore, a high level signal inverted by the inverter circuit INV11 is given to the AND circuits A11 and A12. In this case, the AND circuit A12 outputs the command signal Scom output from the signal generation unit PG1 as the on signal SinL, and the AND circuit A11 outputs the command signal Scom ′ that is an inverted signal of the command signal Scom as the on signal SinH. To do. When an abnormality occurs, the abnormality holding signal SfbFF output from the signal holding circuit FF1 becomes high level. Therefore, the low level signal inverted by the inverter circuit INV2 is given to the AND circuits A11 and A12. As a result, the AND circuits A11 and A12 output low level ON signals SinH and SinL, respectively.

The dead time generation unit 12H includes an inverter circuit INV3 and an AND circuit A2. An ON signal SinH output from the AND circuit A11 of the ON command generation unit 11 is given to one input terminal of the AND circuit A2. Further, the state signal SfbL output from the insulating communication unit 20L in FIG. 1 is inverted by the inverter circuit INV3 and applied to the other input terminal of the AND circuit A2. The AND circuit A2 outputs an on / off command signal SctlH. The dead time generation unit 12L includes an inverter circuit INV4 and an AND circuit A3. The ON signal SinL output from the AND circuit A12 of the ON command generation unit 11 is given to one input terminal of the AND circuit A3. Further, the state signal SfbH output from the insulated communication unit 20H in FIG. 1 is inverted by the inverter circuit INV4 and applied to the other input terminal of the AND circuit A3. The AND circuit A3 outputs an on / off command signal SctlL.

During normal operation, when one switching element is turned on, each on / off command signal is generated so that the other switching element is not turned on. Specifically, when the switching element M2 is turned on, the state signal SfbL is at a high level. Therefore, a low level signal inverted by the inverter circuit INV3 is given to the AND circuit A2. Accordingly, regardless of whether the on signal SinH is at a high level or a low level, the AND circuit A2 outputs a low level on / off command signal SctlH. On the other hand, when the switching element M2 is turned off, the state signal SfbL output from the insulated communication unit 20L in FIG. 1 becomes low level. Therefore, a high level signal inverted by the inverter circuit INV3 is given to the AND circuit A2. Thereby, when the ON signal SinH is at the high level, the AND circuit A2 outputs the ON / OFF command signal SctlH at the high level. Thus, when the switching element M2 is on, the high-level on / off command signal SctlL is not output from the AND circuit A2, and the high-level on / off command is provided on condition that the switching element M2 is off. Output of the signal SctlH is permitted. Accordingly, the switching element M1 can be quickly turned on after the switching element M2 is turned off while preventing the switching elements M1 and M2 from being turned on simultaneously. Similarly, when the switching element M1 is on, the high-level on / off command signal SctlL is not output from the AND circuit A3, and the high-level on / off command signal is provided on condition that the switching element M1 is off. Output of SctlL is allowed. Accordingly, the switching element M2 can be quickly turned on after the switching element M1 is turned off while preventing the switching elements M1 and M2 from being turned on simultaneously. In this way, the dead time when the switching elements M1, M2 are turned off is shortened.

When the abnormality holding signal SfbFF output from the signal holding circuit FF1 becomes high level, both the on signals SinH and SinL are maintained at low level. Thereby, the switching elements M1 and M2 are both turned off except when the switching elements M1 and M2 cannot be driven due to a failure.

As described above, when an abnormality occurs, the gate drive unit 22H or 22L turns off the switching element M1 or M2 in response to the abnormality detection signal SfaH or SfaL becoming a high level. Thereby, a system (for example, a power converter described later) including the switching elements M1 and M2 is primarily protected. In addition, when the abnormality holding signal SfbFF becomes high level, the control unit 10 turns off all the switching elements. As a result, the system is secondarily protected, and malfunctions due to abnormalities are prevented. A reset signal RST is supplied to the signal holding circuit FF1 as necessary. For example, when an abnormality is erroneously detected due to noise or the like, the signal holding circuit FF1 can be returned to a normal state by the reset signal RST.

FIG. 4 is a time chart showing an example of changes in various signals and changes in the gate-source voltages of the switching elements M1 and M2 in the first embodiment. Here, an example in which an arm short circuit occurs due to a failure of the switching element M2 will be described.

At time t0, the ON signal SinH, the ON / OFF command signal SctlH, and the ON / OFF command signal SgdlH are each at a high level, and the ON signal SinL, the ON / OFF command signal SctlL, and the ON / OFF command signal SgdlL are each at a low level. The gate-source voltage VgsH of the switching element M1 is VccH, and the gate-source voltage VgsL of the switching element M2 is VeeL. The on / off determination signal SonH is at a high level, and the on / off determination signal SonL is at a low level. The abnormality detection signals SfaH and SfaL are both at a low level. That is, no abnormality has occurred at time t0. Therefore, the state signal SstH and the state signal SfbH are at the same high level as the on / off determination signal SonH, and the state signal SstL and the state signal SfbL are at the same low level as the on / off determination signal SonL.

At time t1, the on signal SinH becomes low level and the on signal SinL becomes high level. In response to the change of the on signal SinH, the on / off command signal SctlH becomes low level. On the other hand, the on / off command signal SctlL is maintained at a low level. As described above, when the state signal SfbH is at the high level, the on / off command signal SctlL is maintained at the low level even when the on signal SinL is at the high level. At time t2, the on / off command signal SgdH becomes a low level with a slight delay from the on / off command signal SctlH. As a result, the gate-source voltage VgsH of the switching element M1 starts to drop.

At time t3, the gate-source voltage VgsH becomes lower than a predetermined off threshold value Vthoff. Thereby, it is determined that the switching element M1 is turned off, the on / off determination signal SonH becomes low level, and the state signal SstH becomes low level. At time t4, the state signal SfbH becomes a low level with a slight delay from the state signal SstH. When the state signal SfbH becomes a low level, the on / off command signal SctlL becomes the same high level as the on signal SinL in response thereto. At time t5, the on / off command signal SgdL becomes high level with a slight delay from the on / off command signal SctlL. As a result, the gate-source voltage VgsL of the switching element M2 starts to rise.

At time t6, the gate-source voltage VgsL becomes higher than a predetermined on-threshold value Vthon. Thereby, it is determined that the switching element M2 is turned on, the on / off determination signal SonL becomes high level, and the state signal SstL becomes high level. At time t7, the state signal SfbL becomes high level with a slight delay from the state signal SstL. Thereafter, the gate-source voltage VgsH is maintained at VeeH, and the gate-source voltage VgsL is maintained at VccL.

At time t8, the ON signal SinH becomes high level and the ON signal SinL becomes low level. In response to the change of the on signal SinL, the on / off command signal SctlL becomes low level. On the other hand, the on / off command signal SctlH is maintained at a low level. As described above, when the state signal SfbL is at the high level, the on-off command signal SctlH is maintained at the low level even when the on-signal SinH is at the high level by the dead time generation unit 12H in FIG. At time t9, the on / off command signal SgdL becomes low level with a slight delay from the on / off command signal SctlL. As a result, the gate-source voltage VgsL of the switching element M2 starts to drop.

At time t10, the gate-source voltage VgsL becomes lower than the off threshold value Vthoff. Thereby, it is determined that the switching element M2 is turned off, the on / off determination signal SonL becomes low level, and the state signal SstL becomes low level. At time t11, the state signal SfbL becomes low level with a slight delay from the state signal SstL. When the state signal SfbL becomes a low level, the on / off command signal SctlH becomes the same high level as the on signal SinH in response thereto. At time t12, the on / off command signal SgdH becomes high level with a slight delay from the on / off command signal SctlH. As a result, the gate-source voltage VgsH of the switching element M1 starts to rise.

At time t13, the gate-source voltage VgsH becomes higher than the ON threshold value Vthon. Thereby, it is determined that the switching element M1 is turned on, the on / off determination signal SonH becomes high level, and the state signal SstH becomes high level. At time t14, the state signal SfbH becomes high level with a slight delay from the state signal SstH.

In that state, a failure occurs in the switching element M2. As a result, the switching element M2 is turned on despite the ON / OFF command signal SgdL being at the low level, and the gate-source voltage VgsL of the switching element M2 becomes higher than the ON threshold value Vthon at time t15. As a result, the on / off determination signal SonL becomes high level and the state signal SstL becomes high level. At time t17, the state signal SfbL becomes high level with a slight delay from the state signal SstL. When the state signal SfbL becomes high level, the on-off command signal SctlH becomes low level by the dead time generator 12H of FIG. 3 even if the on signal SinH is high level.

On the other hand, at time t16, the abnormality detection unit 24H in FIG. 2 detects the arm short circuit, so that the abnormality detection signal SfaH becomes high level. Thereby, the abnormal pulse signal Sfp is inserted into the state signal SstH, and the abnormal pulse signal Sfp is inserted into the state signal SfbH with a slight delay. Further, when the abnormality detection signal SfaH becomes a high level, the gate drive unit 22H in FIG. 2 starts soft shutoff of the switching element M1. As a result, the gate-source voltage VgsH of the switching element M1 gradually decreases.

At time t18, the on / off command signal SgdH becomes a low level with a slight delay from the on / off command signal SctlH. In this case, since the gate drive unit 22H starts the soft shutoff of the switching element M1 in response to the abnormality detection signal SfaH, the soft shutoff of the switching element M1 is continued even when the on / off command signal SgdH becomes low level. The

FIG. 5 is a time chart showing an example of changes in the status signals SfbH and SfbL, the clear signal CLR, the abnormal signals ScnH and ScnL, and the abnormal holding signal SfbFF. Here, the relationship among the status signal SfbH, the counter circuit CN2, the abnormality signal ScnH, and the abnormality holding signal SfbFF will be mainly described. The relationship among the status signal SfbL, the counter circuit CN1, the abnormality signal ScnL, and the abnormality holding signal SfbFF is the same as that in the example of FIG. In the upper part of FIG. 5, the count value of the number of pulses by the counter circuit CN2 of FIG. 3 is shown. The counter circuit CN2 increments the count value when the state signal SfbH changes from the low level to the high level, and resets the count value when the pulse rises to the clear signal CLR in a certain count reset cycle Tr.

In the normal state, when the on / off determination signal SonH becomes high level, the state signal SfbH becomes high level. On the other hand, when an abnormality occurs, the abnormal pulse signal Sfp is inserted into the state signal SfbH, so that a plurality of pulses rise continuously in the state signal SfbH. As described above, the count reset period Tr is set larger than the pulse period Tf of the abnormal pulse signal Sfp. Thus, when an abnormality occurs, the counter circuit CN2 counts at least one pulse of the abnormal pulse signal Sfp. The pulse period Tf is set smaller than the carrier period Tc of pulse width modulation. In this case, with the passage of time, the number of pulses of the abnormal pulse signal Sfp counted when an abnormality occurs becomes larger than the number of pulses of the on / off determination signal SonH counted when normal. In the present embodiment, the presence / absence of an abnormality is determined using the difference between the count value at the normal time and the count value at the time of occurrence of the abnormality.

In the example of FIG. 5, the count reset cycle Tr is set so that the number of times the pulse rises in the state signal SfbH within the count reset cycle Tr at normal time is at most one. Therefore, the upper limit of the count value at normal time is 1. On the other hand, when an abnormality occurs, a plurality of pulses continuously rise in the state signal SfbL by inserting the abnormal pulse signal Sfp, so that the count value becomes 2 or more as time passes. That is, when the count value is 2 or more, it can be identified that an abnormality has occurred. Therefore, the counter circuit CN2 raises the pulse PA to the abnormal signal ScnH when the count value reaches a predetermined value of 2 or more. In the example of FIG. 5, the counter circuit CN2 is a 3-bit counter, and when the count value reaches 3, the pulse PA is raised to the abnormal signal ScnH. When the pulse PA rises, the abnormality holding signal SfbFF becomes high level. Thereafter, the abnormality holding signal SfbFF is maintained at a high level. In this way, the state signals SfbH and SfbL at the normal time can be accurately distinguished from the state signals SfbH and SfbL at the time of occurrence of the abnormality. Therefore, the dead time can be appropriately shortened based on the normal state signals SfbH and SfbL (on / off determination signals SonH and SonL), and the abnormal state signal SfbH and SfbL (abnormal pulse signal Sfp) can be obtained. Based on this, secondary protection of the entire system can be appropriately performed.

Suppose that the gate-source voltage VgsL is inverted due to a failure of the gate of the switching element M2 as an arm short circuit as in the example of FIG. In this case, the failed switching element M2 cannot be turned off. In this example, the abnormality is detected by the abnormality detecting unit on the side of the switching element whose gate is turned on first, that is, the abnormality detecting unit 24H on the side of the switching element M1 in which no failure has occurred. Therefore, in response to the abnormality detection signal SfaH from the abnormality detection unit 24H, the switching element M1 in which no failure has occurred is turned off. Thereby, the switching element M1 can be safely soft-blocked in response to detection of a short circuit.

However, as a case where the gate drive unit 22H turns off the switching element M1 when an arm short-circuit occurs, a case where the gate drive unit 22H turns off the switching element M1 in response to the abnormality detection signal SfaH and a response to the on / off command signal SgdH. In some cases, the gate driver 22H turns off the switching element M1. Specifically, when the abnormality detection unit 24H detects an abnormality, the abnormality detection signal SfaH from the abnormality detection unit 24H becomes a high level. In response to this, the gate driver 22H turns off the switching element M1. Hereinafter, turning off the switching element in response to the abnormality detection signal is referred to as a detection off operation. On the other hand, when the switching element M2 is turned on while the switching element M1 is turned on, the on / off command signal SctlH output from the dead time generation unit 12H becomes a low level. As a result, the on / off command signal SgdH given from the insulating communication unit 20H to the gate drive unit 22H becomes low level, and in response thereto, the gate drive unit 22H turns off the switching element M1. Hereinafter, turning off the switching element in response to the on / off command signal is referred to as a command-off operation.

When the high-level abnormality detection signal SfaH reaches the buffer circuit BF1 of the gate drive unit 22H before the low-level on / off command signal SgdH reaches the buffer circuit BF1 (FIG. 2) of the gate drive unit 22H, gate drive is performed. Detection off operation by the part 22H is performed. Conversely, when the low-level on / off command signal SgdH reaches the buffer circuit BF1 of the gate driver 22H before the high-level abnormality detection signal SfaH reaches the buffer circuit BF1 of the gate driver 22H, the gate driver The command off operation by 22H is performed. When the gate driver 22H performs the detection off operation, the switching element M1 is softly shut off. On the other hand, when the gate drive unit 22H performs the command off operation, the switching element M1 may be hard-blocked.

FIG. 6 is a time chart for explaining changes in various signals when the switching element M1 is hard cut off. The example of FIG. 6 differs from the example of FIG. 4 in the following points. In the example of FIG. 6, after the on / off determination signal SonL becomes high level at time t15, the on / off command signal SctlH becomes low level at time t21. For this reason, the switching element M1 is turned off by the command-off operation of the gate drive unit 22H before the arm short circuit is detected by the abnormality detection unit 24H. Therefore, the switching element M1 is hard cut off. At time t23, the gate-source voltage VgsH becomes smaller than the off threshold value Vthoff. Thereby, the short circuit is eliminated before the arm short circuit is detected by the abnormality detection unit 24H. Therefore, abnormality detection signal SfaH is maintained at a low level, and abnormal pulse signal Sfp is not inserted into state signal SstH.

4 and 6 is called a Type II short circuit (when the MOS channel is conductive) or a Type III short circuit (when the diode is conductive). Since these short circuits can generate a large current, in general, the time from when the short circuit is detected until the target switching element is softly cut off is set to be sufficiently short (for example, Japanese Patent Application Laid-Open No. 2015-139271). reference).

However, as in the example of FIG. 6, there is a case where the command off operation is performed before the detection off operation, and the switching element M1 is hard cut off. Even when the switching element M1 is hard interrupted, the current flowing through the switching element M1 is suppressed if the time from when the arm short circuit occurs until the hard disconnection is short is short. Therefore, the possibility that the switching element M1 is destroyed is low. However, in order to further improve the reliability, it is preferable that the soft shut-off is performed instead of the hard shut-off.

Such a problem is a new problem that occurs when the other switching element is driven based on the on / off state of one switching element in order to shorten the dead time. Such a problem is not described at all in the known literature.

In order to solve such a problem, the ON determination time of the switching elements M1 and M2 (the time from when the switching elements M1 and M2 are turned ON until the ON / OFF determination signals SonH and SonL become high level) is the OFF determination time (switching) It may be set longer than the time from when the elements M1 and M2 are turned off until the on / off determination signals SonH and SonL become low level. Specifically, in each of the on / off determination units 23H and 23L, the value of the resistor R11 shown in FIG. 2 is set to be sufficiently larger than the parallel value of the resistor R11 and the resistor R12. The speed at which the voltage at the positive input terminal of the comparator CP1 rises depends on the value of the resistor R11. On the other hand, the speed at which the voltage at the positive input terminal of the comparator CP1 drops depends on the parallel value of the resistor R11 and the resistor R12. Accordingly, the larger the value of the resistor R11, the longer the ON determination time, and the smaller the value of the resistor R12, the shorter the OFF determination time.

FIG. 7 is a time chart for explaining changes in various signals when the ON determination time is set to be relatively long. The example of FIG. 7 differs from the example of FIG. 4 in the following points. In the example of FIG. 7, since the ON determination time is set to be relatively long, after a certain time has elapsed since the gate-source voltage VgsL of the switching element M2 becomes larger than the ON threshold value Vthon at time t15. At time t15a, the on / off determination signal SonL becomes high level. The time from time t15 to time t15a corresponds to the on determination time. In this case, at time t16 before the command-off operation is performed, the abnormality detection unit 24H detects an arm short circuit, and the abnormality detection signal SfaH becomes high level. In response to this, the soft shut-off of the switching element M1 by the gate driver 22H is started. Thereby, since the switching element M1 is turned off not by hard interruption but by soft interruption, further improvement in reliability is realized.

The ON determination time is set longer than the time required for the abnormality detection units 24H and 24L to detect an arm short circuit, for example. However, between the time when the on / off determination signals SonH and SonL are output and before the switching elements M1 and M2 are turned off by the on / off command signals SgdH and SgdL, a signal delay occurs in the insulating communication units 20H and 20L. Therefore, it is only necessary that the sum of the ON determination time and the delay time generated in the insulated communication units 20H and 20L is larger than the time required to detect the arm short circuit. On the other hand, in order to shorten the dead time, the off determination time is preferably set sufficiently shorter than the on determination time.

As an abnormality of the switching elements M1 and M2, a temperature abnormality, an overvoltage abnormality, an overcurrent, a failure, a characteristic deterioration, or the like may be detected instead of the arm short circuit. The temperature abnormality, overvoltage abnormality, overcurrent, failure, and characteristic deterioration of the switching elements M1 and M2 can be detected by a known detection method.

The time constant at which the temperature rise or characteristic deterioration proceeds is, for example, several ms or more, and the time constant of the dead time is, for example, several hundred ns to several μs. Large enough compared to the time constant. Therefore, the time constant for detecting the temperature abnormality or characteristic deterioration required for the control unit 10 is sufficiently larger than the time constant of the dead time. Therefore, the control unit 10 can protect the system from a temperature rise or characteristic deterioration with a time margin while appropriately securing a dead time. On the other hand, with respect to abnormalities such as short circuit, overvoltage, overcurrent, or failure, as described above, by performing primary protection by the gate drive units 22H and 22L, the control unit 10 can ensure time while appropriately securing the dead time. Secondary protection of the entire system can be performed with sufficient margin.

As described above, in the semiconductor drive device 1 according to the first embodiment, the on / off determination signals SonH and SonL are not transmitted via the dedicated channels of the insulated communication units 20H and 20L, respectively, but are turned on / off determination signals. State signals SstH and SstL are generated based on the SonH and SonL and the abnormality detection signals SfaH and SfaL, and the state signals SstH and SstL are transmitted through one channel of the insulated communication units 20H and 20L, respectively. Thereby, the ON / OFF state of the switching elements M1 and M2 can be transmitted to the control unit 10 without providing a new channel in the insulated communication units 20H and 20L. Therefore, the dead time can be appropriately shortened while suppressing an increase in size and cost of the semiconductor drive device 1.

[Embodiment 2]
The second embodiment of the present invention will be described while referring to differences from the first embodiment. FIG. 8 is a schematic circuit diagram illustrating a specific configuration example of the state signal generation unit 21H, the gate drive unit 22H, the on / off determination unit 23H, and the abnormality detection unit 24H of the semiconductor drive device 1 according to the second embodiment. . The gate drive unit 22H, the on / off determination unit 23H, and the abnormality detection unit 24H in FIG. 8 have the same configuration as the gate drive unit 22H, the on / off determination unit 23H, and the abnormality detection unit 24H in FIG.

8 includes AND circuits A4 and A5, inverter circuits INV5 and INV6, and an OR circuit B4. The abnormality detection signal SfaH from the abnormality detection unit 24H is supplied to one input terminal of the AND circuit A4 and is also supplied to one input terminal of the AND circuit A5 via the inverter circuit INV6. An ON / OFF command signal SgdH is applied to the other input terminal of the AND circuit A4 via the inverter circuit INV6. The output signal of AND circuit A4 and the output signal of AND circuit A5 are applied to one and the other input terminals of OR circuit B4. In the state signal generation unit 21H, when the abnormality detection signal SfaH is at the low level, the on / off determination signal SonH is output as the state signal SstH, and when the abnormality detection signal SfaH is at the high level, the inverted signal of the on / off command signal SgdH Is output as the status signal SstH. The state signal generation unit 21L has the same configuration and function as the state signal generation unit 21H of FIG.

The control unit 10 of the semiconductor drive device 1 according to the second embodiment determines whether there is an abnormality based on the difference between the state signals SfbH, SfbL and the command signals Scom, Scom ′ transmitted by the insulated communication units 20H, 20L. To do. FIG. 9 is a schematic circuit diagram illustrating a specific configuration example of the control unit 10 of the semiconductor drive device 1 according to the second embodiment. The dead time generation units 12H and 12L in FIG. 9 have the same configuration as the dead time generation units 12H and 12L in FIG. 9 includes EXOR circuits Bx1 and Bx2, low-pass filters LPF1 and LPF2, and an OR circuit B5 instead of the counter circuits CN1 and CN2 and the OR circuit B3. The state signal SfbL is supplied to one input terminal of the EXOR circuit Bx1. A command signal Scom is given to the other input terminal of the EXOR circuit Bx1. The state signal SfbH is given to one input terminal of the EXOR circuit Bx2. The command signal Scom 'is input to the other input terminal of the EXOR circuit Bx2.

The EXOR circuit Bx1 outputs a difference determination signal SxoL. If the logic (signal level) is different between the state signal SfbL and the command signal Scom, the difference determination signal SxoL becomes high level. The EXOR circuit Bx2 outputs a difference determination signal SxoH. If the logic (signal level) differs between the state signal SfbH and the command signal Scom ', the difference determination signal SxoH becomes high level. When the abnormality holding signal SfbFF output from the signal holding circuit FF1 is at a low level, the command signal Scom is equal to the on signal SinL, and the command signal Scom 'is equal to the on signal SinH. If no abnormality has occurred, the logic is the same between the state signal SfbL and the command signal Scom and the logic is the same between the state signal SfbH and the command signal Scom 'for most of the period. However, the logic is temporarily different between the state signal SfbL and the command signal Scom or between the state signal SfbH and the command signal Scom ′ due to the delay due to the signal transmission and the on / off operation of the switching elements M1 and M2. Sometimes. In that case, the difference determination signals SxoL and SxoH temporarily become high level. Hereinafter, delay times due to signal transmission and on / off operations of the switching elements M1 and M2 are collectively referred to as operation delay times. Further, in the dead time, since the logic is different between the state signal SfbL and the command signal Scom or between the state signal SfbH and the command signal Scom ′, the difference determination signal SxoL or the difference determination signal SxoH is temporarily at a high level. become.

The difference determination signal SxoL output from the EXOR circuit Bx1 is applied to the low-pass filter LPF1, and the difference determination signal SxoH output from the EXOR circuit Bx2 is applied to the low-pass filter LPF2. The low-pass filter LPF1 generates an abnormal signal ScnL by removing high frequency components from the difference determination signal SxoL. The low-pass filter LPF2 generates an abnormal signal ScnH by removing high frequency components from the difference determination signal SxoH. In this case, when the difference determination signal SxoL is held at a high level for a time longer than the time constant of the low-pass filter LPF1, the abnormal signal ScnL becomes a high level. Further, when the difference determination signal SxoH is held at the high level for a time longer than the time constant of the low-pass filter LPF2, the abnormal signal ScnH becomes the high level. The time constants of the low-pass filters LPF1 and LPF2 are set longer than, for example, a total time of an operation delay time required for one on operation or one off operation and one dead time. Further, the time constants of the low-pass filters LPF1 and LPF2 may be set longer than the carrier cycle Tc.

The abnormal signal ScnL is supplied to one input terminal of the OR circuit B5, and the abnormal signal ScnH is supplied to the other input terminal of the OR circuit B5. The output signal of the OR circuit B5 is given to the signal holding circuit FF1. When one of the abnormal signals ScnH and ScnL becomes high level, the abnormal holding signal SfbFF output from the signal holding circuit FF1 becomes high level.

FIG. 10 is a time chart showing an example of changes in various signals and changes in the gate-source voltages of the switching elements M1 and M2 in the second embodiment. The difference between the example of FIG. 10 and the example of FIG. 4 will be described. In the example of FIG. 10, an abnormality occurs at time t31, and the abnormality detection signal SfaH becomes high level. As a result, the state signal SstH becomes an inverted signal of the on / off command signal SgdH. At this time, since the on / off command signal SgdH is at a high level, the state signal SstH is at a low level. At time t32, the state signal SfbH becomes a low level with a slight delay from the state signal SstH.

FIG. 11 is a time chart showing an example of changes in the command signals Scom 'and Scom, the on / off command signals SctlH and SctlL, the status signals SfbH and SfbL, the difference determination signals SxoH and SxoL, and the abnormal signals ScnH and ScnL. In the period from the time point t1 to the time point t4, the command signal Scom 'is at the low level, while the state signal SfbH is at the high level. Therefore, the difference determination signal SxoH becomes a high level. Further, in the period from the time point t1 to the time point t7, the command signal Scom is at a high level, whereas the state signal SfbL is at a low level. Therefore, the difference determination signal SxoL becomes high level. Similarly, during a period from time t8 to time t11, the command signal Scom is at a low level, while the state signal SfbL is at a high level. Therefore, the difference determination signal SxoL becomes high level. Further, during the period from time t8 to time t13, the command signal Scom 'is at the high level, while the state signal SfbH is at the low level. Therefore, the difference determination signal SxoH becomes a high level.

As described above, the state signal SfbH becomes low level at time t32 due to the occurrence of an abnormality. As a result, the logic does not match between the command signal Scom 'and the state signal SfbH, and the difference determination signal SxoH becomes high level. At time t33 when the time constant Tlp of the low-pass filter LPF1 has elapsed from time t32, the abnormal signal ScnH becomes high level. As a result, the abnormality holding signal SfbFF output from the signal holding circuit FF1 of FIG. 9 becomes high level, and the on signals SinH and SinL become low level. In this way, the state signals SfbH and SfbL at the normal time can be accurately distinguished from the state signals SfbH and SfbL at the time of occurrence of the abnormality. Therefore, the dead time can be appropriately shortened based on the normal state signals SfbH and SfbL (on / off determination signals SonH and SonL), and the entire system based on the abnormal state signal SfbH and SfbL. Secondary protection can be performed appropriately.

[Embodiment 3]
The third embodiment of the present invention will be described while referring to differences from the first embodiment. FIG. 12 is a block diagram showing a basic configuration of the semiconductor drive device 1 according to the third embodiment. In the example of FIG. 12, switching elements M1s and M2s are provided in addition to the switching elements M1 and M2. In this example, the switching elements M1s and M2s are MOSFETs. The switching element M1s shares the drain terminal and the gate terminal with the switching element M1, and the switching element M2s supplies the switching element M2, the drain terminal, and the gate terminal. In this example, overcurrent is detected as an abnormality of the switching elements M1 and M2 by the switching elements M1s and M2s.

FIG. 13 is a schematic circuit diagram illustrating a specific configuration example of the state signal generation unit 21H, the gate drive unit 22H, the on / off determination unit 23H, and the abnormality detection unit 24H in the third embodiment. The state signal generation unit 21H, the gate drive unit 22H, and the on / off determination unit 23H in FIG. 13 have the same configuration as the state signal generation unit 21H, the gate drive unit 22H, and the on / off determination unit 23H in FIG. The abnormality detection unit 24L has the same configuration as the abnormality detection unit 24H of FIG. The abnormality detection unit 24H in FIG. 13 includes resistors R21 and R22 instead of the resistors R16 to R18, the diodes D2 and D3, the transistor Tr5, and the constant current source Idc1 in FIG. The positive side input terminal of the comparator CP2 is connected to the source terminal SourceHs of the switching element M2s via the resistor R22. In the abnormality detection unit 24H, the current of the switching element M1s is converted into a voltage by the resistor R21, and the output signal of the comparator CP2 becomes high level, whereby an overcurrent is detected.

Also in the semiconductor drive device 1 according to the third embodiment, similarly to the first embodiment, the switching elements M1 and M2 are turned on and off in the control unit 10 without providing new channels in the insulated communication units 20H and 20L. Can communicate. Therefore, the dead time can be appropriately shortened while suppressing an increase in size and cost of the semiconductor drive device 1.

[Embodiment 4]
The difference between the fourth embodiment of the present invention and the first embodiment will be described. FIG. 14 is a block diagram showing a basic configuration of the semiconductor drive device 1 according to the fourth embodiment. In the example of FIG. 14, an overcurrent is detected as an abnormality of the switching elements M1 and M2 based on the parasitic inductances of the switching elements M1 and M2. In FIG. 14, an inductor L1 having a parasitic inductance of the switching element M1 and an inductor L2 having a parasitic inductance of the switching element M2 are schematically shown.

FIG. 15 is a schematic circuit diagram illustrating a specific configuration example of the state signal generation unit 21H, the gate drive unit 22H, the on / off determination unit 23H, and the abnormality detection unit 24H in the fourth embodiment. The state signal generation unit 21H, the gate drive unit 22H, and the on / off determination unit 23H in FIG. 15 have the same configuration as the state signal generation unit 21H, the gate drive unit 22H, and the on / off determination unit 23H in FIG. The abnormality detection unit 24L has the same configuration as the abnormality detection unit 24H in FIG.

15 includes an operational amplifier OP1, a capacitor C6, and resistors R25, R26, and R27 instead of the resistors R16 to R18, the diodes D2 and D3, the transistor Tr5, and the constant current source Idc1 in FIG. The negative input terminal of the operational amplifier OP1 is connected to the source terminal SourceHt via the resistor R25. The output terminal of the operational amplifier OP1 is connected to the positive side input terminal of the comparator CP2. In this case, the voltage generated in the inductor L1 in FIG. 14 is integrated by the operational amplifier OP1, and the overcurrent is detected by the output signal of the comparator CP2 becoming high level.

Also in the semiconductor drive device 1 according to the fourth embodiment, similarly to the first embodiment, the switching elements M1 and M2 are turned on and off in the control unit 10 without providing new channels in the insulated communication units 20H and 20L. Can communicate. Therefore, the dead time can be appropriately shortened while suppressing an increase in size and cost of the semiconductor drive device 1.

[Embodiment 5]
A power conversion apparatus according to Embodiment 5 of the present invention will be described. FIG. 16 is a circuit diagram showing a configuration of a power conversion device according to the fifth embodiment. 16 includes inverter device 73 and semiconductor drive device 1 according to any of the first to fourth embodiments. The inverter device 73 is an example of a power conversion unit, and includes switching elements M3 to M8 and an output capacitor 82. The inverter device 73 is a so-called three-phase inverter. The inverter device 73 is an example of a power conversion unit, converts the DC power of the DC power supply 70 into three-phase AC power, and supplies the converted AC power to the motor 74 that is an AC load. In this example, the switching elements M3 to M8 are power MOSFETs. The semiconductor drive device 1 drives the switching elements M3 to M8.

In this case, since the semiconductor drive device 1 according to any of the first to fourth embodiments is used, the dead time can be appropriately shortened while suppressing an increase in size and cost of the semiconductor drive device 1. Further, the power conversion efficiency of the inverter device 73 can be improved by reducing the dead time. Further, when a SiC-MOSFET using a wide band gap semiconductor is applied as the switching elements M3 to M8, it is possible to suppress the deterioration of energization of the parasitic diode due to the SiC crystal defect, and the reliability of the inverter device 73 can be suppressed. Improvement in product performance and increase in product life can be realized.

In this embodiment, a three-phase inverter is used as the power conversion unit. However, the present invention is not limited to this, and an inverter having an arbitrary number of phases may be used. Further, even if the semiconductor drive device 1 according to any one of the first to fourth embodiments is applied to a power conversion device including an AC-DC converter that converts AC power into DC power instead of the inverter device 73 as a power conversion unit. Good.

[Embodiment 6]
A power conversion apparatus according to Embodiment 6 of the present invention will be described. FIG. 17 is a circuit diagram showing a configuration of a power conversion device according to the sixth embodiment. 17 includes boost converter 71 and semiconductor drive device 1 according to any one of the first to fourth embodiments. Boost converter 71 is an example of a voltage converter, and includes switching elements M11 and M12, an input capacitor 80, an output capacitor 82, and a boost reactor 81. In this example, the switching elements M11 and M12 are power MOSFETs.

Boost converter 71 boosts the voltage of DC power supply 70 and supplies power to DC load 72. The semiconductor drive device 1 drives the switching elements M11 and M12.

In the present embodiment, in order to reduce the size of the step-up reactor 81, high-speed switching elements using wide band gap semiconductors are applied as the switching elements M11 and M12. As a result, the carrier cycle can be shortened. For example, the switching elements M11 and M12 are driven so that the carrier cycle Tc is 10 μs and the on-duty is 50%. In that case, the ideal pulse width of the on / off command signal for driving the switching elements M11 and M12 is 5 μs. However, since it is actually necessary to provide a dead time, for example, when the dead times when the switching elements M11 and M12 are turned on and off are 0.5 μs, the effective pulse width of the on / off command signal is 4 μs. Decrease. In this case, the proportion of the time during which current flows through the parasitic diode with poor conduction characteristics increases, and the power conversion efficiency decreases. Furthermore, since the effective maximum on-duty is reduced by adding the dead time, the range in which the voltage can be boosted is reduced.

On the other hand, in the boost converter 71 according to the present embodiment, since the semiconductor drive device 1 can reduce the dead time as described above, the power conversion efficiency is prevented from being lowered and the boostable range is increased. spread.

A state signal generation method suitable when the carrier period is shortened as in this embodiment will be described. In state signal generation units 21H and 21L (FIG. 2) according to the first embodiment, when an abnormality occurs, abnormal pulse signal Sfp having a pulse period shorter than carrier period Tc is inserted into the state signal. In that case, there are restrictions on the signal bands required for the insulated communication units 20H and 20L, or there are restrictions on the calculation speed of a microcomputer or the like provided in the control unit 10. Therefore, in the present embodiment, for example, the pulse period of the abnormal pulse signal Sfp output from the pulse signal generation source CLK1 is set to be larger than the carrier period Tc.

FIG. 18 is a schematic circuit diagram illustrating a specific configuration example of the control unit 10 included in the semiconductor drive device 1 of FIG. The dead time generation units 12H and 12L in FIG. 18 have the same configuration as the dead time generation units 12H and 12L in FIG. 18 includes low pass filters LPF3 and LPF4 and an OR circuit B6 instead of the counter circuits CN1 and CN2 and the OR circuit B3. A state signal SfbL is given to the low-pass filter LPF3, and a state signal SfbH is given to the low-pass filter LPF4. The low-pass filter LPF3 generates an abnormal signal SlpL by removing high frequency components from the state signal SfbL. The low-pass filter LPF4 generates the abnormal signal SlpH by removing high frequency components from the state signal SfbH. The time constants of the low-pass filters LPF3 and LPF4 are set larger than the carrier period Tc of the boost converter 71 and smaller than the pulse width of the abnormal pulse signal Sfp output from the pulse signal generation source CLK1.

FIG. 19 is a time chart for explaining the relationship between the abnormal signals SlpH and SlpL and other various signals. In the example of FIG. 19, the abnormality of the switching element M11 is detected at time t41. In a period before time t41, the state signals SfbH and SfbL represent the on / off states of the switching elements M1 and M2, and the pulse period of the state signals SfbH and SfbL is smaller than the carrier period Tc. Therefore, the abnormal signals SlpH and SlpL output from the low-pass filters LPF3 and LPF4 are maintained at a low level. On the other hand, when an abnormality is detected at time t41, an abnormal pulse signal Sfp having a pulse period Tf larger than the carrier period Tc is inserted into the state signal SfbH. At time t42, the pulse width of the state signal SfbH exceeds the time constant of the low-pass filter LPF4. As a result, the abnormal signal SlpH output from the low-pass filter LPF4 becomes high level. As a result, the abnormality holding signal SfbFF output from the signal holding circuit FF1 becomes high level, and the on signals SinH and SinL become low level. In this way, the state signals SfbH and SfbL at the normal time can be accurately distinguished from the state signals SfbH and SfbL at the time of occurrence of the abnormality. Therefore, the dead time can be appropriately shortened based on the normal state signals SfbH and SfbL (on / off determination signals SonH and SonL), and the abnormal state signal SfbH and SfbL (abnormal pulse signal Sfp) can be obtained. Based on this, secondary protection of the entire power conversion device 150 can be appropriately performed. Furthermore, the restriction on the signal bandwidth required for the insulated communication units 20H and 20L and the restriction on the calculation speed of the control unit 10 are alleviated.

In power conversion device 150 according to the sixth embodiment, since semiconductor drive device 1 according to any of first to fourth embodiments is used, dead time can be reduced while suppressing an increase in size and cost of semiconductor drive device 1. Can be shortened appropriately. In addition, it is possible to achieve both a reduction in dead time and a protection function in the event of an abnormality without depending on the transmission performance of the insulated communication unit and the calculation performance of the microcomputer.

The example of FIG. 17 is an example in which the semiconductor drive device 1 is applied to a power converter 150 including a boost converter 71 as a voltage converter, but a step-down converter or a buck-boost converter is used instead of the boost converter 71 as a voltage converter. The semiconductor drive device 1 according to any of Embodiments 1 to 4 may be applied to the power conversion device that includes the power conversion device.

[Embodiment 7]
A power conversion apparatus according to Embodiment 7 of the present invention will be described. FIG. 20 is a circuit diagram showing a configuration of the power conversion device according to the seventh embodiment. 20 is a step-up inverter system, and includes an inverter device 73 in FIG. 16 and a step-up converter 71 in FIG. The DC voltage of the DC power source 70 is boosted by the boost converter 71, the boosted DC voltage is converted into AC by the inverter device 73, and the converted AC power is supplied to the motor 74 to drive the motor 74. The power conversion device 200 according to the present embodiment is applied to, for example, an electric automobile.

In power conversion device 200 according to the seventh embodiment, since semiconductor drive device 1 according to any of the first to fourth embodiments is used, dead time is prevented while increasing the size and cost of semiconductor drive device 1. Can be shortened appropriately. Further, as in the sixth embodiment, the dead time can be reduced and the protection function in the event of an abnormality can be achieved without depending on the transmission performance of the insulated communication unit and the computing performance of the microcomputer. Furthermore, as in the fifth embodiment, the power conversion efficiency of the inverter device 73 can be improved by shortening the dead time. Further, when SiC-MOSFETs are applied as the switching elements M3 to M8, it is possible to suppress deterioration of energization of the parasitic diode due to SiC crystal defects, improving the reliability of the inverter device 73 and improving the product life. An increase can be realized.

The example of FIG. 20 is an example in which the semiconductor drive device 1 of any one of the first to fourth embodiments is applied to a power conversion device 200 that includes a boost converter 71 as a voltage conversion unit and includes an inverter device 73 as a power conversion unit. However, the semiconductor drive device 1 according to any one of the first to fourth embodiments may be applied to a power conversion device including a step-down converter or a step-up / down converter instead of the step-up converter 71 as a voltage conversion unit, or power conversion The semiconductor drive device 1 according to any one of the first to fourth embodiments may be applied to a power conversion device including an AC-DC converter that converts AC power into DC power instead of the inverter device 73 as a unit.

[Other embodiments]
In the above embodiment, a MOSFET is used as the semiconductor switching element, but the semiconductor switching element is not limited to this. For example, an IGB thyristor or a GTO (Gate Turn-off thyristor) may be used as the semiconductor switching element instead of the MOSFET.

In the above embodiment, the drive timing of the other switching element is controlled based on the on / off state of one of the pair of switching elements connected in series, but the present invention is not limited to this. Three or more switching elements may be connected in series, and drive timings of other switching elements may be controlled based on an on / off state of one of the switching elements.

In the above embodiment, the ON command generation unit 11 and the dead time generation units 12H and 12L of the control unit 10 are realized by hardware, but each function of the control unit 10 may be realized by software. FIG. 21 is a diagram illustrating an example in which each function of the control unit 10 is realized by software. In the example of FIG. 21, the control unit 10 includes a processing device (processor) 51 and a storage device (memory) 52. The processing device 51 is, for example, a CPU (Central Processing Unit), and can read out and execute a program stored in the storage device 52 to realize each function of the control unit 10 in the above embodiment.

In the above embodiment, the gate drive unit drives the switching elements M1 and M2 based on the on / off command signals SgdH and SgdL transmitted by the insulated communication units 20H and 20L, but the present invention is not limited to this. The on / off command signals SgdH and SgdL transmitted by the insulating communication units 20H and 20L may directly drive the switching elements M1 and M2.

DESCRIPTION OF SYMBOLS 1 Semiconductor drive device 10 Control part 11 ON command generation part 12H, 12L Dead time generation part 20H, 20L Insulation communication part 21H, 21L State signal generation part 22H, 22L Gate drive part 23H, 23L On-off determination part 24H, 24L Abnormality detection part M1 to M8 Switching element CLK1 Pulse signal generation source MM1 Signal width expansion circuit FF1 Signal holding circuit LP1 to LP4 Low-pass filter CN1, CN2 Counter circuit

Claims (16)

1. A controller that generates a plurality of on / off command signals for driving a plurality of semiconductor switching elements connected in series;
   An on / off determination section for detecting an on / off state of one of the plurality of semiconductor switching elements and outputting an on / off determination signal representing the detected on / off state; and
   An abnormality detection unit that detects the presence or absence of an abnormality in the one semiconductor switching element and outputs an abnormality detection signal that indicates the presence or absence of the detected abnormality;
   A state signal generation unit that outputs a state signal based on the on / off determination signal output from the on / off determination unit and the abnormality detection signal output from the abnormality detection unit;
   Transmitting one on / off command signal for driving the one semiconductor switching element generated by the control unit while ensuring insulation between the control unit and the one switching element, and the state signal generating unit An insulation communication unit that transmits a state signal output from the state signal generation unit while ensuring insulation between the control unit and the control unit,
   The said control part is a semiconductor drive device which produces | generates the other on-off command signal for driving another semiconductor switching element among these semiconductor switching elements based on the state signal transmitted by the said insulation communication part.
2. The control unit generates the other on / off command signal based on the state signal so that the other semiconductor switching element is not turned on when the one semiconductor switching element is turned on. The semiconductor drive device described.
3. During a period in which an abnormality detection signal indicating that there is no abnormality in the one semiconductor switching element is output from the abnormality detection unit, the state signal represents an on / off state of the one semiconductor switching element, and the abnormality detection The state signal represents that there is an abnormality in the one semiconductor switching element during a period in which an abnormality detection signal indicating that the one semiconductor switching element is abnormal is output from the unit. 2. The semiconductor drive device according to 2.
4. 4. The semiconductor drive device according to claim 3, wherein the status signal indicates on / off of the one semiconductor switching element by a signal level and indicates that there is an abnormality in the one semiconductor switching element by a continuous pulse.
5. The control unit generates the plurality of on / off command signals by pulse width modulation,
   The semiconductor drive device according to claim 4, wherein a period of the continuous pulse of the state signal is shorter than a carrier period of the pulse width modulation.
6. The control unit counts the number of pulses of the state signal every predetermined period, and the plurality of semiconductor switching elements are turned off when the counted number of pulses reaches a threshold value. The semiconductor drive device according to claim 4, wherein the on / off command signal is generated.
7. The abnormality detection unit according to any one of claims 1 to 6, wherein when an abnormality of the one semiconductor switching element is detected, the abnormality detection unit extends and outputs an abnormality detection signal indicating the abnormality in a time axis direction. Semiconductor drive device.
8. The on / off determination unit is an on / off determination unit of one of a plurality of on / off determination units,
   The abnormality detection unit is one abnormality detection unit among a plurality of abnormality detection units,
   The state signal generation unit is one state signal generation unit among a plurality of state signal generation units,
   The insulated communication unit is an insulated communication unit of one of a plurality of insulated communication units,
   The other on / off determination unit of the plurality of on / off determination units detects an on / off state of the other semiconductor switching element and outputs an on / off determination signal indicating the detected on / off state,
   The other abnormality detection unit among the plurality of abnormality detection units detects the presence or absence of abnormality of the other semiconductor switching element and outputs an abnormality detection signal indicating the presence or absence of the detected abnormality.
   The other state signal generation unit among the plurality of state signal generation units is based on the on / off determination signal output from the other on / off determination unit and the abnormality detection signal output from the other abnormality detection unit. Output a status signal,
   The other insulated communication unit among the plurality of insulated communication units transmits the other on / off command signal generated by the control unit while ensuring insulation between the control unit and the other switching element. Transmitting the state signal output from the other state signal generation unit while ensuring insulation between the other state signal generation unit and the control unit,
   The semiconductor drive device according to any one of claims 1 to 7, wherein the control unit generates the one on / off command signal based on a state signal transmitted by the other insulated communication unit.
9. A drive unit that drives the other semiconductor switching element based on the other on / off command signal generated by the control unit and the abnormality detection signal output from the other abnormality detection unit;
   When the one semiconductor switching element is turned on while the other semiconductor switching element is on the basis of the state signal output from the one and other state signal generating parts, the control unit Generating the other on / off command signal for turning off the semiconductor switching element of
   The drive unit turns off the other semiconductor switching element at a first speed when an abnormality detection signal indicating that there is an abnormality in the other semiconductor switching element is output from the other abnormality detection unit, Based on the other on / off command signal for turning off the other semiconductor switching element, the other semiconductor switching element is turned off at a second speed higher than the first speed,
   The other on / off determination unit outputs an on / off determination signal indicating that the other semiconductor switching element is turned off after a first time has elapsed since the other semiconductor switching element is turned off. The on / off determination signal indicating that the other semiconductor switching element is turned on is output after a second time longer than the first time has elapsed since the semiconductor switching element was turned on. Semiconductor drive device.
10. The control unit generates the on / off command signal based on pulse width modulation,
    The semiconductor drive device according to claim 4, wherein a time width of each pulse included in the continuous pulse of the state signal is longer than a carrier period of the pulse width modulation.
11. 11. The semiconductor drive device according to claim 10, wherein the control unit determines the presence / absence of the abnormality based on the state signal that has passed through a low-pass filter having a time constant longer than the carrier cycle.
12. The state signal generation unit outputs the on / off determination signal as the state signal during a period in which an abnormality detection signal indicating that there is no abnormality in the one semiconductor switching element is output from the abnormality detection unit, During a period in which an abnormality detection signal indicating that there is an abnormality in the one semiconductor switching element is output from the abnormality detection unit, an inverted signal of the one on / off command signal transmitted by the insulation communication unit is used as the state signal. The semiconductor drive device according to claim 1, which outputs as
13. The control unit generates the plurality of on / off command signals based on the command signal,
    The semiconductor drive device according to claim 12, wherein the control unit determines the presence or absence of the abnormality based on a difference between the state signal and the command signal.
14. A power conversion unit including a plurality of semiconductor switching elements and performing power conversion between direct current and alternating current;
    A power conversion device comprising: the semiconductor drive device according to any one of claims 1 to 13, which drives the plurality of semiconductor switching elements.
15. A voltage converter including a plurality of semiconductor switching elements and performing at least one of step-up and step-down of a DC voltage;
    A power conversion device comprising: the semiconductor drive device according to any one of claims 1 to 13, which drives the plurality of semiconductor switching elements.
16. A voltage converter having a plurality of first semiconductor switching elements and performing at least one of step-up and step-down of a DC voltage;
    A power conversion unit that has a plurality of second semiconductor switching elements and converts the power output by the voltage conversion unit into AC power;
    A power conversion device comprising: the semiconductor drive device according to any one of claims 1 to 13, which drives the plurality of first and second semiconductor switching elements.

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