WO2019157991A1

WO2019157991A1 - Low quiescent current, high psrr, low-dropout linear regulator circuit

Info

Publication number: WO2019157991A1
Application number: PCT/CN2019/074470
Authority: WO
Inventors: 陈乐峰; 陆文正
Original assignee: 杭州芯元微电子有限公司
Priority date: 2018-02-13
Filing date: 2019-02-01
Publication date: 2019-08-22
Also published as: CN108334149A; CN108334149B

Abstract

A low quiescent current, high PSRR, low-dropout linear regulator circuit. The circuit comprises an error amplifier (10), an adjusting component (20), a voltage dividing circuit (30), and a frequency band enhancing circuit (40). A drain electrode of the adjusting component (20) is connected to an input end of the voltage dividing circuit (30); a gate electrode of same is connected to an output end of the error amplifier (10). An output end of the voltage dividing circuit (30) is connected to an input end of the error amplifier (10). An end of the frequency band enhancing circuit (40) is connected to a substrate of the adjusting component (20). The frequency band enhancing circuit (40) forms a second path that runs from a power supply voltage end to an output end and is different from a first path that passes through the adjusting component (20). With one frequency band enhancing circuit (40) being provided in an existing low-dropout linear regulator, by generating an additional zero frequency, noise of a power supply voltage at a certain frequency point is eliminated, thus increasing the PSRR around the frequency.

Description

Low Quiescent Current High PSRR Low Dropout Linear Regulator Circuit

Technical field

The present invention relates to the field of integrated circuits, and more particularly to a low quiescent current high PSRR low dropout linear regulator circuit.

Background technique

Low Dropout Regulator (LDO) has the advantages of low output noise, simple circuit structure, small chip area and small electric ripple. It is an important part of power management circuit. The low dropout linear regulator circuit provides low output ripple power and better power supply rejection ratio (PSRR, Power Supply Rejection Ratio) for low noise performance for noise sensitive circuits such as analog and RF circuits. Therefore, it is widely used in handheld devices and portable electronic products.

With the rapid development of integrated circuits, the operating frequency of the chip continues to increase, and the PSRR performance of the low-dropout linear regulator circuit is also reduced. The power supply noise affects the performance of the entire system through the low-dropout linear regulator circuit, resulting in the system not meeting the application requirements in high-frequency working environments. For example, the prior art low dropout linear regulator circuit shown in Figure 1, the low dropout linear regulator circuit has high gain to ensure good line and load regulation, so it can attenuate the noise of the low frequency input supply. Since the bandwidth of the low-dropout linear regulator circuit is limited and the PSRR decreases as the frequency increases, the high-frequency noise outside the bandwidth of the low-dropout linear regulator circuit cannot be attenuated by the low-dropout linear regulator circuit itself. As a result, the PSRR continues to decrease, as shown in Figure 2.

Therefore, improving the PSRR characteristics of the low-dropout linear regulator circuit is an urgent problem to be solved.

Summary of the invention

The embodiment of the invention provides a low quiescent current high PSRR low dropout linear regulator circuit. The circuit includes: an error amplifier for amplifying an error of a signal of a forward input terminal and a negative input terminal; wherein, the signal of the forward input terminal is a reference signal; and the adjusting component comprises a first PMOS transistor; wherein, the first a gate of the PMOS transistor is connected to an output end of the error amplifier; a drain of the first PMOS transistor provides a circuit output end of the output voltage; and a voltage dividing circuit is connected between the drain of the first PMOS transistor and the ground, Providing a voltage division signal to a negative input terminal of the error amplifier; a band enhancement circuit coupled between the substrate of the adjustment element and a power supply voltage terminal; the band enhancement circuit forming a slave power supply voltage terminal A second path to the output that is different from the first path through the adjustment element, thereby generating an additional zero in the frequency domain.

Advantageously, said band enhancement circuit comprises: a first resistor, a capacitor and a gain buffer; said gain buffer comprising a second PMOS transistor;

The first resistor is coupled between a substrate of the first PMOS transistor and a supply voltage terminal; the capacitance is coupled between a substrate of the PMOS transistor and a source of the second PMOS transistor; A gate of the second PMOS transistor is coupled to a drain output of the first PMOS transistor; the first resistor and the capacitor form the additional zero in the frequency domain.

Preferably, the frequency of the additional zero is:

Where Rc is the resistance of the first resistor and Cc is the capacitance of the capacitor.

Preferably, after the noise of the power supply voltage is eliminated at one frequency point, the PSRR of the frequency point and its nearby frequency is:

PSRR=A(s)□(1+sRcCc);

among them,

VOUT is the output voltage and VDD is the supply voltage.

Preferably, the band enhancement circuit further includes a current source connected between the power supply voltage terminal and the source of the second PMOS transistor, and the current of the current source flows from the power supply voltage terminal to the source of the second PMOS transistor.

Preferably, the voltage dividing circuit includes a second resistor and a third resistor connected in series.

In the embodiment of the present invention, a band enhancement circuit is disposed in the original low dropout linear regulator, and the PSRR near the frequency is increased by generating an extra zero point to eliminate noise of the power supply voltage at a certain frequency point. In addition, by adjusting the resistance of the band enhancement circuit to move the notch frequency position, it can be used to cancel the frequency of some specific interference signals to improve the PSRR at the frequency point and its vicinity, helping the low dropout linear regulator in different scenarios. Application in .

DRAWINGS

1 is a low voltage difference linear regulator circuit in the prior art;

2 is a graph of PSRR of a low dropout linear regulator circuit in the prior art;

3 is a circuit diagram of a low quiescent current high PSRR low dropout linear regulator according to a first embodiment of the present invention;

4 is a circuit diagram of a low quiescent current high PSRR low dropout linear regulator according to a second embodiment of the present invention;

5 is a PSRR graph of a low quiescent current high PSRR low dropout linear regulator circuit according to an embodiment of the present invention;

6 is a circuit diagram of a low quiescent current high PSRR low dropout linear regulator according to a third embodiment of the present invention;

FIG. 7 is a graph showing changes in PSR of different resistors Rc according to an embodiment of the present invention.

Detailed ways

In order to make the technical solutions and the advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below through the accompanying drawings and embodiments.

3 is a circuit diagram of a low quiescent current high PSRR low dropout linear regulator circuit according to a first embodiment of the present invention. As shown in FIG. 3, the present invention provides a low quiescent current high PSRR low dropout linear regulator circuit including: an error amplifier 10, an adjustment component 20, a voltage dividing circuit 30, and a band enhancement circuit. 40.

The error amplifier 10 has three ports: a forward input terminal, a negative input terminal and an output terminal. The forward input terminal is connected to the input voltage VREF, and the negative input terminal is connected to the voltage VFB supplied from the voltage dividing circuit 30.

The adjustment component 20 can be a power transistor or a MOS power transistor. The adjusting component 20 acts as an LDO output transistor, and acts like a general linear regulator to adjust the output current by the magnitude of the voltage applied to its gate according to the magnitude of the load. In one example, the trim element 20 is implemented by a PMOS transistor with the source of the PMOS coupled to the VDD terminal, the gate coupled to the output of the error amplifier 10, and the drain providing the VOUT output. The PMOS operation provides an output voltage in its linear region.

Voltage divider circuit 30 is coupled between the VOUT output and ground and provides a divided output signal to the negative input of error amplifier 10. In one example, voltage divider circuit 30 is a series circuit of resistor R1 and resistor R2, and a series connection node between resistor R1 and resistor R2 provides a divided output signal.

The error amplifier 10 compares the divided output signal as the feedback voltage VFB with the input voltage VREF, and the difference between the two is amplified by the error amplifier 10 to control the voltage drop of the adjusting element 20, thereby stabilizing the output voltage. When the output voltage VOUT decreases, the difference between the feedback voltage VFB and the input voltage VDD increases, the drive current output from the error amplifier 10 increases, and the voltage drop of the adjustment element 20 decreases, thereby increasing the output voltage; conversely, if the output voltage VOUT exceeds The required set value, the front drive current output from the error amplifier 10 is reduced, thereby lowering the output voltage. During the power supply process, the output voltage VOUT correction is continuously performed, and the adjustment time is limited only by the loop reaction speed of the error amplifier 10 and the adjustment element 20. Because of the high gain of the low dropout linear regulator circuit to ensure good line and load regulation, it is able to attenuate the noise of the low frequency supply voltage.

In the present invention, a band enhancement circuit 40 is disposed in the conventional low dropout linear regulator. The band enhancement circuit 40 is connected at one end to the PMOS substrate in the adjustment element 20, and the other end is connected to the power supply voltage VDD. The power supply voltage VDD passes through the band enhancement circuit 40 and is input to the adjustment element 20. Thereby increasing the path through the band enhancement circuit 40 to the output, the band enhancement circuit 40 generates an additional zero point, which can be improved by designing the frequency value of the zero point to eliminate the noise of the power supply voltage VDD at a certain frequency point. The PSRR of the frequency. The significance of the band enhancement circuit 40 is that a frequency zero is inserted between the power supply and the LDO output to filter out signals from the power supply near the frequency; from the power supply to the output, the power supply is not DC but high frequency. The AC signal is filtered out, which is equivalent to the band resistance enhancement (or broadening effect).

4 is a circuit diagram of a low quiescent current high PSRR low dropout linear regulator circuit according to a second embodiment of the present invention. As shown in FIG. 4, in the circuit provided by the embodiment of the present invention, the band enhancement circuit 40' includes a resistor Rc, a capacitor Cc, and a gain buffer 41.

One end of the resistor Rc and the capacitor Cc are connected to the substrate of the PMOS transistor in the adjustment element 20, and the other end of the resistor Rc is connected to the power supply voltage VDD; the other end of the capacitor Cc is connected to the source of the PMOS transistor in the gain buffer 41. The gate of the PMOS transistor in the gain buffer 41 is connected to the drain output terminal (ie, the output voltage VOUT) of the PMOS transistor in the adjustment element 20, the drain of the PMOS transistor in the gain buffer 41 is grounded, and the substrate is connected to VDD. The gain buffer 41 has two functions, one is the influence of the isolation capacitor Cc on the output terminal, because the output terminal does not directly see Cc; the other function is because the resistor Rc, the capacitor Cc channel output is high impedance state (because it is the Cc end) Must be superimposed to the output through the buffer so as not to affect the position of the added notch frequency zero point, otherwise the zero position is uncontrollable or invalid.

Let VDD = Vac + Vdc, where Vac is a small AC signal, equivalent to fluctuations in the supply voltage, Vdc is the DC voltage. If Vac = 0, Vx = VDD = Vdc, the band enhancement circuit 40 has no effect at this time, and its PSRR is the same as in the conventional low dropout linear regulator. The PSRR at this time is:

If Vac = Va · sin (2π · f · t), two signals Vy and Vz are superimposed on the output terminal VOUT. Wherein, the signal Vz is generated through path 1 (notch loop notch loop, that is, from the power supply voltage VDD through the output terminal of the adjusting component 20); the signal Vy is passed through the path 2 (ie, the enhancement loop, from the power supply voltage VDD via the RcCc and the gain) Buffer 41 to output) is generated. In FIG. 4, Vx is the low pass filtered voltage of Vac, Va is the voltage after Vx is phase shifted by 90 degrees, and Va is coupled to Vy through gain buffer 41.

The signals Vy and Vz superimposed on the output VOUT will cancel or partially cancel each other at a specific frequency Fz, which is determined by:

According to Fz, Rc can be adjusted to shift the notch frequency position to provide additional attenuation at that frequency, such as attenuating 1 kHz noise present on the supply voltage VDD, thereby increasing the PSRR near that frequency, which helps improve The performance of low dropout linear regulators in different application scenarios.

Therefore, without changing the zero pole in the conventional low dropout linear regulator circuit, the noise of the power supply voltage VDD at a certain frequency Fz is eliminated by introducing an extra zero to increase the PSRR at the frequency point and its vicinity.

Assumed

After increasing the second path from the power supply VDD to the output, the PSRR is:

PSRR=A(s)·(1+sRcCc) (3)

That is, the resistance Rc of the band enhancement circuit 40 and the capacitor Cc constitute an additional zero in the frequency domain, which can be used to cancel noise at the frequency and its nearby frequencies. Since the product RcCc of the resistor Rc and the capacitor Cc is usually large, a gain buffer 41 is added to prevent the capacitor Cc from being directly connected to the load, which has no effect on the zero-pole loop of the normal path of the original low-dropout linear regulator.

Of course, since the PMOS transistor in the trimming element 20 exhibits a back gate effect at different frequencies, A(s) is affected when the resistor Rc is larger, but we are interested in rejecting the power supply voltage VDD at certain frequency points. Noise, rather than eliminating the supply voltage VDD noise (wideband noise) over the entire frequency range, so a single point of cancellation of the supply voltage VDD noise is achieved by adjusting RcCc.

FIG. 5 is a PSRR graph of a low quiescent current high PSRR low dropout linear regulator circuit according to an embodiment of the present invention. As shown in FIG. 5, line 1 is the PSRR value of the prior art low dropout linear regulator at different frequencies. The PSRR value starts to change at the frequency Z=BW, and the PSRR value at the frequency higher than the BW decreases significantly; Line 2 is the PSRR value at different frequencies using the low dropout linear regulator of the embodiment of the present invention. The PSRR value is maintained at a stable value at BW and at a frequency point Z'x greater than BW, and the PSRR value begins to change at frequencies greater than Z'x.

6 is a circuit diagram of a low quiescent current high PSRR low dropout linear regulator circuit according to a third embodiment of the present invention. As shown in FIG. 6, the difference from the foregoing embodiment is that the current source 42 is further included in the band enhancement circuit 40".

A current source 42 is coupled between the VDD terminal and the source of the PMOS transistor in the gain buffer 41 to provide a constant current to the drain of the PMOS transistor in the gain buffer 41.

The current source 42 is for the gain buffer 41 to independently adjust the DC operating point and the bandwidth. Since the RcCc can only generate a 90-degree phase shift, by adjusting the bandwidth of the gain buffer 41, an additional phase shift can be added to achieve better. Power supply noise cancellation effect.

FIG. 7 is a graph showing changes in PSR of different resistors Rc according to an embodiment of the present invention. As shown in Figure 7, it can be seen in the simulation experiment that the PSRR can be adjusted by the resistor Rc. For different resistances, the frequency position of the zero point varies within a certain range, showing different suppression effects at different frequencies.

The band enhancement circuit 40 generates an additional zero point, which will eliminate or partially cancel the noise at a certain frequency point, obtain the frequency Fz of the additional zero point according to the formula (2), and adjust the Rc to move the notch frequency position, which can be used to cancel a certain The frequency of these specific interfering signals is used to increase the PSRR at this frequency point and its vicinity, helping the application of low dropout linear regulators in different scenarios. For example, in GSM system 217Hz, VDD noise is usually relatively large, we hope that the low dropout linear regulator provides the largest noise reduction near this frequency point.

The specific embodiments of the present invention have been described in detail with reference to the preferred embodiments of the present invention. All modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims

A low dropout linear regulator circuit comprising:

An error amplifier (10) for amplifying an error of a signal of a forward input terminal and a negative input terminal; wherein the signal at the forward input terminal is a reference signal;

An adjustment component (20) comprising a first PMOS transistor; wherein a gate of the first PMOS transistor is coupled to an output of the error amplifier (10); a drain of the first PMOS transistor provides a circuit output of an output voltage;

a voltage dividing circuit (30) connected between the drain of the first PMOS transistor and the ground for providing a voltage dividing signal to the negative input terminal of the error amplifier;

a band enhancement circuit (40) coupled between the substrate of the adjustment element (20) and a supply voltage terminal; the band enhancement circuit (40) forming a voltage supply terminal to an output terminal Unlike the second path through the first path of the adjustment element, an additional zero in the frequency domain is thereby generated.
The low dropout linear regulator circuit according to claim 1, wherein said band enhancement circuit (40) comprises: a first resistor (Rc), a capacitor (Cc), and a gain buffer (41); The gain buffer (41) includes a second PMOS transistor;

The first resistor is coupled between a substrate of the first PMOS transistor and a supply voltage terminal; the capacitance is coupled between a substrate of the PMOS transistor and a source of the second PMOS transistor; A gate of the second PMOS transistor is coupled to a drain output of the first PMOS transistor; the first resistor and the capacitor form the additional zero in the frequency domain.
The low dropout linear regulator circuit of claim 2 wherein the frequency of the additional zero is:

Where Rc is the resistance of the first resistor and Cc is the capacitance of the capacitor.
The low-dropout linear regulator circuit according to claim 2, wherein after the noise of the power supply voltage is cancelled at one frequency point, the PSRR of the frequency point and its nearby frequency is:

PSRR=A(s)□(1+sRcCc);

among them,
VOUT is the output voltage and VDD is the supply voltage.
The low dropout linear regulator circuit of claim 2, wherein said band enhancement circuit (40) further comprises a current source (42) coupled between the supply voltage terminal and the source of the second PMOS transistor The current of the current source flows from the power supply voltage terminal to the source of the second PMOS transistor.
A low dropout linear regulator circuit according to claim 1, wherein said voltage dividing circuit (30) comprises a second resistor (R1) and a third resistor (R2) connected in series.