WO2019153308A1

WO2019153308A1 - Ripple optimization control method for pfc circuit output voltage and related circuit

Info

Publication number: WO2019153308A1
Application number: PCT/CN2018/076332
Authority: WO
Inventors: 唐疑军; 许明军; 宋安国; 刘晓红; 杨冬梅; 刘鹏飞; 吴壬华
Original assignee: 深圳欣锐科技股份有限公司
Priority date: 2018-02-11
Filing date: 2018-02-11
Publication date: 2019-08-15
Also published as: CN109075697A; CN109075697B

Abstract

Disclosed in an embodiment of the present application are a ripple optimization control method for power factor correction (PFC) circuit output voltage and a related circuit; the ripple optimization control circuit comprises a PFC circuit, an energy compensation circuit and a voltage current sampling circuit that are connected in sequence; the energy compensation circuit is converted into a step-down circuit when the input voltage of the PFC circuit is greater than a target threshold or the phase of the input voltage of the PFC circuit is within a set phase interval; the energy compensation circuit is converted into a step-up circuit when the input voltage of the PFC circuit is lower than the target threshold or the phase of the input voltage of the PFC circuit is not in the set phase interval. The output voltage ripple of the PFC circuit may be effectively reduced by means of the ripple optimization control circuit.

Description

Ripple optimization control method and related circuit of PFC circuit output voltage

Technical field

The present application relates to the field of power electronic control, and in particular to a ripple optimization control method and related circuit for a PFC circuit output voltage.

Background technique

Since the DC voltage is generally generated by the AC power supply through rectification and voltage regulation, it is inevitable that some AC components are present in the DC stability. The AC component superimposed on the DC stability is called the ripple. wave. The composition of the ripple is more complicated. Its shape is generally a harmonic similar to a sine wave with a frequency higher than the power frequency, and the other is a pulse wave with a narrow width. The requirements for ripple are different for different occasions. Since the generated ripple will adversely affect the power quality of the DC side, the stability of the system, and the service life of the DC side equipment, the power supply must have sufficient filtering measures to limit the ripple to a certain range. .

Therefore, the Power Factor Correction (PFC) circuit has been widely used, and the introduction of PFC circuits in electronic power products can improve the utilization efficiency of electric energy. Specifically, in order to smooth the voltage ripple, one or more capacitors are usually disposed at the DC output end of the PFC circuit to filter the ripple. However, in order to obtain a better filtering effect, it is necessary to increase the capacitance, which may result in the entire rectifier circuit. As the volume increases, the power density of the system is greatly reduced. However, the capacitance is too small, the filtering effect is not obvious, and the ripple amplitude of the DC voltage outputted by the PFC circuit is still high.

Summary of the invention

The embodiment of the present application provides a ripple optimization control method and a related circuit for an output voltage of a PFC circuit, which can effectively reduce the output voltage ripple of the PFC circuit.

A first aspect of the embodiments of the present application provides a ripple optimization control circuit, including a PFC circuit, an energy compensation circuit, and a voltage current sampling circuit connected in sequence;

In a case where an input voltage of the PFC circuit is greater than a target threshold or a phase of an input voltage of the PFC circuit is in a set phase interval, the energy compensation circuit is converted into a step-down circuit, and the step-down circuit is configured to reduce An output voltage of the PFC circuit; the energy compensation circuit in a case where an input voltage of the PFC circuit is lower than the target threshold or a phase of an input voltage of the PFC circuit is not in the set phase interval Converted to a boost circuit for boosting the output voltage of the PFC circuit.

In an optional implementation manner, an input voltage of the PFC circuit is an alternating current voltage, and a first output end and a second output end of the PFC circuit are respectively connected to the first input end and the second end of the energy compensation circuit The input end is connected, and the first output end and the second output end of the energy compensation circuit are respectively connected to the first input end and the second input end of the voltage current sampling circuit;

The energy compensation circuit includes: a first switch tube, a second switch tube, an inductor, a capacitor, and a controller;

a drain of the first switch tube is connected to a first output end of the PFC circuit and a first input end of the voltage current sampling circuit, and a source of the first switch tube is connected to a first end of the inductor, a second end of the capacitor is connected to the first end of the capacitor, a second end of the capacitor is connected to a second input end of the voltage current sampling circuit, and a drain of the second switch tube is connected to the inductor a first end and a source of the first switch tube, a source of the second switch tube is connected to a second output end of the PFC circuit and a second input end of the voltage current sampling circuit, the controller The control terminal is respectively connected to the gate of the first switch tube and the gate of the second switch tube;

The controller is configured to control on and off of the first switch tube and the second switch tube according to an input voltage of the PFC circuit or according to an input voltage phase of the PFC circuit to control the The energy compensation circuit is switched to a boost circuit or a buck circuit.

In an optional implementation manner, the PFC circuit further includes a detecting module, configured to detect a phase of an input voltage of the PFC circuit, and pass the output end of the detecting module to the control Transmitting the detected phase of the input voltage;

The controller is specifically configured to send a first pulse width modulation signal to the first switch tube according to an input voltage of the PFC circuit detected by the detecting module or an input voltage phase of the PFC circuit to control the Turning on and off of the first switch tube, and sending a second pulse width modulation signal to the second switch tube to control turning on and off of the second switch tube;

The first pulse width modulation signal and the second pulse width modulation signal are a pair of complementary driving waveforms.

In an alternative implementation, the PFC circuit is a single phase voltage type pulse width modulation rectification circuit.

In an optional implementation manner, the detecting module is a phase locked loop, and the detecting module is configured to detect a phase of the input voltage, and send the detected phase of the input voltage to the controller.

In an optional implementation manner, the first switch tube and the second switch tube are both insulated gate bipolar transistors or power field effect transistors.

A second aspect of the embodiments of the present application provides a ripple optimization control method for a PFC circuit output voltage, which is applied to a ripple optimization control circuit, and the ripple optimization control circuit includes a PFC circuit, an energy compensation circuit, and a voltage current sampling sequentially connected. Circuit, the method comprising:

The energy compensation circuit is converted to a step-down circuit to reduce an output voltage of the PFC circuit if an input voltage of the PFC circuit is greater than a target threshold or a phase of an input voltage of the PFC circuit is within a set phase interval The energy compensation circuit is converted to a boost circuit, and the input voltage of the PFC circuit is lower than the target threshold or the phase of the input voltage of the PFC circuit is not in the set phase interval. The output voltage of the PFC circuit.

a drain of the first switch tube is connected to a first output end of the PFC circuit and a first input end of the voltage current sampling circuit, and a source of the first switch tube is connected to a first end of the inductor, a second end of the capacitor is connected to the first end of the capacitor, a second end of the capacitor is connected to a second input end of the voltage current sampling circuit, and a drain of the second switch tube is connected to the inductor a first end and a source of the first switch tube, a source of the second switch tube is connected to a second output end of the PFC circuit, and a second input end of the voltage current sampling circuit, the controller is controlled The terminals are respectively connected to the gate of the first switch tube and the gate of the second switch tube;

The controller controls on and off of the first switch tube and the second switch tube according to an input voltage of the PFC circuit or according to an input voltage phase of the PFC circuit to control the energy compensation circuit Switch to a boost circuit or a buck circuit.

In an optional implementation manner, the first switch tube and the second switch tube are both insulated gate bipolar transistors or power FETs.

The controller sends a first pulse width modulation signal to the first switch tube to control the first switch according to an input voltage of the PFC circuit detected by the detecting module or an input voltage phase of the PFC circuit. Turning on and off of the tube, and transmitting a second pulse width modulation signal to the second switch tube to control turning on and off of the second switch tube;

The first pulse width modulation signal and the second pulse width modulation signal are a pair of complementary drive waveforms.

It can be seen from the above technical solution that the embodiment of the present application passes the case where the input voltage of the PFC circuit is greater than a target threshold or the phase of the input voltage of the PFC circuit is in a set phase interval, that is, the PFC circuit at this time. Where the output voltage is in the interval of the peak of the voltage ripple, the energy compensation circuit is switched to the step-down circuit to reduce the output voltage; the input voltage of the PFC circuit is lower than the target threshold or When the phase of the input voltage of the PFC circuit is not in the set phase interval, that is, when the output voltage of the PFC circuit is in the interval of the voltage ripple trough period, the energy compensation circuit is switched to the boost circuit. By increasing the output voltage, the output voltage ripple can be effectively reduced.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background art, the drawings to be used in the embodiments of the present application or the background art will be described below.

1 is a schematic diagram of a common rectifier circuit provided by an embodiment of the present application;

2 is a waveform comparison diagram of a single-phase AC voltage before and after rectification filtering according to an embodiment of the present application;

3 is a schematic diagram of a phase setting interval of an output voltage ripple peak period and a low valley period according to an embodiment of the present application;

4 is a schematic diagram of a ripple optimization control circuit according to a second embodiment of the present application;

FIG. 5 is a schematic diagram of a ripple optimization control circuit according to a third embodiment of the present application; FIG.

6 is a schematic diagram of a ripple optimization control circuit including a detection module according to a fourth embodiment of the present application;

7 is a schematic diagram of a complementary driving waveform provided by another embodiment of the present application;

FIG. 8 is a schematic diagram of a software phase locking principle according to another embodiment of the present application.

Detailed ways

The embodiments of the present application are described below in conjunction with the accompanying drawings in the embodiments of the present application.

A rectifier circuit is a converter that converts AC power into DC power. The rectifier circuit can be divided into single-phase, three-phase, and six-equal according to the number of phases of the input power supply. Usually, single-phase rectification is applied to low-power applications, and three-phase and multi-phase rectification are used in high-power applications. The rectifier circuit is classified into a half-wave rectifier circuit, a full-wave rectifier circuit, and a bridge rectifier circuit according to the type. The rectifying circuit in the embodiment of the present application may be a single-phase bridge rectifying circuit, a three-phase bridge rectifying circuit, or another type of rectifying circuit, which is not limited in the embodiment of the present application.

The power factor in Power Factor Correction (PFC) refers to the relationship between the effective power and the total power consumption (apparent power), that is, the effective power divided by the total power consumption (apparent power). ratio. Basically, the power factor can measure the extent to which power is effectively utilized. When the power factor is larger, it means that the power utilization rate is higher. The power factor is a parameter used to measure the power efficiency of a consumer, and the low power factor is a low power factor. The technique for increasing the power factor of a powered device is called power factor correction. The principle of the PFC circuit can be understood as a special circuit to adjust the waveform of the current to compensate for the phase difference between the current and the voltage. In the above rectifier circuit, the PFC circuit is commonly used for rectification to output a DC voltage.

1 is a schematic diagram of a common rectifier circuit. As shown in FIG. 1 , the rectifier circuit includes an AC power source 01, a first inductor 02, a second inductor 03, a first switch transistor 041, a second switch transistor 042, and a third switch. The tube 043 and the fourth switch tube 044, the DC side circuit includes a capacitor 05 and a third inductor 06, and the DC side circuit can obtain a DC voltage D, wherein the first switch tube 041, the second switch tube 042, the third switch tube 043 and the first The four switch tubes 044 can be respectively turned on and off under the action of the applied pulse width modulation signal.

Figure 2 is a simulation diagram of the pulsating DC output voltage and the sinusoidal AC voltage waveform obtained after the sinusoidal AC current is shown in Figure 1. The waveform in the upper part of Figure 2 is the single-phase voltage waveform of the grid and the waveform of the lower half. For the waveform of the rectification and storage capacitor (capacitor 05 in Figure 1) through the PFC circuit, it can be seen from Figure 2 that after charging or discharging the storage capacitor, the ripple of the output voltage is still large, that is, the output The difference between the peak and the valley of the voltage is large, and the voltage waveform is not smooth.

Figure 3 is a schematic diagram of the phase setting interval of the output voltage ripple peak period and trough period. The ripple of the input voltage of the PFC circuit (the upper half of Fig. 3) and the output voltage of the PFC circuit can be seen from Fig. 3 (Fig. 3 Corresponding relationship of the lower half), taking a period (0 to 360°) of the voltage waveform as an example, setting a period of the input voltage phase of 50° to 120° and 230° to 300°, the output The waveform of the voltage is convex upward, which is the peak period of the output voltage ripple; in contrast, the phase of the input voltage is set to be in the range of 0° to 49°, 121° to 229°, and 301° to 360°, and the output is The waveform of the voltage is concave downward, which is the voltage ripple trough period. The waveform of the output voltage has the same voltage ripple peak period and voltage ripple trough period in each period. In order to reduce the voltage ripple and smooth the voltage waveform, it is necessary to solve the problem of the peak voltage ripple period, that is, the voltage is reduced in the convex section on the waveform of the output voltage, and the voltage is raised in the concave section under the waveform of the output voltage to achieve "sharpening". The effect of peak filling valley can obtain a smoother DC voltage waveform, which is to achieve the purpose of reducing voltage ripple.

The white arrows in Figure 3 indicate the ripple peak period and ripple trough period set during a voltage sine wave period. It can be deduced from FIG. 3 that when the phase of the DC output voltage is in the target interval, the amplitude of the ripple of the DC output voltage is greater than the set value; and the DC output is not in the case where the phase of the DC output voltage is not in the target interval. The amplitude of the voltage ripple is not greater than the set value. Those skilled in the art will appreciate that due to the requirement of the volume of the rectifier circuit, the capacitance of the DC bus cannot be increased without limitation, and a capacitor of a small capacity is used, so that the ripple of the DC power source cannot be well filtered out. Therefore, there is a need to study a method of reducing the ripple of the output voltage without increasing the volume of the rectifier circuit.

As shown in FIG. 4, the embodiment of the present application provides a ripple optimization control circuit, where the ripple optimization control circuit includes: a PFC circuit 100, an energy compensation circuit 200, and a voltage current sampling circuit 300 connected in sequence;

Specifically, the first output end 101 and the second output end 102 of the PFC circuit 100 are respectively connected to the first input end 201 and the second input end 202 of the energy compensation circuit 200, and the first output end of the energy compensation circuit 200. The second output terminal 203 and the second output terminal 204 are connected to the first input terminal 301 and the second input terminal 302 of the voltage current sampling circuit 300, respectively.

Specifically, in the case where the input voltage of the PFC circuit 100 is greater than the target threshold or the phase of the input voltage of the PFC circuit 100 is in the set phase interval, the energy compensation circuit 200 can be converted into a buck circuit, and the buck circuit can be used for The output voltage of the PFC circuit 100 is lowered.

In a case where the input voltage of the PFC circuit 100 is lower than the target threshold or the phase of the input voltage of the PFC circuit 100 is not in the set phase interval, the energy compensation circuit 200 may be converted into a boost circuit, the boost circuit It can be used to boost the output voltage of the PFC circuit 100.

The voltage and current sampling circuit mentioned in the embodiment of the present application can be understood as a sampling detection module of the output voltage and the output current of the PFC circuit. The voltage can be sampled by the voltage and current sampling module to stabilize the output voltage, and the current is sampled to increase the feedforward control of the circuit.

In the embodiment of the present application, the energy compensation circuit 200 can be understood as a buck-boost conversion circuit, which can operate in a BUCK step-down circuit during a peak voltage ripple period, and absorbs the peak energy of the voltage ripple, thereby reducing the output voltage of the PFC circuit. It is also possible to operate with the BOOST boost circuit during the voltage ripple period to release the energy absorbed by the energy during the peak voltage ripple, thereby increasing the output voltage of the PFC circuit.

In the embodiment of the present application, an energy compensation circuit is added on the basis of the rectification circuit shown in FIG. 1 , and the energy compensation circuit occupies less space and has low cost. According to the corresponding relationship between the input voltage and the output voltage of the PFC circuit, Where the input voltage of the PFC circuit is greater than a target threshold or when the phase of the input voltage of the PFC circuit is in a set phase interval, that is, when the output voltage of the PFC circuit is in a range of a peak voltage ripple period, The energy compensation circuit is switched to a buck circuit to reduce the output voltage; an input voltage of the PFC circuit is lower than the target threshold or a phase of an input voltage of the PFC circuit is not at the set phase In the case of the section, that is, when the output voltage of the PFC circuit is in the section of the voltage ripple trough period, the energy compensation circuit is switched to the booster circuit to increase the output voltage. Compared with the method of using DC capacitor filtering, the ripple optimization control circuit can effectively reduce the output voltage ripple of the PFC circuit.

In an optional implementation manner, as shown in the ripple optimization control circuit shown in FIG. 5, the input voltage of the PFC circuit 100 is an alternating voltage, and the first output end 101 and the second output end 102 of the PFC circuit 100 respectively and the energy The first input terminal 201 and the second input terminal 202 of the compensation circuit 200 are connected. The first output end 203 and the second output end 204 of the energy compensation circuit 200 are respectively connected to the first input end 301 and the second input of the voltage current sampling circuit 300. End 302 is connected. The energy compensation circuit 200 includes:

The first switch tube 10, the second switch tube 20, the inductor 30, the capacitor 40 and the controller 50;

The drain 11 of the first switch 10 is connected to the first output end 101 of the PFC circuit 100 and the first input end 301 of the voltage and current sampling circuit 300. The source 12 of the first switch 10 is connected to the first end 31 of the inductor 30. The second end 32 of the inductor 30 is connected to the first end 41 of the capacitor 40, the second end 42 of the capacitor 40 is connected to the second input end 302 of the voltage current sampling circuit 300, and the drain 21 of the second switching tube 20 is connected to the second end of the inductor 30. One end 31 and the source 12 of the first switch 10, the source 22 of the second switch 20 is connected to the second output 102 of the PFC circuit 100 and the second input 302 of the voltage and current sampling circuit 300, the controller 50 The control terminal 51 and the control terminal 52 are respectively connected to the gate 13 of the first switching transistor 10 and the gate 23 of the second switching transistor 20;

The controller 50 can be used to control the on and off of the first switch 10 and the second switch 20 according to the input voltage of the PFC circuit 100 or according to the input voltage phase of the PFC circuit 100 to control the energy compensation circuit. 200 switches to a boost circuit or a buck circuit.

Specifically, the controller 50 may control the on and off of the first switch 10 and control the on and off of the second switch 20 to make the energy compensation circuit if the input voltage is greater than the target threshold. 200 is converted into the above-mentioned step-down circuit; the controller 50 can control the on and off of the first switch 10 and control the on and off of the second switch 20 when the input voltage is less than the target threshold. The energy compensation circuit 200 is converted to a boost circuit.

Optionally, the controller 50 can control the on and off of the first switch 10 and control the on and off of the second switch 20 when the phase of the input voltage is in the set phase interval. So that the energy compensation circuit 200 is converted into the above-mentioned step-down circuit; the controller 50 can control the on and off of the first switch 10 and the control when the phase of the input voltage is not in the set phase interval. The two switching tubes 20 are turned on and off to convert the energy compensation circuit 200 into a boosting circuit.

The target threshold and the set phase interval may be preset, or may be set by the user as needed. For example, the set phase interval may be 50° to 120° and 230° to 300°. The above target threshold may be 150V, 200V, 225V, or the like. The controller may control the full control device in the ripple optimization control circuit, or may only control the full control device in the energy compensation circuit.

When the first switch 10 is closed and the second switch 20 is turned off, the inductor 30 and the capacitor 40 in the energy compensation circuit 200 can absorb the energy of the peak voltage ripple. As shown in FIG. 6, the voltage of the first output terminal 101 of the PFC circuit 100 is positive, and the voltage of the second output terminal 102 is negative. It can be seen that when the first switch tube 10 is closed, the second switch tube 20 is turned off, in the figure. The arrow a indicates the current flow direction. At this time, it can be understood that the inductor 30 and the capacitor 40 are charged. The inductor 30 and the capacitor 40 can absorb the energy of the voltage ripple peak period, that is, the energy compensation circuit 200 is a step-down circuit, and the PFC can be lowered at this time. The output voltage of circuit 100.

In contrast, when the second switch tube 20 is closed and the first switch tube 10 is turned off, the inductor 30 and the capacitor 40 in the energy compensation circuit 200 can release energy absorbed during the peak of the voltage ripple. As shown in FIG. 6, it can be seen that when the second switch tube 20 is closed, the first switch tube 10 is turned off, and the arrow b in the figure indicates the current flow direction, and the inductor 30 and the capacitor 40 can be released during the peak of the voltage ripple absorption. The energy, that is, the energy compensation circuit is a booster circuit, at which time the output voltage of the PFC circuit 100 can be increased.

It can be understood that the energy compensation circuit can have two working states. In the peak of the voltage ripple, the BUCK step-down circuit charges the storage capacitor and absorbs energy; during the voltage ripple period, it is the BOOST boost circuit and the capacitor energy. Filling the valley to the DC voltage bus, releasing the energy, thus playing the role of “shaving the peak and filling the valley”, the DC voltage output terminal can obtain a smoother DC voltage waveform, which can finally achieve the purpose of reducing the voltage ripple.

In the embodiment of the present application, the ripple voltage can be effectively reduced by converting the operating state of the energy compensation circuit.

6 is a schematic diagram of a ripple optimization control circuit, and FIG. 6 is obtained based on the ripple optimization control circuit shown in FIG. 5. Optionally, the PFC circuit 100 includes a detection module 60, and the detection module 60 For detecting the phase of the input voltage of the PFC circuit, the output 61 of the detection module 60 is connected to the input 53 of the controller 50;

The detecting module 60 can detect the phase of the input voltage of the PFC circuit 100 and send the phase of the detected input voltage to the controller 50 through the output terminal 61;

Optionally, the detecting module 60 can detect the input voltage of the PFC circuit 100 and send the detected input voltage to the controller 50 through the output terminal 61;

The controller 50 can be specifically configured to send a first pulse width modulation signal to the first switch tube 10 to control the on and off of the first switch tube 10, and send a second pulse width modulation signal to the second switch tube 20 to Controlling the turning on and off of the second switching tube 20;

The first pulse width modulation signal of the first switching transistor 10 and the second pulse width modulation signal of the second switching transistor 20 are a pair of complementary driving waveforms. The complementary driving waveform refers to that the first pulse width modulation signal is opposite to the voltage level of the driving waveform of the second pulse width modulation signal in one cycle, for example, as shown in FIG. 7, the first pulse width modulation signal The driving waveform A of the driving waveform A and the driving waveform B of the second pulse width modulation signal are both rectangular waves, and the complementary waveforms of the A and B waveforms can be understood as the second pulse if the driving waveform of the first pulse width modulation signal is a high voltage at the same time. The driving waveform of the width modulation signal is a low voltage, and if the driving waveform of the first pulse width modulation signal is a low voltage, the driving waveform of the second pulse width modulation signal is a high voltage.

The controller 50 controls the on and off of the first switch 10 and the second switch 20. For details, refer to the detailed description in the corresponding embodiment of the ripple optimization control circuit shown in FIG. No longer.

In the embodiment of the present application, the controller can send the pulse width modulation signal to the first switch tube and the second switch tube to quickly realize the conversion of the working state of the buck-boost conversion circuit, which is simple to implement.

In an optional implementation manner, the PFC circuit 100 is a single-phase voltage type pulse width modulation rectifier circuit. Pulse Width Modulation (PWM) is an analog control method that modulates the bias of the transistor base or MOS transistor gate according to the change of the corresponding load to change the on-time of the transistor or MOS transistor. Realize the change of the output of the switching regulator power supply. This way, the output voltage of the power supply can be kept constant when the operating conditions change, which is a very effective technique for controlling the analog circuit by using the digital signal of the microprocessor.

In an optional implementation manner, the detecting module 60 is a phase locked loop, and the detecting module 60 is configured to detect a phase of the output voltage, and send the detected phase of the output voltage to the controller 50.

The phase locked loop (PLL) is a typical feedback control circuit that can control the frequency and phase of the internal oscillation signal of the loop by using the externally input reference signal to realize the automatic tracking of the input signal frequency to the input signal frequency. The path is generally composed of three parts, mainly including a phase detector, a low pass filter and a voltage controlled oscillator, wherein the phase detector can detect the phase difference from the power grid; the low pass filter can detect the DC of the reaction phase difference. Component; voltage-controlled oscillator, which can change the oscillation frequency and phase according to the DC component of the phase difference of the detected reaction, so that the DC component of the reaction phase difference tends to zero, completing the phase locking; and the frequency-phase feedback channel can be composed of the frequency divider. .

There are two types of phase-locked loops: hardware phase-locked loops and software phase-locked loops (SPLLs). The hardware phase-locked loop tracks and compares a certain phase voltage through a phase-locked loop chip, and outputs a signal with a constant phase difference equal to its frequency to achieve phase locking. The method has the advantages of simple and easy operation, but when the three-phase voltage is unbalanced, obtaining the three-phase phase information from one phase voltage will greatly affect the phase locking accuracy.

Optionally, the detecting module 60 can determine the phase of the input voltage by means of a software phase-locked loop, and the software phase-locked loop has an online modification control algorithm, and does not need to change the advantages of the hardware circuit. The design methods of software phase-locked loop mainly include: zero-crossing comparison method, least squares method and instantaneous reactive power theory method. The zero-crossing comparison phase-locked loop is consistent with the principle of the traditional hardware phase-locked loop. The difference is that the compared square wave signal is digitally calculated to obtain the frequency and phase information, so the phase-locking accuracy is low when the voltage is unbalanced. The least squares method has a fast dynamic response and can accurately lock the phase of the positive sequence voltage, but the harmonic suppression is poor. The software phase-locked loop based on instantaneous reactive power theory mainly integrates the three-phase voltage through software programming method, so as to accurately obtain the phase information of various distortion voltages.

As shown in Figure 8, the schematic diagram of the software phase-locking can sample the AC voltage to the Digital Signal Processing (DSP), put the sampled values into the corresponding array through the software method, and then lock the phase through the SPLL. To determine the phase of the voltage. SPLL can be understood as the phase of the voltage obtained by mathematical operation based on the correspondence between the triangular wave voltage and the sinusoidal voltage. For example, the triangular wave voltage in the figure appears as a straight line, and the highest point voltage indicated on the straight line is 6.28V, and the voltage value on the straight line and the sinusoidal voltage. The voltage phase of the waveform is corresponding, or it can be said to be in a fixed proportional relationship. The voltage value can be obtained by sampling the voltage, and then the phase corresponding to the voltage can be calculated. For example, the known voltage is zV (also the voltage value at a certain point on the line). ), then its corresponding voltage phase = z / 6.28 * 360 °. Specifically, the grid voltage signal can be cyclically sampled in a preset period of the voltage signal wave, and an array of length L is set according to the frequency and sampling frequency of the grid voltage; and the first variable S1 and the second are set. a variable S2, wherein S2=S1+1; generating a first signal wave Ua according to the first variable S1, and generating a second signal wave Ub according to the second variable S2; and the first signal wave Ua and the second signal The wave Ub performs voltage Park transformation to achieve phase locking, and the phase locking method has a small calculation amount and high reliability.

The embodiment of the present application can accurately determine the phase of the input voltage by the principle of the phase locked loop.

Insulated Gate Bipolar Transistor (IGBT) has high operating frequency, low required driving power, low switching loss and fast switching speed, which can make the DC buck-boost circuit quickly convert between buck and boost. . The power field effect transistor has a fast switching speed, a simple driving circuit, and a high operating frequency.

In the embodiment of the present application, the first switch tube and the second switch tube both use an insulated gate bipolar transistor or a power field effect transistor, and the switching speed is fast, so that the buck-boost conversion circuit can quickly realize the step-down circuit and the boost circuit. Conversion between.

The embodiment of the present application further provides a ripple optimization control method for a PFC circuit output voltage, where the ripple optimization control circuit includes a PFC circuit, an energy compensation circuit, and a voltage current sampling circuit connected in sequence; the method includes:

In a case where the input voltage of the PFC circuit is greater than a target threshold or the phase of the input voltage of the PFC circuit is in a set phase interval, the energy compensation circuit is converted into a step-down circuit to reduce an output voltage of the PFC circuit; When the input voltage of the circuit is lower than the target threshold or the phase of the input voltage of the PFC circuit is not within the set phase interval, the energy compensation circuit is converted into a booster circuit to increase the output voltage of the PFC circuit.

This method can be applied to the ripple optimization control circuit in the embodiment shown in FIG.

In the embodiment of the present application, an energy compensation circuit is added on the basis of the PFC circuit, and the energy compensation circuit occupies less space and has low cost, and the ripple voltage can be effectively reduced by the above method.

In an optional implementation manner, the input voltage of the PFC circuit is an AC voltage, and the first output end and the second output end of the PFC circuit are respectively connected to the first input end and the second input end of the energy compensation circuit. The first output end and the second output end of the energy compensation circuit are respectively connected to the first input end and the second input end of the voltage current sampling circuit;

The energy compensation circuit includes: a first switch tube, a second switch tube, an inductor, a capacitor element, and a controller;

The drain of the first switch tube is connected to the first output end and the first input end of the voltage current sampling circuit, the source of the first switch tube is connected to the first end of the inductor, and the second end of the inductor is connected to the capacitor The first end of the capacitor is connected to the second input end of the voltage and current sampling circuit, and the drain of the second switch tube is connected to the first end of the inductor and the source of the first switch tube. a source of the second switch is connected to the second output end of the PFC circuit and a second input end of the voltage current sampling circuit, and the control end of the controller is respectively connected to the gate of the first switch tube and the gate of the second switch tube pole;

The controller may control the lead of the first switch tube and the second switch tube according to whether the input voltage of the PFC circuit is greater than the target threshold value or according to whether the input voltage phase of the PFC circuit is in the set phase interval. Turning on and off to control the above energy compensation circuit to switch to a boost circuit or a buck circuit.

Optionally, the first switch tube and the second switch tube may be insulated gate bipolar transistors or power field effect transistors.

The method can be applied to the ripple optimization control circuit shown in FIG. 5 . For details, refer to the specific description of the corresponding embodiment of the ripple optimization control circuit shown in FIG. 5 , and details are not described herein again.

In an optional implementation manner, the PFC circuit is a single-phase voltage type PWM rectifier circuit. A circuit consisting of a live line and a zero line is called a single-phase circuit. For example, the single-phase voltage in China is generally 220V.

In an optional implementation manner, the PFC circuit further includes a detection module, configured to detect a phase of an input voltage of the PFC circuit, and send a detection to the controller through an output end of the detection module. The phase of the input voltage to which it is obtained;

Optionally, the detecting module can detect an input voltage of the PFC circuit and send the detected input voltage to the controller;

The controller may send a pulse width modulation signal to the first switch tube to control the on and off of the first switch tube according to the input voltage of the PFC circuit detected by the detecting module or the input voltage phase of the PFC circuit. And transmitting a pulse width modulation signal to the second switching tube to control the turning on and off of the second switching tube.

Optionally, the first pulse width modulation signal and the second pulse width modulation signal may be a pair of complementary driving waveforms.

Optionally, the detecting module is a phase locked loop, and the detecting module can detect a phase of the input voltage, and send the detected phase of the input voltage to the controller. Optionally, the foregoing detection module may also implement a phase-locked loop principle by using a software method, so as to send the detected phase of the output voltage to the controller. For the foregoing method, refer to the specific description in the embodiment corresponding to FIG. I will not repeat them here.

The embodiment of the present application can accurately determine the phase of the input voltage through the phase locked loop.

In the several embodiments provided by the present application, the disclosed circuit and method may also be implemented in other manners. For example, the device embodiments described above are illustrative. For example, the division of circuit modules is only a logical function division. In actual implementation, there may be another division manner. For example, multiple modules or components may be combined or integrated. Go to another system, or some features can be ignored or not executed.

The functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

Claims

A ripple optimization control circuit, comprising: a PFC circuit, an energy compensation circuit and a voltage current sampling circuit connected in sequence;

In a case where an input voltage of the PFC circuit is greater than a target threshold or a phase of an input voltage of the PFC circuit is in a set phase interval, the energy compensation circuit is converted into a step-down circuit, and the step-down circuit is configured to reduce An output voltage of the PFC circuit; the energy compensation circuit in a case where an input voltage of the PFC circuit is lower than the target threshold or a phase of an input voltage of the PFC circuit is not in the set phase interval Converted to a boost circuit for boosting the output voltage of the PFC circuit.
The ripple optimization control circuit according to claim 1, wherein the input voltage of the PFC circuit is an alternating current voltage, and the first output end and the second output end of the PFC circuit are respectively associated with the energy compensation circuit The first input end and the second input end are connected, and the first output end and the second output end of the energy compensation circuit are respectively connected to the first input end and the second input end of the voltage current sampling circuit;

The energy compensation circuit includes: a first switch tube, a second switch tube, an inductor, a capacitor, and a controller;

a drain of the first switch tube is connected to a first output end of the PFC circuit and a first input end of the voltage current sampling circuit, and a source of the first switch tube is connected to a first end of the inductor, a second end of the capacitor is connected to the first end of the capacitor, a second end of the capacitor is connected to a second input end of the voltage current sampling circuit, and a drain of the second switch tube is connected to the inductor a first end and a source of the first switch tube, a source of the second switch tube is connected to a second output end of the PFC circuit and a second input end of the voltage current sampling circuit, the controller The control terminal is respectively connected to the gate of the first switch tube and the gate of the second switch tube;

The controller is configured to control on and off of the first switch tube and the second switch tube according to an input voltage of the PFC circuit or according to an input voltage phase of the PFC circuit to control the The energy compensation circuit is switched to a boost circuit or a buck circuit.
The ripple optimization control circuit according to claim 2, wherein the PFC circuit further comprises a detection module, the detection module is configured to detect a phase of an input voltage of the PFC circuit, and pass the detection module The output of the output sends the detected phase of the input voltage to the controller;

The controller is specifically configured to send a first pulse width modulation signal to the first switch tube according to an input voltage of the PFC circuit detected by the detecting module or an input voltage phase of the PFC circuit to control the Turning on and off of the first switch tube, and sending a second pulse width modulation signal to the second switch tube to control turning on and off of the second switch tube;

The first pulse width modulation signal and the second pulse width modulation signal are a pair of complementary driving waveforms.
The ripple optimization control circuit according to any one of claims 1 to 3, wherein the PFC circuit is a single-phase voltage type pulse width modulation rectifier circuit.
The ripple optimization control circuit according to claim 4, wherein the detection module is a phase locked loop, and the detection module is configured to detect a phase of the input voltage, and send the detected location to the controller. The phase of the input voltage.
The ripple optimization control circuit according to claim 5, wherein the first switching transistor and the second switching transistor are both insulated gate bipolar transistors or power field effect transistors.
A ripple optimization control method for a PFC circuit output voltage is applied to a ripple optimization control circuit, the ripple optimization control circuit comprising a PFC circuit, an energy compensation circuit and a voltage current sampling circuit connected in sequence, wherein Methods include:

The energy compensation circuit is converted to a step-down circuit to reduce an output voltage of the PFC circuit if an input voltage of the PFC circuit is greater than a target threshold or a phase of an input voltage of the PFC circuit is within a set phase interval The energy compensation circuit is converted to a boost circuit, and the input voltage of the PFC circuit is lower than the target threshold or the phase of the input voltage of the PFC circuit is not in the set phase interval. The output voltage of the PFC circuit.
The ripple optimization control method for the output voltage of the PFC circuit according to claim 7, wherein the input voltage of the PFC circuit is an alternating current voltage, and the first output end and the second output end of the PFC circuit are respectively The first input end and the second input end of the energy compensation circuit are connected, and the first output end and the second output end of the energy compensation circuit are respectively connected to the first input end and the second input end of the voltage current sampling circuit ;

The energy compensation circuit includes: a first switch tube, a second switch tube, an inductor, a capacitor, and a controller;

a drain of the first switch tube is connected to a first output end of the PFC circuit and a first input end of the voltage current sampling circuit, and a source of the first switch tube is connected to a first end of the inductor, a second end of the capacitor is connected to the first end of the capacitor, a second end of the capacitor is connected to a second input end of the voltage current sampling circuit, and a drain of the second switch tube is connected to the inductor a first end and a source of the first switch tube, a source of the second switch tube is connected to a second output end of the PFC circuit, and a second input end of the voltage current sampling circuit, the controller is controlled The terminals are respectively connected to the gate of the first switch tube and the gate of the second switch tube;

The controller controls on and off of the first switch tube and the second switch tube according to an input voltage of the PFC circuit or according to an input voltage phase of the PFC circuit to control the energy compensation circuit Switch to a boost circuit or a buck circuit.
The ripple optimization control method for the output voltage of the PFC circuit according to claim 8, wherein the first switching transistor and the second switching transistor are both insulated gate bipolar transistors or power field effect transistors.
The ripple optimization control method for the output voltage of the PFC circuit according to any one of claims 7 to 9, wherein the PFC circuit further comprises a detection module, wherein the detection module is configured to detect an input voltage of the PFC circuit. a phase, and transmitting, by the output of the detection module, a phase of the detected input voltage to the controller;

The controller sends a first pulse width modulation signal to the first switch tube to control the first switch according to an input voltage of the PFC circuit detected by the detecting module or an input voltage phase of the PFC circuit. Turning on and off of the tube, and transmitting a second pulse width modulation signal to the second switch tube to control turning on and off of the second switch tube;

The first pulse width modulation signal and the second pulse width modulation signal are a pair of complementary drive waveforms.