WO2019139622A1

WO2019139622A1 - Ferroelectric field-effect transistors for 3d memory arrays and methods of manufacturing the same

Info

Publication number: WO2019139622A1
Application number: PCT/US2018/013604
Authority: WO
Inventors: Prashant Majhi; Elijah V. KARPOV; Brian S. Doyle; Abhishek A. SHARMA; Ravi Pillarisetty
Original assignee: Intel Corporation
Priority date: 2018-01-12
Filing date: 2018-01-12
Publication date: 2019-07-18

Abstract

Methods, apparatus, systems and articles of manufacture are disclosed for a gate all around ferroelectric material field-effect transistor. Examples include a ferroelectric memory device that includes a semiconductor substrate, a semiconductor rod extending in an elongate direction substantially parallel to the semiconductor substrate, a ferroelectric gate insulator coating the semiconductor rod and a gate conductor adjacent the semiconductor rod, the ferroelectric gate insulator positioned between the gate conductor and the semiconductor rod.

Description

FERROELECTRIC FIELD-EFFECT TRANSISTORS FOR 3D MEMORY ARRAYS AND METHODS OF

MANUFACTURING THE SAME

FIELD OF THE DISCLOSURE

[0001] This disclosure relates generally to integrated circuits, and, more particularly, to ferroelectric field-effect transistors for 3D memory arrays and methods of manufacturing the same.

BACKGROUND

[0002] Many memory devices include a matrix or array of individual memory cells arranged in rows and columns. The memory cells in each row are connected to a conductive line referred to as a wordline. The memory cells in each column are connected to a conductive line referred to as a bitline.

Thus, each memory cell is associated with a particular intersection of one bitline and one wordline. By controlling the voltages applied along individual bitlines and wordlines, information (e.g., individual bits) may be stored or read from the corresponding memory cells.

[0003] In recent years, manufactures have begun using ferroelectric materials in memory cells. Ferroelectric materials are of interest to memory applications because of their ability to exhibit and maintain a reversible electric polarization after exposure to an electric field.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 is an example 4x4x3 memory array containing gate-all- around three-dimensional (3D) ferroelectric field-effect transistors.

[0005] FIGS. 2A-2C, 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, 8A-8C, and 9A-9C illustrate stages in an example method of manufacturing the example memory array of FIG 1. [0006] FIG. 10 is an alternate example 4x4x3 memory array containing gate-all-around 3D ferroelectric field transistors.

[0007] FIGS. 11A-11C, 12A-12C, 13A-13C, 14A-14C, 15A-15C, 16A-16C, 17A-17C, 18A-18C and 19A-19C illustrate stages in an example method of manufacturing the example memory array of FIG 10.

[0008] FIG. 20 is a flowchart representative of an example method of manufacturing the example memory array of FIG. 1.

[0009] FIG. 21 is a flowchart representative of an example method of manufacturing the example memory array of FIG. 10.

[0010] FIG. 22 is a top view of a wafer and dies that may include a memory array containing gate-all-around 3D ferroelectric field-effect transistors, in accordance with various examples disclosed herein.

[0011] FIG. 23 is a cross-sectional side view of an IC device that may include a memory array containing gate-all-around 3D ferroelectric field- effect transistors, in accordance with various examples disclosed herein.

[0012] FIG. 24 is a cross-sectional side view of an IC package that may include a memory array containing gate-all-around 3D ferroelectric field- effect transistors, in accordance with various examples disclosed herein.

[0013] FIG. 25 is a cross-sectional side view of an IC device assembly that may include a memory array containing gate-all-around 3D ferroelectric field transistors, in accordance with any of the examples disclosed herein.

[0014] FIG. 26 is a block diagram of an example electrical device that may include a memory array containing gate-all-around 3D ferroelectric field transistors, in accordance with any of the examples disclosed herein.

[0015] The figures are not to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. As used in this patent, stating that any part (e.g., a layer, film, area, region, or plate) is in any way on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween. Stating that any part is in contact with another part means that there is no intermediate part between the two parts. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended, and/or irregular.

DETAILED DESCRIPTION

[0016] In accordance with teachings disclosed herein, example gate- all-around (GAA) ferroelectric field-effect transistors (FeFETs) arranged in a three dimensional (3D) structure may be formed using semiconductor manufacturing processes similar to and/or compatible with processes commonly used in semiconductor device manufacturing.

[0017] Example FeFET memory devices disclosed herein include bitlines that extend substantially parallel to the semiconductor substrate or wafer on which they are formed. Further, some example memory devices include a series of planar wordlines that are substantially perpendicular to the substrate. As used herein,“substantially parallel” and“substantially perpendicular” refer to measurements within three degrees to the referenced measurement (e.g., if a plane is substantially perpendicular to a reference plane, it is oriented between 87° and 93° to the reference plane). Disclosed memory devices offer several advantages when compared to other known memory devices. For instance, examples disclosed herein provide a highly scalable effective cell area for relatively high density memory that can be manufactured at a relatively low cost because the fabrication does not involve a critical lithography process. Furthermore, the structure of disclosed example memory devices (and the associated processes to fabricate such structures) provide the ability to dope extensions of the semiconductor-based bitlines to reduce external resistances. Further still, examples disclosed herein are compatible with back-end-of-line processing to facilitate the integration of the example memory devices with other semiconductor devices (e.g., for embedded memory applications). Additionally, examples disclosed herein provide high effective channel width when compared to typical FeFETs. . [0018] Example FeFETs used in memory devices disclosed herein include a ferroelectric material as the gate insulator between a gate conductor (corresponding to a memory wordline) and a semiconductor rod

(corresponding to a memory bitline). Ferroelectric materials exhibit a nonlinear electric polarization under the application of an external electric field that can be reversed with an electric field applied in the opposite direction. Furthermore, ferroelectric materials retain at least some polarization (a remnant polarization) even when the electric field is removed. These properties make ferroelectric materials suitable for non-volatile memory application including embedded memory technology.

[0019] FIG. 1 illustrates an example 4x4x3 memory array 100 that is formed on an example substrate 102. The example memory array 100 includes a number of bitlines 106 intersected by a number of wordlines 104. Each intersection of the bitlines 106 and the wordlines 104 corresponds to a separate gate-all-around FeFET 108 of the example memory array 100. The substrate 102 may be a wafer or slice, composed of a semiconductor material (e.g., polycrystalline silicon (polysilicon or poly-Si), germanium (Ge), gallium arsenide (GaAs), etc.). Alternatively, the substrate 102 may be a layer of material (semiconductor or otherwise) formed on top of and substantially parallel to a semiconductor wafer. As shown in FIG. 1, the FeFETs 108 are arranged in a 4x4x3 grid based upon the orientation of the bitlines 106 and the wordlines 104. For the purpose of explanation, a set of axes 110 has been included in the example illustration of FIG. 1. As shown in the illustrated example, a top surface 112 of the substrate 102 is substantially parallel to the plane defined by the x-direction and the y-direction of the set of axes 110. Elongate lengths of the bitlines 106 extend substantially parallel to the x- direction and, thus, substantially parallel to the top surface 112 of the substrate 102. As shown in the illustrated example, the wordlines 104 are generally planar and oriented substantially parallel to a plane defined by the y-direction and the z-direction of the set of axes 110. Thus, in the illustrated example, the wordlines 104 are oriented within planes that are substantially perpendicular to the top surface 112 of the substrate 102 and substantially perpendicular to the bitlines 106. In the illustrated example, the memory array 100 is generally shaped like a rectangular prism. In other examples, the memory array 100 can be any suitable shape.

[0020] The example bitlines 106 of FIG. 1 are structured as semiconductor rods 114 that extend in an elongate direction substantially parallel to one another (e.g., substantially parallel to the x-direction). The semiconductor rods 114 may include any suitable semiconductor material (e.g., polycrystalline silicon (polysilicon or poly-Si), polycrystalline silicon germanium (poly-SiGe), polycrystalline germanium (poly-Ge), polycrystalline indium gallium arsenide (InGaAs), etc.). In the illustrated example, the semiconductor rods 114 serve as the channels for the multiple FeFETs 108 distributed along the lengths of each rod 114. As shown in FIG. 1, the number of FeFETs 108 positioned along each bitline 114 corresponds to the number of wordlines 104 intersecting the bitlines 106. In some examples, the semiconductor rods 114 extend from an anchor region 116 at a first end of the semiconductor rods to a second anchor region (omitted for the sake of clarity) at a second end of the semiconductor rods.

[0021] In the illustrated example of FIG. 1, the wordlines 104 correspond to gate conductors 118 of the FeFETs 108 that may be powered on and off to selectively activate the channel within the semiconductor rods 114. As shown in the illustrated example, the gate conductors 118 are generally planar in shape and oriented substantially perpendicular to the semiconductor rods 114. In the illustrated example, each gate conductor 118 intersects with each of the semiconductor rods 114 spaced apart in both the y-direction and the z-direction. More particularly, as shown in FIG. 1, the gate conductors 118 extend completely around each of the FeFETs 108 within a plane defined between the opposing lateral surfaces of the gate conductors 118. Thus, in the illustrated example, the FeFETs 108 are implemented as gate-all-around transistors. Furthermore, as shown in FIG. 1, the gate conductor 104 extends continuously from one semiconductor rod 114 to another. As such, each of the FeFETs 108 associated with the same gate conductor 118 may be activated at the same time and correspond to the same wordline 104. [0022] In some examples, the gate conductors 118 are positioned substantially parallel to one another and transversely to the semiconductor rods. In some examples, the gate conductors 118 are evenly distributed along the semiconductor rods 114. At the stage of fabrication of the example memory array 100 represented in FIG. 1, there are spaces between adjacent gate conductors 118 and surrounding the semiconductor rods 114. In some examples, during a later stage of fabrication, these spaces are filled with an isolation material. The gate conductor 118 may include any suitable metal (e.g., one or more of aluminum (Al), tungsten (W), titanium nitride (TiN), thallium nitride (TEN). etc.) or a non-metal conductor (e.g., polysilicon). In the illustrated example, the semiconductor rods 114 have a generally rectangular cross-section. In other examples, the semiconductors rods may be formed with any other suitable shape (e.g., cylindrical cross-section, triangular cross-section, etc.).

[0023] In the illustrated example, the portions of the semiconductor rods 114 surrounded by the gate conductors 118 (at the intersections where the FeFETs 108 are located) are coated by a gate insulator 120. In this example, the gate insulator 120 is in contact with both the semiconductor rods 114 and the gate conductors 118 and separates (e.g., prevents the direct contact of) the semiconductor rods 114 from the gate conductors 118. The gate insulator 120 may include any suitable ferroelectric material (e.g., doped Hafnium Oxide (HfOx) or Hafnium Zcronium Oxide (HZO)). In some examples, the ferroelectric material may have between 2% and 10% dopant levels. In other examples, the dopant levels may be less than 2% or greater than 10%. In some examples, the ferroelectric materials may be doped with one or more of silicon (Si), aluminum (Al), lanthanum (La), Erbium (Er), Gadolinium (Gd) and Strontium (Sr). In some examples, the ferroelectric material may not be doped or doped with any other suitable material.

[0024] In some examples, each FeFET 108 has an associated source/drain region in the corresponding semiconductor rod 114. In some examples, there is no source/drain metal contacts associated with each individual FeFET 108. Instead, in some examples, the semiconductor rods 114 are lightly doped and the regions of the semiconductor rods 114 extending between adjacent gate conductors 104 are modulated by the fringing field of the gate conductors 118.

[0025] In the illustrated example, each FeFET 108 in the memory array 100 stores at least a single bit of data. In some examples, the data stored in particular ones of the FeFETs 108 are read and/or written by biasing the corresponding wordline 104 and corresponding bitline 106. Data may be stored by the FeFETs 108 based on the ferroelectric properties of the ferroelectric gate insulator 120. In particular, ferroelectric materials maintain an electric polarization in the absence of an electric field that can be reversed by the application of an electric field in the opposite direction to the previous electric field that induced the current polarization within the material. Thus, data is read from the FeFETs 108 in the memory array 100 by detecting the direction of polarization of the gate insulator 120. Data may be written to the FeFETs 108 by applying the appropriate electric field to the gate insulator 120 to bias the polarization to the particular direction representative of the memory value to be stored. Data may be read by detecting the polarization of the FeFET 108 (e.g., based on the conductivity in the corresponding bitline 106). As mentioned above, each FeFET 108 stores at least one bit of information. In some example, multiple bits may be stored by a single FeFET 108 by applying different voltages to achieve different levels of (e.g., partial) polarization within the ferroelectric material. The ferroelectric properties of the gate insulator 120 enable the memory array 100 to be implemented as non-volatile memory in some examples.

[0026] As mentioned above, the FeFETs 108 in the memory array 100 of FIG. 1 are formed at the intersections of the bitlines 106 and the wordlines 104. In the memory array 100 of FIG. 1, there are a total of 48 FeFETs 108 arranged in a 4x4x3 grid (e.g., three wordlines 104 x four rows of bitlines 106 x four columns of bitlines 106). However, examples disclosed herein may be implemented with any other suitable number of wordlines 104 intersecting any suitable number of rows and columns of bitlines 106. Further, the number of rows of the bitlines 106 may be greater or less than the number of columns of the bitlines 106. In some examples, the size of the example memory array 100 is primarily limited by the length of the semiconductor rods 114. The length of the semiconductor rods 114 may be limited by the fact that during the fabrication process, as described more fully below, the semiconductor rods 114 are suspended exclusively at their ends (e.g., by the anchor regions 116 at each end of the rods). In some examples, the semiconductor rods 114 may extend longitudinally (e.g., in the x-direction) a length ranging between 0.5 microns and 5 microns. In some examples, the length of the semiconductor rods 114 may be less than 0.5 microns or greater than 5 microns.

[0027] In some examples, the length of a gate conductor 118 extending along the length of the semiconductor rods 114 (e.g., in the x-direction) is between 15-30 nanometers. In other examples, the length of the gate conductors 118 may be less than 15 nanometers or greater than 30 nanometers. In some examples, the spacing between adjacent gate conductors 118 (e.g., in the x-direction) is between 15-50 nanometers. In some examples, such dimensions may result in 20 to 130 gate conductors 118 fitting along a single semiconductor rod 114, which corresponds to 20-130 FeFETs per bitline 106.

[0028] In some examples, the lateral and vertical spacing (e.g., in either the y-direction or the z-direction) between semiconductor rod 114 is 20- 50 nanometers. In other examples, the spacing may be larger or smaller than this range. Further, in some examples, the spacing in the y-direction may be different than the spacing in the z-direction. In some examples, the width and thickness of a semiconductor rod 114 (e.g., in the y-direction and the z- direction) is approximately 20 nanometers. In some examples, the width of the semiconductor rods 114 may be different than their thickness. In some examples, a memory array may include up to 100 semiconductor rods 114 spaced vertically in the z-direction and any suitable number of semiconductor rods 114 spaced horizontally in the y-direction (e.g., approximately 1000 rods along a 40 micron distance). Assuming there are 20 wordlines 104 (gate conductors 118) per bitline 106 (semiconductor rods 114), the above dimensions would result in a memory array of 100 ^c 1000 ^c 20 = 2 million FeFETs (e.g., 2 Mb of memory). [0029] FIGS. 2A-2C, 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, 8A-8C, and 9A-9C illustrate progressive stages of fabrication of the example memory array 100 of FIG. 1. In particular, FIG. 2A illustrates a cut-away view of an example structure 202 formed on the top surface 112 of semiconductor substrate 102 that includes alternating layers of a semiconductor material 204 and an isolation material 206. FIG. 2B illustrates a cross-sectional view of the structure 202 of FIG. 2A facing in the x-direction of the set of axes 110. FIG. 2C illustrates a cut-away top view of the example structure 202 of FIG. 2B taken along the line 205. For simplicity and clarity, the substrate 102 and the anchor region 116 shown in FIG. 2A are omitted in FIGS. 2B and 2C. In the illustrated examples, the structure 202 corresponds to the general shape of the memory array 100 of FIG. 1 with the different layers of the semiconductor material 204 serving as the basis to form the semiconductor rods 114 shown in FIG. 1. Thus, the semiconductor material 204 may be any suitable material to be used for the semiconductor rods 114 (e.g., poly crystalline silicon

(polysilicon or poly-Si), germanium (Ge), gallium arsenide (GaAs), etc.). The layers of isolation material 206 may include any suitable dielectric material (e.g., an oxide).

[0030] In some examples, the anchor region 116 corresponds to an extension of the alternating layers of material 204, 206. In FIG. 2A, the anchor region 116 is shown as being wider than the rest of the structure 202. This is provided for the sake of clarity to demarcate the anchor region 116 from the rest of the structure 202 that will subsequently be processed to form the memory array 100. In some examples, the alternating layers of materials 204, 206 are coextensive with the anchor region 116.

[0031] As shown in the illustrated example, the bottom and top layers of the structure 202 correspond to the isolation material 206 such that each layer of the semiconductor material 204 is sandwiched between two layers of the isolation material 206. In some examples, each layer in the structure 202 is formed by a successive chemical vapor deposition (CVD) process.

Alternatively, any other suitable process may be used to deposit the alternating layers of the semiconductor and isolation materials on top of one another to be substantially parallel to the substrate 102.

[0032] FIG. 3A illustrates a cut-away view of an example structure 302 corresponding to the structure 202 of FIGS. 2A-2C after trenches 304 have been etched through the layers of the semiconductor material 204 and the isolation material 206. FIG. 3B illustrates a cross-sectional view of the example structure 302 of FIG. 3 A facing in the x-direction of the set of axes 110. FIG. 3C illustrates a cut-away top view of the example structure 302 of FIG. 3B taken along the line 306. For simplicity and clarity, the substrate 102 and the anchor region 116 shown in FIG. 3A are omitted in FIGS. 3B and 3C. As shown in the illustrated example, the trenches 304 extend longitudinally in the x-direction and extend through all of the alternating layers of materials 204, 206. In this manner, each of the layers of semiconductor material 204 are dividing into isolated length of material extending out from the anchor region 116. In this example, the isolated lengths of the semiconductor material 204 correspond to the semiconductor rods 114 (and, thus, the bitlines 106) of the memory array 100 of FIG. 1. In some examples, the trenches 304 are formed by photoresist etching trenches into the layered semiconductor material 204 and isolation material 206. Alternatively, any other suitable means of forming trenches 304 may be employed to form structure 302.

[0033] FIG. 4A illustrates a cut-away view of an example structure 402 corresponding to the structure 302 of FIG. 3 A after the isolation material 206 has been removed adjacent the semiconductor rods 114. FIG. 4B illustrates a cross-sectional view of the example structure 402 of FIG. 4A facing in the x-direction of the set of axes 110. FIG. 4C illustrates a cut-away top view of the example structure 402 of FIG. 4B taken along the line 406.

For simplicity and clarity, the substrate 102 and the anchor region 116 shown in FIG. 4A are omitted in FIGS. 4B and 4C. In some examples, the isolation material 206 has been removed using a wet etching process to selectively remove the isolation material 206 and not the semiconductor 204.

Alternatively, any other suitable means of removing isolation material 206 and not the semiconductor material 204 may be implemented. In some examples, the etching process is controlled to limit the removal of the isolation material 206 in the anchor region 116. Maintaining the isolation material 206 within the anchor region 116 provides a solid foundation to support the

semiconductor rods 114, which, at this stage of the fabrication process, are suspended in space except at their ends attached to the anchor region 116 (and a second anchor region not shown at the opposite end of the rods). Thus, in the illustrated example, the entire exterior surface of each semiconductor rod 114 along its entire length is exposed to the surrounding environment.

[0034] FIG. 5A illustrates a cut-away view of an example structure 502 corresponding to the structure 402 of FIG. 4A after ferroelectric material 504 has been deposited onto the semiconductor rods 114. FIG. 5B illustrates a cross-sectional view of the example structure 502 of FIG. 5 A facing in the x- direction of the set of axes 110. FIG. 5C illustrates a cut-away top view of the example structure 502 of FIG. 5B taken along the line 506. For simplicity and clarity, the substrate 102 and the anchor region 116 shown in FIG. 5 A are omitted in FIGS. 5B and 5C. In some examples, the ferroelectric material 504 is deposited via atomic layer deposition (ALD). Alternatively, any other suitable method may be used to deposit the ferroelectric material 504. In some examples, the deposited ferroelectric material 504 may be between 3 and 12 nanometers thick. In other examples, the deposited ferroelectric material 504 may be less than 3 nanometers or greater than 12 nanometers thick. In some examples, the ferroelectric material 504 coats the semiconductor rods 114 so that the entire exterior surface of the rods is covered by the semiconductor material. In some examples, the ferroelectric material corresponds to the gate insulator 120 for the FeFETs 108 of FIG. 1.

[0035] FIG. 6A illustrates a cut-away view of an example structure 602 corresponding to the structure 502 of FIG. 5 A after gate conductor material 604 has been deposited around the semiconductor rods 114. FIG. 6B illustrates a cross-sectional view of the example structure 602 of FIG. 6A facing in the x-direction of the set of axes 110. FIG. 6C illustrates a cut-away top view of the example structure 602 of FIG. 6B taken along the line 606. For simplicity and clarity, the substrate 102 and the anchor region 116 shown in FIG. 6A are omitted in FIGS. 6B and 6C. In the illustrated example, the gate conductor material 604 serves as the basis to form the gate conductors 118 (and associated wordlines 104) of FIG. 1. Thus, the gate conductor material 604 may be any suitable material for the gate conductors 118 as described above. As shown in the illustrated example, the gate conductor material 604 fills the space or openings between adjacent ones of the semiconductor rods 114. However, the gate conductor material 604 does not directly contact the semiconductor rods 114 because of the layer of ferroelectric material 504 positioned therebetween on the exterior surfaces of the rods. In some examples, the gate conductor material is deposited using an ALD process. In other examples, CVD or any other suitable method may be used to deposit the gate conductor material 604.

[0036] FIG. 7 A illustrates a cut-away view of an example structure 702 corresponding to the structure 602 of FIG. 6 A after trenches 704 have been etched through the gate conductor material 604. FIG. 7B illustrates a cross-sectional view of the example structure 702 of FIG. 7 A facing in the x- direction of the set of axes 110. FIG. 7C illustrates a cut-away top view of the example structure 702 of FIG. 7B taken along the line 706. For simplicity and clarity, the substrate 102 and the anchor region 116 shown in FIG. 7 A are omitted in FIGS. 7B and 7C. In the illustrated example, the trenches 704 are etched into the gate conductor material 604 using any suitable process(es) that selectively removes the gate conductor material 604 without removing the semiconductor rods 114 or the ferroelectric material 504 disposed thereon. More particularly, as shown in the illustrated examples, the regions where the gate conductor material 604 is removed, as defined by the trenches 704, extend entirely through the gate conductor material 604 along planes that are substantially parallel to one another and substantially perpendicular to the semiconductor rods 114. As a result, after the etching process(es), the gate conductor material 604 is divided into vertically oriented planar segments as shown in the illustrated example. In this example, the planar segments of the gate conductor material 604 that remain after the etching process(es) correspond to the gate conductors 118 (and, thus, the wordlines 104) of the memory array 100 of FIG. 1.

[0037] By selectively etching the gate conductor material 604 as described above, portions of the ferroelectric material 120 on the

semiconductor rods 114 are exposed within the trenches 704 between adjacent ones of the gate conductors 118. That is, while the gate conductor material 604 has been removed from the trenches, as represented in FIGS. 7A-7C, the semiconductor rods 114 (and the associated ferroelectric material 504 formed thereon) remain and extend through the trenches 704 and adjacent ones of the gates conductors 118. In this manner, the multiple intersections between the bitlines 106 (e.g., the semiconductor rods 114) and the wordlines 104 (e.g., the gate conductors 118) corresponding to the individual FeFETs 108 of FIG. 1 may be formed.

[0038] FIG. 8A illustrates a cut-away view of an example structure 802 corresponding to the structure 702 of FIG. 7 A after the exposed portions of the ferroelectric material 504 in FIG. 7 A have been removed and corresponds the stage of fabrication of the memory array 100 shown in FIG. 1. FIG. 8B illustrates a cross-sectional view of the example structure 802 of FIG. 8 A facing in the x-direction of the set of axes 110. FIG. 8C illustrates a cut away top view of the example structure 802 of FIG. 8B taken along the line 804. For simplicity and clarity, the substrate 102 and the anchor region 116 shown in FIG. 8 A are omitted in FIGS. 8B and 8C. In the illustrated examples, the exposed portions (e.g., portions not coated by ferroelectric material 504) of the semiconductor rods 114 correspond to the areas within the trenches 704 and between adjacent gate conductors 118. However, the ferroelectric material 504 may not be removed along the regions in alignment with the gate conductors 118 (e.g., between the gate conductors 118 and the semiconductor rods 114). That is, in some examples, the ferroelectric material 504 is divided into separate lengths along the semiconductor rod 114 corresponding to the intersections with the gate conductors 118. Any suitable etching process may be implemented to remove the ferroelectric material 504. In some examples, the ferroelectric material in the trenches 704 is not removed such that the ferroelectric material extends continuously from one gate conductor to the next as shown in FIG. 7 A. .

[0039] FIG. 9A illustrates a cut-away view of an example structure 902 corresponding to the structure 802 of FIG. 8 A (and memory array 100 of FIG. 1) after the open spaces within the trenches 704 shown in FIG. 8 have been filled with isolation material 904. FIG. 9B illustrates a cross-sectional view of the example structure 902 of FIG. 8 A facing in the x-direction of the set of axes 110. FIG. 9C illustrates a cut-away top view of the example structure 902 of FIG. 9B taken along the line 906. For simplicity and clarity, the substrate 102 and the anchor region 116 shown in FIG. 9 A are omitted in FIGS. 9B and 9C. The isolation material 904 may include any suitable dielectric material (e.g., an oxide). In some examples, the isolation material 904 is deposited using a CVD process. Alternatively, any other suitable process may be implemented to deposit the isolation material 904.

[0040] FIG. 10 illustrates an alternative example 4x4x3 memory array 1000 of FeFETs 1002 constructed in accordance with teachings disclosed herein. The example memory array 1000 of FIG. 10 has a substantially similar structure to the example memory array 100 of FIG. 1. Accordingly, for the sake of brevity, the same reference numerals used in connection with FIG. 1 will be used for the corresponding components in the example memory array 1000 of FIG. 10.

[0041] A difference between the example memory array 1000 of FIG. 10 and the example memory array of FIG. 1 is the structure of the

semiconductor rods. In particular, as shown in FIG. 10, the memory array 1000 includes semiconductor rods 1004 with an outer wall 1006 made of a first material and an inner core 1008 made of a second material. In some examples, the outer wall 1006 includes any suitable semiconductor material (e.g., polycrystalline silicon (polysilicon or poly-Si), germanium (Ge), gallium arsenide (GaAs), etc.). The inner core includes any suitable isolation material (e.g., a carbon doped SiCh, S13N4 or, any other suitable SiOCN family oxide, etc.). In contrast to the semiconductor rods 1004 of FIG. 10, the

semiconductor rods 114 of FIG. 1 include a semiconductor material that is solid through its entire cross section. Thus, the semiconductor rods 114 of FIG. 1 provide a full body channel for the FeFETs 1002 of FIG. 1. By contrast, the semiconductor rods 1004 of FIG. 10 provide a thin channel (e.g., limited to the semiconductor material of the outer wall 1006) for the FeFETs 1002 of FIG. 10.

[0042] While the semiconductor rods 114, 1004 of the example memory arrays 100, 1000 of FIGS. 1 and 10 are different, they still serve the same purpose. That is, the semiconductor rods 1004 of FIG. 10 correspond to different bitlines 1010 of the memory array 1000 of FIG. 1 in a similar manner that the semiconductor rods 114 of FIG. 1 correspond to the bitlines 106 of the memory array 100 of FIG. 1. Furthermore, in the illustrated examples, the semiconductor rods 114, 1004 of FIGS. 1 and 10 have a generally similar shape and are arranged in a similar manner. For example, as shown in the illustrated example, the semiconductor rods 1004 of FIG. 10 extend substantially parallel to one another in the x-direction of the set of axes 110 in a similar manner as the semiconductor rods 114 of FIG. 1.

[0043] Furthermore, many of the other components of the memory arrays 100, 1000 in FIGS. 1 and 10 are similar. For example, the memory array 1000 of FIG. 10 includes similar gate conductors 118 (and

corresponding wordlines 104) to those described above in FIG. 1 such that the description provided above may be applied equally to this example. Further, the semiconductor rods 1004 of FIG. 10 are coated by a gate insulator 120 to separate the semiconductor rods 1004 from the gate conductors 118 as described above in connection with FIG. 1.

[0044] FIGS. 11A-11C, 12A-12C, 13A-13C, 14A-14C, 15A-15C, 16A-16C, 17A-17C, 18A-18C and 19A-19C illustrate progressive stages of fabrication of the example memory 1000 of FIG. 10. In particular FIGS. 11A- 11C respectively illustrate a cut-away view, a cross-sectional view, and a cut away top view (taken along the line 1104) of an example structure 1102 that is used as the basis to from the example memory array 1000 of FIG. 10. The views of the example structure 1102 shown in FIGS. 11 A-l 1 C generally correspond to the views of the example structure 202 shown in FIGS. 2A-2C with alternating layers of materials successively deposited on each other. However, unlike the example structure 202 shown in FIGS. 2A-2C, the alternating layers in the example structure 1102 of FIGS. 11A-11C correspond to first and second isolation material 1106, 1108. In the illustrated example, the second isolation material 1108 corresponds to the material used for the inner cores 1008 of the semiconductor rods 1004 of FIG. 10. The first isolation material 1108 is different than the second isolation material 1108 and may be selected based on its etchability from the second isolation material 1108. Example materials for the first isolation material includes a carbon doped (e.g., with dopant levels ranging from 1% to 8%) SiCh, S13N4 or, any other suitable SiOCN family oxide, etc. Similar materials may be used in the second isolation material but with different compositions to facilitate the selective etching one relative to the other. As shown in the illustrated examples, the bottom and top layers of the structure 1102 correspond to the first isolation 1106 such that each layer of the second isolation material 1108 is sandwiched between two layers of the first isolation material 1106. In some examples, each layer in the structure 1102 is formed by a successive CVD process. Alternatively, any other suitable process may be used to deposit the alternating layers of the first and second isolation materials 1106, 1108.

[0045] FIGS. 12A-12C illustrate a cut-away view, a cross-sectional view, and a cut-away top view (taken along the line 1206) of an example structure 1202 corresponding to the structure 1102 of FIGS. 11 A-l 1C after trenches 1204 have been etched through the layers of the first and second isolation material 1106, 1108. The process to etch the trenches 1204 in FIGS. 12A-12C is similar to the process to etch the trenches 304 of FIGS. 3A-3C except that different materials are involved. Further, in some examples, the trenches 1204 shown in FIGS. 12A-12C may be larger than the trenches 304 FIGS. 3A-3C to provide space for the outer walls 1006 of the semiconductors 1004 to be added during a later manufacturing process. The result of the etching process is to divide the second isolation material into elongate segments corresponding to the inner cores 1008 of the semiconductor rods 1004 of the example memory array 1000 of FIG. 10. [0046] FIGS. 13A-13C respectively illustrate a cut-away view, a cross- sectional view, and a cut-away top view (taken along the line 1306) of an example structure 1302 corresponding to the structure 1202 of FIGS. 12A-12C after the first isolation material 1106 has been removed adjacent the inner cores 1008 of the semiconductor rods 1004. The process to remove the first isolation material 1106 as represented in FIGS. 13A-13C is similar to the process to remove the isolation material 206 from the semiconductor rods 105 as represented in FIGS. 4A-4C except that different materials are involved.

The result of this process is to expose the external surface of the inner cores 1008 of the semiconductor rods 1004.

[0047] FIGS. 14A-14C respectively illustrate a cut-away view, a cross- sectional view, and a cut-away top view (taken along the line 1406) of an example structure 1402 corresponding to the structure 1302 of FIGS. 13A-13C after the deposition of the semiconductor material 1404 onto the inner cores 1008 of the semiconductor rods 1004. The process to deposit the

semiconductor material 1404 as represented in FIGS. 14A-14C is similar to the process to deposit the ferroelectric material 504 on the semiconductor rods 114 as represented in FIGS. 5A-5C except that different materials are involved. Furthermore, the processes represented in FIGS. 14A-14C relative to the processes represented in FIGS. 5A-5C may differ in the thickness of the coating or layer of the material being deposited. For example, the thickness of the semiconductor material 1404 may be between 5 and 20 nanometers. In other examples, the thickness of semiconductor material 1404 may be less than 5 nanometers or greater than 20 nanometers. The result of deposition of the semiconductor material 1404 is the completion of the formation of the semiconductor rods 1004 (and, thus, the bitlines 1010) of the example memory array 1000 of FIG. 10.

[0048] The remaining stages in the method of manufacturing the example memory array 1000 represented in FIG. 15A-15C, 16A-16C, 17A- 17C, 18A-18C, and 19A-19C substantially correspond to the respective stages in the method of manufacturing the memory array 100 represented in FIGS. 5A-5C, 6A-6C, 7A-7C, 8A-8C, and 9A-9C as outlined above. Thus, FIGS. 15A-15C represent the deposition of the ferroelectric material 504 onto the exposed exterior surfaces of the semiconductor rods 1004. FIGS. 16A-16C represent the deposition of the gate conductor material 604 to fill the spaces between the semiconductor rods 1004 coated with the ferroelectric material 504. FIGS. 17A-17C represent etching the gate conductor material 114 to form the individual gate conductors 118 (and corresponding wordlines 104) for the example memory array 1000. FIGS. 18A-18C represent the removal of the ferroelectric material 504 from the surface of the semiconductor rods 1004 in the region between adjacent ones of the gate conductors 118. The example structure 1802 shown in FIG. 18A corresponds to the example memory array 1000 at the stage of fabrication represented in FIG. 10. Finally, FIGS. 19A- 19C represent filling in the remaining space between the gate conductors 118 and around the semiconductor rods 1004 with the isolation material 904.

[0049] FIG. 20 is a flowchart of an example method 2000 of manufacturing the example memory array 100 of FIG. 1. The example method 2000 begins at block 2002 by depositing a layer of isolation material 206 substantially parallel to the substrate 102. At block 2004, a layer of semiconductor material 204 is deposited substantially parallel to the substrate 102 on the layer of isolation material 206. In some examples, the layer of semiconductor material 204 serves as the basis for a particular row of bitlines 106 of the memory array 100. At block 2006, the example method 2000 determines whether another layer of semiconductor material 204 is to be deposited. As mentioned above, each layer of semiconductor material 204 corresponds to a different layer or row of bitlines 106 in the memory array 100. Thus, if the memory array 100 is to include another layer of bitlines 106, the method 2000 returns to block 2002 to deposit another layer of isolation material 206 (block 2002) followed by another layer of semiconductor material 204 (block 2004). For example, if twenty layers of bitlines 106 are desired, blocks 2002 and 2004 are repeated 20 times, including the deposition of the first layers of material. In some examples, the alternating layers of material 204, 206 deposited during each iteration of blocks 2002, 2004 are deposited on an upper surface of the most recently deposited layer of material. If there are no additional layers of semiconductor material 204 to be deposited (block 2006), the method 2000 proceeds to block 2007. At block 2007, another layer of isolation material 206 is deposited on the top layer of semiconductor material 204. That is, the layer of isolation material 206, is deposited on the last layer of semiconductor material 204 deposited before exiting the loop at block 2006. In this manner, each layer of semiconductor material 204 is positioned between two layers of isolation material 206. In some examples, the stage of manufacturing after completion of blocks 2002- 2007 corresponds to the example structure 202 of FIGS. 2A-2C.

[0050] At block 2008, the trenches 304 are etched through the alternating layers of material 204, 206 to form semiconductors rods 114. At this stage in the process, the semiconductor rods 114 are laterally separated by the trenches 304 and vertically separated by segments of the layers of isolation material 206. In some examples, the formed semiconductor rods 114 are to function as the bitlines 106 of the memory array 100. In some examples, regions of the alternating layers of material 204, 206 are not etched away. In this example, the regions of the material that is not etched away corresponds to the anchor regions 116 of the memory array 100. In some examples, the stage of manufacturing after completion of block 2008 corresponds to the example structure 302 of FIGS. 3A-3C.

[0051] At block 2010, the isolation material 206 between the semiconductor rods 114 is removed. In some examples, the isolation material 206 is removed with a wet etching process. In this example, the isolation material in the anchor regions 116 is not removed. In some examples, the stage of manufacturing after completion of block 2010 corresponds to the example structure 402 of FIGS. 4A-4C.

[0052] At block 2012, a ferroelectric material is deposited onto the exterior surface of the semiconductors rods 1141h some examples, the entire length of the semiconductor rods 114 are coated with ferroelectric material. In some examples, the deposited ferroelectric material corresponds to the gate insulator 120 for the FeFETs 108 of the memory array 100. In some examples, the stage of manufacturing after completion of block 2012 corresponds to the example structure 502 of FIGS. 5A-5C

[0053] At block 2014, the gate conductor material 604 is deposited to fill the gaps between the ferroelectric material coated semiconductor rods 114. In some examples, the deposited gate conductor material 604 serves as the basis to form the gate conductors 118, which correspond to the wordlines 104 of the memory array 100. In some examples, the stage of manufacturing after completion of block 2014 corresponds to the example structure 602 of FIGS. 6A-6C.

[0054] At block 2016, the gate conductor material 604 is etched into separate wordlines 104. In some examples, the gate conductor material 604 is selectively etched to expose, without removing, portions of the ferroelectric material coated semiconductor rods 114 that extend between adjacent ones of the wordlines 104. In some examples, the stage of manufacturing after completion of block 2016 corresponds to the example structure 702 of FIGS. 7A-7C.At block 2018, the ferroelectric material is removed from the exposed portions of the semiconductor rods 114. In some examples, the stage of manufacturing after completion of block 2018 corresponds to the example structure 802 of FIGS. 8A-8C. Block 2018 is optional and, therefore, may be omitted in some examples.

[0055] At block 2020, the isolation material 904 is deposited to fill the gaps between the separate wordlines 104 and the exposed portions of the semiconductor rods 114. In some examples, the stage of manufacturing after completion of block 2020 corresponds to the example structure 902 of FIGS. 9A-9C. Thereafter, the example method 2000 of FIG. 20 ends and manufacturing may proceed to other back-end-of-line processes.

[0056] Although the example method 2000 is described with reference to the flowchart illustrated in FIG. 20, many other methods of manufacturing the example memory array 100 in accordance with the teachings disclosed herein may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated or combined. Similarly, additional operations may be included in the manufacturing process before, in between or after the blocks shown in FIG. 20.

[0057] FIG. 21 is a flowchart of an example method 2100 of manufacturing the example memory array 1000 of FIG. 10. The example method 2100 begins at block 2102 by depositing a layer of first isolation material 1106 substantially parallel to the substrate 102. At block 2104, a layer of second isolation material 1108 is deposited substantially parallel to the substrate 102 on the layer of first isolation material 1106. In some examples, the layer of second isolation material 1108 serves as the basis for the inner cores 1008 of the semiconductor rods 1004 of the memory array 1000. At block 2106, the example method 2100 determines whether another layer of second isolation material 1108 is to be deposited. As mentioned above, each layer of second isolation material 1108 corresponds to a different layer or row semiconductor rods 1004, which correspond to bitlines 1010 in the memory array 1000. Thus, if the memory array 1000 is to include another layer of bitlines 1010, the method 2100 returns to block 2102 to deposit another layer of first isolation material 1106 (block 2102) followed by another layer of second isolation material 1108 (block 2104). In some examples, the alternating layers of material 1106, 1108 deposited during each iteration of blocks 2102, 2104 are deposited on an upper surface of the most recently deposited layer of material. If there are no additional layers of second isolation material 1108 to be deposited (block 2106), the method 2100 proceeds to block 2108. At block 2108, another layer of first isolation material 1106 is deposited on the top layer of second isolation material 1108. That is, the layer of first isolation material 1106, is deposited on the last layer of second isolation material 1108 deposited before exiting the loop at block 2106. In this manner, each layer of second isolation material 1108 is positioned between two layers of first isolation material 1106. In some examples, the stage of manufacturing after completion of blocks 2102-2108 corresponds to the example structure 1102 of FIGS. 11A-11C.

[0058] At block 2110, the trenches 1204 are etched through the alternating layers of material 1106, 1108 to form semiconductors rod cores 1008. At this stage in the process, the semiconductor rod cores (e.g., the inner cores 1008) are laterally separated by the trenches 1204 and vertically separated by segments of the layers of first isolation material 1106. In some examples, the formed semiconductor rod cores 1008 are to function as the cores of the bitlines 1010 of the memory array 1000. In some examples, regions of the alternating layers of material 1106, 1108 corresponding to an anchor region for the semiconductor rod cores 1008 are not etched away. In some examples, the stage of manufacturing after completion of block 2110 corresponds to the example structure 1202 of FIGS. 12A-12C.

[0059] At block 2112, the first isolation material 1106 between the semiconductor rod cores 1008 is removed. In some examples, the isolation material 1106 is removed with a wet etching process. In some examples, the stage of manufacturing after completion of block 2112 corresponds to the example structure 1302 of FIGS. 13A-13C.

[0060] At block 2114, a semiconductor material is deposited onto the exterior surface of the semiconductors rod cores 1008 to form semiconductors rods 1004. In some examples, the entire length of the semiconductor rod cores 114 are coated with semiconductor material. This semiconductor material corresponds to the outer wall 1006 of the semiconductor rods 1004. In some examples, the stage of manufacturing after completion of block 2114 corresponds to the example structure 1402 of FIGS. 14A-14C.

[0061] At block 2116, a ferroelectric material 504 is deposited onto the exterior surface of the semiconductors rods 1004. In some examples, the entire length of the semiconductor rods 1004 are coated with the ferroelectric material 504. In some examples, the deposited ferroelectric material corresponds to the gate insulator 120 for the FeFETs 1002 of the memory array 1000. In some examples, the stage of manufacturing after completion of block 2116 corresponds to the example structure 1502 of FIGS. 15A-15C

[0062] At block 2118, the gate conductor material 604 is deposited to fill the gaps between the ferroelectric material coated semiconductor rods 1004. In some examples, the deposited gate conductor material 604 serves as the basis to form the gate conductors 118, which correspond to the wordlines 104 of the memory array 1000. In some examples, the stage of manufacturing after completion of block 2118 corresponds to the example structure 1602 of FIGS. 16A-16C.

[0063] At block 2120, the gate conductor material 604 is etched into separate wordlines 104. In some examples, the gate conductor material 604 is selectively etched to expose, without removing, portions of the ferroelectric material coated semiconductor rods 1004 that extend between adjacent ones of the wordlines 104. In some examples, the stage of manufacturing after completion of block 2120 corresponds to the example structure 1702 of FIGS. 17A-17C. At block 2122, the ferroelectric material 504 is removed from the exposed portions of the semiconductor rods 1004. In some examples, the stage of manufacturing after completion of block 2122 corresponds to the example structure 1802 of FIGS. 18A-18C. Block 2122 is optional and, therefore, may be omitted in some examples.

[0064] At block 2124, the isolation material 904 is deposited to fill the gaps between the separate wordlines 104 and the exposed portions of the semiconductor rods 1004. In some examples, the stage of manufacturing after completion of block 2124 corresponds to the example structure 1902 of FIGS. 19A-19C. Thereafter, the example method 2100 of FIG. 21 ends and manufacturing may proceed to other back-end-of-line processes.

[0065] Although the example method 2100 is described with reference to the flowchart illustrated in FIG. 21, many other methods of manufacturing the example memory array 1000 in accordance with the teachings disclosed herein may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated or combined. Similarly, additional operations may be included in the manufacturing process before, in between or after the blocks shown in FIG. 21.

[0066] The example memory arrays with gate-all-around 3D ferroelectric field transistors disclosed herein may be included in any suitable electronic component. FIGS. 22-26 illustrate various examples of apparatuses that may include any of the example memory arrays disclosed herein.

[0067] Although the example method 2100 is described with reference to the flowchart illustrated in FIG. 21, many other methods of manufacturing the example memory array 1000 in accordance with the teachings disclosed herein may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated or combined. Similarly, additional operations may be included in the manufacturing process before, in between or after the blocks shown in FIG. 20.

[0068] FIG. 22 is a top view of a wafer 2200 and dies 2202 that may include one or more gate-all-around 3D ferroelectric field transistors in a memory array, or may be included in an IC package whose substrate includes one or more gate-all-around 3D ferroelectric field transistors in a memory array (e.g., as discussed below with reference to FIG. 24) in accordance with any of examples disclosed herein. The wafer 2200 may be composed of semiconductor material and may include one or more dies 2202 having IC structures formed on a surface of the wafer 2200. Each of the dies 2202 may be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is complete, the wafer 2200 may undergo a singulation process in which the dies 2202 are separated from one another to provide discrete "chips" of the semiconductor product. The die 2202 may include one or more gate-all-around 3D ferroelectric field transistors in a memory array (e.g., as discussed below with reference to FIG. 23), one or more transistors (e.g., some of the transistors 2340 of FIG. 23, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some examples, the wafer 2200 or the die 2202 may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive- bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 2202. For example, a memory array formed by multiple memory devices may be formed on a same die 2202 as a processing device (e.g., the processing device 2602 of FIG. 26) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0069] FIG. 23 is a cross-sectional side view of an IC device 2300 that may include one or more gate-all-around 3D ferroelectric field transistors in a memory array, or may be included in an IC package whose substrate includes one or more gate-all-around 3D ferroelectric field transistors in a memory array (e.g., as discussed below with reference to FIG. 24), in accordance with any of examples disclosed herein. One or more of the IC devices 2300 may be included in one or more dies 2202 (FIG. 22). The IC device 2300 may be formed on a substrate 2302 (e.g., the wafer 2200 of FIG.

7) and may be included in a die (e.g., the die 2202 of FIG. 7). The substrate 2302 may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The substrate 2302 may include, for example, a crystalline substrate formed using a bulk silicon or a sibcon-on-insulator (SOI) substructure. In some examples, the substrate 2302 may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II- VI, III-V, or IV may also be used to form the substrate 2302. Although a few examples of materials from which the substrate 2302 may be formed are described here, any material that may serve as a foundation for an IC device 2300 may be used. The substrate 2302 may be part of a singulated die (e.g., the dies 2202 of FIG. 22) or a wafer (e.g., the wafer 2200 of FIG. 22).

[0070] The IC device 2300 may include one or more device layers 804 disposed on the substrate 2302. The device layer 2304 may include features of one or more transistors 2340 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 2302. The device layer 2304 may include, for example, one or more source and/or drain (S/D) regions 2320, a gate 2322 to control current flow in the transistors 2340 between the S/D regions 2320, and one or more S/D contacts 2324 to route electrical signals to/from the S/D regions 2320. The transistors 2340 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 2340 are not limited to the type and configuration depicted in FIG. 8 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nano wire transistors.

[0071] Each transistor 2340 may include a gate 2322 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some examples, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.

[0072] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 2340 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

[0073] In some examples, when viewed as a cross-section of the transistor 2340 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other examples, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other examples, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U- shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0074] In some examples, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some examples, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0075] The S/D regions 2320 may be formed within the substrate 2302 adjacent to the gate 2322 of each transistor 2340. The S/D regions 2320 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate 2302 to form the S/D regions 2320. An annealing process that activates the dopants and causes them to diffuse farther into the substrate 2302 may follow the ion-implantation process. In the latter process, the substrate 2302 may first be etched to form recesses at the locations of the S/D regions 2320. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 2320. In some implementations, the S/D regions 2320 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some examples, the S/D regions 2320 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further examples, one or more layers of metal and/or metal alloys may be used to form the S/D regions 2320.

[0076] In some examples, the device layer 2304 may include one or more gate-all-around 3D ferroelectric field transistors in a memory array, in addition to or instead of transistors 2340. A memory array with gate- all-around 3D ferroelectric field transistors included in a device layer 2304 may be referred to as a "front end" device. In some examples, the IC device 2300 may not include any front end memory array. One or more gate-all- around 3D ferroelectric field transistors in a memory array in the device layer 2304 may be coupled to any suitable other ones of the devices in the device layer 2304, to any devices in the metallization stack 2319 (discussed below), and/or to one or more of the conductive contacts 2336 (discussed below). [0077] Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 2340 and/or gate-all-around 3D ferroelectric field transistors in a memory array) of the device layer 2304 through one or more interconnect layers disposed on the device layer 2304 (illustrated in FIG. 23 as interconnect layers 2306-2310).

For example, electrically conductive features of the device layer 2304 (e.g., the gate 2322 and the S/D contacts 2324) may be electrically coupled with the interconnect structures 2328 of the interconnect layers 2306-2310. The one or more interconnect layers 2306-2310 may form a metallization stack (also referred to as an "ILD stack") 2319 of the IC device 2300. In some examples, one or more gate-all-around 3D ferroelectric field transistors in a memory array may be disposed in one or more of the interconnect layers 2306-2310, in accordance with any of the techniques disclosed herein. FIG. 23 illustrates the example memory array 100 in the interconnect layer 2308 for illustration purposes, but any number and structure of memory arrays with gate-all-around 3D ferroelectric field transistors may be included in any one or more of the layers in a metallization stack 2319. A memory array included in the metallization stack 2319 may be referred to as a "back-end" device. In some examples, the IC device 2300 may not include any back-end gate-memory array; in some examples, the IC device 2300 may include both front- and back-end memory arrays. One or more memory arrays in the metallization stack 2319 may be coupled to any suitable ones of the devices in the device layer 2304, and/or to one or more of the conductive contacts 2336 (discussed below).

[0078] The interconnect structures 2328 may be arranged within the interconnect layers 2306-2310 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 2328 depicted in FIG. 23). Although a particular number of interconnect layers 2306-2310 is depicted in FIG. 23, examples of the present disclosure include IC devices having more or fewer interconnect layers than depicted. [0079] In some examples, the interconnect structures 2328 may include lines 2328a and/or vias 2328b filled with an electrically conductive material such as a metal. The lines 2328a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 2302 upon which the device layer 2304 is formed. For example, the lines 2328a may route electrical signals in a direction in and out of the page from the perspective of FIG. 23. The vias 2328b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 2302 upon which the device layer 2304 is formed. In some examples, the vias 2328b may electrically couple lines 2328a of different interconnect layers 2306-2310 together.

[0080] The interconnect layers 2306-2310 may include a dielectric material 1626 disposed between the interconnect structures 2328, as shown in FIG. 25. In some examples, the dielectric material 2326 disposed between the interconnect structures 2328 in different ones of the interconnect layers 2306-2310 may have different compositions; in other examples, the composition of the dielectric material 2326 between different interconnect layers 2306-2310 may be the same.

[0081] A first interconnect layer 2306 (referred to as Metal 1 or "Ml ") may be formed directly on the device layer 2304. In some examples, the first interconnect layer 2306 may include lines l628a and/or vias 2328b, as shown. The lines 2328a of the first interconnect layer 2306 may be coupled with contacts (e.g., the S/D contacts 2324) of the device layer 2304.

[0082] A second interconnect layer 2308 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 2306. In some examples, the second interconnect layer 2308 may include vias 2328b to couple the lines 2328a of the second interconnect layer 2308 with the lines 2328a of the first interconnect layer 2306. Although the lines 2328a and the vias 2328b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 2308) for the sake of clarity, the lines 2328a and the vias 2328b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some examples.

[0083] A third interconnect layer 2310 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 2308 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 2306. In some examples, the interconnect layers that are "higher up" in the metallization stack 2319 in the IC device 2300 (i.e., further away from the device layer 2304) may be thicker.

[0084] The IC device 2300 may include a solder resist material 834 (e.g., polyimide or similar material) and one or more conductive contacts 2336 formed on the interconnect layers 2306-2310. In FIG. 8, the conductive contacts 2336 are illustrated as taking the form of bond pads. The conductive contacts 2336 may be electrically coupled with the interconnect structures 2328 and configured to route the electrical signals of the transistor(s) 840 to other external devices. For example, solder bonds may be formed on the one or more conductive contacts 2336 to mechanically and/or electrically couple a chip including the IC device 2300 with another component (e.g., a circuit board). The IC device 2300 may include additional or alternate structures to route the electrical signals from the interconnect layers 2306-2310; for example, the conductive contacts 2336 may include other analogous features (e.g., posts) that route the electrical signals to external components.

[0085] FIG. 24 is a cross-sectional view of an example IC package 2350 that may include one or more gate-all-around 3D ferroelectric field transistors. The package substrate 2352 may be formed of a dielectric material, and may have conductive pathways extending through the dielectric material between the face 2372 and the face 2374, or between different locations on the face 872, and/or between different locations on the face 2374. These conductive pathways may take the form of any of the interconnects 2328 discussed above with reference to FIG. 23. In some examples, any number of gate-all-around 3D ferroelectric field transistors in a memory array (with any suitable structure) may be included in a package substrate 2352. In some examples, no gate-all-around 3D ferroelectric field transistors may be included in the package substrate 2352.

[0086] The IC package 2350 may include a die 2356 coupled to the package substrate 2352 via conductive contacts 2354 of the die 2356, first- level interconnects 858, and conductive contacts 2360 of the package substrate 2352. The conductive contacts 2360 may be coupled to conductive pathways 862 through the package substrate 2352, allowing circuitry within the die 2356 to electrically couple to various ones of the conductive contacts 2364 or to the gate-all-around 3D ferroelectric field transistors in a memory array (or to other devices included in the package substrate 2352, not shown). The first-level interconnects 2358 illustrated in FIG. 24 are solder bumps, but any suitable first-level interconnects 2358 may be used. As used herein, a "conductive contact" may refer to a portion of conductive material (e.g., metal) serving as an electrical interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

[0087] In some examples, an underfill material 2366 may be disposed between the die 2356 and the package substrate 2352 around the first-level interconnects 858, and a mold compound 2368 may be disposed around the die 2356 and in contact with the package substrate 2352. In some examples, the underfill material 2366 may be the same as the mold compound 2368. Example materials that may be used for the underfill material 2366 and the mold compound 2368 are epoxy mold materials, as suitable. Second-level interconnects 2370 may be coupled to the conductive contacts 2364. The second-level interconnects 2370 illustrated in FIG. 24 are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects 2370 may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second -level interconnects 2370 may be used to couple the IC package 2350 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference to FIG. 10. [0088] In FIG. 24, the IC package 2350 is a flip chip package, which may include gate-all-around 3D ferroelectric field transistors in a memory array in the package substrate 2352. In some examples, any number of gate-all-around 3D ferroelectric field transistors (with any suitable structure) may be included in a package substrate 2352. In some examples, no gate-all-around 3D ferroelectric field transistors may be included in the package substrate 2352. The die 2356 may take the form of any of the examples of the die 2302 discussed herein (e.g., may include any of the examples of the IC device 2300). In some examples, the die 2356 may include one or more gate-all-around 3D ferroelectric field transistors in a memory array (e.g., as discussed above with reference to FIG. 22 and FIG. 23); in other examples, the die 2356 may not include any gate-all-around 3D ferroelectric field transistors.

[0089] Although the IC package 2350 illustrated in FIG. 24 is a flip chip package, other package architectures may be used. For example, the IC package 2350 may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2350 may be a wafer-level chip scale package (WLCSP) or a panel fanout (FO) package. Although a single die 2356 is illustrated in the IC package 2350 of FIG. 24, an IC package 2350 may include multiple dies 2356 (e.g., with one or more of the multiple dies 2356 coupled to gate-all-around 3D ferroelectric field transistors in a memory array included in the package substrate 2352). An IC package 2350 may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face 2372 or the second face 2374 of the package substrate 2352. More generally, an IC package 2350 may include any other active or passive components known in the art.

[0090] FIG. 25 is a cross-sectional side view of an IC device assembly 2500 that may include one or more IC packages or other electronic components (e.g., a die) including one or more gate-all-around 3D

ferroelectric field transistors in a memory array, in accordance with any of the examples disclosed herein. The IC device assembly 2500 includes a number of components disposed on a circuit board 2502 (which may be, e.g., a motherboard). The IC device assembly 2500 includes components disposed on a first face 2540 of the circuit board 2502 and an opposing second face 2542 of the circuit board 2502; generally, components may be disposed on one or both faces 2540 and 2542. Any of the IC packages discussed below with reference to the IC device assembly 2500 may take the form of any of the examples of the IC package 2350 discussed above with reference to FIG. 24 (e.g., may include one or more gate-all-around 3D ferroelectric field transistors in a memory array in a package substrate 2352 or in a die).

[0091] In some examples, the circuit board 2502 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2502. In other examples, the circuit board 2502 may be a non-PCB substrate.

[0092] The IC device assembly 2500 illustrated in FIG. 10 includes a package-on-interposer structure 2536 coupled to the first face 2540 of the circuit board 2502 by coupling components 2516. The coupling components 2516 may electrically and mechanically couple the package-on- interposer structure 2536 to the circuit board 2502, and may include solder balls (as shown in FIG. 215), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0093] The package-on-interposer structure 2536 may include an IC package 2520 coupled to an interposer 2504 by coupling components 2518. The coupling components 2518 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2516. Although a single IC package 2520 is shown in FIG. 10, multiple IC packages may be coupled to the interposer 2504; indeed, additional interposers may be coupled to the interposer 2504. The interposer 2504 may provide an intervening substrate used to bridge the circuit board 2502 and the IC package 2520. The IC package 2520 may be or include, for example, a die (the die 2202 of FIG. 22), an IC device (e.g., the IC device 2500 of FIG. 25), or any other suitable component. Generally, the interposer 2504 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 2504 may couple the IC package 2520 (e.g., a die) to a set of BGA conductive contacts of the coupling components 2516 for coupling to the circuit board 2502. In the example illustrated in FIG. 25, the IC package 2520 and the circuit board 2502 are attached to opposing sides of the interposer 2504; in other examples, the IC package 2520 and the circuit board 2502 may be attached to a same side of the interposer 2504. In some examples, three or more components may be interconnected by way of the interposer 2504.

[0094] The interposer 2504 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some examples, the interposer 2504 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 2504 may include metal vias 2508 and interconnects 2510, including but not limited to through-silicon vias (TSVs) 2506. The interposer 2504 may further include embedded devices 2514, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2504. The package-on-interposer structure 2536 may take the form of any of the package-on-interposer structures known in the art. In some examples, the interposer 2504 may include one or more gate-all-around 3D ferroelectric field transistors in a memory array. [0095] The IC device assembly 2500 may include an IC package 2524 coupled to the first face 2540 of the circuit board 2502 by coupling components 2522. The coupling components 2522 may take the form of any of the examples discussed above with reference to the coupling components 2516, and the IC package 2524 may take the form of any of the examples discussed above with reference to the IC package 2520.

[0096] The IC device assembly 2500 illustrated in FIG. 25 includes a package-on-package structure 2534 coupled to the second face 2542 of the circuit board 2502 by coupling components 2528. The package-on- package structure 2534 may include an IC package 2526 and an IC package 2532 coupled together by coupling components 2530 such that the IC package 2526 is disposed between the circuit board 2502 and the IC package 2532.

The coupling components 2528 and 2530 may take the form of any of the examples of the coupling components 2516 discussed above, and the IC packages 2526 and 2532 may take the form of any of the examples of the IC package 2520 discussed above. The package-on-package structure 2534 may be configured in accordance with any of the package-on-package structures known in the art.

[0097] FIG. 26 is a block diagram of an example electrical device 2600 that may include one or more gate-all-around 3D ferroelectric field transistors in a memory array, in accordance with any of the examples disclosed herein. For example, any suitable ones of the components of the electrical device 2600 may include one or more of the IC packages 2550, IC devices 2500, or dies 2302 disclosed herein. A number of components are illustrated in FIG. 26 as included in the electrical device 2600, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some examples, some or all of the components included in the electrical device 2600 may be attached to one or more motherboards. In some examples, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

[0098] Additionally, in various examples, the electrical device 2600 may not include one or more of the components illustrated in FIG. 26, but the electrical device 2600 may include interface circuitry for coupling to the one or more components. For example, the electrical device 2600 may not include a display device 2606, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2606 may be coupled. In another set of examples, the electrical device 2600 may not include an audio input device 2624 or an audio output device 2608, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2624 or audio output device 2608 may be coupled.

[0099] The communication chip 2612 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any

amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 2612 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2612 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2612 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2612 may operate in accordance with other wireless protocols in other examples. The electrical device 2600 may include an antenna 2622 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

[00100] In some examples, the communication chip 2612 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2612 may include multiple communication chips. For instance, a first communication chip 2612 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2612 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, a first communication chip 2612 may be dedicated to wireless communications, and a second communication chip 2612 may be dedicated to wired

communications.

[00101] The electrical device 2600 may include battery/power circuitry 2614. The battery/power circuitry 2614 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 2600 to an energy source separate from the electrical device 2600 (e.g., AC line power).

[00102] The electrical device 2600 may include a display device 2606 (or corresponding interface circuitry, as discussed above). The display device 2606 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[00103] The electrical device 2600 may include an audio output device 2608 (or corresponding interface circuitry, as discussed above). The audio output device 2608 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.

[00104] The electrical device 2600 may include an audio input device 2624 (or corresponding interface circuitry, as discussed above). The audio input device 2624 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

[00105] The electrical device 2600 may include a GPS device 2611 (or corresponding interface circuitry, as discussed above). The GPS device 2611 may be in communication with a satellite-based system and may receive a location of the electrical device 2600, as known in the art.

[00106] The electrical device 2600 may include an other output device 1110 (or corresponding interface circuitry, as discussed above).

Examples of the other output device 1110 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[00107] The electrical device 2600 may include an other input device 2620 (or corresponding interface circuitry, as discussed above).

Examples of the other input device 2620 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[00108] The electrical device 2600 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some examples, the electrical device 2600 may be any other electronic device that processes data.

[00109] The following paragraphs provide various examples of the examples disclosed herein. [00110] Example 1 includes a ferroelectric memory device, comprising a semiconductor substrate, a semiconductor rod extending in an elongate direction substantially parallel to the semiconductor substrate, a ferroelectric gate insulator coating the semiconductor rod, and a gate conductor adjacent the semiconductor rod, the ferroelectric gate insulator positioned between the gate conductor and the semiconductor rod.

[00111] Example 2 includes the ferroelectric memory device of example 1 , wherein a lateral surface of the gate conductor is in a plane substantially perpendicular to the semiconductor substrate.

[00112] Example 3 includes the ferroelectric memory device of any one of examples 1 or 2, wherein the gate conductor is a first gate conductor, the ferroelectric memory device further including a second gate conductor spaced apart from the first gate conductor, the second gate conductor substantially parallel to the first gate conductor.

[00113] Example 4 includes the ferroelectric memory device of any one of examples 1-3, wherein the first gate conductor is in contact with a first portion of the ferroelectric gate insulator along a first length of the semiconductor rod, the second gate conductor in contact with a second portion of the semiconductor rod along a second length of the semiconductor rod, the second length spaced apart from the first length by a third length of the semiconductor rod.

[00114] Example 5 includes the ferroelectric memory device of any one of examples 1-4, wherein the ferroelectric gate insulator coats the semiconductor rod continuously along the first, second, and third lengths of the semiconductor rod.

[00115] Example 6 includes the ferroelectric memory device of any one of examples 1-4, wherein the third length of the semiconductor rod is not coated by the ferroelectric gate insulator.

[00116] Example 7 includes the ferroelectric memory device of any one of examples 1-6, wherein the first and second gate conductors correspond to first and second wordlines in a memory array. [00117] Example 8 includes the ferroelectric memory device of any one of examples 1-7, further including isolation material in contact with the lateral surface of the gate conductor, the isolation material surrounding the semiconductor rod.

[00118] Example 9 includes the ferroelectric memory device of any one of examples 1-8, wherein the semiconductor rod includes an inner core and an outer wall, the inner core including a dielectric material, the outer wall including a semiconductor material.

[00119] Example 10 includes the ferroelectric memory device of any one of examples 1-9, wherein the semiconductor rod is a first

semiconductor rod and the ferroelectric gate insulator is a first ferroelectric gate insulator, the ferroelectric memory device further including a second semiconductor rod spaced apart from the first semiconductor rod and a second ferroelectric gate insulator coating the second semiconductor rod, the second semiconductor rod extending in the elongate direction substantially parallel to the first semiconductor rod.

[00120] Example 11 includes the ferroelectric memory device of any one of examples 1-10, wherein the first and second semiconductor rods are laterally spaced apart in a plane substantially parallel to the semiconductor substrate.

[00121] Example 12 includes the ferroelectric memory device of any one of examples 1-11, wherein the first and second semiconductor rods are vertically spaced apart in a plane substantially perpendicular to the semiconductor substrate.

[00122] Example 13 includes the ferroelectric memory device of any one of examples 1-12, wherein the gate conductor is in contact with the first ferroelectric gate insulator and the second ferroelectric gate insulator.

[00123] Example 14 includes the ferroelectric memory device of any one of examples 1-13, wherein the first and second semiconductor rods correspond to first and second bitlines in a memory grid. [00124] Example 15 includes the ferroelectric memory device of any one of examples 1-14, wherein the gate conductor surrounds the ferroelectric gate insulator and the semiconductor rod.

[00125] Example 16 includes a non-volatile memory apparatus, comprising a semiconductor substrate, a bitline of a memory array, the bitline extending substantially parallel to the semiconductor substrate and including a semiconductor material, a ferroelectric material surrounding an exterior surface of a portion of the bitline, and a wordline of the memory array, the wordline having a lateral surface oriented substantially perpendicular to the semiconductor substrate, the ferroelectric material positioned between the portion of the bitline and the wordline.

[00126] Example 17 includes the non-volatile memory apparatus of example 16, wherein the wordline corresponds to a gate conductor for a transistor at an intersection of the bitline and the wordline.

[00127] Example 18 includes the non-volatile memory apparatus of any one of examples 16 or 17, further including isolation material in a plane substantially parallel to the lateral surface of the wordline, the isolation material surrounding the bitline and in contact with the wordline.

[00128] Example 19 includes the non-volatile memory apparatus of any one of examples 16-18, wherein the bitline further includes a dielectric material, the semiconductor material coating an outside of the dielectric material.

[00129] Example 20 includes the non-volatile memory apparatus of any one of examples 16-19, wherein the bitline is a first bitline and the wordline is a first wordline, the non-volatile memory apparatus further including a second bitline spaced apart from the first bitline and a second wordline spaced apart from the first wordline.

[00130] Example 21 includes the non-volatile memory apparatus of any one of examples 16-20, wherein the portion of the first bitline is a first portion of the first bitline, the ferroelectric material surrounding an exterior surface of a second portion of the first bitline, the second portion of the first bitline separated from the second wordline by the ferroelectric material, the first and second portions of the first bitline spaced apart by a third portion of the first bitline.

[00131] Example 22 includes the non-volatile memory apparatus of any one of examples 16-21, wherein the ferroelectric material surrounds an exterior surface of the third portion of the first bitline.

[00132] Example 23 includes the non-volatile memory apparatus of any one of examples 16-22, wherein the first and second bitlines are laterally spaced apart in a plane substantially perpendicular to the

semiconductor substrate.

[00133] Example 24 includes the non-volatile memory apparatus of any one of examples 16-23, further including a third bitline, the first and third bitlines are vertically spaced apart in a plane substantially parallel to the semiconductor substrate.

[00134] Example 25 includes the non-volatile memory apparatus of any one of examples 16-24, wherein the first wordline extends around and between the first, second, and third bitlines.

[00135] Example 26 includes the non-volatile memory apparatus of any one of examples 16-25, wherein the first wordline is substantially parallel to the second wordline.

[00136] Example 27 includes the non-volatile memory apparatus of any one of examples 16-26, wherein the wordline encompasses the ferroelectric material surrounding the bitline.

[00137] Example 28 includes a system comprising a processor circuit, and a memory array including a semiconductor substrate, a semiconductor rod extending in an elongate direction substantially parallel to the semiconductor substrate, a ferroelectric gate insulator coating the semiconductor rod, and a gate conductor in contact with the ferroelectric gate insulator.

[00138] Example 29 includes the system of example 28, wherein the memory array includes a transistor associated with an intersection of the semiconductor rod and the gate conductor. [00139] Example 30 includes the system of any one of examples 28-29, wherein a lateral surface of the gate conductor is in a plane

substantially perpendicular to the semiconductor substrate.

[00140] Example 31 includes the system of any one of examples 28-30, wherein the gate conductor is a first gate conductor, the memory array further including a second gate conductor spaced apart from the first gate conductor, the second gate conductor substantially parallel to the first gate conductor.

[00141] Example 32 includes the system of any one of examples 28-31, wherein the first gate conductor is in contact with a first portion of the ferroelectric gate insulator along a first length of the semiconductor rod, the second gate conductor in contact with a second portion of the ferroelectric gate insulator along a second length of the semiconductor rod, the second length spaced apart from the first length by a third length of the semiconductor rod.

[00142] Example 33 includes the system of any one of examples 28-32, wherein the ferroelectric gate insulator coats the semiconductor rod continuously along the first, second, and third lengths of the semiconductor rod.

[00143] Example 34 includes the system of any one of examples 28-32, wherein the third length of the semiconductor rod is not coated by the ferroelectric gate insulator.

[00144] Example 35 includes the system of any one of examples 28-34, wherein the first and second gate conductors correspond to first and second wordlines in the memory array.

[00145] Example 36 includes the system of any one of examples 28-35, further including isolation material in contact with the lateral surface of the gate conductor, the isolation material surrounding the semiconductor rod.

[00146] Example 37 includes the system of any one of examples 28-36, wherein the semiconductor rod includes an internal core and an outer wall surrounding the internal core, the internal core including a dielectric material, the outer wall including a semiconductor material. [00147] Example 38 includes the system of any one of examples 28-37, wherein the semiconductor rod is a first semiconductor rod and the ferroelectric gate insulator is a first ferroelectric gate insulator, the memory array further including a second semiconductor rod spaced apart from the first semiconductor rod and a second ferroelectric gate insulator coating the second semiconductor rod, the second semiconductor rod extending in an elongate direction substantially parallel to the first semiconductor rod.

[00148] Example 39 includes the system of any one of examples 28-38, wherein the first and second semiconductor rods are laterally spaced apart in a plane substantially parallel to the semiconductor substrate.

[00149] Example 40 includes the system of any one of examples 28-39, wherein the first and second semiconductor rods are vertically spaced apart in a plane substantially perpendicular to the semiconductor substrate.

[00150] Example 41 includes the system of any one of examples 28-40, wherein the gate conductor is in contact with both the first ferroelectric gate insulator and the second ferroelectric gate insulator.

[00151] Example 42 includes the system of any one of examples 28-41, wherein the first and second semiconductor rods correspond to first and second bitlines in the memory array.

[00152] Example 43 includes the system of any one of examples 28-42, wherein the gate conductor surrounds the ferroelectric gate insulator and the semiconductor rod.

[00153] Example 44 includes a method to manufacture a memory device, comprising forming a semiconductor rod spaced apart from and substantially parallel to a semiconductor substrate, coating an exterior surface of the semiconductor rod with a ferroelectric material, and forming a gate conductor on the ferroelectric material.

[00154] Example 45 includes the method of example 44, wherein the forming of the semiconductor rod includes alternately depositing layers of a first material and a second material, the second material associated with the semiconductor rod, the layers of the first and second materials being substantially parallel to the semiconductor substrate, etching trenches through the layers of the first and second materials, sidewalls of the trenches corresponding to sidewalls of the semiconductor rod, and removing the first material.

[00155] Example 46 includes the method of any one of examples 44-45, wherein the first material is a first isolation material and the second material is a second isolation material.

[00156] Example 47 includes the method of any one of examples 44-46, further including coating an exterior surface of the second isolation material with a semiconductor material.

[00157] Example 48 includes the method of any one of examples 44-45, wherein the first material is an isolation material and the second material is a semiconductor material.

[00158] Example 49 includes the method of any one of examples 44-48, further including forming an array of semiconductor rods arranged in multiple rows and multiple columns, the array of semiconductor rods including the semiconductor rod, the semiconductor rods substantially parallel to one another, and forming a plurality of gate conductors including the gate conductor, the plurality of gate conductors extending transversely to the semiconductor rods and substantially parallel to one another.

[00159] Example 50 includes the method of any one of examples 44-49, wherein the forming of the plurality of gate conductors includes depositing a conductive material around the semiconductor rods, the conductive material filling gaps between the rows and the columns of the array of semiconductor rods, and etching the conductive material to define spaces between separate regions of the conductive material, the separate regions corresponding to the plurality of gate conductors, the spaces extending substantially perpendicularly to the semiconductor substrate.

[00160] Example 51 includes the method of any one of examples 44-50, further including etching the ferroelectric material exposed to the spaces between ones of the plurality of gate conductors. [00161] Example 52 includes the method of any one of examples 44-51, further including depositing isolation material in spaces between ones of the plurality of gate conductors.

[00162] From the foregoing, it will be appreciated that example methods, apparatus and articles of manufacture have been disclosed herein provide a highly scalable effective cell area for relatively high density memory arrays that can be manufactured at a relatively low cost because the fabrication does not involve a critical lithography process. In particular, example memory arrays include elongate semiconductor rods that extend substantially parallel to a semiconductor substrate (e.g., a semiconductor wafer). The

semiconductor rods correspond to the bitlines in the memory array that are intersected by generally planar gate conductors corresponding to the wordlines in the memory array. The gate conductors are oriented substantially perpendicular to the semiconductor rods and completely surround the semiconductor rods, thereby resulting in gate-all-around transistors. Further, the gate insulator between the semiconductor rods and the gate conductor s may be a ferroelectric material.

[00163] Although certain example methods, apparatus and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus and articles of manufacture fairly falling within the scope of the claims of this patent.

Claims

What Is Claimed Is:

1. A ferroelectric memory device, comprising:

a semiconductor substrate;

a semiconductor rod extending in an elongate direction substantially parallel to the semiconductor substrate;

a ferroelectric gate insulator coating the semiconductor rod; and a gate conductor adjacent the semiconductor rod, the ferroelectric gate insulator positioned between the gate conductor and the semiconductor rod.

2. The ferroelectric memory device of claim 1, wherein a lateral surface of the gate conductor is in a plane substantially perpendicular to the semiconductor substrate.

3. The ferroelectric memory device of claim 2, wherein the gate conductor is a first gate conductor, the ferroelectric memory device further including a second gate conductor spaced apart from the first gate conductor, the second gate conductor substantially parallel to the first gate conductor.

4. The ferroelectric memory device of claim 3, wherein the first gate conductor is in contact with a first portion of the ferroelectric gate insulator along a first length of the semiconductor rod, the second gate conductor in contact with a second portion of the semiconductor rod along a second length of the semiconductor rod, the second length spaced apart from the first length by a third length of the semiconductor rod.

5. The ferroelectric memory device of claim 4, wherein the ferroelectric gate insulator coats the semiconductor rod continuously along the first, second, and third lengths of the semiconductor rod.

6. The ferroelectric memory device of claim 4, wherein the third length of the semiconductor rod is not coated by the ferroelectric gate insulator.

7. The ferroelectric memory device of any one of claims 1-6, wherein the semiconductor rod includes an inner core and an outer wall, the inner core including a dielectric material, the outer wall including a semiconductor material.

8. The ferroelectric memory device of any one of claims 1-6, wherein the semiconductor rod is a first semiconductor rod and the ferroelectric gate insulator is a first ferroelectric gate insulator, the ferroelectric memory device further including a second semiconductor rod spaced apart from the first semiconductor rod and a second ferroelectric gate insulator coating the second semiconductor rod, the second semiconductor rod extending in the elongate direction substantially parallel to the first semiconductor rod.

9. The ferroelectric memory device of claim 8, wherein the first and second semiconductor rods are laterally spaced apart in a plane substantially parallel to the semiconductor substrate.

10. The ferroelectric memory device of claim 8, wherein the first and second semiconductor rods are vertically spaced apart in a plane substantially perpendicular to the semiconductor substrate.

11. The ferroelectric memory device of claim 8, wherein the gate conductor is in contact with the first ferroelectric gate insulator and the second ferroelectric gate insulator.

12. The ferroelectric memory device of any one of claims 1-6, wherein the gate conductor surrounds the ferroelectric gate insulator and the semiconductor rod.

13. A non-volatile memory apparatus, comprising:

a semiconductor substrate;

a bitline of a memory array, the bitline extending substantially parallel to the semiconductor substrate and including a semiconductor material;

a ferroelectric material surrounding an exterior surface of a portion of the bitline; and

a wordline of the memory array, the wordline having a lateral surface oriented substantially perpendicular to the semiconductor substrate, the ferroelectric material positioned between the portion of the bitline and the wordline.

14. The non-volatile memory apparatus of claim 13, wherein the bitline further includes a dielectric material, the semiconductor material coating an outside of the dielectric material.

15. The non-volatile memory apparatus of any one of claims 13 or 14, wherein the bitline is a first bitline and the wordline is a first wordline, the non-volatile memory apparatus further including a second bitline spaced apart from the first bitline and a second wordline spaced apart from the first wordline.

16. The non-volatile memory apparatus of claim 15, wherein the first and second bitlines are laterally spaced apart in a plane substantially perpendicular to the semiconductor substrate.

17. The non-volatile memory apparatus of claim 16, further including a third bitline, the first and third bitlines are vertically spaced apart in a plane substantially parallel to the semiconductor substrate.

18. A system comprising:

a processor circuit; and

a memory array including:

a semiconductor substrate;

a ferroelectric gate insulator coating the semiconductor rod; and a gate conductor in contact with the ferroelectric gate insulator.

19. The system of claim 18, wherein the memory array includes a transistor associated with an intersection of the semiconductor rod and the gate conductor.

20. The system of any one of claims 18 or 19, wherein a lateral surface of the gate conductor is in a plane substantially perpendicular to the semiconductor substrate.

21. A method to manufacture a memory device, comprising:

forming a semiconductor rod spaced apart from and substantially parallel to a semiconductor substrate;

coating an exterior surface of the semiconductor rod with a ferroelectric material; and

forming a gate conductor on the ferroelectric material.

22. The method of claim 21, wherein the forming of the semiconductor rod includes:

alternately depositing layers of a first material and a second material, the second material associated with the semiconductor rod, the layers of the first and second materials being substantially parallel to the semiconductor substrate; etching trenches through the layers of the first and second materials, sidewalls of the trenches corresponding to sidewalls of the semiconductor rod; and

removing the first material.

23. The method of claim 22, wherein the first material is an isolation material and the second material is a semiconductor material.

24. The method of claim 21, further including:

forming an array of semiconductor rods arranged in multiple rows and multiple columns, the array of semiconductor rods including the

semiconductor rod, the semiconductor rods substantially parallel to one another; and

forming a plurality of gate conductors including the gate conductor, the plurality of gate conductors extending transversely to the semiconductor rods and substantially parallel to one another.

25. The method of claim 24, wherein the forming of the plurality of gate conductors includes:

depositing a conductive material around the semiconductor rods, the conductive material filling gaps between the rows and the columns of the array of semiconductor rods; and

etching the conductive material to define spaces between separate regions of the conductive material, the separate regions corresponding to the plurality of gate conductors, the spaces extending substantially

perpendicularly to the semiconductor substrate.