WO2019127185A1

WO2019127185A1 - Method and system for on-line condition monitoring of dc-link capacitor in power converter

Info

Publication number: WO2019127185A1
Application number: PCT/CN2017/119254
Authority: WO
Inventors: Junjie GE; Jinlei MENG; Wenliang Zhang; Tinho LI
Original assignee: Abb Schweiz Ag
Priority date: 2017-12-28
Filing date: 2017-12-28
Publication date: 2019-07-04

Abstract

Embodiments of the present disclosure relates to a method and system for on-line condition monitoring of a direct current (DC) -link capacitor in a power converter. The method includes (a) detecting a first waveform of voltage at the DC-link capacitor generated when the power converter operates with an output voltage reference for a plurality of switching periods. The method also includes (b) determining, based on an estimated parameter related to condition monitoring of the DC-link capacitor, an estimated second waveform of voltage at the DC-link capacitor for at least one of the plurality of switching periods; and (c) determining a differential waveform between the first and second waveforms with respect to the at least one switching period of the step (b). In parallel to the step (a), the steps (b) and (c) are repeated by adjusting the estimated parameter step by step until the differential waveform approaches below a predetermined threshold. The method also includes (d) determining, based on the estimated parameter, a target parameter related to the condition monitoring of the DC-link capacitor.

Description

METHOD AND SYSTEM FOR ON-LINE CONDITION MONITORING OF DC-LINK CAPACITOR IN POWER CONVERTER

TECHNICAL FIELD

Example embodiments of the present disclosure generally relate to capacitor monitoring and more particularly, to a method and system for on-line condition monitoring of a direct current (DC) -link capacitor in a power converter.

BACKGROUND

Capacitors, especially electrolytic capacitors (E-Cap) , are widely used in power electronic converters, specifically in the direct-current (DC) -link circuit. However, the capacitors will degrade with time and fail more frequently than other components in the power converters, which will threaten reliability of the power converters. To ensure reliability of power converters, it is desirable to carry out condition monitoring of the capacitors in the power converters so as to enable the indication of future failure occurrences and preventive maintenance.

The capacitor degradation usually manifests by a decrease in capacitance and an increase in equivalent series resistance (ESR) . Earlier detection of the ESR increase or capacitance decrease allows for preventive mitigation actions, such as scheduling shutdown and repairs. Moreover, it is also helpful with evaluation of the expected operational time until failure may happen. Preventing the increase of the ESR or decrease of the capacitance over a specified level provides maintaining the quality of converted power and protects the power converter from failure of DC-link capacitor (s) .

Methods for condition monitoring have been studied for a long time but most of them fail to be applied in real products. Most of the methods require additional hardware such as an external switching circuit, capacitor current sensor, or enhanced voltage sensor which includes an additional sample processing circuit. The impact on the main circuit, mechanical structure, or control circuit may lead to a redesign of the power converters, which is undesirable. Some condition monitoring methods may not require additional hardware, but provide low precision and/or have limited applications in some special scenarios or some certain converters. Moreover, some methods will suspend the normal operations of the power converters.

SUMMARY

Example embodiments of the present disclosure propose a solution for on-line condition monitoring of a direct current (DC) -link capacitor in a power converter.

In a first aspect, example embodiments of the present disclosure provide a method for on-line condition monitoring of a DC-link capacitor in a power converter. The method includes (a) detecting a first waveform of voltage at the DC-link capacitor generated when the power converter operates with an output voltage reference for a plurality of switching periods. The method also includes (b) determining, based on an estimated parameter related to condition monitoring of the DC-link capacitor, an estimated second waveform of voltage at the DC-link capacitor for at least one of the plurality of switching periods; and (c) determining a differential waveform between the first and second waveforms with respect to the at least one switching period of the step (b) . In parallel to the step (a) , the steps (b) and (c) are repeated by adjusting the estimated parameter step by step until the differential waveform approaches below a predetermined threshold. The method also includes (d) determining, based on the estimated parameter, a target parameter related to the condition monitoring of the DC-link capacitor.

In some embodiments, determining the second waveform further comprises determining the second waveform further based on current flowing through the DC-link capacitor.

In some embodiments, the current flowing through the DC-link capacitor is determined based on input current and output current of the power converter or is detected by at least one sensor.

In some embodiments, the target parameter includes at least one of the following: capacitance of the DC-link capacitor and equivalent series resistance (ESR) of the DC-link capacitor.

In some embodiments, the DC-link capacitor includes at least one electrolytic capacitor.

In a second aspect, example embodiments of the present disclosure provide a system for on-line condition monitoring of a DC-link capacitor in a power converter. The system includes a detecting unit configured to perform a step (a) of detect a first waveform of voltage at the DC-link capacitor generated when the power converter operates with an output voltage reference for a plurality of switching periods. The system also includes a determining unit configured to perform steps of (b) determining, based on an estimated parameter related to condition monitoring of the DC-link capacitor, an estimated second waveform of voltage at the DC-link capacitor for at least one of the plurality of switching periods, and (c) determining a differential waveform between the first and second waveforms with respect to the at least one switching period. In parallel to the step (a) , the steps (b) and (c) are repeated by adjusting the estimated parameter step by step until the differential waveform approaches below a predetermined threshold. The determining unit is also configured to perform a step of (d) determining, based on the estimated parameter, a target parameter related to the condition monitoring of the DC-link capacitor.

In some embodiments, the determining unit is configured to determine the second waveform further based on current flowing through the DC-link capacitor.

In a third aspect, example embodiments of the present disclosure provide a computer readable medium having instructions stored thereon, the instructions, when executed on at least one processor, cause the at least one processor to perform the method of the first aspect.

In a fourth aspect, example embodiments of the present disclosure provide a computer program product being tangibly stored on a computer readable storage medium and comprising instructions which, when executed on at least one processor, cause the at least one processor to perform the method of the first aspect.

In a fifth aspect, example embodiments of the present disclosure provide an Internet of Things (IoT) system. The system includes a power converter, and a system for on-line condition monitoring of a DC-link capacitor in the power converter of the second aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

Through the following detailed descriptions with reference to the accompanying drawings, the above and other objectives, features and advantages of the example embodiments disclosed herein will become more comprehensible. In the drawings, several example embodiments disclosed herein will be illustrated in an example and in a non-limiting manner, wherein:

Figs. 1A-1B illustrate curve graphs showing example degradation of ESR and capacitance of a DC-link capacitor;

Fig. 2 illustrates a diagram of an equivalent model of a capacitor;

Fig. 3 illustrates a system for on-line condition monitoring of a DC-link capacitor of a power converter in accordance with some example embodiments of the present disclosure;

Fig. 4 illustrates a schematic diagram of an injection to an output voltage reference used in a power converter in accordance with some example embodiments of the present disclosure;

Fig. 5A illustrates diagrams showing respective waveforms of voltage and current at a DC-link capacitor in accordance with some example embodiments of the present disclosure;

Fig. 5B illustrates diagrams showing respective waveforms of voltage and current of the waveforms of Fig. 5A during a period of time in accordance with some example embodiments of the present disclosure;

Fig. 6A illustrates a diagram showing waveforms of a first waveform of voltage and an estimated second waveform of voltage in accordance with some example embodiments of the present disclosure;

Fig. 6B illustrates a diagram showing a differential waveform between the first and second waveforms of Fig. 6A in accordance with some example embodiments of the present disclosure;

Fig. 7A illustrates a diagram showing waveforms of a first waveform of voltage and an estimated second waveform of voltage in accordance with some other example embodiments of the present disclosure;

Fig. 7B illustrates a diagram showing a differential waveform between the first and second waveforms of Fig. 7A in accordance with some other example embodiments of the present disclosure;

Fig. 8 illustrates a block diagram showing a detailed structure of the determining unit in the system of Fig. 3 in accordance with some example embodiments of the present disclosure;

Fig. 9 illustrates a curve chart showing how an estimated capacitance is adjusted to approach the target capacitance in accordance with some example embodiments of the present disclosure;

Fig. 10A illustrates a curve chart of capacitance values determined according to an example embodiment of the present disclosure at different real capacitance values of DC-link capacitors;

Fig. 10B illustrates a curve chart of capacitance errors at different real capacitance values of DC-link capacitors in accordance with some example embodiments of the present disclosure;

Fig. 11A illustrates a diagram showing waveforms of a first waveform of voltage and an estimated second waveform of voltage in accordance with some example embodiments of the present disclosure;

Fig. 11B illustrates a diagram showing a differential waveform between the first and second waveforms of Fig. 11A in accordance with some example embodiments of the present disclosure;

Fig. 12A illustrates a diagram showing waveforms of a first waveform of voltage and an estimated second waveform of voltage in accordance with some other example embodiments of the present disclosure;

Fig. 12B illustrates a diagram showing a differential waveform between the first and second waveforms of Fig. 12A in accordance with some other example embodiments of the present disclosure;

Fig. 13 illustrates a block diagram showing a detailed structure of the determining unit in the system of Fig. 3 in accordance with some example embodiments of the present disclosure;

Fig. 14 illustrates a curve chart showing how an estimated ESR is adjusted to approach the target ESR in accordance with some example embodiments of the present disclosure;

Fig. 15A illustrates a curve chart of ESR values determined according to an example embodiment of the present disclosure at different real capacitance values of DC-link capacitors;

Fig. 15B illustrates a curve chart of ESR errors at different real ESR values of DC-link capacitors in accordance with some example embodiments of the present disclosure; and

Fig. 16 illustrates a flowchart of a process of on-line condition monitoring of a capacitor in accordance with some example embodiments of the present disclosure.

Throughout the drawings, the same or corresponding reference symbols refer to the same or corresponding parts.

DETAILED DESCRIPTION

The subject matter described herein will now be discussed with reference to several example embodiments. These embodiments are discussed only for the purpose of enabling those skilled persons in the art to better understand and thus implement the subject matter described herein, rather than suggesting any limitations on the scope of the subject matter.

The term “comprises” or “includes” and its variants are to be read as open terms that mean “includes, but is not limited to. ” The term “or” is to be read as “and/or” unless the context clearly indicates otherwise. The term “based on” is to be read as “based at least in part on. ” The term “being operable to” is to mean a function, an action, a motion or a state can be achieved by an operation induced by a user or an external mechanism. The term “one embodiment” and “an embodiment” are to be read as “at least one embodiment. ” The term “another embodiment” is to be read as “at least one other embodiment. ”

Unless specified or limited otherwise, the terms “mounted, ” “connected, ” “supported, ” and “coupled” and variations thereof are used broadly and encompass direct and indirect mountings, connections, supports, and couplings. Furthermore, “connected” and “coupled” are not restricted to physical or mechanical connections or couplings. In the description below, like reference numerals and labels are used to describe the same, similar or corresponding parts in the Figures. Other definitions, explicit and implicit, may be included below.

As mentioned above, a decrease in capacitance and an increase in equivalent series resistance (ESR) can be used as indicators to manifest degradation of a DC-link capacitor in a power converter. Figs. 1A-1B illustrate

curves

101 and 102 showing degradation of ESR and capacitance of a DC-link capacitor, respectively. The

curves

101 and 102 show a lifetime model of the DC-link capacitor. As shown, the capacitance value of the capacitor (C) , e.g. electrolytic capacitor, will decrease over time from its initial value C ₀, while the ESR of the capacitor will increase over time from its initial value R ₀. The widely accepted end-of-life criterion is that the ESR increases to double of the initial value (R ₀) and/or the capacitance decreases to 80%of the initial value (C ₀) . At that time (T _EoL) , the capacitor may be replaced with a new one to guarantee the reliability of the power converter.

It is important to detect the capacitance and/or ESR so as to carry out condition monitoring of the capacitor. Although many efforts have been devoted to the condition monitoring of capacitors, most of existing condition monitoring methods have disadvantages in various aspects which hinder the methods to be applied in real products. For example, most of the methods require additional hardware, leading to a redesign of the power converters. Some condition monitoring methods may not require additional hardware, but provide low precision and/or have limited applications in some special scenarios or some certain converters. Moreover, some methods will suspend the normal operations of the power converters.

According to embodiments of the present disclosure, there is provided a solution for on-line condition monitoring of a direct current (DC) -link capacitor in a power converter. In this solution, the power converter operates with an output voltage reference for a plurality of switching periods to detect a real waveform of voltage at the DC-link capacitor. An estimated waveform of voltage generated at the DC-link capacitor is determined for at least one of the switching periods based on an estimated parameter. The differential waveform between the real waveform and the estimated waveform is determined and used to adjust the estimated parameter. The above process is repeated until the differential waveform is below a predetermined threshold (for example, zero or any other small value) . Then the estimated parameter obtained after a number of times of adjustment can be used to determine a target parameter related to condition monitoring of the DC-link capacitor. In this way, it is helpful for assessing the condition monitoring of the DC-link capacitor in a closed-loop control process without suspending the operations of the power converter. Example embodiments of the present disclosure will be described in detail below with reference to the figures.

An equivalent model of a capacitor will be first introduced before the detailed description of the on-line monitoring of a DC-link capacitor. Fig. 2 shows such an equivalent model 200. In the equivalent model 200, a DC-link capacitor may be equivalent to a resistor 210 and an effective capacitor 220 connected in series to the resistor 210. The equivalent model 200 can be considered as an equivalent model for a single capacitor or an overall equivalent model for multiple capacitors deployed in a DC-link circuit of a power converter.

In Fig. 2, i _in represents input current of the power converter, i _C represents current flowing through the DC-link capacitor, i _out represents output current of the power converter, U _C represents voltage at the effective capacitor 220, and U _dc represents DC bus voltage. Depending on the equivalent model of the DC-link capacitor, capacitance “C” and ESR “R” of the DC-link capacitor may be determined as follows:

Fig. 3 illustrates a system 300 for on-line condition monitoring of a DC-link capacitor of a power converter in accordance with some example embodiments of the present disclosure. Herein the DC-link capacitor to be monitored may include any type of one or more capacitors in the power converter. One example of the DC-link capacitor is an electrolytic capacitor (E-Cap) . The power converter may also be any type of power converters, such as a DC-DC converter, a DC-alternate current (AC) converter, an AC-DC converter, and the like.

The system 300 includes a power converter 301 and a system 302 for on-line condition monitoring of a DC-link capacitor included in the power converter 301. The power converter 301 is connected wiredly or wirelessly to the system 302. In some embodiments, the system 300 may be deployed as an Internet-of-Things (IoT) system. Although one power converter is shown, in some embodiments, more than one power converter may be included and connected to the system 302 to monitor the condition of their DC-link capacitors. In other examples, more than one system 302 may be included to monitor the respective power converters.

The system 302 includes a detecting unit 310 and a determining unit 320. The detecting unit 310 is configured to detect a first waveform of voltage at the DC-link capacitor generated when the power converter operates with an output voltage reference for a plurality of switching periods. The voltage at the DC-link capacitor is represented as U _dc, which is typically equal to the output voltage reference in use. In operations of the power converter, a control signal is used to control the voltage at the DC-link capacitor of the power converter to be the output voltage reference. Specifically, the control signal is used to control a switching element in the power converter to be on and off during the switching periods, so that a certain level of voltage is generated at the DC-link capacitor.

In some embodiments, the voltage at the DC-link capacitor may be measured and sampled as the first waveform by a voltage sensor and processing circuit that is originally included in the power converter 301 and then provided to the detecting unit 310 of the system 302. In some other embodiments, the detecting unit 310 may be constructed to measure and sample the voltage at the DC-link capacitor.

The first waveform of voltage is provided to the determining unit 320 to determine a target parameter related to condition monitoring of the DC-link capacitor in the power converter 301. In some embodiments, in order to reduce the precision requirement of the voltage sensor and improve performance of the on-line condition monitoring, the voltage injection is used. Specifically, if it is assumed that the power converter normally operates with a normal output voltage reference U _r0, the voltage injection can be realized by changing the normal output voltage reference to be an output voltage reference U _dc.

In some embodiments, the normal output voltage reference U _r0 may be adjusted by injecting an additional signal into a control signal (such as a Pulse Width Modulation (PWM) control signal) that is used normally to control the voltage at the DC-link capacitor. Fig. 4 illustrates a schematic diagram of a voltage injection. As shown, the normal output voltage reference U _r0 as indicated by 410 is changed to another output voltage reference as indicated by 420 by superimposing an additional signal with a voltage of u _r. In some examples, the injected signal may be a low frequency signal, such as a 100 Hz square wave.

In some embodiments of the voltage injection, the power converter operates with the output voltage reference U _dc that is different from the normal output voltage reference U _r0 for a plurality of switching periods. To ensure the proper operations of the power converter, the output voltage reference U _dc deviates from the normal output voltage reference U _r0 within a predetermined range. The predetermined range may be configured dependent on an acceptable or tolerable range of output voltage in the power converter. As such, during the switching periods for capacitor condition monitoring, the power converter can still work properly.

Generally, the normal voltage at the DC-link capacitor is a relatively static voltage during the normal operations. By changing the normal output voltage reference, the variation of the voltage at the DC-link will be larger and can be used for analyzing the condition monitoring of the DC-link capacitor. The large variation of the voltage at the DC-link may also reduce the precision requirement of the voltage sensor that is used to detect the waveform at the DC-link capacitor.

Fig. 5A shows example waveforms of voltage 510 and current 520 at the DC-link capacitor. It can be seen that the voltage 510 and current 520 are at relatively static levels during normal operations. When the output voltage reference is changed for the condition monitoring during a time period of around 0.2s to 0.3s by means of voltage injection, there is an obvious variation in the voltage 510 as well as in the current 520. The variation can be seen more clearly in Fig. 5B, which shows waveforms of voltage 510 and current 520 during the specific period of 0.2s to 0.3s.

Upon obtaining, from the detecting unit 310, the first waveform of voltage generated for one or more switching periods, the determining unit 320 is configured to determine a target parameter related to condition monitoring of the DC-link capacitor in the power converter 301 based on the detected first waveform of voltage. The target parameter may include capacitance and/or ESR of the DC-link capacitor.

According to embodiments of the present disclosure, a closed-loop control process is applied in the determining unit 320 to determine the target parameter. The determining unit 320 includes a waveform estimator 322 and a parameter estimator 324 to implement the closed-loop control process. Specifically, the waveform estimator 322 determines, based on an estimated parameter (such as capacitance or ESR) related to the condition monitoring of the DC-link capacitor, an estimated second waveform of voltage at the DC-link capacitor for at least one of the plurality of switching periods. The estimated second waveform of voltage is represented as U _es. The second waveform is provided to the parameter estimator 324 for adjusting the estimated parameter. The adjustment is based on a differential waveform between the real first waveform and the estimated second waveform.

If there is a relatively large differential waveform between the first and second waveforms, the parameter estimator 324 provides the new estimated parameter to the waveform estimator 322 for estimating the second waveform. In parallel to the detecting in the detecting unit 310, the determining of the second waveform of voltage and the differential waveform is repeated in the determining unit 320 by adjusting the estimated parameter for a plurality of times until the differential waveform approaches below a predetermined threshold. If the differential waveform is within the predetermined threshold, the parameter estimator 324 determines that the current estimated parameter is a target parameter that indicates the condition monitoring of the DC-link capacitor. In embodiments of the present disclosure, the waveform estimator 322 and the parameter estimator 324 of the determining unit 320 work in a closed loop to determine the target parameter.

As mentioned, a parameter related to the condition monitoring of the DC-link capacitor may include capacitance and/or an ESR. The determination of the target capacitance “C” and the ESR “R” in the closed-loop control process will be described in detailed below, respectively.

In operation, the parameter estimator 324 may initially set the estimated capacitance, for example, as a random value, a value that was monitored previously for the same DC-link capacitor, or any other value. At the initial stage, the initial estimated capacitance is provided to the waveform estimator 322 to determine an estimated second waveform of voltage U _es at the DC-link capacitor. The estimation of the second waveform of voltage U _es may be performed based on the above Equation (1) , for example, by multiplying the integration of current ic flowing through the DC-link capacitor with an inverse of the estimated capacitance. The second waveform of voltage U _es is then provided to the parameter estimator 324 and is compared with the first waveform of voltage U _dc. The estimated capacitance is then adjusted based on the differential waveform between the first and second waveforms.

Fig. 6A illustrates an example where the variation of the second waveform 620 of voltage U _es is smaller than the variation of the first waveform 610 of voltage U _dc. The differential waveform 630 is shown in Fig. 6B, where Δu _err represents a variation of the differential waveform 630 and may be determined as double of the relatively stable voltage within a half switching cycle 632 of the differential waveform 630 in this example. If Δu _err is greater than a predetermined threshold and the differential waveform indicates that variation of the second waveform 620 of voltage U _es is smaller than the variation of the first waveform 610 of voltage U _dc, it can be determined that the estimated capacitance is larger than the target capacitance. In this case, the parameter estimator 324 may decrease the estimated capacitance.

Fig. 7A illustrates an example where the variation of the second waveform 720 of voltage U _es is larger than the variation of the first waveform 710 of voltage U _dc. The differential waveform 730 is shown in Fig. 7B, where Δu _err represents a variation of the differential waveform 730 and may be determined as an absolute value of double of the relatively stable voltage within a half switching cycle 732 of the differential waveform 730 in this example. If Δu _err is greater than a predetermined threshold and the differential waveform indicates that variation of the second waveform 720 of voltage U _es is larger than the variation of the first waveform 710 of voltage U _dc, it can be determined that the estimated capacitance is smaller than the target capacitance. In this case, the parameter estimator 324 may increase the estimated capacitance.

In some embodiments, the estimated capacitance may be increased or decreased by a predetermined value, or by a value that is determined based on the variation of the differential waveform Δu _err. After being adjusted, the estimated capacitance is provided again to the waveform estimator 322 for estimating a new second waveform. The second waveform is then passed to the parameter estimator 324 and is compared with the first waveform (which may be the real-time waveform of voltage detected from the power converter 301) . If the parameter estimator 324 determines that the differential waveform between the first and second waveforms approaches below the predetermined threshold (for example, Δu _err is zero or below a predetermined small value) , it indicates that the current estimated capacitance is equal to the real capacitance of the DC-link capacitor or there is a small (and acceptable) error between the estimated capacitance and the real capacitance. The parameter estimator 324 may then determine the target capacitance as the estimated capacitance.

The determination of the target capacitance of the DC-link capacitor is described above. There are various ways to implement the functionalities of determining the target capacitance in the determining unit 320. Fig. 8 illustrates an example of a detailed structure of the determining unit 320 in the system 302. It would be appreciated that the elements of the determining unit 320 are provided merely for purpose of illustration. The functionalities of the elements can be implemented in other ways.

As shown, the parameter estimator 324 provides an estimated capacitance to the waveform estimator 322. In the example of Fig. 8, an inverse of the estimated capacitance is provided. The waveform estimator 322 may estimate the second waveform of voltage for one or more switching periods based on the estimated capacitance C and current i _C flowing through the DC-link capacitor. The estimation of the second waveform of voltage may be performed based on the above Equation (1) .

Specifically, the waveform estimator 322 includes an integration element 822 to calculate an integration of the current i _C flowing through the DC-link capacitor. The waveform estimator 322 includes an adder 821 to calculate the current i _C from the input current i _in and output current i _out of the power converter 301. The current i _C may be calculated as subtracting the output current i _out from the input current i _in. The input current i _in and output current i _out may be detected by the detecting unit 310. In some embodiments, instead of indirectly calculating the current i _C from the input currenti _in and output current i _out, at least one sensor may be used to directly detect the current i _C.

The waveform estimator 322 further includes a multiplying unit 823 to determine the second waveform of voltage U _es by multiplying the inverse of the estimated capacitance with the integration of the current i _C. The second waveform of voltage U _es is provided to the parameter estimator 324. The parameter estimator 324 includes an adder 812 to determine a differential waveform between the first waveform of voltage U _dc from the detecting unit 310 and the second waveform of voltage U _es.

The differential waveform between the first and second waveforms may be used to adjust the estimated capacitance in the parameter estimator 324. Specifically, the differential waveform is passed to zero-order holder element 813 and then an integration element 814 to determine the variation of the differential waveform Δu _err. The injected voltage u _r is subtracted by the normal output voltage reference U _r0 in an adder 815 of the parameter estimator 324 to control a quantizer 816 to output a signal indicates the sign of the variation of the differential waveform Δu _err.

The sign signal and the variation of the differential waveform Δu _err are combined in an adder 817 to control the adjustment of the estimated capacitance. In this example, a proportional integral controller 818 is used to the adjustment of the estimated capacitance. The increase or decrease of the estimated capacitance depending on the differential waveform has been described above. The adjusted estimated capacitance may be used to initiate another round of determining the second waveform and the adjustment of the estimated capacitance in the waveform estimator 322 and the parameter estimator 324. If the differential waveform is determined to be within a predetermined threshold, the controller 818 may output the current estimated capacitance as the target capacitance.

According to the embodiments of the present disclosure, by adjusting the estimated capacitance step by step in a closed loop, it is possible to approach the target capacitance for the DC-link capacitor in a precise manner. Fig. 9 illustrates a curve 910 showing how the estimated capacitance is adjusted to approach the real capacitance of the DC-link capacitor. In this example, the real capacitance is 50 uF. The estimated capacitance is initially set as a value smaller than 50 uF and then is increased in a short time and becomes stable in a value that is quite closed to 50 uF. Thus, the target capacitance determined from the estimated capacitance is close to or substantially equal to the real capacitance of the DC-link capacitor.

Fig. 10A shows a curve 1010 of target capacitance values determined according to an example embodiment of the present disclosure at different real capacitance values. Fig. 10B shows a curve 1020 of the capacitance errors at different real capacitance values. As can be seen, the capacitance errors can be constrained to a low level, for example, lower than 0.5%in this example. With the high precision, the on-line condition monitoring of the present disclosure can be applied in real applications.

The closed-loop process of determining the target ESR is similar as that of determining the target capacitance described above. In operation, the parameter 324 may initially set the estimated ESR, for example, as a random value, a value that was monitored previously for the same DC-link capacitor, or any other value. At the initial stage, the initial estimated ESR is provided to the waveform estimator 322 to determine an estimated second waveform of voltage U _es at the DC-link capacitor. The estimation of the second waveform of voltage U _es may be performed based on the above Equations (1) and (2) , by the integration of the current flowing through the DC-link capacitor plus the estimation ESR multiplied by the current. The second waveform of voltage U _es is then provided to the parameter estimator 324 and is compared with the first waveform of voltage U _dc. The estimated ESR is then adjusted based on the differential waveform between the first and second waveforms.

Fig. 11A illustrates an example where the variation of the second waveform 1120 of voltage U _es is smaller than the variation of the first waveform 1110 of voltage U _dc. The differential waveform 1130 is shown in Fig. 11B, where Δu _err represents a variation of the differential waveform 1130 and may be determined as double of a voltage within a half switching cycle 1132 of the differential waveform 1130. If Δu _err is greater than a predetermined threshold and the differential waveform indicates that variation of the second waveform 1120 of voltage U _es is smaller than the variation of the first waveform 1110 of voltage U _dc, it can be determined that the estimated ESR is smaller than the target ESR. In this case, the parameter estimator 324 may increase the estimated ESR.

Fig. 12A illustrates an example where the variation of the second waveform 1220 of voltage U _es is larger than the variation of the first waveform 1210 of voltage U _dc. The differential waveform 1230 is shown in Fig. 12B, where Δu _err represents a variation of the differential waveform 1230 and may be determined as an absolute value of a voltage within a half switching cycle 1232 of the differential waveform 1230. If Δu _err is greater than a predetermined threshold and the differential waveform indicates that variation of the second waveform 1220 of voltage U _es is larger than the variation of the first waveform 1210 of voltage U _dc, it can be determined that the estimated ESR is larger than the target ESR. In this case, the parameter estimator 324 may decrease the estimated ESR.

The determination of the target ESR of the DC-link capacitor is described above. There are various ways to implement the functionalities of determining the target ESR in the determining unit 320. Fig. 13 illustrates an example of a detailed structure of the determining unit 320 in the system 302. It would be appreciated that the elements of the determining unit 320 are provided merely for purpose of illustration. The functionalities of the elements can be implemented in other ways.

As shown, the capacitor estimator provides an estimated ESR to the waveform estimator 322. The estimated ESR is represented as R _ESR. The waveform estimator 322 may estimate the second waveform of voltage for one or more switching periods based on the estimated ESR R _ESR and current i _C flowing through the DC-link capacitor. The estimation of the second waveform of voltage may be performed based on the above Equations (1) and (2) .

Specifically, the waveform estimator 322 includes an integration element 1322 to calculate the integration of the current i _C flowing through the DC-link capacitor. The waveform estimator 322 includes an adder 1321 to calculate the current i _C from the input current i _in and output current i _out of the power converter 301. The current i _C may be calculated as subtracting the output current i _out from the input current i _in. The input current i _in and output current i _out may be detected by the detecting unit 310. In some embodiments, instead of indirectly calculating the current i _C from the input current i _in and output current i _out, at least one sensor may be used to directly detect the current i _C.

The waveform estimator 322 further includes a multiplying unit 823 to determine the voltage across the ESR of the DC-link capacitor by multiplying the current i _C with the estimated ESR. An adder 1324 of the waveform estimator 322 sums the integration of the current i _C and the voltage across the ESR up to determine the second wavefonn of voltage U _es. The second waveform of voltage U _es is provided to the parameter estimator 324. The parameter estimator 324 includes an adder 1311 to determine a differential waveform between the first waveform of voltage U _dc from the detecting unit 310 and the second waveform of voltage U _es.

The differential waveform between the first and second waveforms is used to adjust the estimated capacitance in the parameter estimator 324. Specifically, the differential waveform is passed to a low passband filter 1312 and the filtering result is subtracted from the differential waveform by an adder 1313 to determine the variation of the differential waveform Δu _err. The current i _C is used to control a quantizer 1314 to output a signal indicates the sign of the variation of the differential waveform Δu _err.

The sign signal and the variation of the differential waveform Δu _err are combined in an adder 1315 to control the adjustment of the estimated ESR. In this example, a proportional integral controller 1316 is used to the adjustment of the estimated ESR. The increase or decrease of the estimated ESR depending on the differential waveform has been described above. The adjusted estimated ESR may be used to initiate another round of determining the second waveform and the adjustment of the estimated ESR in the waveform estimator 322 and the parameter estimator 324. If the differential waveform is determined to be within a predetermined threshold, the controller 818 may output the current estimated ESR as the target ESR.

According to the embodiments of the present disclosure, by adjusting the estimated ESR step by step in a closed loop, it is possible to approach the target ESR for the DC-link capacitor in a precise manner. Fig. 14 illustrates a curve 1410 showing how the estimated ESR is adjusted to approach the real ESR of the DC-link capacitor. In this example, the real ESR is 50 m Ω. The estimated ESR is initially set as a value smaller than 50 m Ω and then is increased in a short time and becomes stable in a value that is quite closed to 50 m Ω. Thus, the target ESR determined from the estimated ESR is closed to or substantially equal to the real ESR of the DC-link capacitor.

Fig. 15A shows a curve 1515 of target ESR values determined according to an example embodiment of the present disclosure at different real ESR values. Fig. 15B shows a curve 1520 of the ESR errors at different real ESR values. As can be seen, the ESR errors can be constrained to a low level, for example, lower than 1.5%in this example. With the high precision, the on-line condition monitoring of the present disclosure can be applied in real applications.

According to the embodiments of the present disclosure, the capacitance and/or ESR of the DC-link capacitor in the power converter can be determined to indicate the condition monitoring of the DC-link capacitor. In some embodiments, when the target capacitance and/or ESR of the DC-link capacitor are determined, it is also possible to determine changes of the capacitance and/or ESR during a period of time. In some embodiments, since the changes of the capacitance and/or ESR over time may follow respective curves, such as those shown in Figs. 1A and 1B, when the current capacitance and/or ESR is determined, it is possible to predict when the DC-link capacitor is about to reach the end of life. An alert may be issued to the maintainer of the power converter to notify of possible future failure and preventive maintenance, so that he/she can replace the DC-link capacitor in time.

By applying the on-line condition monitoring of the present disclosure, the capacitance and/or ESR can be calculated in a precise manner, without suspending the operations of the power converter. The on-line condition monitoring may also be implemented without requiring additional hardware to be introduced into the power converter, avoiding a redesign of the power converter. In some examples, the system for on-line condition monitoring can be implemented in software, for example, as a program included in a device with processing capability, and/or firmware. The on-line condition monitoring can be widely applied for any types of power converters deployed in any scenarios.

Fig. 16 illustrates a flowchart of a process 1600 of on-line condition monitoring of a capacitor in accordance with some example embodiments of the present disclosure. In some embodiments, the process 1600 may be implemented in software and/or firmware by means of, for example, the system 302.

At 1610, a first waveform of voltage at the DC-link capacitor is detected, the first waveform of voltage being generated when the power converter operates with an output voltage reference for a plurality of switching periods. At 1620, it is determined, based on an estimated parameter related to condition monitoring of the DC-link capacitor, an estimated second waveform of voltage at the DC-link capacitor for at least one of the plurality of switching periods. At 1630, a differential waveform between the first and second waveforms is determined with respect to the at least one switching period.

At 1640, it is determined whether the differential waveform is below a predetermined threshold. If the differential waveform is above the predetermined threshold, at 1650, the estimated parameter is adjusted. Then the process 1600 proceeds to 1620 to repeating the determining of the second waveform based on the estimated parameter after being adjusted and the determining of the differential waveform. The first waveform of waveform is determined in parallel of the repeating and provided to determine the differential waveform with the new determined second waveform.

If the differential waveform is below the predetermined threshold, the process 1600 proceeds to 1660, where a target parameter related to the condition monitoring of the DC-link capacitor is determined based on the estimated parameter.

In some embodiments, determining the second waveform may further include determining the second waveform further based on current flowing through the DC-link capacitor.

Generally, various embodiments of the present disclosure may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device. While various aspects of embodiments of the present disclosure are illustrated and described as block diagrams, flowcharts, or using some other pictorial representation, it will be appreciated that the blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

The present disclosure also provides at least one computer program product tangibly stored on a non-transitory computer readable storage medium. The computer program product includes computer-executable instructions, such as those included in program modules, being executed in a device on a target real or virtual processor, to carry out the process or method as described above with reference to Fig. 3. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, or the like that perform particular tasks or implement particular abstract data types. The functionality of the program modules may be combined or split between program modules as desired in various embodiments. Machine-executable instructions for program modules may be executed within a local or distributed device. In a distributed device, program modules may be located in both local and remote storage media.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowcharts and/or block diagrams to be implemented. The program code may execute entirely on a machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

The above program code may be embodied on a machine readable medium, which may be any tangible medium that may contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine readable medium may be a machine readable signal medium or a machine readable storage medium. A machine readable medium may include but not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine readable storage medium would include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM) , a read-only memory (ROM) , an erasable programmable read-only memory (EPROM or Flash memory) , an optical fiber, a portable compact disc read-only memory (CD-ROM) , an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

Further, while operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are contained in the above discussions, these should not be construed as limitations on the scope of the present disclosure, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in the context of separate embodiments may also be implemented in combination in a single embodiment. On the other hand, various features that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable sub-combination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

A method for on-line condition monitoring of a direct current (DC) -link capacitor in a power converter, comprising:

(a) detecting a first waveform of voltage at the DC-link capacitor generated when the power converter operates with an output voltage reference for a plurality of switching periods;

(b) determining, based on an estimated parameter related to condition monitoring of the DC-link capacitor, an estimated second waveform of voltage at the DC-link capacitor for at least one of the plurality of switching periods;

(c) determining a differential waveform between the first and second waveforms with respect to the at least one switching period of the step (b) ;

in parallel to the step (a) , repeating the steps (b) and (c) by adjusting the estimated parameter step by step until the differential waveform approaches below a predetermined threshold; and

(d) determining, based on the estimated parameter, a target parameter related to the condition monitoring of the DC-link capacitor.
The method of claim 1, wherein determining the second waveform further comprises:

determining the second waveform further based on current flowing through the DC-link capacitor.
The method of claim 2, wherein the current flowing through the DC-link capacitor is determined based on input current and output current of the power converter or is detected by at least one sensor.
The method of any of claims 1 to 3, wherein the target parameter includes at least one of the following: capacitance of the DC-link capacitor and equivalent series resistance (ESR) of the DC-link capacitor.
The method of any of claims 1 to 4, wherein the DC-link capacitor includes at least one electrolytic capacitor.
A system for on-line condition monitoring of a direct current (DC) -link capacitor in a power converter, comprising:

a detecting unit configured to perform a step (a) of detect a first waveform of voltage at the DC-link capacitor generated when the power converter operates with an output voltage reference for a plurality of switching periods; and

a determining unit configured to perform steps of

(b) determining, based on an estimated parameter related to condition monitoring of the DC-link capacitor, an estimated second waveform of voltage at the DC-link capacitor for at least one of the plurality of switching periods,

(c) determining a differential waveform between the first and second waveforms with respect to the at least one switching period,

wherein in parallel to the step (a) , the steps (b) and (c) are repeated by adjusting the estimated parameter step by step until the differential waveform approaches below a predetermined threshold, and

(d) determining, based on the estimated parameter, a target parameter related to the condition monitoring of the DC-link capacitor.
The system of claim 7, wherein the determining unit is configured to determine the second waveform further based on current flowing through the DC-link capacitor.
The system of claim 7, wherein the current flowing through the DC-link capacitor is determined based on input current and output current of the power converter or is detected by at least one sensor.
The system of any of claims 6 to 8, wherein the target parameter includes at least one of the following: capacitance of the DC-link capacitor and equivalent series resistance (ESR) of the DC-link capacitor.
The system of any of claims 6 to 9, wherein the DC-link capacitor includes at least one electrolytic capacitor.
A computer readable medium having instructions stored thereon, the instructions, when executed on at least one processor, cause the at least one processor to perform the method according to any of claims 1 to 5.
A computer program product being tangibly stored on a computer readable storage medium and comprising instructions which, when executed on at least one processor, cause the at least one processor to perform the method according to any of claims 1 to 5.
An Internet of Things (IoT) system comprising:

a power converter; and

a system for on-line condition monitoring of a direct current (DC) -link capacitor in the power converter according to any of claims 6 to 10.