WO2019117904A1

WO2019117904A1 - Vertical thyristors for cross-point dynamic memories

Info

Publication number: WO2019117904A1
Application number: PCT/US2017/066274
Authority: WO
Inventors: Abhishek A. Sharma; Charles C. Kuo; Shigeki Tomishima
Original assignee: Intel Corporation
Priority date: 2017-12-14
Filing date: 2017-12-14
Publication date: 2019-06-20

Abstract

A memory device comprises a top electrode and a vertical thyristor comprising a stack of alternating P-type material layers and N-type material layers. The memory device also includes a bottom electrode, wherein the vertical thyristor is coupled between back end of line materials including a source line and a bit line. A plurality of memory devices form a vertical thyristor cross-point DRAM array with 4F2 or less density.

Description

VERTICAL THYRISTORS FOR CROSS-POINT DYNAMIC MEMORIES

TECHNICAL FIELD

Embodiments of the disclosure are in the field of integrated circuit structures and, in particular, vertical thyristors for cross-point dynamic memories.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.

Variability in conventional and state-of-the-art fabrication processes may limit the possibility to further extend density through such processes. Consequently, fabrication of the functional components needed for future technology nodes may require the introduction of new methodologies or the integration of new technologies in current fabrication processes or in place of current fabrication processes.

Thus, significant improvements are still needed in the area of memory device manufacture and operation.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a cross-section of a memory device according to one embodiment.

Figure 2 illustrates an angled three-dimensional view of a vertical thyristor cross-point DRAM array.

Figure 3 illustrates an IV curve for the vertical thyristor memory devices.

Figure 4 illustrates a cross-sectional diagram of a BE vertical layer thyristor (VLT) cross- point array next to a standard logic area on a silicon chip.

Figure 5 illustrates a wafer bonding process flow for fabricating a vertical thyristor cross- point DRAM array in a BEOL process in accordance with a first embodiment of the present disclosure.

Figure 6 illustrates an epitaxial growth process flow for fabricating a vertical thyristor cross-point DRAM array in a BEOL process in accordance with a second embodiment uses of the present disclosure. Figure 7 illustrates damascene process flow for fabricating a vertical thyristor cross-point DRAM array in a BEOL process in accordance with a third embodiment of the present disclosure.

Figures 8A and 8B illustrate a wafer composed of a semiconductor material and including one or more dies having integrated circuit (IC) structures formed on a surface of the wafer.

Figure 9 illustrates a block diagram of an electronic system, in accordance with an embodiment of the present disclosure.

Figure 10 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more vertical thyristor memory devices, in accordance with one or more of the embodiments disclosed herein.

Figure 11 illustrates a computing device in accordance with one implementation of the disclosure.

DESCRIPTION OF THE EMBODIMENTS

Vertical thyristors for cross-point dynamic memories is described. In the following description, numerous specific details are set forth, such as specific material and tooling regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as“upper”, “lower”,“above”,“below,”“bottom,” and“top” refer to directions in the drawings to which reference is made. Terms such as“front”,“back”,“rear”, and“side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import. Embodiments described herein may be directed to front-end-of-line (FEOL)

semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

Embodiments described herein may be directed to back-end-of-line (BEOL)

semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modem IC processes, more than 10 metal layers may be added in the BEOL.

Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.

In accordance with an embodiment of the present disclosure, one or more embodiments are directed to structures and architectures for a vertical thyristor cross-point DRAM array. Such embodiments may have applications for one or more of cross-point memory, embedded memory, memory, and memory arrays.

To provide context, a state-of-the-art vertical layer thyristor (VLT) has been proposed that would be fabricated based on existing CMOS silicon wafer processes, which occurs in the front end. Although the state-of-the-art VLT cell unit size is an improvement over the original VLT cell size and shows the possibility for an area of 4 F2 (F: min. feat size), the state-of-the- art VLT poses challenges as well. For example the VLT has a complicated Si front end fabrication process, which faces the challenge of producing deep trenches, narrow isolation, vertical dopant implementation and buried tungsten (W). In addition, the VLT has a high resistive cathode that is fabricated by doped Si and connects through a buried W plug. This results in a high resistive connection with a large junction capacitance. These factors may pose larger problems during actual Si chip operations.

In accordance with an embodiment of the present disclosure, a transistor-less array, e.g. with 4F2 or less density, is fabricated using the back end of line (BEOL) processes and materials. According to one or more embodiments, a memory element is provided comprising a vertical layer thyristor, hereinafter referred to as a vertical thyristor. In a further embodiment, a cross-point array includes a vertical thyristor memory element located a cross-section of each bit line and source line.

The memory device 100 includes a vertical thyristor 102 that operates by changing resistance across a stack of alternating P-type material layers and N-type material layers (also referred to herein as P-type layers and N-type layers). In one embodiment, the stack comprises four layers of alternating P-type layers and N-type layers: a first P-type layer 102A, a first N-type layer 102B, a second P-type layer 102C, and a second N-type layer 102D. The vertical thyristor 102 also includes a top electrode 108 above the layer stack and a bottom electrode 110 below the layer stack. According to one aspect, the vertical thyristor 102 is coupled between back end of line materials, which one embodiment, include a first set of conductive lines 104 and a second set of conductive lines 106. Accordingly, the vertical thyristor 102 is fabricated using the BEOL processes and materials, rather than using FEOL CMOS processes and materials.

In one embodiment, the vertical thyristor 102 is composed of a material selected from the group consisting of amorphous, poly crystalline or single crystal type semiconductors, and oxide semiconductors. More specifically, the vertical thyristor 102 is composed of a material selected from the group consisting of Si, Ge, III-V, and GaN, where III-V include InAs, InGaAs, InP, AlGaAs. In one embodiment, the oxide semiconductors are composed of a material selected from the group consisting of ZnO, InO, CoO, Cu20, NiO, IGZO, and the like.

In one embodiment, the doping range for each of the layers in the vertical thyristor may range from 1E16 cm3 to 1E21 cm3. In one embodiment, each of the P-type and N-type layers have different band gaps due to the fabrication processes of the present disclosure, as described below.

In an embodiment, the top electrode 108 and the bottom electrode 110 are each composed of a material selected from the group consisting of titanium nitride, tantalum nitride, tungsten, palladium and platinum. In one such embodiment, the top electrode 108 and the bottom electrode 110 are composed of a same material.

Figure 2 illustrates an angled three-dimensional view of a vertical thyristor cross-point DRAM array. More specifically, a further embodiment provides a BEOL vertical thyristor cross- point DRAM array 200 comprising a plurality memory elements 102 of stacks of alternating P- type material layers and N-type material layers.

Referring to Figure 2, the vertical thyristor cross-point array 200 includes a first plurality of conductive lines 104 along a first direction on a substrate. In an embodiment, the first plurality of conductive lines 104 is a plurality of bit lines. In an embodiment, the first plurality of conductive lines 104 are coupled to individual top electrodes 108 of the vertical thyristor memory devices 102. A second plurality of conductive lines 106 is along a second direction on the substrate orthogonal to the first direction. In an embodiment, the second plurality of conductive lines 106 is a plurality of source lines. In an embodiment, the second plurality of conductive lines 106 are above a substrate (not shown) and are coupled to individual bottom electrodes 110 of the vertical thyristor memory devices 102. Individual vertical thyristor memory devices 102 are located at cross-sections of the first plurality of conductive lines 104 and the second plurality of conductive lines 106, and each comprise the stack of alternating P-type material layers and N-type material layers 102A-102D. The vertical thyristor memory devices 102 are coupled between the first and second set of conductive lines 104 and 106 through the respective top and bottom electrodes 108 and 110. In another embodiment, the first plurality of conductive lines 104 may comprise source lines and the second plurality of conductive lines 106 may comprise bit lines.

The vertical thyristor memory devices 102 are similar to selectors in that they have and on state and an off state, where the on state is used as a first memory state, and the off state is used as a second memory state.

Figure 3 illustrates an IV curve for the vertical thyristor memory devices 102. The vertical thyristor memory devices 102 switch back and forth between an on state and an off state depending on a bias that is applied. Thus, the vertical thyristor memory devices 102 include an on state current and an off state current, as shown. The on state current is slightly higher than the off state current. For the vertical thyristor memory devices 102 that are in the on state, they remain in the on state as long as a holding current (IH) flowing to the memory devices 102 is maintained. Once the on state current drops below the holding current, the vertical thyristor memory devices 102 switch to the off state. For vertical thyristor memory devices 102 in the off state, they remain in the off state. The value of the holding current is slightly higher than a threshold current (ITH) of the off state current. In order to store a state of the vertical thyristor memory devices 102 the holding current is maintained. However, after the bias is removed, the vertical thyristor memory devices 102 remain in the on state for some amount of time, which is referred to as the holding time (e.g., milliseconds), before returning to the off state, and this is one way of reading the vertical thyristor memory devices 102. To write to one of the vertical thyristor memory devices 102, a voltage is placed on the bit line greater than the threshold voltage Vt. For example, if the threshold voltage Vt is .9 volts, then 1 volt may be placed on the bit line and 0 volts may be placed on the source line. This will turn the thyristor on and swing the device to a low resistance state. This low resistance state will be maintained as long as the current through the thyristor is above a certain holding current. This is how‘ is written onto the device. In order to write‘O’, the bitline can either be held at 0V or a slight negative voltage (between 0V and -0.5V). This will discharge the thyristor and store‘O’.

Figure 4 illustrates a cross-sectional diagram of a BEOL vertical layer thyristor (VLT) cross-point array next to a standard logic area on a silicon chip. As shown, various metal layers M0 through M6 are formed over a substrate 400, although any number of metal layers may be used. A memory area 402 is formed adjacent to a standard logic area 404 (e.g., CMOS logic). In this particular example, the vertical thyristor cross-point DRAM array 406 has been formed using BEOL processes in metal layers Ml through M4. Cathodes and bit lines are formed in Ml, and word lines are formed in M4. Various vias may be used to connect the metal layers to one another. The present embodiments require simple routing and are less resistive compared to silicon connections.

According to the disclosed embodiments, several simplified fabrication processes are provided to make a vertical thyristor device in a BEOL process. In each of the fabrication processes, a standard FEOL CMOS process is used to create logic devices. The vertical thyristor memory cell devices are then formed in the BEOL process. Finally, a cathode connection is made available by a routing via a lower metal line. Each of the fabrication processes are described below with respect to figures 5, 6 and 7. A first embodiment uses a wafer bonding process after FEOL. A second embodiment uses epitaxial growth, and a third embodiment uses an inter-level dielectrics (IL) and a damascene process instead of copper.

Figure 5 illustrates a wafer bonding process flow for fabricating a vertical thyristor cross- point DRAM array in a BEOL process in accordance with a first embodiment of the present disclosure. The second embodiment utilizes only one wafer/die. Referring to Figures 4 and 5, the wafer bonding process may begin by forming sense logic on a first die/wafer up to a desired metal layer, e.g., M0 (block 500). Source lines 410 and bottom electrodes 112 are formed on an adjacent higher metal layer, e.g. Ml (block 502). Although the source lines 410 and sense logic are described as being on metal layers M0 and Ml, the process may be configured to form the source lines 410 and sense logic on any layer.

On a second die, the vertical thyristor layer stack is formed by growing epitaxial layers of alternating P-types layers and N-types layers (e.g., such that P-type layer 406A is at the bottom of the stack) (block 504). It should be understood that growing the alternating layers also includes alternating N-types layers and P-types layers. In one embodiment, dopants may be implanted during the growth of each of the epitaxial layers. For example, P-type dopants, such as boron, aluminum and the like, may be implanted during the growth of P-type layers, while N- types dopants, such as arsenic, phosphorus and the like, are implanted during growth of the N- types layers. At this point, the vertical thyristor stack is a blanket layer.

The first and second die are positioned to face each other and then bonded together (block 506). In one embodiment, the first and second die are also bonded together using vias. Chemical mechanical polishing is performed on the backside of the second wafer to remove unwanted conductive or dielectric materials on the second wafer (block 508).

In one embodiment, an additional dopant may be used on the top surface of the second wafer to enable sufficient contact with the bottom electrodes 112 (block 510). For example, a layer of P++ may be implanted on the top of the second wafer.

The next process step is silicidation for passivation to deposit a metal such as nickel, cobalt, or tungsten, and the thyristor blanket layer stack is annealed to form a layer of cobalt silicide, nickel silicide, tungsten silicide or the like (block 512). The process then continues with traditional metals to form top electrodes 114 and bit lines 408.

Individual thyristor memory cell locations are defined using lithographic patterning and etching to form trenches in the thyristor blanket layer that separate the thyristor memory cells to form a thyristor memory array (block 514). An inter-level dielectrics (ILD) layer 404, e.g., silicon dioxide, is deposited over the thyristor memory array and polished (block 516).

Figure 6 illustrates an epitaxial growth process flow for fabricating a vertical thyristor cross-point DRAM array in a BEOL process in accordance with a second embodiment uses of the present disclosure. Referring to Figures 4 and 6, the wafer bonding process may begin by forming sense logic on a first die/wafer up to a desired metal layer, e.g., M0 (block 600). Source lines 410 are formed on an adjacent higher metal layer, e.g. Ml (block 602). Although the source lines 410 and sense logic are described as being on metal layers M0 and Ml, the process may be configured to form the source lines 410 and sense logic on any layer.

Next, an inter-level dielectrics (ILD) layer, e.g., silicon dioxide, and an etch-stop layer (e.g., SiN) are sequentially deposited and polished on the same metal layer (e.g., Ml) as the bit lines 410, followed by deposition of an oxide layer (block 604). Bottom electrodes 112 and vias are formed over the oxide layer (block 606). In one embodiment, short vias may be formed between the etch stop layer and Ml.

Next, trenches are formed in the ILD layer in locations to be occupied by the vertical thyristor layer stacks (block 608). The vertical thyristor stacks are formed by growing epitaxial layers of alternating N-types layers and P-types layers (block 610). In one embodiment, dopants may be implanted during the growth of each of the epitaxial layers. For example, P-type dopants, such as boron, aluminum and the like, may be implanted during the growth of P-type layers, while N-types dopants, such as arsenic, phosphorus and the like, are implanted during growth of the N-types layers. The next process step is silicidation for passivation to deposit a metal such as nickel, cobalt, or tungsten, and then the vertical thyristor layer stacks are annealed to form a layer of cobalt silicide, nickel silicide, tungsten silicide or the like (block 612). The process then continues with traditional metals to form top electrodes and bit lines. Individual thyristor memory cell locations are defined using lithographic patterning and etching to form a thyristor memory array (block 614).

Figure 7 illustrates damascene process flow for fabricating a vertical thyristor cross-point DRAM array in a BEOL process in accordance with a third embodiment of the present disclosure. The third embodiment utilizes only one wafer/die. Referring to Figures 4 and 7, the wafer bonding process may begin by forming sense logic on a first die/wafer up to a desired metal layer, e.g., M0 (block 700). Source lines 410 are formed on an adjacent higher metal layer, e.g. Ml (block 702). Although the source lines 410 and sense logic are described as being on metal layers M0 and Ml, the process may be configured to form the source lines 410 and sense logic on any layer.

An etch-stop layer (e.g., SiN) is deposited and polished on the same metal layer (e.g.,

Ml) as the source lines 410 (block 704). A thick inter-level dielectrics (ILD) layer is deposited and polished over the etch stop layer (block 706). A Damascene etch is performed for memory definition by forming trenches in the ILD down to the etch-stop layer (block 708). Bottom electrodes 112 and vias are formed in the etch stop layer in locations to be occupied by the vertical thyristor layer stacks (block 712). In one embodiment, short vias may be formed between the etch stop layer and Ml.

The vertical thyristor stacks are formed by growing epitaxial layers of alternating N- types layers and P-types layers or alternating P-types layers and N-types layers in the trenches (block 714). In one embodiment, dopants may be implanted during the growth of each of the epitaxial layers. For example, P-type dopants, such as boron, aluminum and the like, may be implanted during the growth of P-type layers, while N-types dopants, such as arsenic, phosphorus and the like, are implanted during growth of the N-types layers.

The next process step is silicidation for passivation (block 716) in which a metal is deposited such as nickel, cobalt, or tungsten, and then the vertical thyristor layer stacks are annealed to form a layer of cobalt silicide, nickel silicide, tungsten silicide or the like. The process then continues with traditional metals. Individual thyristor memory cell locations are defined using lithographic patterning and etching (block 718).

In an embodiment, the conductive lines 105, 106, 408 and 410 such as bit lines and source lines described above, are composed of one or more metal or metal-containing conductive materials. The conductive interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, interconnect lines or simply interconnects. In a particular embodiment, each of the interconnect lines includes a barrier layer and a conductive fill material. In an

embodiment, the barrier layer is composed of a metal nitride material, such as tantalum nitride or titanium nitride. In an embodiment, the conductive fill material is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof.

Conductive lines, such as bit lines and source lines described above, may be fabricated as a grating structure, where the term“grating” is used herein to refer to a tight pitch grating structure. In one such embodiment, the tight pitch is not achievable directly through

conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning, as is known in the art. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like patterns described herein may have conductive lines spaced at a constant pitch and having a constant width. The pattern may be fabricated by a pitch halving or pitch quartering, or other pitch division, approach.

In an embodiment, examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (Si02)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

In an embodiment, as is also used throughout the present description, lithographic operations may be performed using l93nm immersion lithography (il93), extreme ultra-violet (EUV) and/or electron beam direct write (EBDW) lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, a lithographic mask is a trilayer mask composed of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer.

It is to be appreciated that the layers and materials described in association with embodiments herein are typically formed on or above an underlying semiconductor substrate. In an embodiment, an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, poly crystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, although not depicted, structures described herein may be fabricated as or on underlying lower level back end of line (BEOL) interconnect layers.

The integrated circuit structures described herein may be included in an electronic device. As an example of one such apparatus, Figures 9A and 9B are top views of a wafer and dies that include one or more a vertical thyristor cross-point DRAM arrays, in accordance with one or more of the embodiments disclosed herein.

Referring to Figures 8A and 8B, a wafer 800 may be composed of semiconductor material and may include one or more dies 802 having integrated circuit (IC) structures formed on a surface of the wafer 800. Each of the dies 802 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more vertical thyristor cross- point DRAM arrays, such as described above. After the fabrication of the semiconductor product is complete, the wafer 800 may undergo a singulation process in which each of the dies 802 is separated from one another to provide discrete“chips” of the semiconductor product. In particular, structures that include embedded non-volatile memory structures having an independently scaled selector as disclosed herein may take the form of the wafer 800 (e.g., not singulated) or the form of the die 802 (e.g., singulated). The die 802 may include one or more vertical thyristor cross-point DRAM arrays and/or supporting circuitry to route electrical signals, as well as any other IC components. In some embodiments, the wafer 800 or the die 802 may include an additional memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 802. For example, a memory array formed by multiple memory devices may be formed on a same die 802 as a processing device or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.

Figure 9 illustrates a block diagram of an electronic system 900, in accordance with an embodiment of the present disclosure. The electronic system 900 can correspond to, for example, a portable system, a computer system, a process control system, or any other system that utilizes a processor and an associated memory. The electronic system 900 may include a microprocessor 902 (having a processor 904 and control unit 906), a memory device 908, and an input/output device 909 (it is to be appreciated that the electronic system 900 may have a plurality of processors, control units, memory device units and/or input/output devices in various embodiments). In one embodiment, the electronic system 900 has a set of instructions that define operations which are to be performed on data by the processor 904, as well as, other transactions between the processor 904, the memory device 908, and the input/output device 909. The control unit 906 coordinates the operations of the processor 904, the memory device 908 and the input/output device 909 by cycling through a set of operations that cause instructions to be retrieved from the memory device 908 and executed. The memory device 908 can include a non-volatile memory cell as described in the present description. In an embodiment, the memory device 908 is embedded in the microprocessor 902, as depicted in Figure 9. In an embodiment, the processor 904, or another component of electronic system 900, includes one or more vertical thyristor cross-point DRAM arrays such as those described herein.

Figure 11 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more vertical thyristor memory devices, in accordance with one or more of the embodiments disclosed herein.

Referring to Figure 10, an IC device assembly 1000 includes components having one or more integrated circuit structures described herein. The IC device assembly 1000 includes a number of components disposed on a circuit board 1002 (which may be, e.g., a motherboard). The IC device assembly 1000 includes components disposed on a first face 1040 of the circuit board 1002 and an opposing second face 1042 of the circuit board 1002. Generally, components may be disposed on one or both faces 1040 and 1042. In particular, any suitable ones of the components of the IC device assembly 1000 may include a number of vertical thyristor memory elements, such as disclosed herein.

In some embodiments, the circuit board 1002 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1002. In other embodiments, the circuit board 1002 may be a non-PCB substrate.

The IC device assembly 1000 illustrated in Figure 10 includes a package-on-interposer structure 1036 coupled to the first face 1040 of the circuit board 1002 by coupling components 1016. The coupling components 1016 may electrically and mechanically couple the package-on- interposer structure 1036 to the circuit board 1002, and may include solder balls (as shown in Figure 10), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure 1036 may include an IC package 1020 coupled to an interposer 1004 by coupling components 1018. The coupling components 1018 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1016. Although a single IC package 1020 is shown in Figure 10, multiple IC packages may be coupled to the interposer 1004. It is to be appreciated that additional interposers may be coupled to the interposer 1004. The interposer 1004 may provide an intervening substrate used to bridge the circuit board 1002 and the IC package 1020. The IC package 1020 may be or include, for example, a die (the die 1002 of Figure 10B), or any other suitable component. Generally, the interposer 1004 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 1004 may couple the IC package 1020 (e.g., a die) to a ball grid array (BGA) of the coupling components 1016 for coupling to the circuit board 1002. In the embodiment illustrated in Figure 10, the IC package 1020 and the circuit board 1002 are attached to opposing sides of the interposer 1004. In other embodiments, the IC package 1020 and the circuit board 1002 may be attached to a same side of the interposer 1004. In some embodiments, three or more components may be interconnected by way of the interposer 1004.

The interposer 1004 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 1004 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1004 may include metal interconnects 1010 and vias 1008, including but not limited to through-silicon vias (TSVs) 1006. The interposer 1004 may further include embedded devices 1014, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1004. The package-on-interposer structure 1036 may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly 1000 may include an IC package 1024 coupled to the first face 1040 of the circuit board 1002 by coupling components 1022. The coupling components 1022 may take the form of any of the embodiments discussed above with reference to the coupling components 1016, and the IC package 1024 may take the form of any of the embodiments discussed above with reference to the IC package 1020.

The IC device assembly 1000 illustrated in Figure 10 includes a package-on-package structure 1034 coupled to the second face 1042 of the circuit board 1002 by coupling components 1028. The package-on-package structure 1034 may include an IC package 1026 and an IC package 1032 coupled together by coupling components 1030 such that the IC package 1026 is disposed between the circuit board 1002 and the IC package 1032. The coupling components 1028 and 1030 may take the form of any of the embodiments of the coupling components 1016 discussed above, and the IC packages 1026 and 1032 may take the form of any of the embodiments of the IC package 1020 discussed above. The package-on- package structure 1034 may be configured in accordance with any of the package-on-package structures known in the art.

Figure 11 illustrates a computing device 1100 in accordance with one implementation of the disclosure. The computing device 1100 houses a board 1102. The board 1102 may include a number of components, including but not limited to a processor 1104 and at least one communication chip 1106. The processor 1104 is physically and electrically coupled to the board 1102. In some implementations the at least one communication chip 1106 is also physically and electrically coupled to the board 1102. In further implementations, the communication chip 1106 is part of the processor 1104.

Depending on its applications, computing device 1100 may include other components that may or may not be physically and electrically coupled to the board 1102. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 1106 enables wireless communications for the transfer of data to and from the computing device 1100. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1106 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1100 may include a plurality of communication chips 1106. For instance, a first communication chip 1106 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1106 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1104 of the computing device 1100 includes an integrated circuit die packaged within the processor 1104. In some implementations of the disclosure, the integrated circuit die of the processor includes one or more vertical thyristor memory devices cross-point DRAM arrays, in accordance with implementations of embodiments of the disclosure. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1106 also includes an integrated circuit die packaged within the communication chip 1106. In accordance with another implementation of embodiments of the disclosure, the integrated circuit die of the communication chip includes one or more embedded vertical thyristor memory devices cross-point DRAM arrays, in accordance with

implementations of embodiments of the disclosure.

In further implementations, another component housed within the computing device 1100 may contain an integrated circuit die that includes one or more vertical thyristor memory devices cross-point DRAM arrays, in accordance with implementations of embodiments of the disclosure.

In various implementations, the computing device 1100 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1100 may be any other electronic device that processes data. Thus, embodiments described herein include embedded non-volatile memory structures having vertical thyristor memory devices formed as cross-point DRAM arrays.

The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Example embodiment 1 : A memory device a top electrode and a vertical thyristor comprising a stack of alternating P-type material layers and N-type material layers. The memory device also includes a bottom electrode, wherein the vertical thyristor is coupled between back end of line materials including a source line and a source line.

Example embodiment 2: The memory device of example embodiment 1, wherein the vertical thyristor is composed of a material selected from the group consisting of amorphous, poly crystalline or single crystal type semiconductors, and oxide semiconductors.

Example embodiment 3 : The memory device of example embodiment 1 or 2, wherein the vertical thyristor is composed of a material selected from the group consisting of Si, Ge, III- V, and GaN.

Example embodiment 4: The memory device of example embodiment 1 or 2, wherein the vertical thyristor are composed of a material selected from the group consisting of InO, CoO, Cu20, NiO, and IGZO.

Example embodiment 5 : The memory device of example embodiment 1 , 2, 3 or 4 wherein each of the P-type and N-type layers have different band gaps.

Example embodiment 6: The memory device of example embodiment 1, 2, 3, 4, or 5, wherein the source lines and the bit lines comprise one or more metal-containing conductive materials.

Example embodiment 7: The memory device of example embodiment 1, 2, 3, 4, 5, or 6, wherein an array of vertical thyristor memory devices form a vertical thyristor cross-point DRAM array.

Example embodiment 8: A method of fabricating a thyristor cross-point DRAM array comprises forming sense logic on a first die up to a desired metal layer. Source lines and bottom electrodes are formed on an adjacent higher metal layer. A vertical thyristor layer stack is formed on a second die by growing epitaxial layers of alternating P-types layers and N-types layers. The first and second die are positioned to face one another and are bonded together. Chemical mechanical polishing is performed on a backside of the second wafer to remove unwanted materials. An additional dopant is used on a top surface of the second wafer to enable sufficient contact with the bottom electrodes. Silicidation for passivation is performed to deposit a metal, and the vertical thyristor layer stack is annealed. Individual thyristor memory cell locations are defined using lithographic patterning and etching to form trenches in the vertical thyristor layer stack that separate the thyristor memory cells to form a thyristor memory array. An inter-level dielectrics (ILD) layer is deposited over the thyristor memory array.

Example embodiment 9: The method of example embodiment 8, further comprising implanting dopants during the growth of each of the epitaxial layers.

Example embodiment 10: The method of example embodiment 9 or 10, further comprising forming sense logic on metal layer M0 and forming the source lines and bottom electrodes on metal layer Ml.

Example embodiment 11 : The method of example embodiment 8, 9, or 10, further comprising forming the vertical thyristor layer stack with a material selected from the group consisting of amorphous, poly crystalline or single crystal type semiconductors, and oxide semiconductors.

Example embodiment 12: The method of example embodiment 8, 9, 10, or 11, further comprising forming the vertical thyristor layer stack with a material selected from the group consisting of Si, Ge, III-V, and GaN.

Example embodiment 13: The method of example embodiment 8, 9, 10, or 11, further comprising forming the vertical thyristor layer stack with a material selected from the group consisting of InO, CoO, Cu20, NiO, and IGZO.

Example embodiment 14: The memory device of example embodiment 8, 9, 10, 11, 12, or 13, further comprising providing each of the P-type and N-type layers with different band gaps.

Example embodiment 15: The memory device of example embodiment 8, 9, 10, 11, 12, 13, or 14 further comprising coupling the bottom electrodes to source lines and coupling top electrodes to source lines that are orthogonal to the source lines.

Example embodiment 16: The method of example embodiment 8, 9, 10, 11, 12, 13, 14, or 15, further comprising forming the thyristor cross-point DRAM array with 4F2 or less density.

Example embodiment 17: A method of fabricating a thyristor cross-point DRAM array comprises forming sense logic on a first die up to a desired metal layer. Source lines are formed on an adjacent higher metal layer. An inter-level dielectrics (ILD) layer and an etch-stop layer are sequentially formed on a same metal layer as the bit source lines, followed by deposition of an oxide layer. Bottom electrodes and vias are formed over the oxide layer. Trenches are formed in the ILD layer in locations to be occupied by the vertical thyristor layer stacks. Vertical thyristor layer stacks are formed by growing epitaxial layers of alternating N-types layers and P- types layers. Silicidation for passivation is performed to deposit a metal, and annealing the vertical thyristor layer stacks. Individual thyristor memory cell locations are defined using lithographic patterning and etching to form a thyristor memory array. An inter-level dielectrics (ILD) layer is deposited over the thyristor memory array.

Example embodiment 18: The method of example embodiment 17, further comprising implanting dopants during the growth of each of the epitaxial layers.

Example embodiment 19: The method of example embodiment 17 and 18, further comprising forming sense logic on metal layer M0 and forming the source lines and bottom electrodes on metal layer ML

Example embodiment 20: The method of example embodiment 17, 18, and 19, further comprising forming the vertical thyristor layer stack with a material selected from the group consisting of amorphous, poly crystalline or single crystal type semiconductors, and oxide semiconductors.

Example embodiment 21 : The method of example embodiment 17, 18, 19, and 20, further comprising forming the vertical thyristor layer stack with a material selected from the group consisting of Si, Ge, III-V, and GaN.

Example embodiment 22: The method of example embodiment 17, 18, 19, 20, and 21, further comprising forming the vertical thyristor layer stack with a material selected from the group consisting of InO, CoO, Cu20, NiO, and IGZO.

Example embodiment 23: A method of fabricating a thyristor cross-point DRAM array comprises forming sense logic on a first die up to a desired metal layer. Source lines on an adjacent higher metal layer. An etch-stop layer is deposited on a same metal layer as the source lines. An inter-level dielectrics (ILD) layer is deposited and polished over the etch-stop layer. A Damascene etch is performed for memory definition by forming trenches in the ILD down to the etch-stop layer. Bottom electrodes and vias are formed in the etch-stop layer in locations to be occupied by the vertical thyristor layer stacks. Vertical thyristor layer stacks are formed by growing epitaxial layers of alternating N-types layers and P-types layers. Silicidation for passivation is performed to deposit a metal, and annealing the vertical thyristor layer stacks. Individual thyristor memory cell locations are defined using lithographic patterning and etching to form a thyristor memory array

Example embodiment 24: The method of example embodiment 23, further comprising implanting dopants during the growth of each of the epitaxial layers.

Example embodiment 25 : The method of example embodiment 23 or 24, further comprising forming the vertical thyristor layer stack with a material selected from the group consisting of amorphous, poly crystalline or single crystal type semiconductors, and oxide semiconductors.

Example embodiment 26: A cross-point array comprises a first plurality of conductive lines along a first direction on a substrate. A second plurality of conductive lines is along a second direction on the substrate orthogonal to the first direction. A plurality of individual memory elements is located at each cross-section of the first plurality of conductive lines and the second plurality of conductive lines. Each of the memory elements include a top electrode, a vertical thyristor means, and a bottom electrode. The first plurality of conductive lines and the second plurality of conductive lines comprise back end of line materials.

Example embodiment 27 : The method of embodiment 26, wherein the vertical thyristor means comprises a stack of alternating P-type material layers and N-type material layers.

Example embodiment 28: The method of embodiment 27, wherein each of the P-type and N-type layers have different band gaps.

Claims

CLAIMS What is claimed is:

1 . A memory device, comprising:

a top electrode;

a vertical thyristor comprising a stack of alternating P-type material layers and N-type material layers; and

a bottom electrode, wherein the vertical thyristor is coupled between back end of line materials including a source line and a bit line.

2. The memory device of claim 1, wherein the vertical thyristor is composed of a material selected from the group consisting of amorphous, poly crystalline or single crystal type semiconductors, and oxide semiconductors.

3. The memory device of claim 2, wherein the vertical thyristor is composed of a material selected from the group consisting of Si, Ge, III-V, and GaN.

4. The memory device of claim 2, wherein the vertical thyristor are composed of a material selected from the group consisting of InO, CoO, Cu20, NiO, and IGZO.

5. The memory device of claim 1, 2, 3, or 4, wherein each of the P-type and N-type layers have different band gaps.

6. The memory device of claim 1, 2, 3, or 4, wherein the source lines and the bit lines comprise one or more metal-containing conductive materials.

7. The memory device of claim 1, 2, 3, or 4, wherein an array of vertical thyristor memory devices form a vertical thyristor cross-point DRAM array.

8. A method of fabricating a thyristor cross-point DRAM array, the method comprising: forming sense logic on a first die up to a desired metal layer;

forming source lines and bottom electrodes on an adjacent higher metal layer;

forming a vertical thyristor layer stack on a second die by growing epitaxial layers of alternating P-types layers and N-types layers;

positioning the first and second die to face one another and bonding the first and second die together;

performing chemical mechanical polishing on a backside of the second wafer to remove unwanted materials;

using an additional dopant on a top surface of the second wafer to enable sufficient contact with the bottom electrodes;

performing silicidation for passivation to deposit a metal, and annealing the vertical thyristor layer stack; defining individual thyristor memory cell locations using lithographic patterning and etching to form trenches in the vertical thyristor layer stack that separate the thyristor memory cells to form a thyristor memory array; and

depositing an inter-level dielectrics (ILD) layer over the thyristor memory array.

9. The method of claim 8, further comprising implanting dopants during the growth of each of the epitaxial layers.

10. The method of claim 8 or 9, further comprising forming sense logic on metal layer M0 and forming the source lines and bottom electrodes on metal layer Ml.

1 1 . The method of claim 8 or 9, further comprising forming the vertical thyristor layer stack with a material selected from the group consisting of amorphous, poly crystalline or single crystal type semiconductors, and oxide semiconductors.

12. The method of claim 11, further comprising forming the vertical thyristor layer stack with a material selected from the group consisting of Si, Ge, III-V, and GaN.

13. The method of claim 11, further comprising forming the vertical thyristor layer stack with a material selected from the group consisting of InO, CoO, Cu20, NiO, and IGZO.

14. The method of claim 8 or 9, further comprising providing each of the P-type and N-type layers with different band gaps.

15. The method of claim 8 or 9, further comprising coupling the bottom electrodes to source lines and coupling top electrodes to bit lines that are orthogonal to the source lines.

16. The method of claim 8 or 9, further comprising forming the thyristor cross-point DRAM array with 4F² or less density.

17. A method of fabricating a thyristor cross-point DRAM array, the method comprising: forming sense logic on a first die up to a desired metal layer;

forming source lines on an adjacent higher metal layer;

sequentially forming an inter-level dielectrics (ILD) layer and an etch-stop layer on a same metal layer as the source lines, followed by deposition of an oxide layer;

forming bottom electrodes and vias over the oxide layer;

forming trenches in the ILD layer in locations to be occupied by the vertical thyristor layer stacks;

forming vertical thyristor layer stacks by growing epitaxial layers of alternating N-types layers and P-types layers;

performing silicidation for passivation to deposit a metal, and annealing the vertical thyristor layer stacks;

defining individual thyristor memory cell locations using lithographic patterning and etching to form a thyristor memory array; and depositing an inter-level dielectrics (ILD) layer over the thyristor memory array.

18. The method of claim 17, further comprising implanting dopants during the growth of each of the epitaxial layers.

19. The method of claim 17 or 18, further comprising forming sense logic on metal layer M0 and forming the source lines and bottom electrodes on metal layer Ml.

20. The memory device of claim 17 or 18, further comprising forming the vertical thyristor layer stack with a material selected from the group consisting of amorphous, poly crystalline or single crystal type semiconductors, and oxide semiconductors.

21 . The memory device of claim 20, further comprising forming the vertical thyristor layer stack with a material selected from the group consisting of Si, Ge, III-V, and GaN.

22. The memory device of claim 20, further comprising forming the vertical thyristor layer stack with a material selected from the group consisting of InO, CoO, Cu20, NiO, and IGZO.

23. A method of fabricating a thyristor cross-point DRAM array, the method comprising: forming sense logic on a first die up to a desired metal layer;

forming source lines on an adjacent higher metal layer;

depositing an etch-stop layer on a same metal layer as the source lines;

depositing and polishing an inter-level dielectrics (ILD) layer over the etch-stop layer; performing a Damascene etch for memory definition by forming trenches in the ILD down to the etch-stop layer;

forming bottom electrodes and vias in the etch-stop layer in locations to be occupied by the vertical thyristor layer stacks;

performing silicidation for passivation to deposit a metal, and annealing the vertical thyristor layer stacks; and

defining individual thyristor memory cell locations using lithographic patterning and etching to form a thyristor memory array.

24. The method of claim 23, further comprising implanting dopants during the growth of each of the epitaxial layers.

25. The method of claim 23 or 24, further comprising forming the vertical thyristor layer stack with a material selected from the group consisting of amorphous, poly crystalline or single crystal type semiconductors, and oxide semiconductors.