WO2019095788A1

WO2019095788A1 - 10g-kr high-speed signal optimization method and system

Info

Publication number: WO2019095788A1
Application number: PCT/CN2018/103410
Authority: WO
Inventors: 刘法志
Original assignee: 郑州云海信息技术有限公司
Priority date: 2017-11-16
Filing date: 2018-08-31
Publication date: 2019-05-23
Also published as: CN107943627A

Abstract

The present invention provides a 10G-KR high-speed signal optimization method and system. The method comprises: obtaining a signal system topology structure; obtaining a standard insertion loss of a signal link; sequentially adjusting FFE, CTLE, and DFE parameter values to obtain an insertion loss after each adjustment; and determining optimal FFE, CTLE, and DFE parameter values according to a ratio of the insertion loss after each adjustment to the standard insertion loss. By adjusting the FFE, CTLE, and DFE parameters in the signal system topology structure, and the comparing the ratio of the insertion loss of a signal to the standard insertion loss to determine optimal parameter values, the present invention solves the problem of high signal loss caused by the fact that the FFE, CTLE, and DFE parameters in the existing 10G-KR high-speed signal depend on personal experience and manufacturer setting values, obtains a better signal link status under the condition of ensuring that electronic components are not changed, reduces the signal loss, improves the signal quality and the signal system stability, and avoids the economic loss.

Description

10G-KR high speed signal optimization method and system

The invention claims the priority of the Chinese patent application filed on November 16, 2017, the Chinese Patent Office, the application number is 201711139309.9, and the application name is "a 10G-KR high-speed signal optimization method and system", the entire contents of which are incorporated by reference. In the present invention.

Technical field

The invention relates to the field of signal transmission, and in particular to a 10G-KR high-speed signal optimization method and system.

Background technique

With the development of electronic communication technology, the rate of signal transmission has become faster and faster. Currently, the bus bandwidth has been developed to 100 Gbps/400 Gbps, and is moving toward 1000 Gbps bandwidth. XAUI/XLAUI, SFP+, PCIE, SATA, and QPI are all serial buses. The transmission distance is short, and the intra-board traces are generally limited to 50cm or less.

For the high performance computing platform of the ATCA (Advanced Telecom Computing Architecture) architecture, the IEEE released the 802.3ap standard in 2007 due to the need for long backplane routing. This standard proposes the Backplane Ethernet concept. Also commonly referred to as the backplane Ethernet interface standard. In the backplane Ethernet interface standard, there are two parallel and serial 10G backplanes: Parallel (10GBASE-KX4) splits 10G signals into 4 channels, each with a rate of 3.125Gb/s (similar In XAUI); serial (10GBASE-KR, referred to as 10G-KR) defines a channel, which uses 64b-66b encoding at a rate of 10.3125Gb/s.

In the existing 10G-KR signal scheme, parameters such as FFE (Forward Feedback Equalizer), CTLE (Continuous Time Linear Equalizer), and DFE (Decision Feedback Equalizer) parameters The settings are often based on personal experience or factory settings. The setting of these parameters leads to large signal loss. When there is environmental interference, such as electromagnetic interference from external electronic components, the signal quality will be poor and the system stability will be affected.

Therefore, how to reduce signal loss and improve signal quality is a technical problem that is urgently needed to be solved by those skilled in the art.

Summary of the invention

The object of the present invention is to provide a 10G-KR high-speed signal optimization method and system, which aims to solve the problem that the FFE, CTLE and DFE parameters in the existing 10G-KR high-speed signal rely on personal experience and manufacturer setting values to cause large signal loss. To reduce signal loss and improve signal quality.

In order to achieve the above technical purpose, the present invention provides the following technical solutions:

In a first aspect, the present invention provides a 10G-KR high speed signal optimization method, comprising the following steps:

Acquire the signal system topology;

Obtain the standard insertion loss of the signal link;

Adjust the FFE, CTLE, and DFE parameter values in turn to obtain the insertion loss after each adjustment;

The optimal FFE, CTLE, and DFE parameter values are determined based on the ratio of the insertion loss to the standard insertion loss per adjustment.

Optionally, the system topology is specifically: the SerDes chip sends a signal from the Tx end, passes through the connector and the backplane to reach another connector after the first single-board link, and then passes through the second board, and passes through the Retimer. After the chip passes through the remaining link of the second board, it finally reaches the Rx end of the SerDes chip.

Optionally, the standard insertion loss is a signal link insertion loss when the FFE, CTLE, and DFE parameter values are factory set values.

Optionally, the determining the optimal FFE, CTLE, and DFE parameter value is specifically: adjusting the value of the FFE until the insertion loss value is 50% of the standard insertion loss at 5 GHz; adjusting the value of the CTLE parameter until when The insertion loss at 5 GHz is relative to 60% after adjusting the FFE value; the value of the DFE parameter is adjusted until the insertion loss is 10% after adjusting the CTLE value at 10 GHz.

In a second aspect, the present invention provides a 10G-KR high speed signal optimization system, including:

a topology acquisition module for acquiring a signal system topology;

Standard insertion loss acquisition module for obtaining standard insertion loss of a signal link;

a parameter adjustment module for sequentially adjusting the value of the FFE, CTLE, and DFE parameters to obtain the insertion loss after each adjustment;

A parameter determining module is configured to determine an optimal FFE, CTLE, and DFE parameter value according to a ratio of an insertion loss to a standard insertion loss per adjustment.

Optionally, the parameter determining module includes:

An FFE parameter determining unit for adjusting the value of the FFE until the insertion loss value is 50% of the standard insertion loss at 5 GHz;

a CTLE parameter determining unit for adjusting the value of the CTLE parameter until the insertion loss is 60% after adjusting the FFE value at 5 GHz;

A DFE parameter determining unit for adjusting the value of the DFE parameter until the insertion loss is 40% after adjusting the CTLE value at 10 GHz.

The effects provided in the Summary of the Invention are merely the effects of the embodiments, and not all of the effects of the invention. One of the above technical solutions has the following advantages or benefits:

Compared with the prior art, the present invention adjusts the FFE, CTLE, and DFE parameters in the signal system topology, and determines the optimal parameter size by the ratio of the insertion loss of the signal to the standard insertion loss, thereby solving the existing 10G. - The FFE, CTLE and DFE parameters in the KR high-speed signal rely on personal experience and the large signal loss caused by the manufacturer's set value. In the case of ensuring that the electronic components are not changed, a better signal link condition is obtained, and signal loss is reduced. Improve signal quality and signal system stability to avoid economic losses.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can obtain other drawings according to the provided drawings without any creative work.

FIG. 1 is a flowchart of a 10G-KR high-speed signal optimization method according to an embodiment of the present invention;

2 is a schematic structural diagram of a KR signal system according to an embodiment of the present invention;

3 is a system frame diagram of a SerDes chip according to an embodiment of the present invention;

4 is a topological structural diagram of a KR signal system according to an embodiment of the present invention;

FIG. 5 is a comparison diagram of insertion loss under different parameters of a KR signal system according to an embodiment of the present invention; FIG.

FIG. 6 is a structural block diagram of a 10G-KR high-speed signal optimization system according to an embodiment of the present invention.

Detailed ways

In order to clearly illustrate the technical features of the present solution, the present invention will be described in detail below through the specific embodiments and the accompanying drawings. The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and arrangements of the specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of simplicity and clarity, and is not in the nature of the description of the various embodiments and/or arrangements discussed. It is noted that the components illustrated in the drawings are not necessarily drawn to scale. The description of the known components and processing techniques and processes is omitted to avoid unnecessarily limiting the present invention.

A 10G-KR high-speed signal optimization method and system provided by an embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

As shown in FIG. 1 , an embodiment of the present invention discloses a 10G-KR high-speed signal optimization method, including the following steps:

Step 101: Acquire a signal system topology. Referring to Figure 2, this figure is a structural diagram of the KR signal system. In the KR signal system structure diagram shown in FIG. 2, the core of the KR signal system is the SerDes chip, and the SerDes chip located on the board A (also referred to as the first board) arrives through the differential via the package via. The orthogonal connector, after passing through the backplane and then passing through the orthogonal connector, reaches the board B (also referred to as the second board).

Referring to Figure 3, the figure is a system frame diagram of the SerDes chip. In Figure 3, after the serial signal passes through the serializer, the forward feedback equalizer FFE equalizes the forward disturbance, and then transmits the drive through CML (Current Mode Logic). After transmitting the drive, it passes through P and N respectively. The high speed line is then driven by the CML and then passed through the continuous time linear equalizer CTLE. CTLE can amplify the high-frequency components of the signal, and achieve the separation of useful signals through its own zero and pole. After that, the signal is then subjected to a decision feedback equalizer DFE to correct the bit signal, thereby reducing inter-symbol interference, thereby ensuring the quality of the high-speed signal. Finally, the serializer is obtained through the deserializer.

See Figure 4, which is a topographical diagram of the KR signal system. In Figure 4, starting from the Tx end of the SerDes chip, after passing through the connector after the A-board A link, after passing through the backplane, after reaching another connector, it passes through the single-board B-link, and then passes through the Retimer chip. After the remaining link of the board B, it finally reaches the Rx end of the SerDes chip.

Step 102: Acquire a standard insertion loss of the signal link.

In the conventional design of the signal system, the FFE, CTLE, and DFE parameters are often given by the manufacturer. As a specific example, refer to Figure 5, the insertion loss comparison chart of the KR signal system shown in Figure 5, and the curve A represents Standard insertion loss at a given parameter given by the manufacturer. In Fig. 5, the abscissa represents the frequency, and the frequency increases direction from left to right; the ordinate represents the insertion loss, and the insertion loss increases from the top to the bottom. In the 10G-KR high-speed signal optimization method provided in this embodiment, the standard insertion loss is used as a reference standard for adjusting the FFE, CTLE, and DFE parameter values.

When the loss curve is located above the curve A representing the standard insertion loss, it means that the insertion loss is lower than the standard insertion loss in the frequency range shown on the entire abscissa. Furthermore, the system can reduce the insertion loss requirement. For example, as shown by the B curve in FIG. 5, the curve B is located above the curve A, that is, the curve B is in the entire frequency range, and the insertion loss is lower than the standard insertion loss.

However, due to electromagnetic interference of external electronic components, system instability is likely to occur, resulting in unnecessary economic loss. To this end, the FFE, CTLE and DFE parameter values need to be adjusted to achieve 10G-KR high-speed signal optimization, prompt signal and system stability.

Step 103: Adjust the FFE, CTLE, and DFE parameter values in sequence to obtain the insertion loss after each adjustment.

Step 104: Determine the optimal FFE, CTLE, and DFE parameter values according to the ratio of the insertion loss to the standard insertion loss after each adjustment.

Adjusting the FFE parameters, since the FFE parameters are mainly for inter-symbol interference, the value of the FFE is adjusted by the signal itself and the coefficient until the insertion loss value is about 50% of the standard insertion loss at 5 GHz. Through the adjustment of the FFE parameters, on the one hand, the inter-symbol interference is minimized, and on the other hand, the time requirement of the previous segment is guaranteed. As an example, after adjusting the TTE parameter value, the insertion loss in the entire 0 to 10 GHz frequency range can be seen in curve C shown in FIG. Comparing curve C and curve A in Fig. 5, it can be seen that the insertion loss at a frequency of 5 GHz is 50% of the standard insertion loss at 5 GHz after FFE parameter adjustment.

Adjust the CTLE parameter until the insertion loss is about 60% after adjusting the FFE value at 5 GHz, which is about 30% of the standard insertion loss. By adjusting the CTLE parameter, the adjusted output tends to be linear. The ratio of low frequency to high frequency can be adjusted to ensure the quality of the output signal. As an example, after adjusting the CTLE parameter value, the insertion loss in the entire 0 to 10 GHz frequency range can be seen in the curve D shown in FIG. Comparing curve D, curve C and curve A in Fig. 5, it can be seen that the insertion loss at a frequency of 5 GHz is 30% of the standard insertion loss at 5 GHz after the CTLE parameter adjustment, that is, the insertion after only the FFE parameter adjustment at 5 GHz. 60% of the loss.

Adjust the DFE parameters until the insertion loss is about 40% after adjusting the CTLE value at 10 GHz, which is about 12% of the standard insertion loss. By adjusting the DFE parameters, avoid the nonlinear problem that may occur after CTLE adjustment. On the other hand, the decision-making feedback minimizes the insertion loss of the system. As an example, after adjusting the DFE parameter value, the insertion loss in the entire 0 to 10 GHz frequency range can be seen in the curve E shown in FIG. Comparing curve E, curve D and curve A in Fig. 5, it can be seen that the insertion loss at a frequency of 10 GHz is 12% of the standard insertion loss at 10 GHz after the FFE parameter adjustment, that is, after the FFE and CTLE parameters are adjusted at 10 GHz. 40% of the insertion loss. After the above steps adjust the FFE, CTLE and DFE parameter values, the optimal FFE, CTLE and DFE parameter values can be determined.

The above is a 10G-KR high speed signal optimization method provided by the embodiment of the present application. The method adjusts the parameters of the FFE, CTLE and DFE in the signal system topology, and determines the optimal parameter size by adjusting the ratio of the insertion loss of the signal to the standard insertion loss. Through the above method, the problem that the FFE, CTLE and DFE parameters in the existing 10G-KR high-speed signal rely on personal experience and the manufacturer's setting value is large, and the problem of large signal loss is obtained, and the better is obtained without changing the electronic components. The signal link condition reduces signal loss, improves signal quality and stability of the signal system, and avoids the economic loss caused thereby.

In addition, the present invention is based on the 10G-KR high-speed signal optimization method provided by the above embodiment, and also provides a 10G-KR high-speed signal optimization system. The specific embodiments of the system are described in detail below with reference to the accompanying drawings and embodiments.

Referring to FIG. 6, which is a structural block diagram of a 10G-KR high-speed signal optimization system according to an embodiment of the present invention.

As shown in FIG. 6, the 10G-KR high-speed signal optimization system provided by the present invention includes:

The topology acquisition module 601, the standard insertion loss acquisition module 602, the parameter adjustment module 603, and the parameter determination module 604.

The topology acquiring module 601 is configured to acquire a signal system topology;

The system topology is specifically: the SerDes chip sends a signal from the Tx end, passes through the connector and the backplane to reach another connector after the first board link, and then passes through the second board, and then passes through the Retimer chip. After the remaining link of the second board, it finally reaches the Rx end of the SerDes chip.

a standard insertion loss acquisition module 602, configured to acquire a standard insertion loss of a signal link;

The standard insertion loss is the signal link insertion loss when the FFE, CTLE, and DFE parameter values are factory-set values.

The parameter adjustment module 603 is configured to sequentially adjust the value of the FFE, CTLE, and DFE parameter values to obtain the insertion loss after each adjustment;

The parameter determining module 604 is configured to determine an optimal FFE, CTLE, and DFE parameter value according to a ratio of an insertion loss to a standard insertion loss per adjustment.

The above is a 10G-KR high speed signal optimization system provided by the embodiment of the present application. The system can adjust the FFE, CTLE, and DFE parameters in the signal system topology, and determine the optimal parameter size by adjusting the ratio of the insertion loss of the signal to the standard insertion loss. The system solves the problem that the FFE, CTLE and DFE parameters in the existing 10G-KR high-speed signal rely on personal experience and manufacturer's set value to cause large signal loss, and obtain a better signal chain without changing the electronic components. Road conditions, to achieve reduced signal loss, improve signal quality and signal system stability, to avoid the resulting economic losses.

As a possible implementation, in the foregoing system, the parameter determining module 604 may specifically include: an FFE parameter determining unit 6041, a CTLE parameter determining unit 6042, and a DFE parameter determining unit 6043.

The FFE parameter determining unit 6041 is configured to adjust the value of the FFE until the insertion loss value is 50% of the standard insertion loss at 5 GHz; the FFE parameter adjustment minimizes the inter-symbol interference on the one hand, and ensures the inter-symbol interference on the other hand. The time requirement for the previous paragraph.

The CTLE parameter determining unit 6042 is configured to adjust the value of the CTLE parameter until the insertion loss is 60% after adjusting the FFE value at 5 GHz; the CTLE parameter adjustment ensures that the adjusted output tends to be linear, and on the other hand, can be adjusted The ratio of low frequency to high frequency ensures the quality of the output signal.

The DFE parameter determining unit 6043 is configured to adjust the value of the DFE parameter until the insertion loss is 40% after adjusting the CTLE value at 10 GHz; by adjusting the DFE parameter, avoiding nonlinear problems that may occur after the CTLE adjustment, On the one hand, the insertion loss of the system is minimized by decision feedback.

The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. Within the scope.

Claims

A 10G-KR high speed signal optimization method, comprising the steps of:

Acquire the signal system topology;

Obtain the standard insertion loss of the signal link;

Adjust the FFE, CTLE, and DFE parameter values in turn to obtain the insertion loss after each adjustment;

The optimal FFE, CTLE, and DFE parameter values are determined based on the ratio of the insertion loss to the standard insertion loss per adjustment.
The 10G-KR high-speed signal optimization method according to claim 1, wherein the system topology is specifically: the SerDes chip sends a signal from the Tx end, passes through the connector and the back after the first single-board link. After the board reaches the other connector, it passes through the second board, passes through the Retimer chip, passes through the remaining link of the second board, and finally reaches the Rx end of the SerDes chip.
The 10G-KR high-speed signal optimization method according to claim 1, wherein the standard insertion loss is a signal link insertion loss when the FFE, CTLE, and DFE parameter values are factory-set values.
The method for optimizing 10G-KR high-speed signals according to claim 1, wherein the determining the optimal FFE, CTLE, and DFE parameter values is specifically: adjusting the value of the FFE until the insertion loss value is 5 GHz. Is 50% of the standard insertion loss; adjust the value of the CTLE parameter until the insertion loss is at 60% relative to the adjusted FFE value at 5 GHz; adjust the value of the DFE parameter until the insertion loss is relative to the adjusted CTLE value at 10 GHz 40%.
A 10G-KR high speed signal optimization system, comprising:

a topology acquisition module for acquiring a signal system topology;

Standard insertion loss acquisition module for obtaining standard insertion loss of a signal link;

a parameter adjustment module for sequentially adjusting the value of the FFE, CTLE, and DFE parameters to obtain the insertion loss after each adjustment;

A parameter determining module is configured to determine an optimal FFE, CTLE, and DFE parameter value according to a ratio of an insertion loss to a standard insertion loss per adjustment.
The 10G-KR high-speed signal optimization system according to claim 5, wherein the system topology is specifically: the SerDes chip sends a signal from the Tx end, passes through the connector and the back after the first single-board link. After the board reaches the other connector, it passes through the second board, passes through the Retimer chip, passes through the remaining link of the second board, and finally reaches the Rx end of the SerDes chip.
A 10G-KR high speed signal optimization system according to claim 5, wherein said standard insertion loss is a signal link insertion loss when the FFE, CTLE and DFE parameter values are factory set values.
The 10G-KR high-speed signal optimization system according to claim 5, wherein the parameter determining module comprises:

An FFE parameter determining unit for adjusting the value of the FFE until the insertion loss value is 50% of the standard insertion loss at 5 GHz;

a CTLE parameter determining unit for adjusting the value of the CTLE parameter until the insertion loss is 60% after adjusting the FFE value at 5 GHz;

A DFE parameter determining unit for adjusting the value of the DFE parameter until the insertion loss is 40% after adjusting the CTLE value at 10 GHz.