WO2019041306A1

WO2019041306A1 - Message processing and corresponding apparatus

Info

Publication number: WO2019041306A1
Application number: PCT/CN2017/100186
Authority: WO
Inventors: Yu Chen; Jie Chen; Dongyang DU; Keeth Saliya JAYASINGHE
Original assignee: Nokia Solutions And Networks Oy; Nokia Shanghai Bell Co., Ltd
Priority date: 2017-09-01
Filing date: 2017-09-01
Publication date: 2019-03-07
Also published as: CN111052614A; CN111052614B

Abstract

It is provided a method, comprising generating an ordered sequence of U check bits for an ordered sequence of K information bits by a CRC algorithm based on a polynomial; determining d determined groups among D groups, wherein each of the D groups has a respective group index g, each of the D groups consists of at least one of the K information bits and a respective one of the U check bits; arranging the K information bits and the U check bits into a code block, wherein for each of the d determined groups, the respective information bits and the respective check bit are arranged at the code block positions not later than the code block position K or K+d; the polynomial consists of an outer bit sequence directly followed by D-1 bits having a value of 0 directly followed by the outer bit sequence.

Description

MESSAGE PROCESSING AND CORRESPONDING APPARATUS

Field of the invention

The present invention relates to an apparatus， a method， and a computer program product related to message processing， in particular to cyclic redundancy check in connection with polar coding.

Abbreviations

3GPP 3^rd Generation Partnership Project

5G 5^th Generation

BER Bit Error Rate

BLER Block Error Ratio

CRC Cyclic Redundancy Check

DCI Downlink Control Information

DL Downlink

eMBB Enhanced Mobile Broadband

FAR False Alarm Rate

LDPC Low Density Parity Check

mMTC Massive MTC

MTC Machine-type Communication

NR New Radio

PC Polar Coding

QPSK Quadrature Phase Shift Keying

RAN Radio Access Network

RRC Radio Resource Control

RX Receive/Reception

TBCC Tail-biting Convolution Code

TX Transmit/Transmission

UCI Uplink Control Information

UL Uplink

XOR Exclusive OR

Background of the invention

Polar code is a new and promising channel coding scheme to approach communication channel capacity， which is a linear block code developed by Erdal

[1] . It is the first channel code with an explicit construction to achieve the capacity of symmetric binary-input， discrete， memoryless channels (Bl-DMCs) . With the help of list decoders [2] ， polar codes have comparable and sometimes even better performance compared to the state-of-the-art codes like LDPC and turbo codes， meanwhile the decoding complexity of polar codes is as low as O (LN log N) . Here N is the encoded block length and L is the list size. These features make polar codes very attractive for many applications， like digital communications and storage. Polar codes are under investigation in the 3GPP 5G channel coding study item for potential 5G applications [4] . The agreed working assumption is that polar codes will be used for eMBB control channels.

A brief overview on polar codes is provided in this section. This overview provides background introduction for the detailed discussion on the proposed scheme for polar codes. Polar codes are based on the concept of polarization [1] . The basic building block in polar codes can be depicted as shown in Fig. 1， taken from [1] .

In Fig. 1， u_i refer to the input bits of the encoder， and y_i refer to the output/encoded bits of the encoder. It can be shown that in this configuration， the mutual information I (U₁； Y₁， Y₂) decreases compared to the pre-polarized pair I (U₁； Y₁) ， while I (U₂； Y₁， Y₂， U₁) increases compared to I (U₂； Y₂) . In this way， one channel is degraded and the other one is upgraded.

By systematically replicating and stacking such basic blocks， longer polar codes can be constructed. For example， Fig. 2 (taken from [1] ) characterizes a length-4 polar code.

As the number of layers grows， the channels are kept being degraded and upgraded. In other words， the polarization effect becomes more and more visible. Eventually， some channels would have zero capacity and the others would become error-free. The idea of polar codes is to choose the error-free channels to transmit information bits and force the value of the bits transmitted in the zero-capacity channels to be some known value， e.g.， 0. These bits are called frozen bits in the literature.

By choosing the K best channels out of the total N polarized channels， one gets a rate K/N polar code. In the example shown in Fig. 2， one may pick K ＝ 2 with (u₃， u₄) as information bits， and (u₁， u₂) as frozen bits. In effect， a polar code of rate 1/2 is constructed.

In 3GPP， the use of the polar coding graph shown in Fig. 3 is agreed， which is equivalent to the classical coding graph of [1] shown in Fig. 2. Hence， it is shown here for convenience.

The following is agreed in 3GPP NR for control channels [3] ：

Agreement：

· J CRC bits are provided (which may be used for error detection and may also be used to assist decoding and potentially for early termination)

- J may be different in DL and UL

- J may depend on the payload size in the UL (0 not precluded)

· In addition， J’assistance bits are provided in reliable locations (which may be used to assist decoding and potentially for early termination)

· J + J’＜＝ the number of bits required to satisfy the FAR target (n_FAR) + 6

- For DL：

○ J’＝ 3 or 6， to be downselected at June adhoc

○ J”＝ 0， i.e. additional assistance bits are not provided in unreliable location

○ At least some of the J + J’bits are appended

○ FFS until June adhoc：

■ how the J + J’bits are obtained

○ If J’＝6， working assumption that at least some of the J + J’bits are distributed (including to support early termination in the code construction) (Consideration of J’＝6 proposals without distributed J+J’bits are not precluded. )

○ If J’＝3， FFS until June adhoc whether some of the J + J’bits are distributed (including to support early termination in the code construction)

○ Consideration of distribution of bits shall consider complexity versus benefit and comparison to implementable purely implementation based methods for early termination

The CRC bit may be transmitted after all of its corresponding information bits. Though they may be transmitted early but the CRC check has to wait until all the corresponding information bits are decoded. From the early termination point of view， it would be beneficial if the CRC bits are distributed as front as possible， so that the decoding can be terminated early when an error is detected. Furthermore， the current transmission scheme proposed in [5] has some complexity in implementation.

In this document， the CRC polynomial is defined by the coefficients， i.e. the polynomial x^c (n) + x^c (n-1) +...+x^c (1) +1 is denoted by [c (n) c (n-1) ... c (1) ] . It may also be denoted by its hexadecimal form. The hexadecimal form is denoted starting with “0x” .

In [5] ， the polynomial used for 19bit CRC is given by [0xD1D79] . However， it does not have good distribution property. The distributing property means the degree the CRC bits can be transmitted in the front position of a code block so that the CRC bit check can be done as early as possible.

In [6] ， 0x2D0B5 19-bit CRC is used for downlink and 0x385 is used for uplink. It can be seen the distributing property of 0x385 is not optimum.

In [7] ， many polynomials are given， but their distribution property is also not good enough.

In [8] and [9] ， a distributed CRC transmission scheme is given， wherein the CRC bits are generated by conventional CRC generator. The information bits and CRC bits are transmitted in the order determined by the interleaving pattern and the receiver uses the same interleaving pattern to deinterleaving the information bits. This scheme has the benefits that a single interleaving pattern is used for all the code block sizes. The complexity is reduced greatly. The early termination is done based on CRC checking. When all the decoding paths fail the CRC check， then the decoding terminates. The CRC checking can be performed by conventional CRC detector or by checking all the corresponding information bits of the specific CRC bit.

In [10] ， another scheme based on special parity bits for early termination is studied. However， it is not based on CRC and its error detection capability is much lower than that of a CRC based scheme.

References

[1] E. Arikan， “Channel polarization： A method for constructing capacity achieving codes for symmetric binary-input memoryless channels， ” IEEE Trans. Inf. Theory， vol. 55， no. 7， pp. 3051-3073， Jul. 2009.

[2] I. Tal and A. Vardy， “List decoding of polar codes， ” IEEE Trans. Inf. Theory， vol. 61， no. 5， pp. 2213-2226， May 2015.

[3] Meeting Report of 3GPP TSG RAN WG1 #88

[4] Meeting Report of 3GPP TSG RAN WG1 #87

[5] R1-1708316， Study of early termination techniques for Polar code， Intel Corporation

[6] R1-1708049， Comparison of CA Polar Codes and PC-CA Polar Codes， Samsung

[7] https： //users. ece. cmu. edu/～koopman/crc/

[8] 3GPP R1-1708833， Design details of distributed CRC， Nokia， Alcatel-Lucent Shanghai Bell

[9] 3GPP R1-1708832， Early termination benefits of CRC distribution， Nokia， Alcatel-Lucent Shanghai Bell

[10] 3GPP R1-1708488， Distributed simple parity check Polar codes， NTT DOCOMO， INC.

Summary of the invention

It is an object of the present invention to improve the prior art.

According to a first aspect of the invention， there is provided an apparatus， comprising at least one processor， at least one memory including computer program code， and the at least one processor， with the at least one memory and the computer program code， being arranged to cause the apparatus to at least perform generating an ordered sequence of U check bits p₁ to p_U for an ordered sequence of K information bits b_K to b₁ by a cyclic redundancy check algorithm based on a polynomial of order U； determining d determined groups among D groups， wherein each of the D groups has a respective group index g， each of the group indices is unique among the D group indices， and each of the D groups consists of at least one of the K information bits b₁ to b_K and a respective one of D distributed check bits of the U check bits such that each of the D distributed check bits is contained in exactly one of the D groups； arranging the K information bits and the U check bits into a code block comprising K+U bits ordered at code block positions 1 to K+U， wherein each of the K information bits and the U check bits is unambiguously related to one of the K+U bits of the code block； for each of the d determined groups， the respective at least one information bits and the respective check bit are arranged at the code block positions not later than the code block position K+td； the D distributed check bits are p _(U-D) /2+1 to p _(U+D) /2； for each of the D groups， if the respective one of the distributed check bits is p_y， the at least one information bit of the group are determined as the following information bits： b_g b_g+S b_g+2S b_g+3S ... b_g+nS， such that g+nS ≤ K and g＝ (U+D) /2-y+1； the polynomial consists of an outer bit sequence directly followed by D-1 bits having a value of 0 directly followed by the outer bit sequence； the outer bit sequence has a first bit of value 1 and a last bit of value 1； if the outer bit sequence comprises more than 2 bits， at least one of the bits of the outer bit sequence is 0； if U is odd then D and S are odd， and if U is even then D and S are even； K， U， D， and y are integers equal to or larger than 1； S is an integer larger than D and smaller than K； n is an integer equal to or larger than 0； K， U， D， and S are predetermined； g is an integer equal to or larger than 1 and equal to or smaller than D； d is an integer equal to or larger than 1 and equal to or smaller than D； and t is either equal to 0 or equal to 1.

According to a second aspect of the invention， there is provided an apparatus， comprising at least one processor， at least one memory including computer program code， and the at least one processor， with the at least one memory and the computer program code， being arranged to cause the apparatus to at least perform， for a value of g， retrieving respective at least one grouped information bit b_g， b_g+S， b_g+2S， ...， b_g+nS and a respective grouped check bit p_y from a code block of K+U bits， wherein the K+U bits are arranged in the code block at code block positions 1 to K+U， the code block positions of the respective at least one grouped information bit and the respective grouped check bit are predetermined for the value of g and are not later than the code block position K+t； and the K+U bits of the code block consist of K information bits of an ordered sequence of information bits b_K to b₁ and U check bits of an ordered sequence of check bits p₁ to p_U such that each of the K information bits and the U check bits is unambiguously related to one of the K+U bits of the code block； generating a generated check bit for the respective at least one grouped information bit as mod (b_g+b_g+S+b_g+2S+...+b_g+nS， 2) ， checking if the generated check bit is equal to the grouped check bit； inhibiting a retrieving of the bits at the code block positions different from the code block positions predetermined for the value of g if the generated check bit is different from the grouped check bit； wherein g+nS ≤ K and g＝ (U+D) /2-y+1； if U is odd then D and S are odd， and if U is even then D and S are even； K， U， D， and y are integers equal to or larger than 1； S is an integer larger than D and smaller than K； n is an integer equal to or larger than 0； K， U， D， and S are predetermined； and g is an integer equal to or larger than 1 and equal to or smaller than D； and t is either equal to 0 or equal to 1.

According to a third aspect of the invention， there is provided a method， comprising generating an ordered sequence of U check bits p₁ to p_U， for an ordered sequence of K information bits b_K to b₁ by a cyclic redundancy check algorithm based on a polynomial of order U； determining d determined groups among D groups， wherein each of the D groups has a respective group index g， each of the group indices is unique among the D group indices， and each of the D groups consists of at least one of the K information bits b₁ to b_K and a respective one of D distributed check bits of the U check bits such that each of the D distributed check bits is contained in exactly one of the D groups； arranging the K information bits and the U check bits into a code block comprising K+U bits ordered at code block positions 1 to K+U， wherein each of the K information bits and the U check bits is unambiguously related to one of the K+U bits of the code block； for each of the d determined groups， the respective at least one information bits and the respective check bit are arranged at the code block positions not later than the code block position K+td； the D distributed check bits are p _(U-D) /2+1 to p _(U+D) /2； for each of the D groups， if the respective one of the distributed check bits is p_y， the at least one information bit of the group are determined as the following information bits： b_g b_g+S b_g+2S b_g+3S ... b_g+nS， such that g+nS ≤ K and g＝ (U+D) /2-y+1； the polynomial consists of an outer bit sequence directly followed by D-1 bits having a value of 0 directly followed by the outer bit sequence； the outer bit sequence has a first bit of value 1 and a last bit of value 1； if the outer bit sequence comprises more than 2 bits， at least one of the bits of the outer bit sequence is 0； if U is odd then D and S are odd， and if U is even then D and S are even； K， U， D， and y are integers equal to or larger than 1； S is an integer larger than D and smaller than K； n is an integer equal to or larger than 0； K， U， D， and S are predetermined； g is an integer equal to or larger than 1 and equal to or smaller than D； d is an integer equal to or larger than 1 and equal to or smaller than D； and t is either equal to 0 or equal to 1.

According to a fourth aspect of the invention， there is provided a method， comprising， for a value of g， retrieving respective at least one grouped information bit b_g， b_g+S， b_g+2S， ...， b_g+nS and a respective grouped check bit p_y from a code block of K+U bits， wherein the K+U bits are arranged in the code block at code block positions 1 to K+U， the code block positions of the respective at least one grouped information bit and the respective grouped check bit are predetermined for the value of g and are not later than the code block position K+t； and the K+U bits of the code block consist of K information bits of an ordered sequence of information bits b_K to b₁ and U check bits of an ordered sequence of check bits p₁ to p_U such that each of the K information bits and the U check bits is unambiguously related to one of the K+U bits of the code block； generating a generated check bit for the respective at least one grouped information bit as mod (b_g+b_g+S+b_g+2S+...+b_g+nS， 2) ， checking if the generated check bit is equal to the grouped check bit； inhibiting a retrieving of the bits at the code block positions different from the code block positions predetermined for the value of g if the generated check bit is different from the grouped check bit； wherein g+nS ≤ K and g＝ (U+D) /2-y+1； if U is odd then D and S are odd， and if U is even then D and S are even； K， U， D， and y are integers equal to or larger than 1； S is an integer larger than D and smaller than K； n is an integer equal to or larger than 0； K， U， D， and S are predetermined； and g is an integer equal to or larger than 1 and equal to or smaller than D； and t is either equal to 0 or equal to 1.

Each of the methods of the third and fourth aspects may be a method of message processing.

According to a fifth aspect of the invention， there is provided a computer program product comprising a set of instructions which， when executed on an apparatus， is configured to cause the apparatus to carry out the method according to any of the third and fourth aspects. The computer program product may be embodied as a computer-readable medium or directly loadable into a computer.

Further details are set out in the respective dependent claims.

According to some embodiments of the invention， at least one of the following advantages may be achieved：

· Decoding may be terminated early；

· Receiver may determine the respective bit positions based on simple rules；

· Encoding/decoding complexity may be low；

· CRC polynomial may have a good distribution property；

· Rule based interleaving/deinterleaving instead of usage of an interleaving/deinterleaving pattern.

It is to be understood that any of the above modifications can be applied singly or in combination to the respective aspects to which they refer， unless they are explicitly stated as excluding alternatives.

Brief description of the drawings

Further details， features， objects， and advantages are apparent from the following detailed description of the preferred embodiments of the present invention which is to be taken in conjunction with the appended drawings， wherein：

Fig. 1 shows a basic building block of polar codes；

Fig. 2 shows an encoding graph of a length-4 polar code；

Fig. 3 shows an encoding graph of a length-N polar code；

Fig. 4 shows a distribution property of embodiment 1 of the invention；

Fig. 5 shows a distribution property of embodiment 2 of the invention；

Fig. 6 shows an apparatus according to an embodiment of the invention；

Fig. 7 shows a method according to an embodiment of the invention；

Fig. 8 shows an apparatus according to an embodiment of the invention；

Fig. 9 shows a method according to an embodiment of the invention； and

Fig. 10 shows an apparatus according to an embodiment of the invention.

Detailed description of certain embodiments

Herein below， certain embodiments of the present invention are described in detail with reference to the accompanying drawings， wherein the features of the embodiments can be freely combined with each other unless otherwise described. However， it is to be expressly understood that the description of certain embodiments is given by way of example only， and that it is by no way intended to be understood as limiting the invention to the disclosed details.

Moreover， it is to be understood that the apparatus is configured to perform the corresponding method， although in some cases only the apparatus or only the method are described.

According to some embodiments of the invention， the CRC bits are distributed more forward in the code block， while low encoding/decoding complexity is kept. For example， according to some embodiments of the invention， the distribution property of the CRC polynomial is better than that of the polynomials of references [5] to [9] and/or a lower complexity than the polynomial of reference [10] .

According to some embodiments of the invention， at the transmitter side， the following activities are performed：

The U CRC bits (also named check bits) p₁ to p_U are generated for the K information bits， e.g. by a conventional CRC generator using a polynomial of order U. Each CRC bit relates to some information bits. Some of the CRC bits (up to D CRC bits) are distributed between the information bits during transmission. The distributed CRC bits are transmitted in the order of the index of the related information bits.

Suppose the K information bits are indexed in natural order and especially in descending order starting from K to 1. The transmission of the information bits and CRC bits are：

1. Transmit the information bit with index 1； and then transmit information bit with index 1+S； And then 1+2S and so on until the calculated information index， i.e. 1+nS， where n is a natural number larger than or equal to 0， exceeds K (the max index of the information bits) . 1+nS is the largest number no larger than block size K. Then transmit a first one of the CRC bits (not necessarily CRC bit p₁ with index 1， see below) .

2. Transmit the information bit with index 2； then similar to step 1 transmit the information bit(s) with index 2+S， 2+2S， ... ， 2+nS， until the max index of the information bits is exceeded， and then transmit a second one of the CRC bits (not necessarily CRC bit p₂) .

3. Repeat the transmission until the Dth of the CRC bits and their related information bits are transmitted.

4. Transmit the remaining information bits.

5. Transmit the remaining CRC bits.

In order to explain the concept， the information bits and the related CRC bit transmitted in one of the steps above are considered as a group Gg with group index g corresponding to the number of the step.

If the polynomial for the CRC generation is appropriately selected as described below， the CRC bit of the group g can be generated and checked by：

P (g) ＝ mod (b (g) +b (g+S) +... +b (g+nS) ， 2) where P (g) is the CRC bit of group g， and g+nS is the max natural number no larger than the block size K； and b (g) ， b (g+S) ， ... ， b (g+nS) are the corresponding information bits. “mod (s， m) ” denotes the modulo function， here modulo 2. g may be different from the index y of the check bit p_y (see below) .

In order to distinguish the two kinds of indexing for the check bits， P (g) (capital “P” ) indicates a check bit indexed by the corresponding group number and p_y (minuscule “p” ) indicates a check bit indexed according to the order of the generated check bits. The indexing of the information bits is always the same regardless if an information bit is written as b_x or b (x) .

The D distributed CRC bits are the CRC bits in the middle of the CRC bit sequence p₁ to p_U. If the generated CRC bits p_y are indexed from 1 to U for the U CRC bits， from left to right， then the D distributed CRC bits are the bits indexed from (U-D) /2 + 1 to (U+D) /2. Accordingly， the relation between the group index g and the index y of the check bit p_y comprised in the group is g＝ (U+D) /2-y+1. That is： p_y ＝ P ( (U+D) /2-y+1) .

The transmission order of the bits of one group may be for example

· {b (g) b (g+S) ... b (g+nS) P (g) } or

· {P (g) b (g) b (g+S) ... b (g+nS) } or

· {b (g+nS) ... b (g+S) b (g) P (g) } or

· {P (g) b (g+nS) ... b (g+S) b (g) } .

As a still other option， the check bit P (g) may interleave the information bit sequence {b (g) b(g+S) ... b (g+nS) } or {b (g+nS) ... b (g+S) b (g) } at a predetermined position. Also， instead of the ascending or descending order of the information bits， the information bits in the sequence of the information bits may be permutated.

That is， the bits of one group may be transmitted without any bit not belonging to the group interleaving the bit sequence of the group.

If the groups are transmitted according to an ascending order of g， the transmission order of the CRC bits is the reversal order， i.e. from p _(U+D) /2 down to p _{(U-D) /2 + 1}. However， in some embodiments of the invention， the groups may be transmitted in descending order， or in any other predefined order.

This scheme is particularly very useful for uplink because the UE does not need to store a large interleaving pattern.

In some embodiments of the invention， the check bits and information bits may be transmitted in an arbitrary but predefined sequence. As long as all the bits of at least one group are transmitted latest at position K， early termination still can be improved compared to a case where the check bits are transmitted after the information bits.

According to some embodiments of the invention， the polynomial of order U has to fulfill the following requirements：

· the polynomial consists of an outer bit sequence directly followed by D-1 bits having a value of 0 directly followed by the outer bit sequence；

· the outer bit sequence has a first bit of value 1 and a last bit of value 1；

· if the outer bit sequence comprises more than 2 bits， at least one of the bits of the outer bit sequence is 0；

· if U is odd then D and S are odd， and if U is even then D and S are even.

For the parameters and variables， the following conditions apply：

· K， U， D， and y are integers equal to or larger than 1，

· S is an integer larger than D and smaller than K，

· n is an integer equal to or larger than 0，

· K， U， D， and S are predetermined，

· g is an integer equal to or larger than 1 and equal to or smaller than D.

Some example polynomials fulfilling the above requirements are indicated below：

For 19bit CRC， the CRC bits may be generated from any of the below polynomials， wherein the parameter D is 5 and S is 12：

For 20bit CRC， the CRC bits may be generated from any of the below polynomials， wherein the parameter D is 5 and S is 12：

′0x1820C1′ ′0x1420A1′ ′0x1C20E1′ ′0x122091′ ′0x1A20D1′ ′0x1620B1′ ′0x1E20F1′ ′0x112089′ ′0x1920C9′ ′0x1520A9′ ′0x1D20E9′ ′0x132099′ ′0x1B20D9′ ′0x1720B9′ ′0x1F20 F9′ ′0x10A085′ ′0x18A0C5′ ′0x14A0A5′ ′0x1CA0E5′ ′0x12A095′ ′0x1AA0D5′ ′0x16A0B5′ ′0x1EA0F5′ ′0x11A08D′ ′0x19A0CD′ ′0x15A0AD′ ′0x1DA0ED′ ′0x13A09D′ ′0x1BA0DD′ ′0x17A0BD′ ′0x1FA0FD′ ′0x106083′ ′0x1860C3′ ′0x1460A3′ ′0x1C60E3′ ′0x126093′ ′0x1A60D3′ ′0x1660B3′ ′0x1E60F3′ ′0x11608B′ ′0x1960CB′ ′0x1560AB′ ′0x1D60EB′ ′0x13609B′ ′0x1B60DB′ ′0x1760BB′ ′0x1F60FB′ ′0x10E087′ ′0x18E0C7′ ′0x14E0A7′ ′0x1CE0E7′ ′0x12E097′ ′0x1AE0D7′ ′0x16E0B7′ ′0x1EE0F7′ ′0x11E08F′ ′0x19E0CF′ ′0x15E0AF′ ′0x1DE0EF′ ′0x13E09F′ ′0x1BE0DF′ ′0x17E0BF′ ′0x1FE0FF′ ′0x102081′

For 19bit CRC， the CRC bits may also be generated from any of the below polynomials， and the parameter D is 3 and S is 11.

′0xB4969′ ′0x84909’ ′0x9692D’ ′0xE09C1’ ′0xD09A1’ ′0x8590B’ ′0x83907’ ′0x81903′ ′0x90921′ ′0x91923′ ′0x9592B′ ′0x99933′ ′0x9F93F′ ′0xA0941′ ′0xA594B′ ′0xBC979′ ′0xD29A5′ ′0xD79AF′ ′0xD99B3′ ′0xDA9B5′ ′0xF19E3′ ′0xF39E7′ ′0xF89F1′ ′0xE59CB′ ′0xC698D′ ′0xF19E3′ ′0xF39E7′ ′0xF89F1′ ′0xFB9F7′ ′0xE59CB′

At the receiver side， the decoder may successively decodes the coded block. The steps are：

1. Decode all the information bits related of the first group， as well as the CRC bit of the first group.

2. Check the CRC bit based on the decoded information bits of the first group. The check may be made by modulo 2 of the sum of the information bits of the first group： P(g) ＝ mod (b (g) +b (g+S) +... +b (g+nS) ， 2) . Thus， the check can be made much earlier than the decoding of all the information bits and check bits ( “early termination” ) .

3. Decode the information bits of the second group， as well as the CRC bit of the second group. The CRC check is done by comparing it with the decoded CRC bit of the second group with the modulo 2 of the sum of the information bits of the second group.

4. Similarly， decode the information bits CRC bit of the following groups. The CRC check is done for a CRC bit of a specific group by comparing it with the modulo 2 of the sum of the information bits of the group.

5. If one of these CRC checks fails， another decoding path may be tried. If it is found during these CRC checks that all the decoding paths fail to pass the CRC check， the decoding may be terminated.

If a group is transmitted without another bit interleaving the bits of the group， some particular advantages may be achieved. In this case， the information bits and the cRC bit are transmitted in a direct sequence and may be evaluated immediately， such that a large buffer is not required.

In particular， if the transmission is performed in an order， wherein the groups are transmitted first according to a predefined order of the group index (e.g. ascending or descending) ， followed by the remaining information bits and the remaining check bits， and if each of the groups starts or ends with its respective check bit， the information bits of the group are those between the check bit of the group and the previous or subsequent check bit， respectively. Thus， deinterleaving may be performed during the decoding. If a bit is information bit， it is deinterleaved according to its index. For example， for the first CRC bit (transmitted at the end of the group) ， the information bits received before it are those with

index

1， 1+S， ... ， 1+nS， where 1+nS is max index that no larger than the block size， so the information bits can be deinterleaved in the same way to

information queue

1， 1+S， ... ， 1+nS. Correspondingly， in this case， the information bits received after the first check bit and before the second check bit are those of the second group etc.

The information bits and CRC bits after the last distributed CRC bits (remaining information bits and remaining check bits) are not interleaved so they do not need to be deinterleaved. Accordingly， the complexity is low. That is， the interleaving and deinterleaving can be done by counting the information bit index， so an interleaving pattern is not required. In order to evaluate the remaining check bits， the receiver may perform a CRC check of the deinterleaved information bits by the polynomial used to generate the CRC bits and compare the result with the deinterleaved CRC bits.

In the above description of the receiving side， it is assumed that the groups are received in an ascending order of the group index. However， this is not mandatory. The groups may be received in an arbitrary order of the group index if the order is known to the receiver.

Even more， the bits of at least one group may be received with other bits interleaving the bits of the at least one group. In some of these cases， the receiver may have to know an interleaving scheme if it cannot deinterleave based on a rule. In some embodiments， all the bits of at least one group are received prior to position K of the codeword comprising the K information bits and the U check bits.

Some advantages of the scheme according to some embodiments of the invention are：

1. The UE does not need to store an interleaving/deinterleaving pattern. Instead， the interleaving is rule based. This is simpler and more flexible and requires less memory. Conventional schemes require that the UE stores an interleaving/deinterleaving pattern.

2. The checking for early termination is very simple because may only involves the information bits between the CRC bits. In previous scheme， CRC detector or complex checking is required.

3. The solution is based on some unique CRC polynomials which are newly proposed and which have good error detection capability.

4. In particular， the CRC bits may be distributed much front with these new polynomials compared to previous schemes. Thus， they have better early termination performance， for example about 20％gain over previous scheme.

In the conventional case， when the code block is decoded， CRC generation may start immediately after the K information bits and the first CRC bit had been read. That is， after the K information bits had been read， a first polynomial division may be performed in order to generate the first CRC bit. If the generated first CRC bit does not match the retrieved first check bit， the CRC check fails and the code block may be discarded. And so on for the second， third， ... CRC bits.

In some embodiments， the bits of at least one group are arranged in the code block on positions not later than K+1. For d groups (1 ≤ d ≤ D) the bits of the d groups are arranged in the code block on positions not later than K+d， e.g. for D groups not later than on position K+D. In this case， early termination may be performed as early as in a conventional code block with CRC bits generated based on an arbitrary polynomial， wherein， the check bits are arranged starting with the first check bit (most significant check bit) .

Note that the above restriction describes a worst case in terms of positioning the bits of at least one group as front as possible. In some embodiments， all the bits of the d groups may be arranged at positions earlier than position K+d. For example， in a preferred case， if the first group comprises I bits (I-1 information bits and 1 check bit) ， the bits of the first group may be positioned at positions 1 to I.

According to the embodiments of the invention where the bits of at least one group are positioned not later than position K+1， a check bit may be generated based on the modulo operation for the group： P (g) ＝ mod (b (g) +b (g+S) +... +b (g+nS) ， 2) ， and may be compared with the retrieved check bit of the group to decide on early termination. Hence， early termination may be performed as fast as in the conventional case. The same applies correspondingly to each of the d groups which are positioned in the code block not later than position K+d.

In addition， these embodiments of the invention provide an advantage： The generating of the distributed check bits by the modulo function for early termination is easier than a polynomial division. Hence， if decoding is early terminated， the computational effort is reduced.

On the other hand， if decoding is not early terminated， polynomial division may still be performed in order to evaluate the remaining check bits. Hence， in case of successful decoding， the total computational effort is increased compared to the conventional case.

Therefore， in some embodiments of the invention， regardless of whether the bits of d groups are arranged at positions 1 to K or positions 1 to K+d， generating of the check bits by the modulo function is performed only if the transmission quality is poor (worse than a certain threshold) such that early termination will likely occur. If the transmission quality is better than the threshold， check bits are not generated by the modulo function but polynomial division is performed only. The receiver may decide on the quality of the transmission e.g. based on a quality of previous transmissions (number of early terminations in a certain time period， and/or number of successful transmissions in a certain time period， and/or percentage of early terminations in a certain time period) ， and/or based on an estimation of the reference signal of the current transmission (if available) .

Some example embodiments are described at greater detail. In these embodiments， the groups are transmitted in ascending order of the group index without any interleaving bits between the bits of one group. The remaining information bits follow the groups and are followed by the remaining check bits.

Embodiment 1：

In this embodiment， we give one example for CRC distribution scheme based on 19bit CRC whose polynomial is [0xA10A1] ， D＝5 and S＝12.

First， the distributing property can be examined by the percent of the bits before each CRC bit. It is shown in Fig. 4. Each of the lines shows the percentage of bits of the code block transmitted before the respective distributed check bit. The lowest line is for the first distributed check bit， the second lowest line is for the second distributed check bit， etc. For example， for 40 information bits， the first CRC bit of the 19 CRC bits is transmitted after four information bits (b1 b13 b25 b37) . Thus， there are 4/ (40+19) ＝ 6.7％of the bits in front of the first CRC bit. For the second CRC bit， another four information bits (b2 b14 b26 b38) are in front of the second CRC bit such that 9 bits (8 information bits and the first CRC bit) are in front of the second CRC bit， corresponding to 9/ (40+19) ＝ 15.25％.

It can be seen from Fig. 4， that the distribution property is very good. The five distributed CRC bits are transmitted in very front position， less than 42％of the code block.

Suppose K＝16， the transmission order is：

{b1 b13 P1 b2 b14 P2 b3 b15 P3 b4 b16 P4 b5 P5 b6 b7 b8 b9 b10 b11 b12 p₁ p₂ p₃ p₄ p₅ p₆ p₇ p₁₃ p₁₄ p₁₅ p₁₆ p₁₇ p₁₈ p₁₉} .

Note that check bits P1 to P5 are indexed by the group index and correspond to p₁₂ to p₈， respectively， indexed by the CRC result index. That is， group 1 comprises the bits b1， b13， and P1＝p₁₂； group 2 comprises the bits b2， b14， and P2＝p₁₁， ...， and group 5 comprises the bits b5 and P5＝p₈.

Embodiment 2：

In this embodiment， we give one example for CRC distribution scheme based on 19bit CRC whose polynomial is [0x9604B] ， D＝7 and S＝13.

First， the distributing property may be examined by the percent of the bits before each CRC bit. It is shown in Fig. 5 corresponding to Fig. 4. It can be seen from Fig. 5， it is very good. The seven distributed CRC bits are transmitted in very front position， less than 55％of the code block.

Suppose K＝16， the transmission order is：

{b1 b14 P1 b2 b15 P2 b3 b16 P3 b4 P4 b5 P5 b6 P6 b7 P7 b8 b9 b10 b11 b12 b13 p₁ p₂ p₃ p₄ p₅ p₆ p₁₄ p₁₅ p₁₆ p₁₇ p₁₈ p₁₉}

Embodiment 3：

For the distributed CRC transmission scheme with a 11bit CRC， the following CRC one of the following polynomials may be used.

With the following CRC polynomials， D＝5， S＝8， most of the CRC bitsare distributed to the front， meanwhile they have a minimum Hamming weight of 4 for K up to 57.

[0xD0D]

[0xB0B]

With the following CRC polynomial， D＝3， S＝7， three CRC bits are distributed to the front (40％of all information bits) ， meanwhile they have a minimum Hamming weight of 4 for K up to 106.

[0xC99]

[0x993]

With the following CRC polynomial， D＝1， S＝6， one CRC bit is distributed to the front (60％of all information bits) ， meanwhile they have a minimum Hamming weight of 4 for K up to 187.

[0x965]

[0xA69]

With the following CRC polynomial， D＝1， S＝6， one CRC bit is distributed to the front (15％of all information bits) ， meanwhile it has a minimum Hamming weight of 4 for K up to 187.

[0xEFB]

[0xDF7]

Fig. 6 shows an apparatus according to an embodiment of the invention. The apparatus may be a code block interleaving unit of an eNodeB or a UE or an element thereof. Fig. 7 shows a method according to an embodiment of the invention. The apparatus according to Fig. 6 may perform the method of Fig. 7 but is not limited to this method. The method of Fig. 7 may be performed by the apparatus of Fig. 6 but is not limited to being performed by this apparatus.

The apparatus comprises generating means 10， determining means 20， and arranging means 30. Each of the generating means 10， determining means 20， and arranging means 30 may be a generator， determinator， and arranger， respectively. Each of the generating means 10， determining means 20， and arranging means 30 may be a generating processor， determining processor， and arranging processor， respectively.

The generating means 10 generates an ordered sequence of U check bits p₁ to p_U for an ordered sequence of K information bits b_K to b₁ by a cyclic redundancy check algorithm based on a polynomial of order U (S10) .

The polynomial consists of an outer bit sequence directly followed by D-1 bits having a value of 0 directly followed by the outer bit sequence， i.e. the same bit sequence as that in front of the D-1 bits having the value 0. The outer bit sequence has a first bit of value 1 and a last bit of value 1. The outer bit sequence may consist of only one bit having a value of 1. If the outer bit sequence comprises more than 2 bits， at least one of the bits of the outer bit sequence is 0. If U is odd then D and S (see below) are odd， and if U is even then D and S are even.

The determining means 20 determines d determined groups among D groups G_g (S20) . Each of the D groups G_g has a respective group index g， and each of the group indices is unique among the D group indices. Each of the D groups consists of at least one of the K information bits b₁ to b_K and a respective one of D distributed check bits of the U check bits (S20) . Each of the D distributed check bits is contained in exactly one of the D groups. The D distributed check bits are p _(U-D) /2+1 to p _(U+D) /2. For each of the D groups G_g， if the respective one of the distributed check bits is p_y， the at least one information bit of the group are determined as the following information bits： b_g b_g+S b_g+2S b_g+3S ... b_g+nS， such that g+nS ≤ K and g＝ (U+D) /2-y+1. d is an integer with 1 ≤ d ≤ D.

The arranging means 30 arranges the K information bits and the U check bits into a code block comprising K+U bits ordered at positions 1 to K+U (S30) . Each of the K information bits and the U check bits is unambiguously related to one of the K+U bits of the code block. For each of the d determined groups G_g， the respective at least one information bits and the respective check bit are arranged at code block positions of the code block not later than the code block position K+td. t is a constant. Either t＝0 or t＝1.

K， U， D， and y are integers equal to or larger than 1. S is an integer larger than D and smaller than K. n is an integer equal to or larger than 0. K， U， D， and S are predetermined. g is an integer equal to or larger than 1 and equal to or smaller than D.

Fig. 8 shows an apparatus according to an embodiment of the invention. The apparatus may be a code block deinterleaving unit of an eNodeB or a UE or an element thereof. Fig. 9 shows a method according to an embodiment of the invention. The apparatus according to Fig. 8 may perform the method of Fig. 9 but is not limited to this method. The method of Fig. 9 may be performed by the apparatus of Fig. 8 but is not limited to being performed by this apparatus.

The apparatus comprises retrieving means 110， generating means 120， checking means 130， and inhibiting means 140. Each of the retrieving means 110， generating means 120， checking means 130， and inhibiting means 140 may be a retriever， generator， checker and inhibitor， respectively. Each of the retrieving means 110， generating means 120， checking means 130， and inhibiting means 140 may be a retrieving processor， generating processor， checking processor， and inhibiting processor， respectively.

The retrieving means 110 retrieves， for a value of g， respective at least one grouped information bit b_g， b_g+S， b_g+2S， ...， b_g+nS and a respective grouped check bit py from a code block of K+U bits (S110) .

The K+U bits are arranged in the code block at code block positions 1 to K+U. The code block positions of the respective at least one grouped information bit and the respective grouped check bit are predetermined for the value of g and are not later than the code block position K+t. The K+U bits of the code block consist of K information bits of an ordered sequence of information bits b_K to b₁ and U check bits of an ordered sequence of check bits p₁ to p_U. Each of the K information bits and the U check bits is unambiguously related to one of the K+U bits of the code block. t is a constant. Either t＝0 or t＝1.

The generating means 120 generates a generated check bit for the respective at least one grouped information bit as mod (b_g+b_g+S+b_g+2S+...+b_g+nS， 2) (S120) .

The checking means 130 checks if the generated check bit generated in S120 is equal to the grouped check bit retrieved from the code block (S130) .

If the generated check bit is different from the grouped check bit (S130 ＝ “no” ) ， the inhibiting means 140 inhibits a retrieving of the bits at the code block positions different from the code block positions predetermined for the value of g (S140) .

Also in this embodiment， the following relationships apply for the parameters and variables： g+nS ≤ K and g＝ (U+D) /2-y+1. If U is odd then D and S are odd， and if U is even then D and S are even. K， U， D， and y are integers equal to or larger than 1. S is an integer larger than D and smaller than K. n is an integer equal to or larger than 0. K， U， D， and S are predetermined. g is an integer equal to or larger than 1 and equal to or smaller than D.

In some embodiments of the invention， one or more of the following additional restrictions may apply：

· D ≥ 2， such that at least one bit of the polynomial different from the outer bit sequence is 0；

· U ＞ D， such that there are more check bits than the grouped check bits； and

· K ≥ U， such that the number of information bits is not larger than the number of check bits.

Fig. 10 shows an apparatus according to an embodiment of the invention. The apparatus comprises at least one processor 410， at least one memory 420 including computer program code， and the at least one processor 410， with the at least one memory 420 and the computer program code， being arranged to cause the apparatus to at least perform at least one of the methods according to Figs. 7 and 9.

Some embodiments of the invention are described wherein the information bits and check bits are transmitted and received， respectively， in a specific sequence. However， according to some embodiments of the invention， only a code block comprising the information bits and check bits in the specific sequence is provided which may be transmitted from a transmitting device not belonging to an apparatus of some embodiments of the invention.

Also， an apparatus according to some embodiments of the invention may not receive the code block but may fetch the code block from some place， e.g. the place where the former apparatus stored the code block. Hence， although some embodiments of the invention transmit the code block and receive the code block， respectively， neither transmitting the code block nor receiving the code block are essential for some embodiments of the invention.

Some embodiments of the invention may be employed in 3GPP devices， e.g. in the encoding unit and/or decoding unit thereof. However， embodiments of the invention are not limited to 3GPP devices. They may be employed in any kind of devices where CRC bits are used to protect a transmission and early termination may be useful. In particular， they may be employed in devices employing polar (de-) coding for transmission and/or reception. However， embodiments of the invention are not limited to the use of polar coding in the transmission. Other coding examples are Hamming code， LDPC code， convolutional code， Turbo code and BCH code.

One piece of information may be transmitted in one or plural messages from one entity to another entity. Each of these messages may comprise further (different) pieces of information.

Names of network elements， protocols， and methods are based on current standards. In other versions or other technologies， the names of these network elements and/or protocols and/or methods may be different， as long as they provide a corresponding functionality.

The format of the messages and information elements is not limited the those shown in some of the figures. These formats are to be seen as examples only.

If not otherwise stated or otherwise made clear from the context， the statement that two entities are different means that they perform different functions. It does not necessarily mean that they are based on different hardware. That is， each of the entities described in the present description may be based on a different hardware， or some or all of the entities may be based on the same hardware. It does not necessarily mean that they are based on different software. That is， each of the entities described in the present description may be based on different software， or some or all of the entities may be based on the same software. Each of the entities described in the present description may be embodied in the cloud.

According to the above description， it should thus be apparent that example embodiments of the present invention provide， for example， a base station such as a eNodeB， or a component such as a TX path or an encoding unit or a RX path or a decoding unit thereof， or a terminal such as a User Equipment or a MTC device， or a component such as a TX path or an encoding unit or a RX path or a decoding unit thereof， an apparatus embodying the same， a method for controlling and/or operating the same， and computer program (s) controlling and/or operating the same as well as mediums carrying such computer program (s) and forming computer program product (s) .

Implementations of any of the above described blocks， apparatuses， systems， techniques or methods include， as non-limiting examples， implementations as hardware， software， firmware， special purpose circuits or logic， general purpose hardware or controller or other computing devices， or some combination thereof.

It is to be understood that what is described above is what is presently considered the preferred embodiments of the present invention. However， it should be noted that the description of the preferred embodiments is given by way of example only and that various modifications may be made without departing from the scope of the invention as defined by the appended claims.

Claims

Apparatus， comprising at least one processor， at least one memory including computer program code， and the at least one processor， with the at least one memory and the computer program code， being arranged to cause the apparatus to at least perform

generating an ordered sequence of U check bits p₁ to p_U for an ordered sequence of K information bits b_K to b₁ by a cyclic redundancy check algorithm based on a polynomial of order U；

determining d determined groups among D groups， wherein each of the D groups has a respective group index g， each of the group indices is unique among the D group indices， and each of the D groups consists of at least one of the K information bits b₁ to b_K and a respective one of D distributed check bits of the U check bits such that each of the D distributed check bits is contained in exactly one of the D groups；

arranging the K information bits and the U check bits into a code block comprising K+U bits ordered at code block positions 1 to K+U， wherein

each of the K information bits and the U check bits is unambiguously related to one of the K+U bits of the code block；

for each of the d determined groups， the respective at least one information bits and the respective check bit are arranged at the code block positions not later than the code block position K+td；

the D distributed check bits are p _(U-D) /2+1 to p _(U+D) /2；

for each of the D groups， if the respective one of the distributed check bits is p_y， the at least one information bit of the group are determined as the following information bits： b_g b_g+S b_g+2S b_g+3S ... b_g+nS， such that g+nS ≤ K and g＝ (U+D) /2-y+1；

the polynomial consists of an outer bit sequence directly followed by D-1 bits having a value of 0 directly followed by the outer bit sequence；

the outer bit sequence has a first bit of value 1 and a last bit of value 1；

if the outer bit sequence comprises more than 2 bits， at least one of the bits of the outer bit sequence is 0；

if U is odd then D and S are odd， and if U is even then D and S are even；

K， U， D， and y are integers equal to or larger than 1； S is an integer larger than D and smaller than K； n is an integer equal to or larger than 0； K， U， D， and S are predetermined； g is an integer equal to or larger than 1 and equal to or smaller than D； d is an integer equal to or larger than 1 and equal to or smaller than D； and t is either equal to 0 or equal to 1.
The apparatus according to claim 1， wherein for each of the d determined groups， the respective at least one information bits and the respective check bit are arranged without any other bit interleaving the respective at least one information bit and the respective check bit.
The apparatus according to claim 2， wherein for each of the d determined groups， the information bits are arranged in a respective type of sequence {b_g b_g+S b_g+2S b_g+3S ... b_g+nS} or {b_g+nS ... b_g+3S b_g+2S b_g+S b_g} ， wherein the respective sequence is arranged directly following the respective check bit p_y， or the respective check bit p_y is arranged directly following the respective sequence， or the respective check bit p_y is arranged interleaving the respective sequence of the information bits at a respective predetermined position relative to the respective sequence of the information bits.
The apparatus according to claim 3， wherein the type of sequence is the same for all the D groups， and a position of the respective check bit relative to the sequence is the same for all the D groups.
The apparatus according to any of claims 1 to 4， wherein d＝D.
The apparatus according to claim 5， wherein the information bits not contained in any of the D groups and the check bits not contained in any of the D groups are arranged at the code block positions following the code block positions at which the information bits and the check bits of the D groups are arranged.
The apparatus according to any of claims 1 to 6， wherein at least one of D ≥ 2； U ＞ D； and K ≥ U.
Apparatus， comprising at least one processor， at least one memory including computer program code， and the at least one processor， with the at least one memory and the computer program code， being arranged to cause the apparatus to at least perform， for a value of g，

retrieving respective at least one grouped information bit b_g， b_g+S， b_g+2S， ...， b_g+nS and a respective grouped check bit p_y from a code block of K+U bits， wherein

the K+U bits are arranged in the code block at code block positions 1 to K+U，

the code block positions of the respective at least one grouped information bit and the respective grouped check bit are predetermined for the value of g and are not later than the code block position K+t； and

the K+U bits of the code block consist of K information bits of an ordered sequence of information bits b_K to b₁ and U check bits of an ordered sequence of check bits p₁ to p_U such that each of the K information bits and the U check bits is unambiguously related to one of the K+U bits of the code block；

generating a generated check bit for the respective at least one grouped information bit as mod (b_g+b_g+S+b_g+2S+...+b_g+nS， 2) ，

checking if the generated check bit is equal to the grouped check bit；

inhibiting a retrieving of the bits at the code block positions different from the code block positions predetermined for the value of g if the generated check bit is different from the grouped check bit； wherein

g+nS ≤ K and g＝ (U+D) /2-y+1；

if U is odd then D and S are odd， and if U is even then D and S are even；

K， U， D， and y are integers equal to or larger than 1； S is an integer larger than D and smaller than K； n is an integer equal to or larger than 0； K， U， D， and S are predetermined； and g is an integer equal to or larger than 1 and equal to or smaller than D； and t is either equal to 0 or equal to 1.
The apparatus according to claim 8， wherein， for the value of g， the respective at least one grouped information bit and the respective grouped check bit are arranged in the code block without any other bit interleaving the respective at least one grouped information bit and the respective grouped check bit.
The apparatus according to claim 9， wherein， for the value of g， the respective at least one grouped information bit are arranged in a respective ordered information bit sequence of {b_g b_g+S b_g+2S b_g+3S ... b_g+nS} or {b_g+nS ... b_g+3S b_g+2S b_g+S b_g} ， and the information bit sequence is arranged directly following the respective grouped check bit p_y， or the respective grouped check bit p_y is arranged directly following the respective information bit sequence， or the respective grouped check bit p_y is arranged interleaving the respective information bit sequence at a predetermined position relative to the information bit sequence for the value of g.
The apparatus according to any of claims 8 to 10， wherein the at least one processor， with the at least one memory and the computer program code， being arranged to cause the apparatus to further perform

repeating the retrieving， generating， checking， and inhibiting for each value of g between 1 and d， wherein

the code block positions of the respective at least one grouped information bit and the respective grouped check bit are predetermined for each of the values of g and are not later than the code block position K+td；

d is an integer equal to or larger than 1 and equal to or smaller than D.
The apparatus according to claim 11， wherein d＝D； and

each of the K information bits and the U check bit is assigned to only one of the values of g or to none of the values of g.
The apparatus according to any of claims 8 to 12， wherein the at least one processor， with the at least one memory and the computer program code， being arranged to cause the apparatus to further perform

retrieving remaining information bits of the K information bits and remaining check bits of the U check bits， wherein the remaining information bits and the remaining check bits are not retrieved for any of the values of g；

assigning an information bit index between 1 and K to each of the remaining information bits based on the respective code block position of the respective remaining information bit according to a first predetermined rule such that each of the retrieved information bits and the remaining information bits has a unique information bit index；

assigning a check bit index between 1 and U to each of the remaining check bits based on the respective code block position of the respective remaining check bit according to a second predetermined rule such that each of the retrieved check bits and the remaining check bits has a unique check bit index；

arranging the K grouped information bits and remaining information bits in the ordered sequence of the information bits b_K to b₁ according to their respective information bit indices；

arranging the U grouped check bits and remaining check bits in the ordered sequence of the check bits p₁ to p_U according to their respective check bit indices；

generating an ordered sequence of U generated check bits for the ordered sequence of the information bits by a cyclic redundancy check algorithm based on a polynomial of order U；

checking if the ordered sequence of the generated check bits is equal to the ordered sequence of the check bits；

discarding the ordered sequence of the information bits if the ordered sequence of the generated check bits is not equal to the ordered sequence of the check bits； wherein

g， g+S， g+2S， ...， g+nS denote the respective information bit indices of the grouped information bits for one of the values of g；

y denotes the respective check bit index of the grouped check bit retrieved for one of the values of g；

the polynomial consists of an outer bit sequence directly followed by D-1 bits having a value of 0 directly followed by the outer bit sequence；

the outer bit sequence has a first bit of value 1 and a last bit of value 1；

if the outer bit sequence comprises more than 2 bits， at least one of the bits of the outer bit sequence is 0.
The apparatus according to claim 13 dependent on claim 9， wherein

the code block comprises the grouped information bits and the grouped check bits for different values of g according to a predetermined sequence of the values of g between 1 and D， followed by the remaining information bits arranged in a predetermined first order and the remaining check bits arranged in a predetermined second order， and

the at least one processor， with the at least one memory and the computer program code， being arranged to cause the apparatus to further perform

determining the predetermined code block positions based on the values of K， U， D， and S， the predetermined sequence of the values of g， the respective information bit sequence of the grouped information bits for each value of g， the respective position of the respective grouped check bit relative to the respective sequence of the grouped information bits for each value of g， the predetermined first order， and the predetermined second order.
The apparatus according to claim 14， wherein at least one of

the respective information bit sequence of the grouped information bits is the same for all values of g，

the position of the respective grouped check bit relative to the respective sequence is the same for all values of g，

the first order is either ascending or descending， and

the second order is either ascending or descending.
The apparatus according to any of claims 8 to 15， wherein at least one of D ≥ 2； U ＞ D； and K ≥ U.
Method， comprising

generating an ordered sequence of U check bits p₁ to p_U for an ordered sequence of K information bits b_K to b₁ by a cyclic redundancy check algorithm based on a polynomial of order U；

determining d determined groups among D groups， wherein each of the D groups has a respective group index g， each of the group indices is unique among the D group indices， and each of the D groups consists of at least one of the K information bits b₁ to b_K and a respective one of D distributed check bits of the U check bits such that each of the D distributed check bits is contained in exactly one of the D groups；

arranging the K information bits and the U check bits into a code block comprising K+U bits ordered at code block positions 1 to K+U， wherein

each of the K information bits and the U check bits is unambiguously related to one of the K+U bits of the code block；

for each of the d determined groups， the respective at least one information bits and the respective check bit are arranged at the code block positions not later than the code block position K+td；

the D distributed check bits are p _(U-D) /2+1 to p _(U+D) /2；

for each of the D groups， if the respective one of the distributed check bits is p_y， the at least one information bit of the group are determined as the following information bits： b_g b_g+S b_g+2S b_g+3S ... b_g+nS， such that g+nS ≤ K and g＝ (U+D) /2-y+1；

the polynomial consists of an outer bit sequence directly followed by D-1 bits having a value of 0 directly followed by the outer bit sequence；

the outer bit sequence has a first bit of value 1 and a last bit of value 1；

if the outer bit sequence comprises more than 2 bits， at least one of the bits of the outer bit sequence is 0；

if U is odd then D and S are odd， and if U is even then D and S are even；

K， U， D， and y are integers equal to or larger than 1； S is an integer larger than D and smaller than K； n is an integer equal to or larger than 0； K， U， D， and S are predetermined； g is an integer equal to or larger than 1 and equal to or smaller than D； d is an integer equal to or larger than 1 and equal to or smaller than D； and t is either equal to 0 or equal to 1.
The method according to claim 17， wherein for each of the d determined groups， the respective at least one information bits and the respective check bit are arranged without any other bit interleaving the respective at least one information bit and the respective check bit.
The method according to claim 18， wherein for each of the d determined groups， the information bits are arranged in a respective type of sequence {b_g b_g+S b_g+2S b_g+3S ... b_g+nS} or {b_g+nS ... b_g+3S b_g+2S b_g+S b_g} ， wherein the respective sequence is arranged directly following the respective check bit p_y， or the respective check bit p_y is arranged directly following the respective sequence， or the respective check bit p_y is arranged interleaving the respective sequence of the information bits at a respective predetermined position relative to the respective sequence of the information bits.
The method according to claim 19， wherein the type of sequence is the same for all the D groups， and a position of the respective check bit relative to the sequence is the same for all the D groups.
The method according to any of claims 17 to 20， wherein d＝D.
The method according to claim 21， wherein the information bits not contained in any of the D groups and the check bits not contained in any of the D groups are arranged at the code block positions following the code block positions at which the information bits and the check bits of the D groups are arranged.
The method according to any of claims 17 to 22， wherein at least one of D ≥ 2； U ＞ D； and K ≥ U.
Method， comprising， for a value of g，

retrieving respective at least one grouped information bit b_g， b_g+S， b_g+2S， ...， b_g+nS and a respective grouped check bit p_y from a code block of K+U bits， wherein

the K+U bits are arranged in the code block at code block positions 1 to K+U，

the code block positions of the respective at least one grouped information bit and the respective grouped check bit are predetermined for the value of g and are not later than the code block position K+t； and

the K+U bits of the code block consist of K information bits of an ordered sequence of information bits b_K to b₁ and U check bits of an ordered sequence of check bits p₁ to p_U such that each of the K information bits and the U check bits is unambiguously related to one of the K+U bits of the code block；

generating a generated check bit for the respective at least one grouped information bit as mod (b_g+b_g+S+b_g+2S+...+b_g+nS， 2) ，

checking if the generated check bit is equal to the grouped check bit；

inhibiting a retrieving of the bits at the code block positions different from the code block positions predetermined for the value of g if the generated check bit is different from the grouped check bit； wherein

g+nS ≤ K and g＝ (U+D) /2-y+1；

if U is odd then D and S are odd， and if U is even then D and S are even；

K， U， D， and y are integers equal to or larger than 1； S is an integer larger than D and smaller than K； n is an integer equal to or larger than 0； K， U， D， and S are predetermined； and g is an integer equal to or larger than 1 and equal to or smaller than D； and t is either equal to 0 or equal to 1.
The method according to claim 24， wherein， for the value of g， the respective at least one grouped information bit and the respective grouped check bit are arranged in the code block without any other bit interleaving the respective at least one grouped information bit and the respective grouped check bit.
The method according to claim 25， wherein， for the value of g， the respective at least one grouped information bit are arranged in a respective ordered information bit sequence of {b_g b_g+S b_g+2S b_g+3S ... b_g+nS} or {b_g+nS ... b_g+3S b_g+2S b_g+S b_g} ， and the information bit sequence is arranged directly following the respective grouped check bit p_y， or the respective grouped check bit p_y is arranged directly following the respective information bit sequence， or the respective grouped check bit p_y is arranged interleaving the respective information bit sequence at a predetermined position relative to the information bit sequence for the value of g.
The method according to any of claims 24 to 26， further comprising

repeating the retrieving， generating， checking， and inhibiting for each value of g between 1 and d， wherein

the code block positions of the respective at least one grouped information bit and the respective grouped check bit are predetermined for each of the values of g and are not later than the code block position K+td；

d is an integer equal to or larger than 1 and equal to or smaller than D.
The method according to claim 27， wherein d＝D； and

each of the K information bits and the U check bit is assigned to only one of the values of g or to none of the values of g.
The method according to any of claims 24 to 28， further comprising

retrieving remaining information bits of the K information bits and remaining check bits of the U check bits， wherein the remaining information bits and the remaining check bits are not retrieved for any of the values of g；

assigning an information bit index between 1 and K to each of the remaining information bits based on the respective code block position of the respective remaining information bit according to a first predetermined rule such that each of the retrieved information bits and the remaining information bits has a unique information bit index；

assigning a check bit index between 1 and U to each of the remaining check bits based on the respective code block position of the respective remaining check bit according to a second predetermined rule such that each of the retrieved check bits and the remaining check bits has a unique check bit index；

arranging the K grouped information bits and remaining information bits in the ordered sequence of the information bits b_K to b₁ according to their respective information bit indices；

arranging the U grouped check bits and remaining check bits in the ordered sequence of the check bits p₁ to p_U according to their respective check bit indices；

generating an ordered sequence of U generated check bits for the ordered sequence of the information bits by a cyclic redundancy check algorithm based on a polynomial of order U；

checking if the ordered sequence of the generated check bits is equal to the ordered sequence of the check bits；

discarding the ordered sequence of the information bits if the ordered sequence of the generated check bits is not equal to the ordered sequence of the check bits； wherein

g， g+S， g+2S， ...， g+nS denote the respective information bit indices of the grouped information bits for one of the values of g；

y denotes the respective check bit index of the grouped check bit retrieved for one of the values of g；

the polynomial consists of an outer bit sequence directly followed by D-1 bits having a value of 0 directly followed by the outer bit sequence；

the outer bit sequence has a first bit of value 1 and a last bit of value 1；

if the outer bit sequence comprises more than 2 bits， at least one of the bits of the outer bit sequence is 0.
The method according to claim 29 dependent on claim 25， wherein

the code block comprises the grouped information bits and the grouped check bits for different values of g according to a predetermined sequence of the values of g between 1 and D， followed by the remaining information bits arranged in a predetermined first order and the remaining check bits arranged in a predetermined second order， and the method further comprises

determining the predetermined code block positions based on the values of K， U， D， and S， the predetermined sequence of the values of g， the respective information bit sequence of the grouped information bits for each value of g， the respective position of the respective grouped check bit relative to the respective sequence of the grouped information bits for each value of g， the predetermined first order， and the predetermined second order.
The method according to claim 30， wherein at least one of

the respective information bit sequence of the grouped information bits is the same for all values of g，

the position of the respective grouped check bit relative to the respective sequence is the same for all values of g，

the first order is either ascending or descending， and

the second order is either ascending or descending.
The method according to any of claims 24 to 31， wherein at least one of D ≥ 2； U ＞ D； and K ≥ U.
A computer program product comprising a set of instructions which， when executed on an apparatus， is configured to cause the apparatus to carry out the method according to any of claims 17 to 32.
The computer program product according to claim 33， embodied as a computer-readable medium or directly loadable into a computer.