WO2019037782A1

WO2019037782A1 - Decoding method and decoder for polar code

Info

Publication number: WO2019037782A1
Application number: PCT/CN2018/102297
Authority: WO
Inventors: 郭晗
Original assignee: 华为技术有限公司
Priority date: 2017-08-25
Filing date: 2018-08-24
Publication date: 2019-02-28
Also published as: CN109428608A

Abstract

A decoding method and a decoder for a polar code. The decoding method comprises: acquiring data to be decoded; respectively starting to perform successive cancellation list (SCL) decoding and successive cancellation (SC) decoding on the data; obtaining a decoding result of the SC decoding; where it is determined that the decoding result of the SC decoding is correct, stopping the SCL decoding; and outputting the decoding result of the SC decoding. The decoding method for a polar code provided can respectively perform SCL decoding and SC decoding on data to be decoded, and where it is determined that a decoding result of the SC decoding is correct, the SC decoding result is output as a final decoding result of the data and the SCL decoding on the data is stopped. The present invention reduces a decoding delay and improves the decoding efficiency on the premise that the accurate decoding performance of decoding of a polar code is ensured.

Description

Polarization code decoding method and decoder

This application claims the priority of the Chinese Patent Application filed on August 25, 2017, the Chinese Patent Application No. PCT Application No. In this application.

Technical field

The present application relates to the field of communications and, more particularly, to a decoding method and decoder for a polarization code in the field of communications.

Background technique

Communication systems usually use channel coding to improve the reliability of data transmission to ensure the quality of communication. The Polar code is the first code that theoretically proves that Shannon capacity can be obtained and has low decoding complexity. The Polar code is a linear block code, and its decoding can be serially cancelled (SC). A decoding method or a serial cancellation list (SCL) decoding method performs decoding.

SC decoding and SCL decoding each have their own strengths. From the perspective of decoding performance, SC decoding can achieve good performance when the code length is long, but when the code length is short or medium length, the SC decoding performance of the Polar code is poor. For SCL decoding, the performance of SCL decoding is improved relative to the performance of SC decoding. However, from the processing delay of decoding, the complexity of SCL decoding is higher than that of SC decoding. The time is large, and the SC decoding complexity is low, the decoding accuracy is low, but the decoding delay is small.

Summary of the invention

The present application provides a decoding method and decoder for a polarization code. The data to be decoded is subjected to SCL decoding and SC decoding, respectively. When it is determined that the decoding result of the SC decoding is correct, the SC decoding result is output as the final decoding result of the data, and stops. SCL decoding of the data is performed. The polar code decoding reduces the decoding delay and improves the decoding efficiency under the premise of ensuring accurate decoding performance.

In a first aspect, a method for decoding a polarization code is provided, the method comprising: acquiring data to be decoded; respectively starting a serial cancellation list SCL decoding and serial cancellation SC decoding on the data; The decoding result of the SC decoding; if it is determined that the decoding result of the SC decoding is correct, the SCL decoding is stopped; and the decoding result of the SC decoding is output.

The method for decoding a polarization code provided by the first aspect performs serial cancellation list SCL decoding and serial cancellation SC decoding in parallel by data to be decoded. Since the SC decoding delay is small, the decoding accuracy is low and the bit error rate is high. The delay of SCL decoding is larger, but the decoding accuracy is higher and the bit error rate is lower. Therefore, the data to be decoded is subjected to SC decoding and SCL decoding, respectively, and the SC decoding result is obtained first. When it is determined that the decoding result of the SC decoding is correct, the SCL decoding of the data is stopped, and The decoding result of the SC decoding is used as the final decoding result. The polar code decoding reduces the decoding delay and improves the decoding efficiency under the premise of ensuring accurate decoding performance.

In a possible implementation manner of the first aspect, in a case where it is determined that the decoding result of the SC decoding is incorrect, the method further includes: performing the SCL decoding; and outputting the decoding result of the SCL decoding. .

In a possible implementation manner of the first aspect, the separately performing serial cancellation list SCL decoding and serial cancellation SC decoding on the data includes: performing the SCL decoding on the data in parallel and the SC Decoding.

In a possible implementation manner of the first aspect, the method further includes: performing a cyclic redundancy CRC check on the decoding result of the SC decoding; and determining, in the case that the CRC check passes, determining the SC decoding The decoding result is correct, or if the CRC check fails, it is determined that the decoding result of the SC decoding is incorrect.

In a possible implementation of the first aspect, the search width of the SCL decoding is 8 decoding paths. In this implementation, the decoding delay is lower and the decoding accuracy is relatively better.

In a second aspect, a decoder is provided for performing the decoding method of the polarization code in the first aspect and various implementations described above. The decoder includes an acquisition circuit, an SCL decoding circuit, an SC decoding circuit, and an output circuit. The acquisition circuit is configured to acquire data to be decoded; the SCL decoding circuit is configured to perform serial cancellation list SCL decoding on the data; and the SC decoding circuit is configured to perform serial cancellation SC translation on the data. The SC decoding circuit is further configured to obtain a decoding result of the SC decoding; and when determining that the decoding result of the SC decoding is correct, the SCL decoding circuit is further configured to stop the SCL decoding; And an output circuit, configured to output a decoding result of the SC decoding.

In a third aspect, a decoder is provided, comprising a processor, a transceiver and a memory for supporting the decoder to perform a corresponding function in the above decoding method. The memory stores instructions for performing specific signal transceiving under the driving of a processor for invoking the instruction to implement the decoding method of the polarization code in the first aspect and various implementations thereof.

A fourth aspect provides a decoder, including a processing module, a storage module, and a transceiver module, for supporting the decoder to perform the functions in the foregoing first aspect or any possible implementation manner of the first aspect, the function may be The hardware implementation may also be implemented by hardware, and the hardware or software includes one or more modules corresponding to the above functions.

In a fifth aspect, a readable medium is provided for storing instructions comprising instructions for performing the decoding method of the first aspect or any of the possible implementations of the first aspect.

DRAWINGS

1 is a schematic diagram of an SC decoding path.

2 is a schematic diagram of an SCL decoding path.

FIG. 3 is a schematic flow chart of a typical SCL decoding processing manner.

4 is a schematic diagram of a communication system of a decoding method and a decoder applicable to the polarization code of the present application.

FIG. 5 is a schematic flowchart of a method for decoding a polarization code according to an embodiment of the present invention.

FIG. 6 is a schematic flow chart of a method for decoding a polarization code according to another embodiment of the present invention.

Figure 7 is a schematic block diagram of a decoder in accordance with one embodiment of the present invention.

Figure 8 is a schematic block diagram of a decoder in accordance with another embodiment of the present invention.

Figure 9 is a schematic block diagram of a decoder in accordance with another embodiment of the present invention.

Detailed ways

The technical solutions in the present application will be described below with reference to the accompanying drawings.

The terms "component," "module," "system," and the like, as used in this specification, are used to mean a computer-related entity, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and a computing device can be a component. One or more components can reside within a process and/or execution thread, and the components can be located on one computer and/or distributed between two or more computers. Moreover, these components can execute from various computer readable media having various data structures stored thereon. A component may, for example, be based on signals having one or more data packets (eg, data from two components interacting with another component between the local system, the distributed system, and/or the network, such as the Internet interacting with other systems) Communicate through local and/or remote processes.

It should be understood that the technical solutions of the present application can be applied to various communication systems, such as: long term evolution (LTE) system, LTE/LTE-A frequency division duplex (FDD) system, LTE/LTE. -A time division duplex (TDD) system, universal mobile telecommunication system (UMTS), worldwide interoperability for microwave access (WiMAX) communication system, public land mobile network (public) Land mobile network, PLMN) system, device to device (D2D) network system or machine to machine (M2M) network system, wireless fidelity (Wi-Fi) system, wireless local area network ( Wireless local area networks (WLAN) and future 5G communication systems.

It should also be understood that, in the embodiment of the present invention, the terminal device may also be referred to as a user equipment (UE), a mobile station (MS), a mobile terminal, etc., and the terminal device may be connected by using a wireless device. A radio access network (RAN) communicates with one or more core network devices, for example, the terminal device may include various handheld devices with wireless communication capabilities, in-vehicle devices, wearable devices, computing devices, or connected to a wireless modem. Other processing equipment. It may also include a subscriber unit, a cellular phone, a smart phone, a wireless data card, a personal digital assistant (PDA) computer, a tablet computer, a wireless modem, and a handheld device. ), laptop computer, machine type communication (MTC) terminal, station (STA) in wireless local area networks (WLAN). It can be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a wireless local loop (WLL) station, and a next-generation communication system, for example, a terminal device in a 5G network or a future evolution. A terminal device or the like in a public land mobile network (PLMN) network. The embodiments of the present invention are not limited herein.

It should also be understood that the base station may also be referred to as a network side device or an access network device, and the network side device may be a device for communicating with the terminal device, and the network device may be an evolved base station (evolutional Node B, eNB) in the LTE system. Or eNodeB), gNB or access point in NR, base transceiver station, transceiver node, etc., or in-vehicle device, wearable device, network device in future 5G network or network side device in future evolved PLMN system. For example, the network side device may be an access point (AP) in the WLAN, or may be a global system for mobile communication (GSM) or code dvision multiple access (CDMA). Base Transceiver Station (BTS) in CDMA. It may also be an evolved NodeB (eNB or eNodeB) in an LTE system. Alternatively, the network device may also be a Node B of a 3rd Generation (3G) system. In addition, the network device may also be a relay station or an access point, or an in-vehicle device, a wearable device, and a future 5G network. a network device in the network or a network device in a future evolved PLMN network. The embodiments of the present invention are not limited herein. For convenience of description, in all embodiments of the present invention, the above devices for providing wireless communication functions to the MS are collectively referred to as network devices.

Polar code is a high-performance channel coding scheme proposed in recent years. It has the characteristics of high performance, low complexity and flexible rate matching. It has become the coding method of control information in 5G systems. In the actual engineering, the decoding method of the Polar code is SCL decoding and SC decoding. A Polar code having a code length of N may correspond to a binary decoding code tree composed of N layer edges. SC coding can be described as a decoding path search process on the code tree.

1 is a schematic diagram of an SC decoding path. As can be seen from FIG. 1, SC decoding starts from the root node of the code tree and gradually expands on the decoding code tree, and each layer selects a relative probability from two candidate paths. The one with a large value, that is, the search width is 1. And the path expansion of the next layer is performed on the basis of the selected decoding path. An example of an SC decoding path with a simple code length N=4 is shown in FIG. 1, and a solid black line in FIG. 1 indicates a selected SC decoding path. A decoding result is finally obtained through the decoding path, and the decoding result is verified to determine whether the decoding result is correct.

It can be seen from the above SC decoding process that no matter which layer of the code tree is in the SC decoding process, only one of the two candidate decoding paths is selected, and finally a bit estimation sequence, that is, a decoding result is obtained. Therefore, the SC decoding calculation has lower complexity and a smaller decoding delay. Since only one of the two candidate decoding paths is selected at a time, the reliability of the decoding result is not high, and the decoding result is not necessarily accurate. Therefore, the performance of SC decoding is low.

2 is a schematic diagram of an SCL decoding path. As an improvement to SC coding, SCL decoding allows multiple candidate decoding paths to be reserved. As can be seen from FIG. 2, the SCL decoding starts from the root node of the code tree and is gradually expanded on the code tree. Each layer selects L strips from 2L candidate decoding paths, that is, the search width is L. And the path expansion of the next layer is performed on the basis of the selected L decoding paths. A schematic diagram of a simple SCL decoding process with a code length N = 4 and a search width of 4 is shown in FIG. The four black solid lines in Figure 2 indicate the selected four SCL decoding paths. At the end of decoding, one path with the largest reliability metric is selected from the four SCL decoding paths, and the corresponding bit estimation sequence is the decoding result.

FIG. 3 is a schematic flow chart of a typical SCL decoding processing manner, and FIG. 3 shows the whole process of processing a hard bit. All hard bit processing starts from the first stage to the last stage. End the loop process until all hard bit processing is complete. The stage is equivalent to the layer of the decoding code tree in FIG. 1 or FIG. 2. In the typical SCL decoding process, L (ie, the search width is L) decoding path | (path) exists, and each piece is calculated. The maximum log likelihood ratio (LLR) of the decoding path is obtained as a branch metric and a path metric for each decoding path, wherein the branch metric is used to calculate the cumulative metric. By comparing the path metrics of each of the candidate 2L decoding paths, selecting L decoding paths from the alternative 2L decoding paths, iterating to the next hard bit (hard value) In the calculation, when all the hard bits are all calculated, the decoding result of the most accurate decoding path is selected by the hard bit stream check routing of the L decoding paths, as the final Output the result.

The flow of a typical SCL decoding processing method mainly includes the following steps:

1. Calculate the stage number m required for the current decoding of hard bits, m is a positive integer greater than 1, and select the LLR and the metric cumulative value of each stage cache of stage(1) to stage(m).

2. Each decoding path is synchronized from stage(1) to stage(m) to obtain LLR by stage.

3. Calculate the branch metric (BM) value and the path metric (PM) value of each decoding path, and have 2L alternative decoding path metric values, representing 2L alternative decoding paths. .

4. Selecting L decoding paths from 2L candidate decoding paths to obtain L decoding values of the currently decoded hard bits.

5. Determine whether the current hard bits (hard values) that need to be decoded are all translated.

6. If not all are translated, calculate the metric cumulative value (psum) of stage(1)~stage(m) and continue processing the next hard bit.

7. If all processing is performed, the optimal decoding result is obtained according to the result of the code stream verification routing.

As can be seen from the above, the basic features of SCL decoding are as follows:

1. The path formed from the root node of the code tree to any node in the decoding process corresponds to a path metric.

2. Starting from the root node, the information bit (bit) is extended to the path.

3. When each layer is extended to the next layer, each layer selects L strips with larger path metric values in the current layer.

4. During the decoding process until the last layer is extended. If it is a cyclic redundancy check (CRC) to assist decoding, the path with the smallest absolute value of the metric in the path through the cyclic redundancy check is selected as the decoding result.

It can be known from the above SCL decoding process that in the SCL decoding process, regardless of which layer of the code tree, L candidate decoding paths are selected from 2L candidate paths, and finally L bit estimation sequences are obtained, and L candidates are obtained. The decoding path reliability metric is calculated to obtain the final decoding result. Therefore, the complexity of SCL decoding calculation is higher, and the decoding delay is larger. Since L strips are selected from 2L candidate paths each time, the reliability of the decoding result is high, and the accuracy of the decoding result is good. Therefore, the performance of SCL is higher.

Based on the problem that the SCL decoding delay is large but the decoding precision is high, and the performance of the SC decoding is low but the delay is small, the present application provides a method for decoding a polarization code, so that the polarization code is decoded. The decoding delay is reduced while maintaining good decoding performance. Considering the accuracy of the decoding result, the delay in the decoding process is considered, and the effect of reducing the decoding delay and ensuring the accuracy of the decoding result is achieved.

4 is a schematic diagram of a communication system of a decoding method and a decoder applicable to the polarization code of the present application. As shown in FIG. 4, the communication system 100 includes a network device 102 that can include multiple antennas, such as

antennas

104, 106, 108, 110, 112, and 114. Additionally, network device 102 may additionally include a transmitter chain and a receiver chain, as will be understood by those of ordinary skill in the art, which may include multiple components related to signal transmission and reception (eg, processor, modulator, multiplexer) , encoder, demultiplexer or antenna, etc.).

Network device 102 can communicate with a plurality of terminal devices, such as terminal device 116 and terminal device 122. However, it will be appreciated that network device 102 can communicate with any number of terminal devices similar to

terminal device

116 or 122.

Terminal devices

116 and 122 can be, for example, cellular telephones, smart phones, portable computers, handheld communication devices, handheld computing devices, satellite radios, global positioning systems, PDAs, and/or any other for communicating over wireless communication system 100. Suitable for equipment.

As shown in FIG. 4, terminal device 116 is in communication with

antennas

112 and 114, wherein

antennas

112 and 114 transmit information to terminal device 116 over forward link 118 and receive information from terminal device 116 over reverse link 120. In addition, terminal device 122 is in communication with antennas 104 and 106, wherein antennas 104 and 106 transmit information to terminal device 122 over forward link 124 and receive information from terminal device 122 over reverse link 126.

For example, in an FDD system, for example, the forward link 118 can utilize a different frequency band than that used by the reverse link 120, and the forward link 124 can utilize a different frequency band than that used by the reverse link 126.

As another example, in a TDD system and a full duplex system, the forward link 118 and the reverse link 120 can use a common frequency band, and the forward link 124 and the reverse link 126 can use a common frequency band.

Each antenna (or set of antennas consisting of multiple antennas) and/or regions designed for communication is referred to as a sector of network device 102. For example, the antenna group can be designed to communicate with terminal devices in sectors of the network device 102 coverage area. In the process in which network device 102 communicates with

terminal devices

116 and 122 via

forward links

118 and 124, respectively, the transmit antenna of network device 102 may utilize beamforming to improve the signal to noise ratio of

forward links

118 and 124. In addition, when the network device 102 uses beamforming to transmit signals to the randomly dispersed

terminal devices

116 and 122 in the relevant coverage area, the network device 102 uses a single antenna to transmit signals to all of its terminal devices. Mobile devices are subject to less interference.

At a given time, network device 102, terminal device 116, or terminal device 122 may be a wireless communication transmitting device and/or a wireless communication receiving device. When transmitting data, the wireless communication transmitting device can encode the data for transmission. In particular, the wireless communication transmitting device may acquire (eg, generate, receive from other communication devices, or store in memory, etc.) a certain number of data bits to be transmitted over the channel to the wireless communication receiving device. Such data bits may be included in a transport block (or multiple transport blocks) of data that may be segmented to produce multiple code blocks.

In addition, the communication system 100 can be a PLMN network or a D2D network or an M2M network or other network. FIG. 4 is only a simplified schematic diagram of an example, and the network may also include other network devices, which are not drawn in FIG. 4 .

The method for decoding a polarization code provided by the present application is described in detail below with reference to FIG. 5. FIG. 5 is a schematic flowchart of a method for decoding a polarization code 200 according to an embodiment of the present invention. The method 200 can be applied to FIG. The embodiment of the present invention is not limited thereto.

As shown in FIG. 5, the decoding method 200 includes:

S210. Acquire data to be decoded.

S220, respectively, performing serial cancellation list SCL decoding and serial cancellation SC decoding on the data.

S230, obtaining a decoding result of the SC decoding.

S240. If it is determined that the decoding result of the SC decoding is correct, the SCL decoding is stopped.

S250. Output a decoding result of the SC decoding.

Specifically, in the present application, when decoding the data to be decoded, the data to be decoded is first acquired, and then the data to be decoded is respectively subjected to serial offset list SCL decoding and serial offset SC translation. The code, that is, the data to be decoded is decoded in parallel by using two decoding methods. Due to the low complexity of the SC decoding process, there is only one candidate decoding path in the decoding process, which is relatively short in time. Therefore, the decoding result of the SC decoding (SC decoding result) is first obtained. When the SC decoding result is obtained, the SCL decoding of the data is in progress, that is, the SCL decoding has not ended yet, and the SCL decoding result has not been obtained yet. Since the accuracy of the SC decoding is low, the SC decoding result is not necessarily accurate, and it is necessary to determine whether to stop the SCL decoding of the data according to the SC decoding result. That is, in the case that it is determined that the decoding result of the SC decoding is correct, the SCL decoding of the data is stopped, and the decoding result of the SC decoding is output, that is, the decoding result of the SC decoding is used as the final decoding. result.

The method for decoding a polarization code provided by the present application performs serial cancellation list SCL decoding and serial cancellation SC decoding in parallel by data to be decoded. Since the SC decoding delay is small, the decoding accuracy is low and the bit error rate is high. The delay of SCL decoding is larger, but the decoding accuracy is higher and the bit error rate is lower. Therefore, the data to be decoded is subjected to SC decoding and SCL decoding, respectively, and the SC decoding result is obtained first. When it is determined that the decoding result of the SC decoding is correct, the SCL decoding of the data is stopped, and The decoding result of the SC decoding is used as the final decoding result. The polar code decoding reduces the decoding delay and improves the decoding efficiency under the premise of ensuring accurate decoding performance.

Optionally, in an embodiment, if it is determined that the decoding result of the SC decoding is incorrect, the method 200 further includes:

S260, the SCL decoding is continued.

S270, outputting the decoding result of the SCL decoding.

Specifically, since the smaller decoding delay SC, SC thus obtained first decoding result, the decoding result is assumed SC obtained at time T _1, at this time, the decoded data SCL ongoing process, i.e., SCL translation The code has not finished yet, and the SCL decoding result has not been obtained yet. Therefore, in the case that it is determined that the decoding result of the SC decoding is incorrect, it is necessary to continue SCL decoding the data, and it is assumed that the SCL decoding result of the data is obtained at time T ₂ , wherein the T ₂ time is later than T _{At 1} o'clock, the decoding result of the SCL decoding is output, that is, the SCL decoding result is output as the final decoding result of the data.

Optionally, as an embodiment, the data start serial cancellation list SCL decoding and serial cancellation SC decoding respectively are performed, including:

The serial offset list SCL decoding and the serial cancellation SC decoding are performed in parallel on the data.

Specifically, in an embodiment of the present invention, SCL decoding and SC decoding may be performed on the data in parallel, that is, the time for performing SCL decoding and SC decoding on the data at least partially overlaps. Since the time taken for SC decoding is short, when the time for performing SCL decoding and SC decoding on the data at least partially overlaps, the length of time for obtaining the decoding result can be further shortened as a whole. Optionally, as an embodiment, SCL decoding and SC decoding may be started on the data at the same time, so that the decoding delay may be further reduced. For example, assume that the data starts decoding and SCL SC decoded time T _1, T ₃ time decoding result obtained SC, SC assumption is correct decoding result, the decoding of this long used as T ₃ -T ₁ . Suppose this data starts at time T ₁ SCL decoded, T ₂ SC decoding start time, T ₄ SC decoding result is obtained in time, wherein, at time T _1, T ₂ time, T ₃ and T ₄ time time time The sequence is sequentially postponed, and if the SC decoding result is correct, the duration used for this decoding is T ₄ -T ₁ . Compared to starting SCL decoding and SC decoding at the same time, the decoding duration used is increased, that is, the decoding delay is large.

It should be understood that, in the embodiment of the present invention, when performing SCL decoding and SC decoding on the data in parallel, the SC decoding result may be obtained earlier than the SCL decoding result. The embodiments of the present invention are not limited herein.

The method for decoding a polarization code provided by the present application performs SCL decoding and SC decoding in parallel on the data to be decoded, and performs verification on the decoding result of the SC decoding first, and determines that the SC decoding result is correct. At the time, the SC decoding result is output as the final result of the decoding. The decoding delay can be further reduced to improve the decoding efficiency.

Optionally, as an embodiment, the decoding method 200 further includes:

S231. Perform a cyclic redundancy CRC check on the decoding result of the SC decoding.

S232, if the CRC check is passed, determining that the decoding result of the SC decoding is correct, or

In the case that the CRC check fails, it is determined that the decoding result of the SC decoding is incorrect.

Specifically, after the decoding result of the SC decoding is obtained, the SC decoding result is subjected to CRC check. That is, the CRC auxiliary code is used as an inner code, and is input into the data information to perform polarization code encoding as a part of the information symbol. At the decoding end, the SC decoding algorithm first generates an alternative decoding codeword, that is, the decoding result of the SC decoding, and then performs CRC decoding on the decoding result of the SC decoding, and decodes the CRC. The result is compared with the actually received CRC auxiliary code. If the two are the same, that is, the CRC check passes, it is determined that the decoding result of the SC decoding is correct. If the two are not the same, that is, the CRC check fails, it is determined that the decoding result of the SC decoding is incorrect.

It should be understood that, in addition to the CRC check to determine whether the decoding result of the SC decoding is correct, the decoding result of the SC decoding may be verified by other methods, for example, by using parity check (parity check, The embodiment of the present invention is not limited herein.

Optionally, as an embodiment, the search width of the SCL decoding is 8 decoding paths.

Specifically, it can be seen from the SCL decoding process shown in FIG. 2 and FIG. 3 that in the SCL decoding process, the larger the search width, the more the SCL decoding path, and the more accurate the probability of decoding results. Large, that is, the higher the accuracy of the decoding result, the lower the bit error rate. However, the larger the search width, the more the decoded path, the larger the calculation amount, and therefore the larger the delay. In the case that the SC decoding result is incorrect, considering the balance between the SCL decoding delay and the decoding accuracy, the search width in the SCL decoding process is 8, that is, there are 8 decoding paths simultaneously. The code delay is low and the decoding accuracy is relatively good.

It should be understood that in the embodiment of the present invention, the value of the search width in the SCL decoding process may be other values, for example, 2, or 4, or 16, or the like. The embodiment of the present invention is not limited herein as long as the positive integer of the value of the decoding width is 2.

A method for decoding a polarization code according to an embodiment of the present invention will be described below with reference to FIG. FIG. 6 is a schematic flow chart of a method for decoding a polarization code according to an embodiment of the present invention. In the upper half of the dotted line frame in FIG. 6, the flow of the typical SCL decoding processing mode is shown, and the lower half of the dotted line frame is the flow of the typical SC decoding processing mode. The essence of SC decoding is SCL decoding of a single decoding path, and the two parts are executed in parallel. Since the number of decoding paths (path) of SC decoding is small, only two-choice path selection is needed, so the calculation is simple. Compared with the SCL decoding processing delay, the SC decoding result will be obtained earlier. When the SC decoding result is correct, the SCL decoding is terminated by the decoding end decision, and the output is the SC decoding result. When the SC decoding result is wrong, the SCL needs to be executed, and finally the result of the SCL decoding is output.

The SCL decoding process is similar to the steps described in FIG. 3, and is not described here for brevity.

The main steps of the SC decoding process are as follows:

3. Calculate the BM and PM of each decoding path, and have 2 candidate PM values, representing 2 alternative decoding paths.

4. Select one decoding path from the two alternative decoding paths to obtain a decoded value of the currently decoded hard bit.

5. Determine whether the current hard bits that need to be decoded are all translated.

7. If all processing is performed, the SC decoding result is obtained, and the SC decoding result is verified.

8. If it is verified that the SC decoding result is incorrect, the SC decoding portion ends, and the SCL decoding continues until the SCL decoding result is generated and output.

9. If it is verified that the SC decoding result is correct, the SCL decoding termination signal is issued, the SCL decoding portion is forcibly terminated, and the SC decoding result is directly output.

The method for decoding a polarization code provided by an embodiment of the present invention utilizes the features of simple SC decoding, small delay, and high accuracy of SCL decoding, and performs SC decoding and SCL decoding in parallel through data to be decoded. In the case where the SC decoding result obtained first is correct, the SC decoding result is taken as the final decoding result. The decoding speed is improved, the decoding delay is reduced, the accuracy of the decoding result is ensured, and the decoding efficiency is improved.

It should also be understood that, in the embodiments of the present invention, the sizes of the above processes and the sequence numbers of the steps do not imply a sequence of execution orders, and the order of execution of each process should be determined by its function and internal logic, and should not be The implementation of the embodiments of the invention imposes any limitations.

The decoding method of the polarization code provided by the embodiment of the present invention is described in detail above with reference to FIG. 1 to FIG. 6. The decoder provided by the embodiment of the present invention will be described in detail below with reference to FIG. 7 to FIG.

FIG. 7 shows a schematic block diagram of a decoder 300 according to an embodiment of the present invention. As shown in FIG. 7, the decoder 300 includes an acquisition circuit 310, an SCL decoding circuit 320, an SC decoding circuit 330, and an output circuit. 340.

The obtaining circuit 310 is configured to acquire data to be decoded.

The SCL decoding circuit 320 is configured to perform serial cancellation list SCL decoding on the data.

The SC decoding circuit 330 is configured to perform serial cancellation SC decoding on the data.

The SC decoding circuit 330 is also used to obtain the SC decoding result.

In the case where it is determined that the decoding result of the SC decoding is correct, the SCL decoding circuit 320 is further configured to stop the SCL decoding.

The output circuit 340 is configured to output the decoded result of the SC decoding.

The decoder provided by the present application performs serial cancellation list SCL decoding and serial cancellation SC decoding in parallel by data to be decoded, respectively. Since the SC decoding delay is small, the decoding accuracy is low and the bit error rate is high. The delay of SCL decoding is larger, but the decoding accuracy is higher and the bit error rate is lower. Therefore, the data to be decoded is subjected to SC decoding and SCL decoding, respectively, and the SC decoding result is obtained first. When it is determined that the decoding result of the SC decoding is correct, the SCL decoding of the data is stopped, and The decoding result of the SC decoding is used as the final decoding result. The polar code decoding reduces the decoding delay and improves the decoding efficiency under the premise of ensuring accurate decoding performance.

Optionally, as an embodiment, in the case that it is determined that the decoding result of the SC decoding is incorrect, the SCL decoding circuit 320 is further configured to continue the SCL decoding. The output circuit 340 is further configured to: output the decoded result of the SCL decoding.

Optionally, as an embodiment, the SCL decoding circuit 320 and the SC decoding circuit 330 decode the data in parallel.

Optionally, as an embodiment, the decoder 300 further includes a check circuit 350, configured to perform a cyclic redundancy CRC check on the decoded result of the SC decoding; In the case of passing, it is determined that the decoding result of the SC decoding is correct, or if the CRC check fails, it is determined that the decoding result of the SC decoding is incorrect.

Optionally, as an embodiment, the SCL decoding circuit 320 has a search width of eight decoding paths.

It should be noted that in the embodiment of the present invention, each circuit included in the decoder 300 may be composed of logic devices for supporting each circuit to perform the above various functions.

It should be understood that the above-mentioned and other operations and/or functions of the respective circuits in the decoder 300 in the embodiment of the present invention implement the respective processes of the respective methods in FIG. 5 and FIG. 6, respectively, and are not described herein again for brevity.

FIG. 8 is a schematic block diagram of a decoder 400 in accordance with an embodiment of the present invention. As shown in FIG. 8, the decoder 400 includes a processor 410, a memory 420, and a transceiver 430. The processor 410, the memory 420, and the transceiver 430 communicate with each other through an internal connection path to transfer control and/or data signals. .

This memory 410 is used to store program code.

The transceiver 430 is configured to perform specific signal transceiving under the driving of the processor 410 to implement the decoding method in the above embodiments.

The processor 420 is configured to invoke the program code to implement the decoding method in the above embodiments of the present invention.

It should be understood that the above-described and other operations and/or functions of the various components in the decoder 400 in accordance with the embodiments of the present invention implement the respective processes of the various methods in FIG. 5 and FIG. 6, respectively, and are not described herein again for brevity.

The various components in decoder 400 communicate with one another via a communication connection, i.e., processor 410, memory 420, and transceiver 430, through internal connection paths, to communicate control and/or data signals. The foregoing method embodiments of the present application may be applied to a processor, or the processor may implement the steps of the foregoing method embodiments. The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the foregoing method embodiments may be completed by an integrated logic circuit of hardware in a processor or an instruction in a form of software. To avoid repetition, it will not be described in detail here. The above processor may be a central processing unit (CPU), a network processor (NP) or a combination of a CPU and an NP, a digital signal processor (DSP), an application specific integrated circuit (application). Specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component. The methods, steps, and logical block diagrams disclosed in this application can be implemented or executed. The general purpose processor may be a microprocessor or the processor or any conventional processor or the like. The steps of the method disclosed in connection with the present application may be directly embodied by the execution of the hardware decoding processor or by a combination of hardware and software modules in the decoding processor. The software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like. The storage medium is located in the memory, and the processor reads the information in the memory and combines the hardware to complete the steps of the above method.

The memory 420 can include read only memory and random access memory and provides instructions and data to the processor 410. A portion of the memory 420 may also include a non-volatile random access memory. For example, the memory 420 can also store information of the device type. A person skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

It is to be understood that the memory in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory may be a read-only memory (ROM), a programmable read only memory (ROMM), an erasable programmable read only memory (erasable PROM, EPROM), or an electrical Erase programmable EPROM (EEPROM) or flash memory. The volatile memory can be a random access memory (RAM) that acts as an external cache. It should be noted that the memories of the systems and methods described herein are intended to comprise, without being limited to, these and any other suitable types of memory.

It should be noted that in the embodiment of the invention, the processor 410 may be implemented by a processing module, the memory 420 may be implemented by a storage module, and the transceiver 430 may be implemented by a transceiver module. As shown in FIG. 9, the decoder 500 may include a processing module 510. The storage module 520 and the transceiver module 530.

The decoder 400 shown in FIG. 8 or the decoder 500 shown in FIG. 9 can implement the steps shown in FIG. 5 and FIG. 6 described above. To avoid repetition, details are not described herein again.

The embodiment of the present invention further provides a readable medium for storing program code, the program code comprising instructions for executing the decoding method of the polarization code of the embodiment of the present invention in FIG. 5 and FIG. The readable medium may be a ROM or a RAM, which is not limited in the embodiment of the present invention.

It should be understood that the terms "and/or" and "at least one of A or B" herein are merely an association describing the associated object, indicating that there may be three relationships, for example, A and/or B, Representation: There are three cases where A exists separately, A and B exist at the same time, and B exists separately. In addition, the character "/" in this article generally indicates that the contextual object is an "or" relationship.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods for implementing the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present invention.

A person skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

The functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product. Based on such understanding, the technical solution of the present invention, which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including The instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

The above is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It should be covered by the scope of the present invention. Therefore, the scope of the invention should be determined by the scope of the claims.

Claims

A method for decoding a polarization code, comprising:

Obtaining data to be decoded;

Performing serial cancellation list SCL decoding and serial cancellation SC decoding on the data, respectively;

Obtaining a decoding result of the SC decoding;

Stopping the SCL decoding if it is determined that the decoding result of the SC decoding is correct;

The decoded result of the SC decoding is output.
The decoding method according to claim 1, wherein in the case that it is determined that the decoding result of the SC decoding is incorrect, the method further includes:

Continue to perform the SCL decoding;

The decoding result of the SCL decoding is output.
The decoding method according to claim 1 or 2, wherein said separately performing serial cancellation list SCL decoding and serial cancellation SC decoding on said data comprises:

The SCL decoding and the SC decoding are performed in parallel on the data.
The decoding method according to any one of claims 1 to 3, wherein the decoding method further comprises:

Performing a cyclic redundancy CRC check on the decoding result of the SC decoding;

In case the CRC check passes, it is determined that the decoding result of the SC decoding is correct, or

In case the CRC check fails, it is determined that the decoding result of the SC decoding is incorrect.
The decoding method according to any one of claims 1 to 4, characterized in that the search width of the SCL decoding is eight decoding paths.
A decoder, comprising:

Acquiring a circuit for acquiring data to be decoded;

An SCL decoding circuit, configured to perform serial cancellation list SCL decoding on the data;

An SC decoding circuit, configured to perform serial cancellation SC decoding on the data;

The SC decoding circuit is further configured to obtain a decoding result of the SC decoding;

In the case that it is determined that the decoding result of the SC decoding is correct, the SCL decoding circuit is further configured to stop the SCL decoding;

And an output circuit, configured to output a decoding result of the SC decoding.
The decoder according to claim 6, wherein in the case of determining that the decoding result of the SC decoding is incorrect, the SCL decoding circuit is further configured to continue the SCL decoding;

The output circuit is further configured to output a decoding result of the SCL decoding.
The decoder according to claim 6 or 7, wherein said SCL decoding circuit and said SC decoding circuit decode said data in parallel.
A decoder according to any one of claims 6 to 8, wherein said decoder further comprises a check circuit for: decoding result of said SC decoding Performing a cyclic redundancy CRC check;

In case the CRC check passes, it is determined that the decoding result of the SC decoding is correct, or

In case the CRC check fails, it is determined that the decoding result of the SC decoding is incorrect.
The decoder according to any one of claims 6 to 9, wherein the search width of the SCL decoding circuit is eight decoding paths.
A readable storage medium, comprising instructions that, when executed on a processor, cause the processor to perform the decoding method of any one of claims 1 to 5.