WO2019005081A1 - Group iii-nitride transistor structure with embedded diode - Google Patents

Group iii-nitride transistor structure with embedded diode Download PDF

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Publication number
WO2019005081A1
WO2019005081A1 PCT/US2017/040135 US2017040135W WO2019005081A1 WO 2019005081 A1 WO2019005081 A1 WO 2019005081A1 US 2017040135 W US2017040135 W US 2017040135W WO 2019005081 A1 WO2019005081 A1 WO 2019005081A1
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layer
iii
layers
heterostructure
device structure
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PCT/US2017/040135
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French (fr)
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Han Wui Then
Sansaptak DASGUPTA
Marko Radosavljevic
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Intel Corporation
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Priority to PCT/US2017/040135 priority Critical patent/WO2019005081A1/en
Publication of WO2019005081A1 publication Critical patent/WO2019005081A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
    • H01L29/66219—Diodes with a heterojunction, e.g. resonant tunneling diodes [RTD]
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Definitions

  • Diodes are a common circuit element used in integrated circuits (ICs). Diodes are useful for protecting circuitry from over-voltages, such as those associated with electrostatic discharge (ESD) events. Absent a protection circuit, discharge through a device such as a transistor, can cause catastrophic damage to an IC. Diodic protection circuits may therefore be configured as part of a functional IC to shunt surges in potential away from circuitry that could otherwise be damaged.
  • Group Ill-Nitride (IUPAC 13-N) semiconductor materials offer the benefit of a relatively wide bandgap ( ⁇ 3.4eV), enabling higher breakdown voltages than Si-based devices.
  • Group Ill-Nitride (III-N) semiconductor materials also offer high carrier mobility. However, III-N diodes with sufficiently low on-resistance tend to be an area-intensive circuit element even when monolithically integrated with transistors of an IC.
  • III-N diode structures enabling a smaller area are therefore advantageous at least for enabling dimensional scaling of the device platforms that employ them.
  • FIG. 1A is a plan view of a III-N transistor and diode arranged onto an IC, in accordance with some embodiments;
  • FIG. IB and 1C are cross-sectional views of the III-N transistor and diode shown in FIG. 1A;
  • FIG. 2 is a schematic of a diode protection circuit, in accordance with some embodiments
  • FIG. 3 is a cross-sectional view an exemplary III-N heteroj unction transistor including an embedded diode, in accordance with some embodiments;
  • FIG. 4 is a cross-sectional view an exemplary III-N heteroj unction transistor structure including an embedded diode, in accordance with some embodiments;
  • FIG. 5 is a flow diagram illustrating methods of forming III-N heteroj unction transistor structure including an embedded diode, in accordance with some embodiments
  • FIG. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, and 61 are cross-sectional views of a III-N heteroj unction transistor structure including an embedded diode evolving as selected operations in the method of FIG. 5 are performed, in accordance with some embodiments;
  • FIG. 7 illustrates a mobile computing platform and a data server machine employing an IC having a III-N heterostructure diode, in accordance with embodiments.
  • FIG. 8 is a functional block diagram of an electronic computing device, in accordance with some embodiments.
  • a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.
  • the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.
  • the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
  • the terms “coupled” and “connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other.
  • connection may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other.
  • Coupled may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).
  • over refers to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy.
  • one material or material disposed over or under another may be directly in contact or may have one or more intervening materials.
  • one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers.
  • a first material "on” a second material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies.
  • a diode and transistor employing an integrated Group Ill-Nitride heterostructure are described herein. Devices in accordance with one or more of the embodiments described herein reduce the area of an IC needed to support diode structures relative to separate diode and transistor architectures.
  • a III-N heterostructure that includes a heteroj unction between a first III-N material layer or lamella over a second III-N material layer is employed within a diode.
  • This diode material stack is formed over a Ga-face of third and fourth III-N material layers employed within a transistor.
  • complementary two-dimensional charge carrier sheets e.g., one 2D hole gas and one 2D electron gas
  • the transistor may employ one of the 2D charge sheets while the other of the 2D charge sheets may be employed within the diode.
  • the diode With material layers of the III-N heterostructure grown in a stack, the diode may be vertically integrated or "embedded" within the footprint of the transistor.
  • a gate of the transistor may modulate one of the 2D charge carrier sheets (e.g., 2D electron gas) controlling the electrical coupling between a source and drain of the transistor.
  • the gate of the transistor is also electrically coupled to at least one of the transistor source and drain through a rectifying junction between the first III- N material layer that has a first conductivity type (e.g., the same conductivity type as the source and drain) and the second III-N material layer in which the second 2D charge carrier sheet (e.g., 2D hole gas) resides.
  • first conductivity type e.g., the same conductivity type as the source and drain
  • the second 2D charge carrier sheet e.g., 2D hole gas
  • both a gate-source diode and gate-drain diode may be embedded within the footprint of the transistor.
  • FIG. 1A is plan view of an integrated circuit structure 100 including a pair of Group
  • Diodes 105 are configured with one terminal in common (e.g., anode) and require approximately the same xy area (e.g., footprint) as transistor 110. Between diodes 105 and transistor 110 is a region of isolation dielectric 180, further increasing the footprint of IC structure 100.
  • a stripe of a first contact metal 120 and stripes of a second contact metal 140 are spaced apart on either side at some predetermined design rule pitch.
  • stripes of source/drain contact metal 145 on either side of gate electrode 125 are spaced apart at the design rule pitch.
  • Interconnect metallization 150, 151, and 152 pass over the lower level conductors with conductive vias 135 linking various terminals of the diodes 105 to various terminals of transistor 110.
  • interconnect metallization 150 conveys a voltage Vin in a terminal of diodes 105 and to the gate electrode of transistor 110.
  • Interconnect metallization 151 conveys a voltage Vcc to a terminal of diodes 150 and to the source of transistor 110.
  • Interconnect metallization 152 conveys a voltage Vss to a terminal of diodes 150 and to the drain of transistor 110.
  • FIG. IB and 1C are cross-sectional views of IC structure 100.
  • FIG IB is a sectional view along the A- A' line illustrated in FIG. 1 A.
  • a two-dimensional (2D) charge carrier sheet 166 is formed between a first III-N material layer 160 and a second III-N material layer 165.
  • charge carrier sheet 166 is coupled to a first terminal through a Schottky (rectifying) metal semiconductor junction between III-N material layer 160 and first terminal contact metal 120.
  • 2D charge carrier sheet 166 is further coupled to impurity-doped semiconductor 130, which further interfaces contact metal 140.
  • 2D charge carrier sheet 166 is coupled to a first terminal through a Schottky (rectifying) 2D charge carrier sheet 166 is coupled to impurity-doped
  • FIG. 2 is schematic of an electrical circuit 200 including at least one III-N heteroj unction diode vertically integrated or embedded within the heterostructure of a III-N transistor.
  • circuit 200 may be implemented within a smaller area than if implemented with the architecture shown in FIG. 1A-1C.
  • Circuit 200 can be implemented as a single IC chip and may be implemented in any electronic device, such as, but not limited to, smartphones, ultrabook computers, embedded devices (e.g., intemet of things, automotive applications, etc.), or wearables.
  • a III-N transistor 205 is to be protected from electrical surges by diodes 211, 212, and 213.
  • Transistor 205 includes a first terminal (e.g., source) coupled to a first supply rail 206 maintained at a nominal supply voltage (e.g., Vcc), and a second terminal (e.g., drain) coupled to second supply rail 207 maintained at a nominal reference voltage (e.g., Vss).
  • a third terminal (e.g., gate) of transistor 205 is coupled to a signal input 208, which conveys an input voltage Vin.
  • transistor 205 is protected by diodes 21 1 and 212 connecting signal input 208 to the supply rails 206, 207 (e.g., Vcc and Vss, respectively), and by diode 213 connecting supply rail 206 to supply rail 207.
  • diodes 21 1, 212 and 213 are maintained in the off-state (e.g., reverse biased) such that signal input 208 is effectively disconnected from supply rails 206, 207 while transistor 205 is driven by the supply voltage across rails 206, 207.
  • the transient upon experiencing a potential surge between signal input 208 and supply rails 206 and 207, the transient will forward bias one or more of diodes 21 1, 212 and 213, turning them on.
  • Which of diodes 21 1 , 212 and 213 become forward biased is dependent on the charge polarity of the surge relative to the supply rail potentials. Charge accumulated at voltage input 208 is thereby dissipated or shunted through the diode path around transistor 205.
  • one or more diodes of a protection circuit employ a III-N heterostructure further employed by transistor 205.
  • One or more of diodes 21 1 , 212, 213 may be thereby vertically integrated monolithically with transistor 205, reducing the IC footprint of the integrated device.
  • Such transistor-diode integrated device structures may have one or more of the features described further below.
  • Any of the III-N heterostructure integrated devices described further herein may also be employed in any other suitable protection circuit designs.
  • Any of the III-N heterostructure integrated devices described further herein may also be employed in circuits having functions other than ESD protection, such as, but not limited to, high voltage power management circuitry.
  • FIG. 3 is a cross-sectional view of an exemplary Group III-N device 301 including a heteroj unction field effect transistor (HFET) vertically integrated with heteroj unction diodes, in accordance with some embodiments.
  • the HFET of device 301 may be transistor 205 (FIG. 2) that is protected by the embedded diodes configured according to one or more of the diodes in protection circuit 200, for example.
  • the HFET is a high electron mobility transistor (HEMT), and more specifically, is a metal oxide semiconductor (MOS) HEMT with a recessed gate electrode 325 and a gate dielectric 124.
  • HEMT high electron mobility transistor
  • MOS metal oxide semiconductor
  • III-N material layers 360, 365, 370 and 378 form a III-N
  • III-N polarization layer 365 is positioned over a III-N channel layer 360.
  • III-N material layers 370 and 378, which form a rectifying (diodic) semiconductor junction, are separated from III-N channel layer 360 by III-N polarization layer 365.
  • Polarization layer 365 comprises an alloy distinct from the alloy of channel layer 360, thereby inducing a variation in the polarization field strength (e.g., spontaneous and/or piezoelectric) between these two III-N layers.
  • a two-dimensional charge carrier sheet 341 e.g., 2D electron gas or "2DEG" is formed within channel layer 360 in the absence of any externally applied field.
  • Polarization layer 365 also comprises an alloy distinct from the alloy employed in III-N material layer 370, thereby also inducing a variation in the polarization field strength (e.g., spontaneous and/or piezoelectric) between these two III-N layers.
  • a second two-dimensional charge sheet 342 of a conductivity type complementary to 2D charge carrier sheet 341 e.g., 2D hole gas or "2DHG" is formed within III-N material layer 370 in the absence of any externally applied field.
  • 2D charge sheet 342 may functionally be considered a terminal (e.g., anode) of the integrated diode.
  • III-N material layer 378 is impurity doped to have a conductivity type complementary to that of 2D charge sheet 342. III-N material layer 378 may thereby function as the complementary terminal (e.g., cathode) of the integrated diode. Hence, where 2D charge sheet 342 is a 2DHG, III-N material layer 378 has donor dopants or impurities to have n-type conductivity.
  • the semiconductor junction of III-N material layer 370 and III-N material layer 378 is an P-type/N-type junction suitable for diodic (rectifying) current conduction.
  • the doping level of III-N material layer 378 may be predetermined to establish a P-N junction of suitable depletion width, forward voltage, and electrical breakdown characteristics.
  • III-N material layer 378 is doped with donor impurities to between l ei 8 atoms/cm 3 and l el 9 atoms/cm 3 .
  • One exemplary N-type donor dopant atom suitable for such dopant levels in III-N materials is Si.
  • An alternative donor dopant atom is Ge.
  • gate electrode 325 is located within a recess in the III-N heterostructure that extends a depth (e.g., z-dimension) through III-N material layers 378 and 370, and into polarization layer 365.
  • the recess depth into polarization layer 365 may be predetermined to tune threshold voltage (Vt) of the transistor.
  • Vt threshold voltage
  • recessed gate electrode 325 may be at a depth relative to III-N channel layer 360 to ensure a positive Vt for an enhancement mode n-type transistor.
  • Gate electrode 325 is also electrically coupled to III-N material layer 378.
  • Gate electrode 325 is capacitively coupled through gate dielectric 124 to one or more layers of the III-N heterostructure (e.g., III-N channel layer 360).
  • Gate electrode 325 also forms a metal-semiconductor junction with III-N material layer 378.
  • this metal-semiconductor junction is non-rectifying, and advantageously an ohmic junction, enabling gate electrode 325 to be directly coupled to a first terminal 351 (e.g., cathode) of the integrated III-N diode.
  • source and drain semiconductor 330 is within recesses in the III- N heterostructure that are located on opposite sides of gate electrode 325.
  • the source and drain recesses also extend through III-N material layer 370, and polarization layer 365, landing on III-N channel layer 360.
  • Source and drain semiconductor 330 are in physical contact with a oplane (e.g., Ga-face) of III-N channel layer 360.
  • Source and drain semiconductor 330 have access an edge thickness of 2D charge carrier sheet 341 buried below the heteroj unction between polarization layer 365 and III-N channel layer 360. Modulation of 2D charge carrier sheet 341 by the field effect of gate electrode 325 may thereby control electrical coupling between source and drain
  • III-N channel layer 360 and source and drain semiconductor 330 may be a heteroj unction with the composition of source and drain semiconductor 330 being distinct from that of at least III-N channel layer 360.
  • source and drain semiconductor 330 is also a III-N material.
  • source and drain semiconductor 330 may be InGaN.
  • source and drain semiconductor 330 include 5-20% In (In x Gai- x N with 5% ⁇ x ⁇ 20%).
  • the alloy composition of source and drain semiconductor 330 may be constant or graded between III-N channel layer 360 and contact metal 140.
  • source and drain semiconductor 330 is epitaxial, having the same crystallinity and orientation as III-N channel layer 360.
  • Source and drain semiconductor 330 is advantageously include impurity dopants to have a first conductivity type (e.g., Si donor impurities for n-type conductivity).
  • the doping level of source and drain semiconductor 330 is advantageously as high as practical for lowest transistor terminal resistance.
  • the doping level of source and drain semiconductor 330 may be at least an order of magnitude higher than that of III-N material layer 378, for example.
  • the impurity dopant level is over l ei 9 atoms/cm 3 , and more advantageously over le20 atoms/cm 3 .
  • Si is one exemplary dopant atom for which such high (N+) doping levels may be achieved in III-N alloys.
  • An alternative N-type dopant is Ge.
  • source and drain semiconductor 330 are each electrically coupled to III-N material layer 370, with the gate recess separating bifurcating the III-N material layer 370 that is in contact with source semiconductor from the III-N material layer 370 that is contact with the drain semiconductor.
  • the III-N heterostructure is stripe having a width in the y-dimension (out of the plane of FIG. 3) that is no more than that of the gate electrode so that the diodic III-N material layers 378 and 370 are physically separated from each other by intervening gate electrode 325.
  • Source semiconductor 330 has a first conductivity type with a high concentration of dopant impurities (e.g., N+), forming an abrupt semiconductor-semiconductor junction with III-N material layer 370.
  • dopant impurities e.g., N+
  • a tunnel junction 352 is formed between III-N material layer 370 and source/drain semiconductor 370, enabling contact metal 140 to be directly coupled to a second terminal (e.g., anode) of the integrated III-N diode.
  • device 301 integrates two back-to-back III-N heteroj unction diodes sharing in common a first terminal (e.g., cathode) electrically tied to gate electrode 325, and having separate second terminals (e.g., anodes) electrically tied to one of source and drain semiconductor 330.
  • first terminal e.g., cathode
  • second terminals e.g., anodes
  • three diode terminals are illustrated in FIG. 3, various features described in the context of FIG. 3 are also applicable to a single III-N heteroj unction diode having two terminals (cathode and anode) between only a gate electrode and source semiconductor, or between only a gate electrode and drain
  • 2D charge sheets 341 and 342 originate from different polarization field strengths associated with the different compositions of layers within the III-N heterostructure.
  • the location of 2D charge sheets 341 , 342 is also a function of the III-N crystal polarity, with the locations illustrated in FIG. 3 being indicative of a Ga-polar III-N crystal.
  • the III-N heterostructures employed in device 301 has monocrystalline
  • microstructure e.g., Wurtzite
  • crystal quality of the III-N crystal may vary dramatically, for example as a function of the techniques employed to form the crystal.
  • dislocation density with layers of the III-N heterostructure may range between 10 8 -10 n /cm 2 .
  • the Wurtzite crystalline III-N heterostructure lacks inversion symmetry, and more particularly the ⁇ 0001 ⁇ or "c" planes are not equivalent.
  • One of the ⁇ 0001 ⁇ planes is typically referred to as the Ga-face (+c polarity) and the other referred to as the N-face (-c polarity).
  • the oaxis of the III-N material layers is shown in FIG. 3.
  • the illustrated embodiment may be referred to as Ga polarity (+c) because the three bonds of Ga (or other group III element) in material layers 360, 365, 370 and 378 point away from the top-side gate electrode 325 and top-side contact metal 140 (i.e., point toward an underlying substrate or bottom side).
  • the (000-1) plane of III-N layer 365 is proximal to the (0001) plane of III-N channel layer 360.
  • 2D charge carrier sheet 341 is formed within III-N channel layer 360, for example at about 3-4 nm of the heteroj unction formed with the overlying polarization layer 365.
  • III-N material layer 370 is proximal to the (0001) plane of underlying polarization layer 365.
  • 2D charge carrier sheet 342 is formed within III-N material layer 370, for example at about 3-4 nm of the heteroj unction formed with polarization layer 365.
  • polarization layer 365 has a higher Al content than III-N channel layer 360.
  • Polarization layer 365 may be binary A1N.
  • Polarization layer 365 may also be an AlGaN alloy.
  • Exemplary AlGaN embodiments include 25-40% Al (Al x Gai- x N where 0.25 ⁇ x ⁇ 0.4).
  • Polarization layer 365 may also be an InAlN alloy or a quatemary alloy, which are also suitable as a polarization material and may offer advantages with respect to tuning the lattice constant to better match that of one or more other material layers (e.g., layers 360 and/or 370).
  • Exemplary InAlN embodiments include less than 20% In (In x Ali- x N where 0 ⁇ x ⁇ 0.2), with 17% In having the advantage of an exceptional lattice match with binary GaN.
  • Exemplary quaternary alloys include In x Ga y Ali- x - y N with 0 ⁇ x ⁇ 0.2 and 0 ⁇ y ⁇ 0.2.
  • III-N channel layer 360 may be binary GaN, as in the example shown in FIG. 3.
  • III- N channel layer 360 may also be an AlGaN or InAlN alloy, or even a quatemary alloy, as long as the polarization field strength difference between layers 365 and 360 is sufficient to induce formation of 2D charge carrier sheet 341.
  • III-N material layer 370 may also be binary GaN, as in the example shown in FIG. 3.
  • III-N material layer 370 may also be an AlGaN or InAlN alloy, or even a quaternary alloy, as long as the polarization field strength difference between layers 365 and 370 is sufficient to induce formation of 2D charge carrier sheet 342.
  • III-N material layer 378 may also be binary GaN, as in the example shown in FIG. 3.
  • III-N material layer 378 may also be an AlGaN or InAIN alloy, or even a quaternary alloy.
  • quaternary alloys such as In x Ga y Ali- x - y N where 0 ⁇ x ⁇ 0.2, 0 ⁇ y ⁇ 0.2 are also possible for either or both of III-N material layers 360, 370, and 378.
  • III-N material layer 378 may form a homojunction III-N material layer 378 as in FIG. 3, or III-N material layer 378 may form a heteroj unction with III-N material layer 370.
  • At least III-N channel layer 360 is intrinsic and not intentionally doped with impurities associated with a particular conductivity type.
  • Channel layer 360 in the intrinsic state can be expected to have higher charge carrier mobility than is possible for a material of higher impurity doping.
  • Intrinsic impurity (e.g., Si) levels in channel layer 360 are advantageously less than l ei 7 atoms/cm 3 , and in some exemplary embodiments is between l el4 and l ei 6 atoms/cm 3 .
  • channel layer 360 is intrinsic binary GaN (i-GaN).
  • Polarization layer 365 and III-N material layer 370 may each also be intrinsic and not intentionally doped with impurities, for example to simplify formation the III-N heterostructure.
  • polarization layer 365 has a thickness Tl of at least 30 nm, and
  • both 2D charge carrier sheets 341 and 342 will form whereas at lower thicknesses, polarization layer 365 may be unable to induce 2D charge carrier sheet 342 with sufficient density of states. Thicknesses of 30 nm, or more, can be readily accommodated where lattice mismatch between layers 360, 365 and 370 is not extreme. For example, where III-N channel layer 360 is i-GaN, a polarization layer 365 of binary A1N would be limited to a thickness Tl of only 1 -3 nm, which may not be adequate with respect to forming 2D charge carrier sheet 342.
  • binary A1N may be well-suited for a polarization layer of an HFET
  • other polarization layer alloys having a closer lattice match with GaN may offer advantages in the context of the diode(s) embedded within device 301.
  • III-N material layer 370 has a thickness T2 of at least 3-4 nm to accommodate 2D charge carrier sheet 342. Material layer 370 may be thicker however, particularly to avoid depleting the 2D charge carrier sheet at the P-N
  • Thickness T2 may therefore depend on the impurity doping level of III-N material layer 378 with examples ranging from 5 nm to 20 nm and thicknesses of at least 10 nm being advantageous.
  • III-N channel layer 360 has a thickness T3 of at least 3-4 nm.
  • Channel layer 360 may be considerably thicker however.
  • III-N channel layer 360 is at least part of a buffer structure upon which material layers 365-378 are grown.
  • III-N channel layer 360 may be formed over multiple buffer structure layers (not depicted).
  • thickness T3 may vary widely (e.g., 3-3000 nm) as a function of the layer composition within the III-N heterostructure.
  • the illustrated III-N heterostructure may further be disposed over any substrate suitable for hosting III-N crystals.
  • channel layer 360 is disposed over a SiC substrate.
  • the substrate is a cubic semiconductor, such as monocrystalline silicon.
  • template structures may be formed on a cubic substrate surface, such as a (100) surface.
  • III-N crystals may also be grown on other surfaces (e.g., 110, 11 1, miscut or offcut, for example 2-10° toward [1 10] etc.).
  • III-N material layers 360, 365, 370 and 378 may also be over a host substrate material upon which the III-N crystal has been bonded, in which case the host substrate may be crystalline, or not (e.g., glass, polymer, etc.).
  • gate electrode 325 may be selected based on the metal- semiconductor workfunction difference relative to III-N channel layer 360 to achieve a desired transistor threshold voltage.
  • III-N channel layer 360 is binary GaN
  • charge carrier sheet 341 is a 2DEG
  • gate electrode 325 advantageously includes at least one of Ni, W, Pt, or TiN.
  • each of these metals or metallic compounds may be associated with a particular work function (or metal-semiconductor work function difference) that has an impact transistor threshold voltage.
  • metals/metallic compounds known to make ohmic contacts to n-type III-N materials may also be suitable for making a non-rectifying contact to III-N material layer 378.
  • gate electrode 325 is illustrated as homogeneous in FIG. 3, a stack or laminate of metals may also be employed.
  • a contact metal 328 then contacts both gate electrode 325 and III-N material layer 378 to serve as both the gate and diode contact metal.
  • the composition of contact metal 328 may be selected based on the metal-semiconductor workfunction difference and surface states of III-N material layer 378 to provide the desired diode contact resistance.
  • contact 328 may include at least one of Ti, Al, or W, for example.
  • Other metals known to make ohmic contacts to n-type III-N materials may also be suitable for making ohmic contact to III-N material layer 378.
  • source and drain semiconductor 330 has n-type
  • contact metal 140 may be any suitable metal, such as at least one of Ti, Al, or W, for example. Other metals known to make ohmic contacts to n-type III-N materials may be suitable alternatives for making ohmic contact to source and drain semiconductor 330.
  • Gate dielectric 124 may be any high-k (e.g., bulk permittivity of 9, or more) or conventional dielectric material (e.g., bulk permittivity of 3.5-8) known to be suitable for the purpose in III-N FETs.
  • gate electrode 325 is further electrically insulated and/or decoupled from polarization layer 365 and III-N material layer 370 by a dielectric sidewall spacer 326.
  • Dielectric sidewall spacer may be any low-k (e.g., bulk permittivity of 3, or less) or conventional dielectric material (e.g., bulk permittivity of 3.5-8) known to be suitable for the purpose of reducing capacitive coupling between gate electrodes and adjacent semiconductors.
  • low-k e.g., bulk permittivity of 3, or less
  • conventional dielectric material e.g., bulk permittivity of 3.5-8
  • an insulative dielectric material 380 is over III-N material layer 370.
  • dielectric material 380 is over a c-plane (Ga-face) of III- N material layer 370, laterally (e.g., x-dimension) separating III-N material layer 378 from source and drain semiconductor 330.
  • the length of III-N material layer 370 and dielectric material 380 separating III-N material layer 378 from source and drain semiconductor 330, III-N material layer 378 prevents an electrically non-rectifying short between III-N material layer 378 and source and drain semiconductor 330.
  • Dielectric material 380 may be of any composition known to be suitable as a passivation and/or protective encapsulant of III-N devices, such as, but not limited to silicon oxides (SiO), silicon nitrides (SiN), silicon oxynitrides (SiON), silicon carbonitrides (SiCN), or low-k materials (e.g., carbon doped silicon dioxide (SiOC), porous dielectrics, etc.), and metal oxides (e.g., AI2O3).
  • SiO silicon oxides
  • SiN silicon nitrides
  • SiON silicon oxynitrides
  • SiCN silicon carbonitrides
  • low-k materials e.g., carbon doped silicon dioxide (SiOC), porous dielectrics, etc.
  • metal oxides e.g., AI2O3
  • FIG. 4 is a cross-sectional view of a Group III-N device structure 401 that includes a III-N transistor and integrated III-N diode, in accordance with some alternative
  • III-N device structure 401 shares many of the structural features of device 301 (e.g., FIG. 3), with the shared features having the same reference number.
  • One terminal of the III-N diode however further includes an additional III-N material layer 475, which may be employed for example to tune the forward and reverse current/voltage characteristics of the integrated diode(s).
  • III-N material layer 475 is therefore further illustrated in FIG. 4 as introducing a resistor 453 into the diodic connection between gate electrode 325 and source/drain semiconductor 330.
  • III-N material layer 475 includes impurity dopants to have a conductivity type complementary to that of III-N material layer 378.
  • III-N material layer 475 is doped with acceptor impurities to be P-type. While III-N materials can be challenging to dope p-type, acceptor impurity levels of l el7 atoms/cm 3 to l el 8 atoms/cm 3 are achievable, for example with Mg doping of binary GaN.
  • the presence of p-type (acceptor) dopants in III-N material layer 475 may also advantageously serve as a source of charge carriers for 2D charge carrier sheet 342.
  • the thickness of III-N material layer 475 may vary, for example between 3nm and 10 nm, to achieve the desired diode characteristics.
  • the III-N devices described above may be fabricated using a variety of methods.
  • FIG. 5 is a flow diagram illustrating methods 501 for forming III-N transistors integrated with III-N diodes, in accordance with some embodiments.
  • Methods 501 begin at operation 505 where a substrate including a crystalline seed layer is received.
  • the substrate received at operation 505 may be any of those described above, for example.
  • a III-N epitaxial growth process is employed to grow a crystalline Ga-polar III-N heterostructure on the substrate seeding surface.
  • the heterostructure grown induces the formation of two, complementary, 2D charge carrier sheets.
  • the epitaxial growth performed at operation 510 may form a continuous crystal over an entire surface of a substrate, or may be limited to islands or mesas occupying only a portion of a substrate surface as controlled through a templating pattern.
  • a Ga-face of a III-N crystal grown with any polarity is exposed at operation 510.
  • a III-N crystal may be first grown with N-polarity over a substrate, and the substrate then removed to expose the Ga-face to subsequent processing.
  • Methods 501 continue at operation 520 where source and drain semiconductor is formed in a manner that ensures at least one of the source and drain semiconductor is coupled to both of the 2D charge carrier sheets present within the heterostructure.
  • the formation process may further entail forming a recess through layers of the III-N
  • heterostructure and deposition or growth of semiconductor within the recess Any patterning techniques may be employed to form the recess and any epitaxial growth technique or deposition process may be employed, for example to form any of the source and drain semiconductor compositions described above.
  • Methods 501 continue where a gate electrode is formed in a manner that ensures the gate electrode will be coupled (e.g., capacitively) to a first of the 2D charge carrier sheets and also coupled (e.g., with rectification) to a second of the 2D charge carrier sheets.
  • Any deposition process(es) suitable for the chosen gate dielectric and gate electrode may be employed at operation 520.
  • one or more of physical vapor deposition, chemical vapor deposition, or atomic layer deposition may be employed to deposit one or more gate dielectric layer and one or more the metal or metallic compound, such as any of those described elsewhere herein.
  • Methods 501 continue at operation 540 where one or more interlay er dielectrics (ILDs) and/or interconnect routing levels are formed using any techniques known to be suitable for the purpose.
  • ILDs interlay er dielectrics
  • BEOL back-end-of-line
  • one or more interconnect levels may be employed to form a monolithic protection circuit (e.g., circuit 200) that includes the III-N transistor and diode(s) fabricated by methods 501.
  • an IC including a III-N transistor with one or more vertically integrated III-N diode is substantially complete and may be singulated and packaged following any suitable techniques.
  • FIG. 6A-6I are cross-sectional views of Group III-N device 401 evolving as selected operations in the methods 501 are performed, in accordance with some embodiments.
  • III-N heterostructure 615 has been epitaxially grown over a crystalline seeding surface of a substrate (not depicted).
  • III-N heterostructure 615 may have been grown within an opening of amorphous material (not depicted) defining any suitable template structure.
  • the seeding surface is SiC.
  • the seeding surface is a (100) cubic semiconductor surface is exposed within trenches extending in a ⁇ 110> direction of the substrate.
  • Growth of III-N heterostructure 615 may include deposition of a seed layer (not depicted) and further include growth of intrinsic GaN using first epitaxial growth conditions (e.g., a first growth pressure, a first growth temperature, and a first V/III growth precursor ratio) to form III-N channel layer 360. Following an initial growth period, growth conditions may be changed to a second growth pressure, temperature, and/or a second V/III growth precursor ratio to form III-N polarization layer 365. Following this second growth period, growth conditions may be changed back to the first (GaN) growth conditions, or changed to a third growth pressure, temperature, and/or a third V/III growth precursor ratio to form III- N material layer 370.
  • first epitaxial growth conditions e.g., a first growth pressure, a first growth temperature, and a first V/III growth precursor ratio
  • III-N material growths may be by any known technique, such as, but not limited to metal-organic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE), or molecular beam epitaxy (MBE). In some embodiments, elevated temperatures of 600 °C, or more, are employed.
  • MOCVD metal-organic chemical vapor deposition
  • VPE vapor phase epitaxy
  • MBE molecular beam epitaxy
  • FIG. 6B is a cross-sectional view illustrating patterning of III-N heterostructure 615 for the gate electrode, in accordance with some embodiments.
  • a lithographic and etch patterning process defines a trench or via pattern including a recess 625 through III-N material layers 378, 475, 370 and into III-N polarization layer 365. The recess is then backfilled with a permanent or sacrificial gate stack.
  • FIG. 6C is a cross-sectional view illustrating formation of a sacrificial "dummy" or "mandrel" gate electrode stack 610, in accordance with some embodiments.
  • the sacrificial gate stack may include one or more dielectric layer (e.g., SiN, SiO, SiON, SiOC, etc.), or semiconductor (e.g., polysilicon), for example. Any deposition process and planarization process known to be suitable for backfilling the recess 625 with the desired sacrificial gate stack may be utilized.
  • FIG. 6D is a cross-sectional view illustrating formation of source and drain recesses 630 on opposite sides of the gate electrode recess.
  • an amorphous hardmask (e.g., SiN, SiO, SiON, SiOC, etc.) 616 is deposited over III-N heterostructure 615 prior to forming source and drain recesses 630.
  • Source and drain recesses 630 are then lithographically define and propagated by etch into amorphous hardmask 616 and heterostructure 615, removing a nominal surface thickness (e.g., 5-10 nm) of III-N channel layer 360.
  • FIG. 6E is a cross-sectional view illustrating formation of source and drain semiconductor 330 epitaxially grown within source and drain recesses 630 to at least partially backfill the recesses.
  • Source and drain semiconductor 330 may be epitaxially grown from the Ga-face of III-N channel layer 360.
  • Amorphous hardmask 616 prevents semiconductor growth over the masked III-N surfaces.
  • recesses 630 are backfilled with InGaN material that is doped with n-type impurities in-situ during epitaxial growth.
  • n-type impurities may be implanted subsequent to growth and then made electrically active, for example with a thermal anneal.
  • FIG. 6F is a cross-sectional view illustrating replacement of the sacrificial gate stack with a permanent gate stack including gate dielectric 124 and gate electrode 325.
  • the gate replacement process may include selective removal of the sacrificial gate stack, deposition and etching of dielectric sidewall spacer 326, deposition of gate dielectric 124 and deposition of gate electrode 325. Any deposition and planarization techniques known to be suitable for the chosen materials may be employed to implement the gate replacement process.
  • FIG. 6G is a cross-sectional view illustrating formation of a recess 680 that extends through III-N material layer 378 to sever any contact between source and drain
  • III-N etch is to electrically separate terminals of the diode and may entail any lithographic patterning and III-N etch process(es) known to be suitable for the chosen composition of III-N material layer 378.
  • Any suitable ILD deposition and planarization process is then employed to form dielectric material 380, backfilling the recess 680 to electrically insulate/isolate III-N material layer 378 from source and drain semiconductor 330.
  • Contact metals 140 and 328 may then be formed concurrently or serially by any suitable backend metallization process (e.g., trench/via etch and metal backfill and polish) to arrive at device structure 401 illustrated in FIG. 61 and as described elsewhere herein.
  • FIG. 7 illustrates a system 700 in which a mobile computing platform 705 and/or a data server machine 706 employs circuitry including at least one III-N heteroj unction transistor structure including an embedded or integrated diode, for example in accordance with some embodiments described elsewhere herein.
  • the server machine 706 may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a circuitry 750.
  • the mobile computing platform 705 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like.
  • the mobile computing platform 705 may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 710, and a battery 715. Whether disposed within the integrated system 710 illustrated in the expanded view
  • the circuit includes at least one III-N heteroj unction transistor structure including an embedded or integrated diode, for example in accordance with some embodiments described elsewhere herein.
  • Circuitry 750 may be further attached to a board, a substrate, or an interposer 760 along with a power management integrated circuit (PMIC).
  • PMIC power management integrated circuit
  • PMIC 730 may perform battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to battery 715 and with an output providing a current supply to other functional modules.
  • Circuitry 750 includes RF (wireless) integrated circuitry (RFIC) further including a wideband RF (wireless) transmitter and/or receiver (TX/RX including a digital baseband and an analog front end module comprising a power amplifier on a transmit path and a low noise amplifier on a receive path).
  • RFIC includes at least one III-N heteroj unction transistor structure including an embedded or integrated diode, for example in a over-voltage protection circuit as describe elsewhere herein.
  • the RFIC has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • Wi-Fi IEEE 802.11 family
  • WiMAX IEEE 802.16 family
  • IEEE 802.20 long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • LTE long term evolution
  • Ev-DO HSPA+
  • FIG. 8 is a functional block diagram of a computing device 800, arranged in accordance with at least some implementations of the present disclosure.
  • Computing device 800 may be found inside platform 705 or server machine 706, for example.
  • Device 800 further includes a motherboard 802 hosting a number of components, such as, but not limited to, a processor 804 (e.g., an applications processor), which may further incorporate at least one III-N heteroj unction transistor structure including an embedded or integrated diode, for example in accordance with some embodiments described elsewhere herein.
  • Processor 804 may be physically and/or electrically coupled to motherboard 802.
  • processor 804 includes an integrated circuit die packaged within the processor 804.
  • the term "processor” or "microprocessor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory.
  • one or more communication chips 806 may also be physically and/or electrically coupled to the motherboard 802. In further implementations,
  • computing device 800 may include other components that may or may not be physically and electrically coupled to motherboard 802. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, touchscreen display, touchscreen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like.
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor
  • a digital signal processor e.g., ROM
  • crypto processor e.g., a crypto processor
  • chipset an antenna
  • touchscreen display
  • Communication chips 806 may enable wireless communications for the transfer of data to and from the computing device 800.
  • the term "wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • Communication chips 806 may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein.
  • computing device 800 may include a plurality of communication chips 806.
  • a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • a Group Ill-Nitride (III-N) device structure comprise a heterostructure having four or more layers comprising III-N material, wherein a first layer of the heterostructure comprises donor dopants.
  • the structure comprises a gate electrode within a recess that extends through two or more of the layers, wherein the gate electrode is in electrical contact with the first layer.
  • the structure comprises a source and a drain comprising donor dopants, wherein at least one of the source and the drain are spaced apart from the first layer by a second layer of the heterostructure.
  • the heterostructure in any of the first examples includes a third layer separated from the first layer by the second layer and located between the second layer and a fourth layer.
  • the third layer has a higher Al content than the second and fourth layers.
  • the third layer comprises Al x Gai- x N, In y A - y N, or In y Ali- y - z GazN.
  • the second and fourth layers comprise binary GaN, and x is between 0.25 and 0.4, y is less than 0.2, or z is less than 0.2.
  • the second layer thickness is less lOnm and the third layer thickness is at least 30 nm.
  • the heterostructure has Ga-polarity and a two-dimensional hole gas is present within the second layer, and a two-dimensional electron gas is present within the fourth layer.
  • the gate electrode is separated from a plurality of the layers of the heterostructure by one or more dielectric layer.
  • the heterostructure further comprises a fifth layer between the first material layer and the second material layer, the fifth layer comprising acceptor dopants.
  • the source and drain comprise In x Gai- x N with x between 0.05 and 0.2, the source and drain have an impurity concentration of at least lei 9 atoms/cm 3 , and the first III-N material layer is impurity doped to less than lei 9 atoms/cm 3 .
  • the first and the second layers comprise a rectifying heteroj unction.
  • the structure further comprises one or more non-rectifying metal-semiconductor junction located between the gate electrode and the first III-N material layer.
  • the second III-N material layer and at least one of the source and the drain comprise a non- rectifying heteroj unction.
  • a computer platform includes one or more RF transceiver, and an antenna coupled to the RF transceiver, wherein the RF transceiver has one or more signal input coupled to the gate electrode in any of the first through thirteenth examples.
  • the system includes a processor communicatively coupled to the RF transceiver, and a battery coupled to at least one of the processor and RF transceiver.
  • a method of forming a Group Ill-Nitride (III-N) device structure comprises forming heterostructure comprising III-N material layers and complementary two-dimensional charge carrier sheets, forming source and drain
  • forming the heterostructure further comprises epitaxially growing four or more layers, the layers including a first layer comprising donor impurities.
  • Forming the gate electrode further comprises forming a first recess in the heterostructure, the recess extending through two or more of the layers, and forming a gate dielectric within the recess.
  • the method comprises depositing gate electrode material over the gate dielectric and in electrical contact with the first layer.
  • Forming the source and drain semiconductor further comprises forming second recesses in the heterostructure on opposite sides of the first recess and spaced apart from the first layer by a second of the layers, the second recesses extending through two or more of the layers, and epitaxially growing a III-N material comprising donor impurities within the second recesses.
  • epitaxially growing the four or more layers further comprises growing a second layer between the first layer and a third layer grown over a Ga-face of a fourth layer.
  • growing the third layer further comprises growing a III-N material with higher Al content than the second and fourth layers.
  • epitaxially growing the third layer further comprises growing a layer of Al x Gai- x N, In y Ah- y N, or In y Ali- y-zGazN, and epitaxially growing the second and fourth layers further comprises growing binary GaN.
  • growing the second and fourth layers further comprises epitaxially growing binary GaN, and wherein x is between 0.25 and 0.4, y is less than 0.2, or z is less than 0.2.
  • epitaxially growing the third layer further comprises growing a layer of Al x Gai- x N, InyAli-yN, or In y Ali- y - z GazN to a thickness of 30nm, or more.
  • heterostructure further comprises epitaxially growing a fifth layer between the first layer and the second layer, the fifth layer comprising acceptor impurities.
  • the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed.
  • the scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

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Abstract

Diodes employing a Group III-Nitride heterostructure are vertically integrated with a Group III-Nitride heterostructure of a transistor. The area of an IC occupied by diode structures may be reduced relative to conventional diode and transistor architectures. A III-N heterostructure that includes a heterojunction between a first II-N material layer or lamella over a second III-N material layer is over third and fourth III-N material layers. Through control of the compositions of the second and fourth III-N material layers relative to the third III-N material layer that separates them, complementary two-dimensional charge carrier sheets (e.g., one 2D hole gas and one 2D electron gas) may be induced within the second and fourth III-N material layer. One of the 2D charge sheets may be employed within the transistor while the other may be employed within the diode.

Description

GROUP III-NITRIDE TRANSISTOR STRUCTURE WITH EMBEDDED DIODE
BACKGROUND
Diodes are a common circuit element used in integrated circuits (ICs). Diodes are useful for protecting circuitry from over-voltages, such as those associated with electrostatic discharge (ESD) events. Absent a protection circuit, discharge through a device such as a transistor, can cause catastrophic damage to an IC. Diodic protection circuits may therefore be configured as part of a functional IC to shunt surges in potential away from circuitry that could otherwise be damaged. Group Ill-Nitride (IUPAC 13-N) semiconductor materials offer the benefit of a relatively wide bandgap (~3.4eV), enabling higher breakdown voltages than Si-based devices. Group Ill-Nitride (III-N) semiconductor materials also offer high carrier mobility. However, III-N diodes with sufficiently low on-resistance tend to be an area-intensive circuit element even when monolithically integrated with transistors of an IC.
III-N diode structures enabling a smaller area are therefore advantageous at least for enabling dimensional scaling of the device platforms that employ them.
BRIEF DESCRIPTION OF THE DRAWINGS The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Also, various physical features may be represented in their simplified "ideal" forms and geometries for clarity of discussion, but it is nevertheless to be understood that practical implementations may only approximate the illustrated ideals. For example, smooth surfaces and square intersections may be drawn in disregard of finite roughness, corner-rounding, and imperfect angular intersections characteristic of structures formed by nanofabrication techniques. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures:
FIG. 1A is a plan view of a III-N transistor and diode arranged onto an IC, in accordance with some embodiments; FIG. IB and 1C are cross-sectional views of the III-N transistor and diode shown in FIG. 1A;
FIG. 2 is a schematic of a diode protection circuit, in accordance with some embodiments; FIG. 3 is a cross-sectional view an exemplary III-N heteroj unction transistor including an embedded diode, in accordance with some embodiments;
FIG. 4 is a cross-sectional view an exemplary III-N heteroj unction transistor structure including an embedded diode, in accordance with some embodiments;
FIG. 5 is a flow diagram illustrating methods of forming III-N heteroj unction transistor structure including an embedded diode, in accordance with some embodiments;
FIG. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, and 61 are cross-sectional views of a III-N heteroj unction transistor structure including an embedded diode evolving as selected operations in the method of FIG. 5 are performed, in accordance with some embodiments;
FIG. 7 illustrates a mobile computing platform and a data server machine employing an IC having a III-N heterostructure diode, in accordance with embodiments; and
FIG. 8 is a functional block diagram of an electronic computing device, in accordance with some embodiments.
DETAILED DESCRIPTION
One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein.
Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents.
In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that the present invention may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive. As used in the description and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).
The terms "over," "under," "between," and "on" as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies.
As used throughout this description, and in the claims, a list of items joined by the term "at least one of or "one or more of can mean any combination of the listed terms. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C.
A diode and transistor employing an integrated Group Ill-Nitride heterostructure are described herein. Devices in accordance with one or more of the embodiments described herein reduce the area of an IC needed to support diode structures relative to separate diode and transistor architectures. As described further below, a III-N heterostructure that includes a heteroj unction between a first III-N material layer or lamella over a second III-N material layer is employed within a diode. This diode material stack is formed over a Ga-face of third and fourth III-N material layers employed within a transistor. Through control of the compositions of the second and fourth III-N material layers relative to the third III-N material layer that separates them, complementary two-dimensional charge carrier sheets (e.g., one 2D hole gas and one 2D electron gas) may be induced within the second and fourth III-N material layer. The transistor may employ one of the 2D charge sheets while the other of the 2D charge sheets may be employed within the diode. With material layers of the III-N heterostructure grown in a stack, the diode may be vertically integrated or "embedded" within the footprint of the transistor. As described further below, a gate of the transistor may modulate one of the 2D charge carrier sheets (e.g., 2D electron gas) controlling the electrical coupling between a source and drain of the transistor. The gate of the transistor is also electrically coupled to at least one of the transistor source and drain through a rectifying junction between the first III- N material layer that has a first conductivity type (e.g., the same conductivity type as the source and drain) and the second III-N material layer in which the second 2D charge carrier sheet (e.g., 2D hole gas) resides. Where the gate of the transistor is electrically coupled to each of the transistor source and drain through back-to-back rectifying junctions of the first and second III-N material layers, both a gate-source diode and gate-drain diode may be embedded within the footprint of the transistor. FIG. 1A is plan view of an integrated circuit structure 100 including a pair of Group
III-N diodes 105 and a Group III-N transistor 110 onto an IC. Structure 100 is an example provided for comparison to embedded diode architectures described further below. Diodes 105 are configured with one terminal in common (e.g., anode) and require approximately the same xy area (e.g., footprint) as transistor 110. Between diodes 105 and transistor 110 is a region of isolation dielectric 180, further increasing the footprint of IC structure 100. For diodes 105, a stripe of a first contact metal 120 and stripes of a second contact metal 140 are spaced apart on either side at some predetermined design rule pitch. Similarly, stripes of source/drain contact metal 145 on either side of gate electrode 125 are spaced apart at the design rule pitch. Interconnect metallization 150, 151, and 152 pass over the lower level conductors with conductive vias 135 linking various terminals of the diodes 105 to various terminals of transistor 110. In one exemplary embodiment, interconnect metallization 150 conveys a voltage Vin in a terminal of diodes 105 and to the gate electrode of transistor 110. Interconnect metallization 151 conveys a voltage Vcc to a terminal of diodes 150 and to the source of transistor 110. Interconnect metallization 152 conveys a voltage Vss to a terminal of diodes 150 and to the drain of transistor 110.
FIG. IB and 1C are cross-sectional views of IC structure 100. FIG IB is a sectional view along the A- A' line illustrated in FIG. 1 A. As shown, a two-dimensional (2D) charge carrier sheet 166 is formed between a first III-N material layer 160 and a second III-N material layer 165. For diodes, charge carrier sheet 166 is coupled to a first terminal through a Schottky (rectifying) metal semiconductor junction between III-N material layer 160 and first terminal contact metal 120. For diodes 105, 2D charge carrier sheet 166 is further coupled to impurity-doped semiconductor 130, which further interfaces contact metal 140. For transistor 110, 2D charge carrier sheet 166 is coupled to a first terminal through a Schottky (rectifying) 2D charge carrier sheet 166 is coupled to impurity-doped
semiconductor 130, which further interfaces source/drain metal 145. For transistor 110, 2D charge carrier sheet 166 is further coupled to a gate stack forming a metal-oxide- semiconductor (MOS) junction. In the illustrated example, 2D charge carrier sheet 166 is to be gated by gate electrode 125 through gate dielectric 124. As can be see in FIG. 1A-1C, the addition of diodes 105 nearly doubles the footprint of IC structure 100 beyond what is needed by transistor 110, and the footprint is further increased with the area occupied by isolation dielectrics 180, 185. FIG. 2 is schematic of an electrical circuit 200 including at least one III-N heteroj unction diode vertically integrated or embedded within the heterostructure of a III-N transistor. With diodes embedded within a III-N transistor as further described below, circuit 200 may be implemented within a smaller area than if implemented with the architecture shown in FIG. 1A-1C. Circuit 200 can be implemented as a single IC chip and may be implemented in any electronic device, such as, but not limited to, smartphones, ultrabook computers, embedded devices (e.g., intemet of things, automotive applications, etc.), or wearables. In circuit 200, a III-N transistor 205 is to be protected from electrical surges by diodes 211, 212, and 213. Transistor 205 includes a first terminal (e.g., source) coupled to a first supply rail 206 maintained at a nominal supply voltage (e.g., Vcc), and a second terminal (e.g., drain) coupled to second supply rail 207 maintained at a nominal reference voltage (e.g., Vss). A third terminal (e.g., gate) of transistor 205 is coupled to a signal input 208, which conveys an input voltage Vin. In circuit 200, transistor 205 is protected by diodes 21 1 and 212 connecting signal input 208 to the supply rails 206, 207 (e.g., Vcc and Vss, respectively), and by diode 213 connecting supply rail 206 to supply rail 207.
Under normal operating conditions, diodes 21 1, 212 and 213 are maintained in the off-state (e.g., reverse biased) such that signal input 208 is effectively disconnected from supply rails 206, 207 while transistor 205 is driven by the supply voltage across rails 206, 207. However, upon experiencing a potential surge between signal input 208 and supply rails 206 and 207, the transient will forward bias one or more of diodes 21 1, 212 and 213, turning them on. Which of diodes 21 1 , 212 and 213 become forward biased is dependent on the charge polarity of the surge relative to the supply rail potentials. Charge accumulated at voltage input 208 is thereby dissipated or shunted through the diode path around transistor 205. In accordance with some embodiments, one or more diodes of a protection circuit (e.g., diodes 21 1, 212 and 213) employ a III-N heterostructure further employed by transistor 205. One or more of diodes 21 1 , 212, 213 may be thereby vertically integrated monolithically with transistor 205, reducing the IC footprint of the integrated device. Such transistor-diode integrated device structures may have one or more of the features described further below. Any of the III-N heterostructure integrated devices described further herein may also be employed in any other suitable protection circuit designs. Any of the III-N heterostructure integrated devices described further herein may also be employed in circuits having functions other than ESD protection, such as, but not limited to, high voltage power management circuitry.
FIG. 3 is a cross-sectional view of an exemplary Group III-N device 301 including a heteroj unction field effect transistor (HFET) vertically integrated with heteroj unction diodes, in accordance with some embodiments. The HFET of device 301 may be transistor 205 (FIG. 2) that is protected by the embedded diodes configured according to one or more of the diodes in protection circuit 200, for example. In some embodiments, the HFET is a high electron mobility transistor (HEMT), and more specifically, is a metal oxide semiconductor (MOS) HEMT with a recessed gate electrode 325 and a gate dielectric 124.
In device 301 , III-N material layers 360, 365, 370 and 378 form a III-N
heterostructure. Within the III-N heterostructure, a III-N polarization layer 365 is positioned over a III-N channel layer 360. III-N material layers 370 and 378, which form a rectifying (diodic) semiconductor junction, are separated from III-N channel layer 360 by III-N polarization layer 365. Polarization layer 365 comprises an alloy distinct from the alloy of channel layer 360, thereby inducing a variation in the polarization field strength (e.g., spontaneous and/or piezoelectric) between these two III-N layers. Where spontaneous and/or piezoelectric polarization field strengths are sufficiently different between polarization layer 365 and III-N channel layer 360, a two-dimensional charge carrier sheet 341 (e.g., 2D electron gas or "2DEG") is formed within channel layer 360 in the absence of any externally applied field.
Polarization layer 365 also comprises an alloy distinct from the alloy employed in III-N material layer 370, thereby also inducing a variation in the polarization field strength (e.g., spontaneous and/or piezoelectric) between these two III-N layers. Where spontaneous and/or piezoelectric polarization field strengths are sufficiently different between polarization layer 365 and III-N material layer 370, a second two-dimensional charge sheet 342 of a conductivity type complementary to 2D charge carrier sheet 341 (e.g., 2D hole gas or "2DHG") is formed within III-N material layer 370 in the absence of any externally applied field. As described further below, 2D charge sheet 342 may functionally be considered a terminal (e.g., anode) of the integrated diode.
In exemplary embodiments, III-N material layer 378 is impurity doped to have a conductivity type complementary to that of 2D charge sheet 342. III-N material layer 378 may thereby function as the complementary terminal (e.g., cathode) of the integrated diode. Hence, where 2D charge sheet 342 is a 2DHG, III-N material layer 378 has donor dopants or impurities to have n-type conductivity. The semiconductor junction of III-N material layer 370 and III-N material layer 378 is an P-type/N-type junction suitable for diodic (rectifying) current conduction. The doping level of III-N material layer 378 may be predetermined to establish a P-N junction of suitable depletion width, forward voltage, and electrical breakdown characteristics. While dopant levels may therefore vary, in some exemplary embodiments III-N material layer 378 is doped with donor impurities to between l ei 8 atoms/cm3 and l el 9 atoms/cm3. One exemplary N-type donor dopant atom suitable for such dopant levels in III-N materials is Si. An alternative donor dopant atom is Ge.
As further shown in FIG. 3, gate electrode 325 is located within a recess in the III-N heterostructure that extends a depth (e.g., z-dimension) through III-N material layers 378 and 370, and into polarization layer 365. The recess depth into polarization layer 365 may be predetermined to tune threshold voltage (Vt) of the transistor. For example, recessed gate electrode 325 may be at a depth relative to III-N channel layer 360 to ensure a positive Vt for an enhancement mode n-type transistor. Gate electrode 325 is also electrically coupled to III-N material layer 378. Gate electrode 325 is capacitively coupled through gate dielectric 124 to one or more layers of the III-N heterostructure (e.g., III-N channel layer 360). Gate electrode 325 also forms a metal-semiconductor junction with III-N material layer 378. In some embodiments, this metal-semiconductor junction is non-rectifying, and advantageously an ohmic junction, enabling gate electrode 325 to be directly coupled to a first terminal 351 (e.g., cathode) of the integrated III-N diode.
As shown in FIG. 3, source and drain semiconductor 330 is within recesses in the III- N heterostructure that are located on opposite sides of gate electrode 325. The source and drain recesses also extend through III-N material layer 370, and polarization layer 365, landing on III-N channel layer 360. In the illustrated example, source and drain
semiconductor 330 is in physical contact with a oplane (e.g., Ga-face) of III-N channel layer 360. Source and drain semiconductor 330 have access an edge thickness of 2D charge carrier sheet 341 buried below the heteroj unction between polarization layer 365 and III-N channel layer 360. Modulation of 2D charge carrier sheet 341 by the field effect of gate electrode 325 may thereby control electrical coupling between source and drain
semiconductor 330. The junction between III-N channel layer 360 and source and drain semiconductor 330 may be a heteroj unction with the composition of source and drain semiconductor 330 being distinct from that of at least III-N channel layer 360. In some embodiments, source and drain semiconductor 330 is also a III-N material. For example, source and drain semiconductor 330 may be InGaN. Some advantageous InGaN
embodiments include 5-20% In (InxGai-xN with 5% < x < 20%). The alloy composition of source and drain semiconductor 330 may be constant or graded between III-N channel layer 360 and contact metal 140. For some embodiments, source and drain semiconductor 330 is epitaxial, having the same crystallinity and orientation as III-N channel layer 360.
Source and drain semiconductor 330 is advantageously include impurity dopants to have a first conductivity type (e.g., Si donor impurities for n-type conductivity). The doping level of source and drain semiconductor 330 is advantageously as high as practical for lowest transistor terminal resistance. The doping level of source and drain semiconductor 330 may be at least an order of magnitude higher than that of III-N material layer 378, for example. In some exemplary embodiments where the source and/or drain semiconductor 330 is a III-N alloy, the impurity dopant level is over l ei 9 atoms/cm3, and more advantageously over le20 atoms/cm3. Si is one exemplary dopant atom for which such high (N+) doping levels may be achieved in III-N alloys. An alternative N-type dopant is Ge.
As shown in FIG. 3, source and drain semiconductor 330 are each electrically coupled to III-N material layer 370, with the gate recess separating bifurcating the III-N material layer 370 that is in contact with source semiconductor from the III-N material layer 370 that is contact with the drain semiconductor. Hence, the III-N heterostructure is stripe having a width in the y-dimension (out of the plane of FIG. 3) that is no more than that of the gate electrode so that the diodic III-N material layers 378 and 370 are physically separated from each other by intervening gate electrode 325. Source semiconductor 330, has a first conductivity type with a high concentration of dopant impurities (e.g., N+), forming an abrupt semiconductor-semiconductor junction with III-N material layer 370. With access to an edge of 2D charge carrier sheet 342 that has a high density of hole states, a tunnel junction 352 is formed between III-N material layer 370 and source/drain semiconductor 370, enabling contact metal 140 to be directly coupled to a second terminal (e.g., anode) of the integrated III-N diode.
As shown in FIG. 3, device 301 integrates two back-to-back III-N heteroj unction diodes sharing in common a first terminal (e.g., cathode) electrically tied to gate electrode 325, and having separate second terminals (e.g., anodes) electrically tied to one of source and drain semiconductor 330. Although three diode terminals are illustrated in FIG. 3, various features described in the context of FIG. 3 are also applicable to a single III-N heteroj unction diode having two terminals (cathode and anode) between only a gate electrode and source semiconductor, or between only a gate electrode and drain
semiconductor. As noted above, 2D charge sheets 341 and 342 originate from different polarization field strengths associated with the different compositions of layers within the III-N heterostructure. The location of 2D charge sheets 341 , 342 is also a function of the III-N crystal polarity, with the locations illustrated in FIG. 3 being indicative of a Ga-polar III-N crystal. The III-N heterostructures employed in device 301 has monocrystalline
microstructure (e.g., Wurtzite). Although monocrystalline, it is noted that crystal quality of the III-N crystal may vary dramatically, for example as a function of the techniques employed to form the crystal. In exemplary embodiments, dislocation density with layers of the III-N heterostructure may range between 108-10n/cm2. The Wurtzite crystalline III-N heterostructure lacks inversion symmetry, and more particularly the {0001 } or "c" planes are not equivalent. One of the {0001 } planes is typically referred to as the Ga-face (+c polarity) and the other referred to as the N-face (-c polarity). The oaxis of the III-N material layers is shown in FIG. 3. The illustrated embodiment may be referred to as Ga polarity (+c) because the three bonds of Ga (or other group III element) in material layers 360, 365, 370 and 378 point away from the top-side gate electrode 325 and top-side contact metal 140 (i.e., point toward an underlying substrate or bottom side). Hence, the (000-1) plane of III-N layer 365 is proximal to the (0001) plane of III-N channel layer 360. For this orientation, 2D charge carrier sheet 341 is formed within III-N channel layer 360, for example at about 3-4 nm of the heteroj unction formed with the overlying polarization layer 365. Similarly, the (000-1) plane of III-N material layer 370 is proximal to the (0001) plane of underlying polarization layer 365. For this orientation, 2D charge carrier sheet 342 is formed within III-N material layer 370, for example at about 3-4 nm of the heteroj unction formed with polarization layer 365.
For some exemplary embodiments having Ga-polarity, polarization layer 365 has a higher Al content than III-N channel layer 360. Polarization layer 365 may be binary A1N. Polarization layer 365 may also be an AlGaN alloy. Exemplary AlGaN embodiments include 25-40% Al (AlxGai-xN where 0.25 < x < 0.4). Polarization layer 365 may also be an InAlN alloy or a quatemary alloy, which are also suitable as a polarization material and may offer advantages with respect to tuning the lattice constant to better match that of one or more other material layers (e.g., layers 360 and/or 370). Exemplary InAlN embodiments include less than 20% In (InxAli-xN where 0 < x < 0.2), with 17% In having the advantage of an exceptional lattice match with binary GaN. Exemplary quaternary alloys include InxGayAli-x-yN with 0 < x < 0.2 and 0 < y < 0.2.
III-N channel layer 360 may be binary GaN, as in the example shown in FIG. 3. III- N channel layer 360 may also be an AlGaN or InAlN alloy, or even a quatemary alloy, as long as the polarization field strength difference between layers 365 and 360 is sufficient to induce formation of 2D charge carrier sheet 341. III-N material layer 370 may also be binary GaN, as in the example shown in FIG. 3. III-N material layer 370 may also be an AlGaN or InAlN alloy, or even a quaternary alloy, as long as the polarization field strength difference between layers 365 and 370 is sufficient to induce formation of 2D charge carrier sheet 342. III-N material layer 378 may also be binary GaN, as in the example shown in FIG. 3. III-N material layer 378 may also be an AlGaN or InAIN alloy, or even a quaternary alloy. For example, quaternary alloys such as InxGayAli-x-yN where 0 < x < 0.2, 0 < y < 0.2 are also possible for either or both of III-N material layers 360, 370, and 378. III-N material layer 378 may form a homojunction III-N material layer 378 as in FIG. 3, or III-N material layer 378 may form a heteroj unction with III-N material layer 370.
In some advantageous embodiments, at least III-N channel layer 360 is intrinsic and not intentionally doped with impurities associated with a particular conductivity type.
Channel layer 360 in the intrinsic state can be expected to have higher charge carrier mobility than is possible for a material of higher impurity doping. Intrinsic impurity (e.g., Si) levels in channel layer 360 are advantageously less than l ei 7 atoms/cm3, and in some exemplary embodiments is between l el4 and l ei 6 atoms/cm3. In the example illustrated in FIG. 3, channel layer 360 is intrinsic binary GaN (i-GaN). Polarization layer 365 and III-N material layer 370 may each also be intrinsic and not intentionally doped with impurities, for example to simplify formation the III-N heterostructure.
Differences in composition within a III-N heterostructure may induce strain within the III-N material layers where lattice constants are not well-matched. Strain levels may be managed through control of material layer composition and thickness so as to avoid film cracking (i.e., relaxation) within a III-N heterostructure. In some exemplary embodiments where III-N material lattice constants are not matched, material layer thicknesses of device 301 are below the critical thickness to avoid strain relaxation. In other exemplary embodiments where the material layer lattice constant remains the same between different material layers, material layer thicknesses need not be so constrained. In some exemplary embodiments, polarization layer 365 has a thickness Tl of at least 30 nm, and
advantageously more than 30 nm. At such thicknesses, both 2D charge carrier sheets 341 and 342 will form whereas at lower thicknesses, polarization layer 365 may be unable to induce 2D charge carrier sheet 342 with sufficient density of states. Thicknesses of 30 nm, or more, can be readily accommodated where lattice mismatch between layers 360, 365 and 370 is not extreme. For example, where III-N channel layer 360 is i-GaN, a polarization layer 365 of binary A1N would be limited to a thickness Tl of only 1 -3 nm, which may not be adequate with respect to forming 2D charge carrier sheet 342. Hence, while binary A1N may be well-suited for a polarization layer of an HFET, other polarization layer alloys having a closer lattice match with GaN may offer advantages in the context of the diode(s) embedded within device 301.
In some exemplary embodiments, III-N material layer 370 has a thickness T2 of at least 3-4 nm to accommodate 2D charge carrier sheet 342. Material layer 370 may be thicker however, particularly to avoid depleting the 2D charge carrier sheet at the P-N
semiconductor junction formed with III-N material layer 378. Thickness T2 may therefore depend on the impurity doping level of III-N material layer 378 with examples ranging from 5 nm to 20 nm and thicknesses of at least 10 nm being advantageous.
In some embodiments, III-N channel layer 360 has a thickness T3 of at least 3-4 nm. Channel layer 360 may be considerably thicker however. For the embodiments exemplified by FIG. 3, III-N channel layer 360 is at least part of a buffer structure upon which material layers 365-378 are grown. For such embodiments, III-N channel layer 360 may be formed over multiple buffer structure layers (not depicted). Hence, thickness T3 may vary widely (e.g., 3-3000 nm) as a function of the layer composition within the III-N heterostructure. Although not depicted in FIG. 3, the illustrated III-N heterostructure may further be disposed over any substrate suitable for hosting III-N crystals. In some embodiments, channel layer 360 is disposed over a SiC substrate. In other embodiments, the substrate is a cubic semiconductor, such as monocrystalline silicon. For such embodiments, template structures may be formed on a cubic substrate surface, such as a (100) surface. III-N crystals may also be grown on other surfaces (e.g., 110, 11 1, miscut or offcut, for example 2-10° toward [1 10] etc.). III-N material layers 360, 365, 370 and 378 may also be over a host substrate material upon which the III-N crystal has been bonded, in which case the host substrate may be crystalline, or not (e.g., glass, polymer, etc.).
The composition of gate electrode 325 may be selected based on the metal- semiconductor workfunction difference relative to III-N channel layer 360 to achieve a desired transistor threshold voltage. In some embodiments, where III-N channel layer 360 is binary GaN, and charge carrier sheet 341 is a 2DEG, gate electrode 325 advantageously includes at least one of Ni, W, Pt, or TiN. As noted above, each of these metals or metallic compounds may be associated with a particular work function (or metal-semiconductor work function difference) that has an impact transistor threshold voltage. Other
metals/metallic compounds known to make ohmic contacts to n-type III-N materials may also be suitable for making a non-rectifying contact to III-N material layer 378. Although gate electrode 325 is illustrated as homogeneous in FIG. 3, a stack or laminate of metals may also be employed. A contact metal 328 then contacts both gate electrode 325 and III-N material layer 378 to serve as both the gate and diode contact metal. The composition of contact metal 328 may be selected based on the metal-semiconductor workfunction difference and surface states of III-N material layer 378 to provide the desired diode contact resistance. For embodiments where III-N material layer 378 has n-type conductivity, contact 328 may include at least one of Ti, Al, or W, for example. Other metals known to make ohmic contacts to n-type III-N materials may also be suitable for making ohmic contact to III-N material layer 378.
For embodiments where source and drain semiconductor 330 has n-type
conductivity, contact metal 140 may be any suitable metal, such as at least one of Ti, Al, or W, for example. Other metals known to make ohmic contacts to n-type III-N materials may be suitable alternatives for making ohmic contact to source and drain semiconductor 330. Gate dielectric 124 may be any high-k (e.g., bulk permittivity of 9, or more) or conventional dielectric material (e.g., bulk permittivity of 3.5-8) known to be suitable for the purpose in III-N FETs. In the illustrated example, gate electrode 325 is further electrically insulated and/or decoupled from polarization layer 365 and III-N material layer 370 by a dielectric sidewall spacer 326. Dielectric sidewall spacer may be any low-k (e.g., bulk permittivity of 3, or less) or conventional dielectric material (e.g., bulk permittivity of 3.5-8) known to be suitable for the purpose of reducing capacitive coupling between gate electrodes and adjacent semiconductors.
As further shown in FIG. 3, an insulative dielectric material 380 is over III-N material layer 370. In this example, dielectric material 380 is over a c-plane (Ga-face) of III- N material layer 370, laterally (e.g., x-dimension) separating III-N material layer 378 from source and drain semiconductor 330. The length of III-N material layer 370 and dielectric material 380 separating III-N material layer 378 from source and drain semiconductor 330, III-N material layer 378 prevents an electrically non-rectifying short between III-N material layer 378 and source and drain semiconductor 330. Dielectric material 380 may be of any composition known to be suitable as a passivation and/or protective encapsulant of III-N devices, such as, but not limited to silicon oxides (SiO), silicon nitrides (SiN), silicon oxynitrides (SiON), silicon carbonitrides (SiCN), or low-k materials (e.g., carbon doped silicon dioxide (SiOC), porous dielectrics, etc.), and metal oxides (e.g., AI2O3).
FIG. 4 is a cross-sectional view of a Group III-N device structure 401 that includes a III-N transistor and integrated III-N diode, in accordance with some alternative
embodiments. III-N device structure 401 shares many of the structural features of device 301 (e.g., FIG. 3), with the shared features having the same reference number. One terminal of the III-N diode however further includes an additional III-N material layer 475, which may be employed for example to tune the forward and reverse current/voltage characteristics of the integrated diode(s). III-N material layer 475 is therefore further illustrated in FIG. 4 as introducing a resistor 453 into the diodic connection between gate electrode 325 and source/drain semiconductor 330. III-N material layer 475 includes impurity dopants to have a conductivity type complementary to that of III-N material layer 378. Hence, for the illustrated embodiment where III-N material layer 378 is N-type, III-N material layer 475 is doped with acceptor impurities to be P-type. While III-N materials can be challenging to dope p-type, acceptor impurity levels of l el7 atoms/cm3 to l el 8 atoms/cm3 are achievable, for example with Mg doping of binary GaN. The presence of p-type (acceptor) dopants in III-N material layer 475 may also advantageously serve as a source of charge carriers for 2D charge carrier sheet 342. The thickness of III-N material layer 475 may vary, for example between 3nm and 10 nm, to achieve the desired diode characteristics. The III-N devices described above may be fabricated using a variety of methods.
FIG. 5 is a flow diagram illustrating methods 501 for forming III-N transistors integrated with III-N diodes, in accordance with some embodiments. Methods 501 begin at operation 505 where a substrate including a crystalline seed layer is received. The substrate received at operation 505 may be any of those described above, for example. At operation 510, a III-N epitaxial growth process is employed to grow a crystalline Ga-polar III-N heterostructure on the substrate seeding surface. The heterostructure grown induces the formation of two, complementary, 2D charge carrier sheets. The epitaxial growth performed at operation 510 may form a continuous crystal over an entire surface of a substrate, or may be limited to islands or mesas occupying only a portion of a substrate surface as controlled through a templating pattern. Alternatively, a Ga-face of a III-N crystal grown with any polarity is exposed at operation 510. For example, a III-N crystal may be first grown with N-polarity over a substrate, and the substrate then removed to expose the Ga-face to subsequent processing.
Methods 501 continue at operation 520 where source and drain semiconductor is formed in a manner that ensures at least one of the source and drain semiconductor is coupled to both of the 2D charge carrier sheets present within the heterostructure. The formation process may further entail forming a recess through layers of the III-N
heterostructure and deposition or growth of semiconductor within the recess. Any patterning techniques may be employed to form the recess and any epitaxial growth technique or deposition process may be employed, for example to form any of the source and drain semiconductor compositions described above.
Methods 501 continue where a gate electrode is formed in a manner that ensures the gate electrode will be coupled (e.g., capacitively) to a first of the 2D charge carrier sheets and also coupled (e.g., with rectification) to a second of the 2D charge carrier sheets. Any deposition process(es) suitable for the chosen gate dielectric and gate electrode may be employed at operation 520. For example, one or more of physical vapor deposition, chemical vapor deposition, or atomic layer deposition may be employed to deposit one or more gate dielectric layer and one or more the metal or metallic compound, such as any of those described elsewhere herein.
Methods 501 continue at operation 540 where one or more interlay er dielectrics (ILDs) and/or interconnect routing levels are formed using any techniques known to be suitable for the purpose. For embodiments where the transistor-diode structures are to be monolithically integrated into a SOC (system-on-chip), any known back-end-of-line (BEOL) processing may be performed at operation 540 to complete the IC. For example, one or more interconnect levels may be employed to form a monolithic protection circuit (e.g., circuit 200) that includes the III-N transistor and diode(s) fabricated by methods 501. Following operation 540, an IC including a III-N transistor with one or more vertically integrated III-N diode is substantially complete and may be singulated and packaged following any suitable techniques.
FIG. 6A-6I are cross-sectional views of Group III-N device 401 evolving as selected operations in the methods 501 are performed, in accordance with some embodiments. In FIG. 6A, III-N heterostructure 615 has been epitaxially grown over a crystalline seeding surface of a substrate (not depicted). III-N heterostructure 615 may have been grown within an opening of amorphous material (not depicted) defining any suitable template structure. In some embodiments the seeding surface is SiC. In other embodiments, the seeding surface is a (100) cubic semiconductor surface is exposed within trenches extending in a <110> direction of the substrate.
Growth of III-N heterostructure 615 may include deposition of a seed layer (not depicted) and further include growth of intrinsic GaN using first epitaxial growth conditions (e.g., a first growth pressure, a first growth temperature, and a first V/III growth precursor ratio) to form III-N channel layer 360. Following an initial growth period, growth conditions may be changed to a second growth pressure, temperature, and/or a second V/III growth precursor ratio to form III-N polarization layer 365. Following this second growth period, growth conditions may be changed back to the first (GaN) growth conditions, or changed to a third growth pressure, temperature, and/or a third V/III growth precursor ratio to form III- N material layer 370. Following this third growth period, growth conditions may be changed to a fourth growth pressure, temperature, and/or a fourth V/III growth precursor ratio to form III-N material layer 475 with in-situ impurity doping (e.g., Mg). Following this fourth growth period, growth conditions may be changed to a fifth growth pressure, temperature, and/or a fifth V/III growth precursor ratio to form III-N material layer 378 with in-situ impurity doping (e.g., Si). These III-N material growths may be by any known technique, such as, but not limited to metal-organic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE), or molecular beam epitaxy (MBE). In some embodiments, elevated temperatures of 600 °C, or more, are employed.
FIG. 6B is a cross-sectional view illustrating patterning of III-N heterostructure 615 for the gate electrode, in accordance with some embodiments. As shown, a lithographic and etch patterning process defines a trench or via pattern including a recess 625 through III-N material layers 378, 475, 370 and into III-N polarization layer 365. The recess is then backfilled with a permanent or sacrificial gate stack. FIG. 6C is a cross-sectional view illustrating formation of a sacrificial "dummy" or "mandrel" gate electrode stack 610, in accordance with some embodiments. The sacrificial gate stack may include one or more dielectric layer (e.g., SiN, SiO, SiON, SiOC, etc.), or semiconductor (e.g., polysilicon), for example. Any deposition process and planarization process known to be suitable for backfilling the recess 625 with the desired sacrificial gate stack may be utilized. FIG. 6D is a cross-sectional view illustrating formation of source and drain recesses 630 on opposite sides of the gate electrode recess. In the illustrated example, an amorphous hardmask (e.g., SiN, SiO, SiON, SiOC, etc.) 616 is deposited over III-N heterostructure 615 prior to forming source and drain recesses 630. Source and drain recesses 630 are then lithographically define and propagated by etch into amorphous hardmask 616 and heterostructure 615, removing a nominal surface thickness (e.g., 5-10 nm) of III-N channel layer 360.
FIG. 6E is a cross-sectional view illustrating formation of source and drain semiconductor 330 epitaxially grown within source and drain recesses 630 to at least partially backfill the recesses. Source and drain semiconductor 330 may be epitaxially grown from the Ga-face of III-N channel layer 360. Amorphous hardmask 616 prevents semiconductor growth over the masked III-N surfaces. In some specific embodiments, recesses 630 are backfilled with InGaN material that is doped with n-type impurities in-situ during epitaxial growth. Alternatively, n-type impurities may be implanted subsequent to growth and then made electrically active, for example with a thermal anneal.
With high temperature semiconductor growth processes complete, a permanent gate electrode may be fabricated. FIG. 6F is a cross-sectional view illustrating replacement of the sacrificial gate stack with a permanent gate stack including gate dielectric 124 and gate electrode 325. The gate replacement process may include selective removal of the sacrificial gate stack, deposition and etching of dielectric sidewall spacer 326, deposition of gate dielectric 124 and deposition of gate electrode 325. Any deposition and planarization techniques known to be suitable for the chosen materials may be employed to implement the gate replacement process.
FIG. 6G is a cross-sectional view illustrating formation of a recess 680 that extends through III-N material layer 378 to sever any contact between source and drain
semiconductor 330 and a remainder of III-N material layer 378. This III-N etch is to electrically separate terminals of the diode and may entail any lithographic patterning and III-N etch process(es) known to be suitable for the chosen composition of III-N material layer 378. Any suitable ILD deposition and planarization process is then employed to form dielectric material 380, backfilling the recess 680 to electrically insulate/isolate III-N material layer 378 from source and drain semiconductor 330. Contact metals 140 and 328 may then be formed concurrently or serially by any suitable backend metallization process (e.g., trench/via etch and metal backfill and polish) to arrive at device structure 401 illustrated in FIG. 61 and as described elsewhere herein.
FIG. 7 illustrates a system 700 in which a mobile computing platform 705 and/or a data server machine 706 employs circuitry including at least one III-N heteroj unction transistor structure including an embedded or integrated diode, for example in accordance with some embodiments described elsewhere herein. The server machine 706 may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a circuitry 750. The mobile computing platform 705 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 705 may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 710, and a battery 715. Whether disposed within the integrated system 710 illustrated in the expanded view
720, or as a stand-alone discrete or packaged multi-chip module within the server machine 706, the circuit includes at least one III-N heteroj unction transistor structure including an embedded or integrated diode, for example in accordance with some embodiments described elsewhere herein. Circuitry 750 may be further attached to a board, a substrate, or an interposer 760 along with a power management integrated circuit (PMIC). Functionally,
PMIC 730 may perform battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to battery 715 and with an output providing a current supply to other functional modules.
Circuitry 750, in some embodiments, includes RF (wireless) integrated circuitry (RFIC) further including a wideband RF (wireless) transmitter and/or receiver (TX/RX including a digital baseband and an analog front end module comprising a power amplifier on a transmit path and a low noise amplifier on a receive path). The RFIC includes at least one III-N heteroj unction transistor structure including an embedded or integrated diode, for example in a over-voltage protection circuit as describe elsewhere herein. The RFIC has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
FIG. 8 is a functional block diagram of a computing device 800, arranged in accordance with at least some implementations of the present disclosure. Computing device 800 may be found inside platform 705 or server machine 706, for example. Device 800 further includes a motherboard 802 hosting a number of components, such as, but not limited to, a processor 804 (e.g., an applications processor), which may further incorporate at least one III-N heteroj unction transistor structure including an embedded or integrated diode, for example in accordance with some embodiments described elsewhere herein. Processor 804 may be physically and/or electrically coupled to motherboard 802. In some examples, processor 804 includes an integrated circuit die packaged within the processor 804. In general, the term "processor" or "microprocessor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory.
In various examples, one or more communication chips 806 may also be physically and/or electrically coupled to the motherboard 802. In further implementations,
communication chips 806 may be part of processor 804. Depending on its applications, computing device 800 may include other components that may or may not be physically and electrically coupled to motherboard 802. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, touchscreen display, touchscreen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like.
Communication chips 806 may enable wireless communications for the transfer of data to and from the computing device 800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips 806 may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device 800 may include a plurality of communication chips 806. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other
implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure.
It will be recognized that the invention is not limited to the embodiments so described, but can be practiced with modification and alteration without departing from the scope of the appended claims. For example the above embodiments may include specific combinations of features as further provided below.
In one or more first examples, a Group Ill-Nitride (III-N) device structure comprise a heterostructure having four or more layers comprising III-N material, wherein a first layer of the heterostructure comprises donor dopants. The structure comprises a gate electrode within a recess that extends through two or more of the layers, wherein the gate electrode is in electrical contact with the first layer. The structure comprises a source and a drain comprising donor dopants, wherein at least one of the source and the drain are spaced apart from the first layer by a second layer of the heterostructure.
In one or more second examples, in any of the first examples the heterostructure includes a third layer separated from the first layer by the second layer and located between the second layer and a fourth layer.
In one or more third examples, for any of the second examples the third layer has a higher Al content than the second and fourth layers.
In one or more fourth examples, for any of the second or third examples the third layer comprises AlxGai-xN, InyA -yN, or InyAli-y-zGazN. In one or more fifth examples, for any of the fourth examples the second and fourth layers comprise binary GaN, and x is between 0.25 and 0.4, y is less than 0.2, or z is less than 0.2.
In one or more sixth examples for any of the second through the fifth examples the second layer thickness is less lOnm and the third layer thickness is at least 30 nm.
In one or more seventh examples for any of the second through the fifth examples the heterostructure has Ga-polarity and a two-dimensional hole gas is present within the second layer, and a two-dimensional electron gas is present within the fourth layer.
In one or more eighth examples for any of the first through the seventh examples the gate electrode is separated from a plurality of the layers of the heterostructure by one or more dielectric layer.
In one or more ninth examples, for any of the second through the eighth examples the heterostructure further comprises a fifth layer between the first material layer and the second material layer, the fifth layer comprising acceptor dopants.
In one or more tenth examples, for any of the first through the ninth examples the source and drain comprise InxGai-xN with x between 0.05 and 0.2, the source and drain have an impurity concentration of at least lei 9 atoms/cm3, and the first III-N material layer is impurity doped to less than lei 9 atoms/cm3.
In one or more eleventh examples, for any of the first through tenth examples the first and the second layers comprise a rectifying heteroj unction.
In one or more twelfth examples, for any of the first through the eleventh examples the structure further comprises one or more non-rectifying metal-semiconductor junction located between the gate electrode and the first III-N material layer.
In one or more thirteenth examples, for any of the first through the twelfth examples the second III-N material layer and at least one of the source and the drain comprise a non- rectifying heteroj unction.
In one or more fourteenth examples, a computer platform includes one or more RF transceiver, and an antenna coupled to the RF transceiver, wherein the RF transceiver has one or more signal input coupled to the gate electrode in any of the first through thirteenth examples.
In one or more fifteenth examples, for any of the fourteenth examples the system includes a processor communicatively coupled to the RF transceiver, and a battery coupled to at least one of the processor and RF transceiver.
In one or more sixteenth examples, a method of forming a Group Ill-Nitride (III-N) device structure comprises forming heterostructure comprising III-N material layers and complementary two-dimensional charge carrier sheets, forming source and drain
semiconductor electrically coupled to both of the two-dimensional charge carrier sheets, and forming a gate electrode electrically coupled to both of the two-dimensional charge carrier sheets.
In one or more seventeenth examples, forming the heterostructure further comprises epitaxially growing four or more layers, the layers including a first layer comprising donor impurities. Forming the gate electrode further comprises forming a first recess in the heterostructure, the recess extending through two or more of the layers, and forming a gate dielectric within the recess. The method comprises depositing gate electrode material over the gate dielectric and in electrical contact with the first layer. Forming the source and drain semiconductor further comprises forming second recesses in the heterostructure on opposite sides of the first recess and spaced apart from the first layer by a second of the layers, the second recesses extending through two or more of the layers, and epitaxially growing a III-N material comprising donor impurities within the second recesses.
In one or more eighteenth examples, for any of the seventeenth examples epitaxially growing the four or more layers further comprises growing a second layer between the first layer and a third layer grown over a Ga-face of a fourth layer.
In one or more nineteenth examples, for any of the seventeenth through eighteenth examples growing the third layer further comprises growing a III-N material with higher Al content than the second and fourth layers.
In one or more twentieth examples, for any of the nineteenth examples epitaxially growing the third layer further comprises growing a layer of AlxGai-xN, InyAh-yN, or InyAli- y-zGazN, and epitaxially growing the second and fourth layers further comprises growing binary GaN.
In one or more twenty-first examples, for any of the twentieth examples growing the second and fourth layers further comprises epitaxially growing binary GaN, and wherein x is between 0.25 and 0.4, y is less than 0.2, or z is less than 0.2.
In one or more twenty-second examples, for any of the twentieth through twenty -first examples epitaxially growing the third layer further comprises growing a layer of AlxGai-xN, InyAli-yN, or InyAli-y-zGazN to a thickness of 30nm, or more.
In one or more twenty -third examples, for any of the eighteenth through twenty - second examples forming the heterostructure further comprises epitaxially growing a fifth layer between the first layer and the second layer, the fifth layer comprising acceptor impurities.
However, the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

CLAIMS What is claimed is:
1. A Group Ill-Nitride (III-N) device structure, comprising:
a heterostructure having four or more layers comprising III-N material, wherein a first layer of the heterostructure comprises donor dopants;
a gate electrode within a recess that extends through two or more of the layers, wherein the gate electrode is in electrical contact with the first layer; and
a source and a drain comprising donor dopants, wherein at least one of the source and the drain are spaced apart from the first layer by a second layer of the heterostructure.
2. The device structure of claim 1, wherein the heterostructure includes a third layer separated from the first layer by the second layer and located between the second layer and a fourth layer.
3. The device structure of claim 2, wherein the third layer has a higher Al content than the second and fourth layers.
4. The device structure of claim 3, wherein the third layer comprises AlxGai-xN, InyAli-yN, or InyAli-y-zGazN.
5. The device structure of claim 4, wherein:
the second and fourth layers comprise binary GaN; and
x is between 0.25 and 0.4, y is less than 0.2, or z is less than 0.2.
6. The device structure of claim 2, wherein the second layer thickness is less lOnm and the third layer thickness is at least 30 nm.
7. The device structure of claim 2, wherein the heterostructure has Ga-polarity and a two- dimensional hole gas is present within the second layer, and a two-dimensional electron gas is present within the fourth layer.
8. The device structure of claim 1, wherein gate electrode is separated from a plurality of the layers of the heterostructure by one or more dielectric layer.
9. The device structure of claim 2, wherein the heterostructure further comprises a fifth layer between the first material layer and the second material layer, the fifth layer comprising acceptor dopants.
10. The device structure of claim 1, wherein
the source and drain comprise InxGai-xN with x between 0.05 and 0.2;
the source and drain have an impurity concentration of at least lei 9 atoms/cm3; and the first III-N material layer is impurity doped to less than lel9 atoms/cm3.
11. The device structure of claim 1, wherein the first and the second layers comprise a
rectifying heterojunction.
12. The device structure of claim 1, further comprising one or more non-rectifying metal- semiconductor junction located between the gate electrode and the first III-N material layer.
13. The device structure of claim 1, the second III-N material layer and at least one of the source and the drain comprise a non-rectifying heterojunction.
14. A computer platform including:
one or more RF transceiver; and
an antenna coupled to the RF transceiver, wherein the RF transceiver has one or more signal input coupled to the gate electrode recited in any one of claims 1-13.
15. The computer platform of claim 14, comprising:
a processor communicatively coupled to the RF transceiver; and
a battery coupled to at least one of the processor and RF transceiver.
16. A method of forming a Group Ill-Nitride (III-N) device structure, the method comprising: forming heterostructure comprising III-N material layers and complementary two- dimensional charge carrier sheets;
forming source and drain semiconductor electrically coupled to both of the two-dimensional charge carrier sheets; and
forming a gate electrode electrically coupled to both of the two-dimensional charge carrier sheets.
17. The method of claim 16, wherein:
forming the heterostructure further comprises epitaxially growing four or more layers, the layers including a first layer comprising donor impurities;
forming the gate electrode further comprises:
forming a first recess in the heterostructure, the recess extending through two or more of the layers;
forming a gate dielectric within the recess; and
depositing gate electrode material over the gate dielectric and in electrical contact with the first layer; and
forming the source and drain semiconductor further comprises:
forming second recesses in the heterostructure on opposite sides of the first recess and spaced apart from the first layer by a second of the layers, the second recesses extending through two or more of the layers; and
epitaxially growing a III-N material comprising donor impurities within the second recesses.
18. The method of claim 17, wherein:
epitaxially growing the four or more layers further comprises growing a second layer
between the first layer and a third layer grown over a Ga-face of a fourth layer.
19. The method of claim 18, wherein growing the third layer further comprises growing a
III-N material with higher Al content than the second and fourth layers.
20. The method of claim 19, wherein epitaxially growing the third layer further comprises growing a layer of AlxGai-xN, InyAli-yN, or InyAli-y-zGazN; and
epitaxially growing the second and fourth layers further comprises growing binary GaN.
21. The method of claim 20, wherein growing the second and fourth layers further comprises epitaxially growing binary GaN; and
wherein x is between 0.25 and 0.4, y is less than 0.2, or z is less than 0.2.
22. The method of claim 21, wherein epitaxially growing the third layer further comprises growing a layer of AlxGai-xN, InyAli-yN, or InyAli-y-zGazN to a thickness of 30nm, or more.
23. The method of claim 18, wherein forming the heterostructure further comprises epitaxially growing a fifth layer between the first layer and the second al layer, the fifth layer comprising acceptor impurities.
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