WO2019000190A1

WO2019000190A1 - Crc and polar code transmission scheme

Info

Publication number: WO2019000190A1
Application number: PCT/CN2017/090091
Authority: WO
Inventors: Keeth Saliya JAYASINGHE; Yu Chen; Jie Chen; Dongyang DU
Original assignee: Nokia Technologies Oy; Alcatel-Lucent Shanghai Bell Co., Ltd.
Priority date: 2017-06-26
Filing date: 2017-06-26
Publication date: 2019-01-03
Also published as: CN110785937B; CN110785937A

Abstract

A method for encoding a sequence of control information bits, the method comprising: generating a first sequence of bits comprising a sequence of predetermined bits for an encoder and a sequence of control information bits; generating a sequence of error detection and/or error correction bits based on the sequence of predetermined bits for the encoder and the sequence of control information bits; and encoding a redistributed sequence comprising the sequence of predetermined bits for the encoder, the sequence of control information bits and the sequence of error detection and/or error correction bits.

Description

[Title established by the ISA under Rule 37.2] CRC AND POLAR CODE TRANSMISSION SCHEME

Polar codes have been chosen to be used for 5G eMBB (enhanced Mobile Broadband) control channels and maybe also for mMTC (massive Machine Type Communications) because it has advantages compared to the other candidate coding schemes. For example it promises low complexity while achieving close to capacity levels of performance.

A CRC construction mechanism has been proposed with J’bits for the purpose of assisting the polar decoding， where 0＜＝J’＜＝Jmax， aiming for Jmax， e.g. in the region of 8 (other values are not precluded) . This mechanism does not preclude the use of the J bits for assisting decoding and any PC-frozen bits are considered to be among the J’bits.

The following are examples：

J bits CRC + J’bits CRC + basic polar；

J bits CRC + J’bits distributed CRC + basic polar；

J bits CRC + J’Parity Check bits + basic polar； (Parity-Check-Polar) ；

J bits CRC + J’Hash sequence + basic polar；

(J + J’) bits CRC + basic polar.

In the proposals mentioned above there are J CRC bits for error detection and J’ (additional) bits which may be CRC， Parity， or Hash bits used for error correction purposes. The J’error correcting bits can be placed in the non-frozen or frozen bit positions such a way that tree pruning happens whenever an info bit and associated CRC/parity/or Hash bit is available. In R1-1703497 “Details of CRC distribution of Polar design” ， Nokia， Alcatel-Lucent Shanghai Bell in in 3GPP TSG RAN WG1 Meeting #88， Athens， Greece， February 2017， a distributed method is proposed for tree pruning by distributing info and CRC bits such a way that it allows CRC checks to occur much earlier than usually happens.

However， we find there are some restrictions in distributing the CRC bits inside the information bits. As each CRC bit is calculated from approximately 1/3 information bits， the furthest forward in the subchannels that the CRC bit can be placed is after 1 to 3 information bits. Furthermore as the unreliable subchannels are generally the front or forward subchannels， any error is more likely in the unreliable subchannels. Thus if the CRC bit is placed on the subchannel too far back， the bit may miss an opportunity to recover the errors because the error has already happened and decoded and output.

There is hereby provided a method for encoding a sequence of control information bits， the method comprising： generating a first sequence of bits comprising a sequence of predetermined bits for an encoder and a sequence of control information bits； generating a sequence of error detection and/or error correction bits based on the sequence of predetermined bits for the encoder and the sequence of control information bits； and encoding a redistributed sequence comprising the sequence of predetermined bits for the encoder， the sequence of control information bits and the sequence of error detection and/or error correction bits.

Generating a first sequence of bits comprising a sequence of predetermined bits for a polar encoder and a sequence of control information bits may comprise concatenating the sequence of predetermined bits and the sequence of control information bits to form the first sequence of bits.

The method may further comprise applying a first permutation mapping to the first sequence of bits to generate a second sequence of bits such that at least one of the sequence of predetermined bits is distributed inside the sequence of information bits.

The method may further comprise generating the first permutation mapping by： defining a minimum number of information bits m_j to be used to generate a j’th error detection and/or error correction bit； and determining a number of predetermined bits used to generate the error detection and/or error correction bits， from a part of an error detection and/or error correction generator start counting the number of the elements from the generator for the associated with the part of the error detection and/or error correction generator equal to 1； where the number of elements is less than or equal to the number of predetermined bits then set the a part of the permutation mapping defined by the number of elements to be a predetermined bit part； where the number of elements is greater than the number of predetermined bits set the number of predetermined bits parts of the permutation mapping out of the number of elements to be selected as predetermined； ensure there are at least the minimum number of information bits left in the part of the permutation mapping； decrease the number of predetermined bits available to generate the error detection and/or error correction bits by the number of predetermined bit parts defined earlier； set the parts of the permutation mapping with elements equal to 1 to predetermined bits until there are a number of minimum number of information bit elements left equal to 1 for the parts of the permutation mapping； repeat for a further part of the permutation mapping.

The method may further comprise generating the first permutation mapping by： defining a minimum number of information bits m_j to be used to generate a j’th error detection and/or error correction bit； determining a number of frozen bits used to generate the error detection and/or error correction bits； from a column j of an error detection and/or error correction generator matrix G start a loop with an index value k， where k ＝ j+1 to n； count the number of the elements from the column j and k of the error detection and/or error correction generator matrix G equal to 1； where the number of elements is less than or equal to the number of frozen bits then set the row defined by the number of elements to be a frozen bit row； where the number of elements is greater than the number of frozen bits set the number of frozen bits rows out of the number of elements to be frozen； ensure there are at least the minimum number of information bits left in the column； decrease the number of frozen bits available to generate the error detection and/or error correction bits by the number of frozen rows defined in this loop； end the loop and set all of the rows of the mapping with elements equal to 1 to frozen until there are m_j elements left equal to 1 for the column； repeat the loop with an index k for the next column j＝j+1.

Generating a sequence of error detection and/or error correction bits based on the sequence of predetermined bits for the encoder and the sequence of control information bits may comprise applying a generator function to the second sequence of bits.

The method may further comprise concatenating the sequence of error detection and/or error correction bits with the second sequence of bits to generate a third sequence of bits.

The method may further comprise： generating an index or sequence number for any predetermined bits within the third sequence of bits； removing any predetermined bits from the third sequence of bits， wherein the index or sequence number is passed to the decoder so to add the predetermined bits based on the stored index or sequence number of the predetermined bits before error detection and/or error correction is applied.

The method may further comprise： applying a second permutation mapping to the third sequence of bits to generate a fourth sequence of bits； and applying a third permutation mapping to the fourth sequence of bits to generate a fifth sequence of bits.

One of the third and fourth permutation mapping may be configured to distribute the at least one of the error detection and/or error correction bits sequence inside the first sequence bits， and the other of the third and fourth permutation mapping may be configured to generate a sequence of bits such that the fifth sequence of bits is suitable for mapping to subchannels for encoding.

The mapping configured to distribute the at least one of the error detection and/or error correction bits sequence inside the first sequence bits function may be configured to perform at least one of： distribute a specific error detection and/or error correction bit to be adjacent to its corresponding information bits； distribute a specific error detection and/or error correction bit to be just in front of the corresponding information bits； distribute a specific error detection and/or error correction bit to be inside of the corresponding information bits； distribute a specific error detection and/or error correction bit to be just after the corresponding information bits， where the corresponding information bits are those used to generate the error detection and/or error correction bit.

The mapping may be configured to map the error detection and/or error correction bits with fewer corresponding information bits before the error detection and/or error correction bits with more corresponding information bits.

The other of the third and fourth permutation mapping configured to generate a sequence of bits such that the fifth sequence of bits is suitable for mapping to subchannels for encoding may comprise permutating the information bits and predetermined bits such that the predetermined bits can be directly mapped to the worst subchannels.

The method may further comprise mapping the fifth sequence of bits to subchannels for encoding， wherein the mapping comprises one of： mapping at least one error detection and/or error correction bit to a subchannel just after a corresponding information bit from which it is generated； mapping at least one error detection and/or error correction bit just before or in the middle of a corresponding information bit from which it is generated； mapping at least one error detection and/or error correction bit and a corresponding information bit to the worst sub-channels； mapping a corresponding information bit onto the worst channels and mapping the error detection and/or error correction bit just before the first corresponding information bit； mapping a corresponding information bit onto the worst channels and mapping the error detection and/or error correction bit just after the last corresponding information bit； and mapping a corresponding information bit onto the worst channels and mapping the error detection and/or error correction bit in the middle of the corresponding information bit.

The error detection and/or error correction bit may comprise a cyclic redundancy check bit.

The encoding may be a polar encoding and the predetermined bits may be frozen bits.

There is also hereby provided an apparatus for encoding a sequence of control information bits， the apparatus comprising： a processor and memory including computer program code， wherein the memory and computer program code are configured to， with the processor， cause the apparatus to： generate a first sequence of bits comprising a sequence of predetermined bits for an encoder and a sequence of control information bits； generate a sequence of error detection and/or error correction bits based on the sequence of predetermined bits for the encoder and the sequence of control information bits； and encode a redistributed sequence comprising the sequence of predetermined bits for the encoder， the sequence of control information bits and the sequence of error detection and/or error correction bits.

The apparatus caused to generate a first sequence of bits comprising a sequence of predetermined bits for a polar encoder and a sequence of control information bits may be further caused to concatenate the sequence of predetermined bits and the sequence of control information bits to form the first sequence of bits.

The apparatus may be further caused to apply a first permutation mapping to the first sequence of bits to generate a second sequence of bits such that at least one of the sequence of predetermined bits is distributed inside the sequence of information bits.

The apparatus may be further caused to generate the first permutation mapping by： defining a minimum number of information bits m_j to be used to generate a j’th error detection and/or error correction bit； and determining a number of predetermined bits used to generate the error detection and/or error correction bits， from a part of an error detection and/or error correction generator start counting the number of the elements from the generator for the associated with the part of the error detection and/or error correction generator equal to 1； where the number of elements is less than or equal to the number of predetermined bits then set the a part of the permutation mapping defined by the number of elements to be a predetermined bit part； where the number of elements is greater than the number of predetermined bits set the number of predetermined bits parts of the permutation mapping out of the number of elements to be selected as predetermined； ensure there are at least the minimum number of information bits left in the part of the permutation mapping； decrease the number of predetermined bits available to generate the error detection and/or error correction bits by the number of predetermined bit parts defined earlier； set the parts of the permutation mapping with elements equal to 1 to predetermined bits until there are a number of minimum number of information bit elements left equal to 1 for the parts of the permutation mapping； repeat for a further part of the permutation mapping.

The apparatus may be further caused to generate the first permutation mapping by： defining a minimum number of information bits m_j to be used to generate a j’th error detection and/or error correction bit； determining a number of frozen bits used to generate the error detection and/or error correction bits； from a column j of an error detection and/or error correction generator matrix G start a loop with an index value k， where k ＝ j+1 to n； count the number of the elements from the column j and k of the error detection and/or error correction generator matrix G equal to 1； where the number of elements is less than or equal to the number of frozen bits then set the row defined by the number of elements to be a frozen bit row； where the number of elements is greater than the number of frozen bits set the number of frozen bits rows out of the number of elements to be frozen； ensure there are at least the minimum number of information bits left in the column； decrease the number of frozen bits available to generate the error detection and/or error correction bits by the number of frozen rows defined in this loop； end the loop and set all of the rows of the mapping with elements equal to 1 to frozen until there are m_j elements left equal to 1 for the column； repeat the loop with an index k for the next column j＝j+1.

The apparatus caused to generate a sequence of error detection and/or error correction bits based on the sequence of predetermined bits for the encoder and the sequence of control information bits may be caused to apply a generator function to the second sequence of bits.

The apparatus may be further caused to concatenate the sequence of error detection and/or error correction bits with the second sequence of bits to generate a third sequence of bits.

The apparatus may be further caused to： generate an index or sequence number for any predetermined bits within the third sequence of bits； remove any predetermined bits from the third sequence of bits， wherein the index or sequence number is passed to the decoder so to add the predetermined bits based on the stored index or sequence number of the predetermined bits before error detection and/or error correction is applied.

The apparatus may be further caused to： apply a second permutation mapping to the third sequence of bits to generate a fourth sequence of bits； and apply a third permutation mapping to the fourth sequence of bits to generate a fifth sequence of bits.

The apparatus may be further caused to map the fifth sequence of bits to subchannels for encoding， wherein the map causes the apparatus to perform one of： map at least one error detection and/or error correction bit to a subchannel just after a corresponding information bit from which it is generated； map at least one error detection and/or error correction bit just before or in the middle of a corresponding information bit from which it is generated； map at least one error detection and/or error correction bit and a corresponding information bit to the worst sub-channels； map a corresponding information bit onto the worst channels and mapping the error detection and/or error correction bit just before the first corresponding information bit； map a corresponding information bit onto the worst channels and mapping the error detection and/or error correction bit just after the last corresponding information bit； and map a corresponding information bit onto the worst channels and mapping the error detection and/or error correction bit in the middle of the corresponding information bit.

There is also hereby provided an apparatus for encoding a sequence of control information bits， the apparatus comprising： means for generating a first sequence of bits comprising a sequence of predetermined bits for an encoder and a sequence of control information bits； means for generating a sequence of error detection and/or error correction bits based on the sequence of predetermined bits for the encoder and the sequence of control information bits； and means for encoding a redistributed sequence comprising the sequence of predetermined bits for the encoder， the sequence of control information bits and the sequence of error detection and/or error correction bits.

The means for generating a first sequence of bits comprising a sequence of predetermined bits for a polar encoder and a sequence of control information bits may comprise means for concatenating the sequence of predetermined bits and the sequence of control information bits to form the first sequence of bits.

The apparatus may further comprise means for applying a first permutation mapping to the first sequence of bits to generate a second sequence of bits such that at least one of the sequence of predetermined bits is distributed inside the sequence of information bits.

The apparatus may further comprise means for generating the first permutation mapping by： defining a minimum number of information bits m_j to be used to generate a j’th error detection and/or error correction bit； and determining a number of predetermined bits used to generate the error detection and/or error correction bits， from a part of an error detection and/or error correction generator start counting the number of the elements from the generator for the associated with the part of the error detection and/or error correction generator equal to 1； where the number of elements is less than or equal to the number of predetermined bits then set the a part of the permutation mapping defined by the number of elements to be a predetermined bit part； where the number of elements is greater than the number of predetermined bits set the number of predetermined bits parts of the permutation mapping out of the number of elements to be selected as predetermined； ensure there are at least the minimum number of information bits left in the part of the permutation mapping； decrease the number of predetermined bits available to generate the error detection and/or error correction bits by the number of predetermined bit parts defined earlier； set the parts of the permutation mapping with elements equal to 1 to predetermined bits until there are a number of minimum number of information bit elements left equal to 1 for the parts of the permutation mapping； repeat for a further part of the permutation mapping.

The apparatus may further comprise means for generating the first permutation mapping by： defining a minimum number of information bits m_j to be used to generate a j’th error detection and/or error correction bit； determining a number of frozen bits used to generate the error detection and/or error correction bits； from a column j of an error detection and/or error correction generator matrix G start a loop with an index value k， where k ＝ j+1 to n； count the number of the elements from the column j and k of the error detection and/or error correction generator matrix G equal to 1； where the number of elements is less than or equal to the number of frozen bits then set the row defined by the number of elements to be a frozen bit row； where the number of elements is greater than the number of frozen bits set the number of frozen bits rows out of the number of elements to be frozen； ensure there are at least the minimum number of information bits left in the column； decrease the number of frozen bits available to generate the error detection and/or error correction bits by the number of frozen rows defined in this loop； end the loop and set all of the rows of the mapping with elements equal to 1 to frozen until there are m_j elements left equal to 1 for the column； repeat the loop with an index k for the next column j＝j+1.

The means for generating a sequence of error detection and/or error correction bits based on the sequence of predetermined bits for the encoder and the sequence of control information bits may comprise means for applying a generator function to the second sequence of bits.

The apparatus may further comprise means for concatenating the sequence of error detection and/or error correction bits with the second sequence of bits to generate a third sequence of bits.

The apparatus may further comprise： means for generating an index or sequence number for any predetermined bits within the third sequence of bits； means for removing any predetermined bits from the third sequence of bits， wherein the index or sequence number is passed to the decoder so to add the predetermined bits based on the stored index or sequence number of the predetermined bits before error detection and/or error correction is applied.

The apparatus may further comprise： means for applying a second permutation mapping to the third sequence of bits to generate a fourth sequence of bits； and means for applying a third permutation mapping to the fourth sequence of bits to generate a fifth sequence of bits.

The means for mapping configured to distribute the at least one of the error detection and/or error correction bits sequence inside the first sequence bits function may be configured to perform at least one of： distribute a specific error detection and/or error correction bit to be adjacent to its corresponding information bits； distribute a specific error detection and/or error correction bit to be just in front of the corresponding information bits； distribute a specific error detection and/or error correction bit to be inside of the corresponding information bits； distribute a specific error detection and/or error correction bit to be just after the corresponding information bits， where the corresponding information bits are those used to generate the error detection and/or error correction bit.

The means for mapping may be configured to map the error detection and/or error correction bits with fewer corresponding information bits before the error detection and/or error correction bits with more corresponding information bits.

The apparatus may further comprise means for mapping the fifth sequence of bits to subchannels for encoding， wherein the mapping comprises one of： mapping at least one error detection and/or error correction bit to a subchannel just after a corresponding information bit from which it is generated； mapping at least one error detection and/or error correction bit just before or in the middle of a corresponding information bit from which it is generated； mapping at least one error detection and/or error correction bit and a corresponding information bit to the worst sub-channels； mapping a corresponding information bit onto the worst channels and mapping the error detection and/or error correction bit just before the first corresponding information bit； mapping a corresponding information bit onto the worst channels and mapping the error detection and/or error correction bit just after the last corresponding information bit； and mapping a corresponding information bit onto the worst channels and mapping the error detection and/or error correction bit in the middle of the corresponding information bit.

There is also hereby provided a computer program product comprising program code means which when loaded into a computer controls the computer to perform the method steps described herein.

Examples of techniques according to embodiments of the invention are described hereunder in detail， by way of example only， with reference to the accompanying drawings， in which：

Figure 1 illustrates one example of an environment in which embodiments of the present invention may be implemented；

Figure 2 illustrates one example of apparatus for use at the UEs of Figure1；

Figure 3 illustrates one example of apparatus for use at the eNB of Figure 1；

Figure 4 illustrates an example encoder for use in the UEs and eNB of Figures 1 to 3 according to some embodiments；

Figure 5 is a flow diagram of the operation of the encoder as shown in Figure 4 according to some embodiments；

Figure 6 is a flow diagram of the operation of generating the F1 mapping as shown in Figure 5 according to some embodiments； and

Figure 7 is a graph showing BLER against Es/No to show the effect of the encoder shown in Figure 5 according to some embodiments.

Techniques according to embodiments of the present invention are described in detail below， by way of example only.

The concepts as discussed in further detail discuss designs for a flexible CRC distribution scheme to enable the CRC bit to have a higher flexibility to be mapped onto the subchannels and hence can be used to assist the Polar decoding earlier on in the process.

The distribution as disclosed herein can also in some embodiments be used with respect to parity or hash bits， where parity or hash bits are distributed such a way that they can decode together with the information bits and be used to enable the early termination.

Figure 1 schematically shows an example of four user equipments (UEs) (for example， high complexity devices such as smartphones etc.， low complexity devices such as Machine Type Communications (MTC) devices or any other type of wireless communication device) 8 located within the coverage area of a cell operated by a wireless network infrastructure node， which is generally referred to below as a base station (BS) . Figure 1 only shows a small number of base stations， but a radio access network typically comprises a large number of base stations each operating one or more cells.

Each BS 2 of a radio access network is typically connected to one or more core network entities and/or a mobile management entity etc.， but these other entities are omitted from Figure 1 for conciseness.

Figure 2 shows a schematic view of an example of apparatus for each UE 8. The UE 8 may be used for various tasks such as making and receiving phone calls， receiving and sending data from and to a data network， and experiencing， for example， multimedia or other content. The UE 8 may be any device at least capable of both recovering data/information from radio transmissions made by the BS 2， and making radio transmissions from which data/information is recoverable by the BS 2. Non-limiting examples of user equipment (UE) 8 include smartphones， tablets， personal computers， and devices without any user interface， such as devices that are designed for machine type communications (MTC) .

With reference to Figure 2， a baseband processor 34， operating in accordance with program code stored at memory 32， controls the generation and transmission of radio signals via radio-frequency (RF) front end 36 and antenna 38. The RF front end 36 may include an analogue transceiver， filters， a duplexer， and antenna switch. Also， the combination of antenna 38， RF front end 36 and baseband processor 34 recovers data/information from radio signals reaching UE 8 from e.g. BS 2. The UE 8 may also comprise an application processor (not shown) that generates user data for transmission via radio signals， and processes user data recovered from radio signals by baseband processor 34 and stored at memory 32.

The application processor and the baseband processor 34 may be implemented as separate chips or combined into a single chip. The memory 32 may be implemented as one or more chips. The memory 32 may include both read-only memory and random-access memory. The above elements may be provided on one or more circuit boards.

The UE may include additional other elements not shown in Figure 2. For example， the UE 8 may include a user interface such as a key pad， voice command recognition device， touch sensitive screen or pad， combinations thereof or the like， via which a user may control operation of the UE 8. The UE 8 may also include a display， a speaker and a microphone. Furthermore， the UE 8 may comprise appropriate connectors (either wired or wireless) to other devices and/or for connecting external accessories (e.g. hands-free equipment) thereto.

Figure 3 shows an example of apparatus for use at the BS 2 of Figure 1. A baseband processor 20， operating in accordance with program code stored at memory 22， (a) controls the generation and transmission of radio signals via the combination of RF front end 24 and antenna 26； and (b) recovers control information/data from radio transmissions reaching the BS from e.g. UEs 8. The RF front end may include an analogue transceiver， filters， a duplexer， and antenna switch. Both the processor 20 and the memory 22 may be implemented as one or more chips. The memory 22 may include both read-only memory and random-access memory. The above elements may be provided on one or more circuit boards. The apparatus also comprises an interface 28 for transferring data to and from one or more other entities such as e.g. core network entities， mobile management entities， and other base stations in the same access network.

It should be appreciated that the apparatus shown in each of figures 2 and 3 described above may comprise further elements which are not directly involved with the embodiments of the invention described hereafter.

As discussed previously the CRC bits may be distributed between the information bits before the polar coder is applied. For example where：

a0， a1， ...， ak denotes the information bits (k+1 bits) to be transmitted.

After CRC encoding the CRC bits， c， are added after the above bit sequence to create a bit sequence：

a0， a1， ...， ak， c0， c1， ...， cn

where there are n+1 CRC bits.

A permutation operation is then performed on the bits so that the CRC bits can be shifted between the information bits. The operation is denoted by a function F， and the output of the function F may be shown as：

F (a0， a1， ...， ak， c0， c1， ...， cn)

During polar encoding， the information bits are mapped onto the selected subchannels， i.e. as free bits， and the unselected subchannels are used for frozen bits.

The concept as discussed in the embodiments shown hereafter with respect to figures 4 to X is one wherein the CRC bits are generated from part/all of the information bits and part/all of the frozen bits.

For example figure 4 shows an example system suitable for implementing some embodiments. The system comprises a first (F1) mapper 401. The F1 mapper 401 is configured to receive the information k+1 bits

a0， a1， ...， ak，

and furthermore receive the m+1 frozen bits for the polar encoder

f0， f1， ...， fm.

Thus a sequence which is input to the F1 mapper 401 is the combination

f0， f1， ...，fm， a0， a1， ...， ak.

The F1 mapper 401 may then apply the F1 permutation mapping to the sequence to generate

F1 (f0， f1， ...， fm， a0， a1， ...， ak)

This is then passed to a CRC generator 402. The CRC generator 402 may then generate a CRC sequence c0， c1， ...， cn and append or concatenate this to the sequence to form

F1 (f0， f1， ...， fm， a0， a1， ...， ak) ， c0， c1， ...， cn.

This sequence is then passed to a second (F) mapper 403. The F mapper 403 is configured to apply a permutation F to the concatenated sequence to distribute the CRC bits inside the information bits and generate

F (F1 (f0， f1， ...， fro， a0， a1， ...， ak) ， c0， c1， ...， cn)

This sequence is then passed to a third (F2) mapper 404. The F2 mapper 404 is configured to process the sequence to generate

F2 (F (F1 (f0， f1， ...， fm， a0， a1， ...， ak) ， c0， c1， ...， cn) )

This sequence may then be passed to a subchannel mapper 405. The subchannel mapper 404 may be configured to map the sequence onto the subchannels for polar encoding.

The output of the subchannel mapper 405 may be passed to the polar encoder 406. The polar encoder 406 is configured to apply a polar encoding (and optionally a rate matching) to the output of the subchannel mapper 405 to generate the polar encoded information bits with CRC bits distributed within the information bits.

In some embodiments the F2 mapper 404 may be placed before the F mapper 404， in other words the F2 processing may be applied before the F processing.

With respect to the receiver the operations are then performed in the reverse order from polar decoding， inverse F2 operations， inverse F mapping， inverse F1 mapping etc.

With respect to figure 5 the operations performed by the system shown in figure 4 is shown.

Thus for example the first operation is one of receiving/determining and then concatenating the information bits and the frozen bits as shown in figure 5 by step 501.

The following operation is one of applying the permutation F1 to the concatenated sequence as shown in figure 5 by step 503.

The next operation if one of generating the CRC encoding bits as shown in figure 5 by step 505.

Having generated the CRC encoding bits they are then concatenated to the F1 operated sequence as shown in figure 5 by step 507.

The next operation is applying a permutation F to the combined sequence including the CRC encoding bits to distribute the CRC bits between the information bits as shown in figure 5 by step 509.

Having applied the permutation to distribute the CRC bits between the information bits the following operation is one applying a further F2 permutation as shown in figure 5 by step 511. (In some embodiments the step 511 may occur before the step 509)

Having applied the F2 permutation the bit sequence may then be mapped to the subchannels as shown in figure 5 by step 513.

The mapped subchannel bit sequence may then be polar encoded (and optionally rate matched) as shown in figure 5 by step 515.

With respect to Figure 6 a flow diagram showing the generation of the permutation of the frozen bits and information bits， the F1 mapping applied by the F1 mapper 401 is shown.

In some embodiments where G is the CRC generator matrix and the frozen bits are set to zero (though any predefined value is feasible) . Furthermore in this example there are n CRC bits to be generated.

Firstly the minimum number of information bits to be used to generate each CRC bit by m_jfor j^th CRC bit is defined as shown in figure 6 by step 601.

Secondly a value Ze is defined for a number of frozen bits used to generate the CRC bits as shown in figure 6 by step 603.

Thirdly for a column of G defined as the column j a loop k is initialized

For k ＝ j+1 to n

For the matrix G， a value R_jk is defined as the number of the elements equal ＝1 for both column j and k.

If R_jk ＜＝ Ze then the R_jk row is set to frozen (in other words transmit the frozen bits on this row) .

If R_jk＞Ze， set Ze rows out of R_jk to frozen and end both the k and the j loops.

Meanwhile， ensure there are at least m_j elements left equal to 1.

Then set Ze ＝ Ze-F_k， where F_k is finally the number of frozen rows for loop k and end the k loop so that the k loop is finished as shown in figure 6 by step 605.

Set all the rows with elements 1 to frozen until there are m_j ones left for column j as shown in figure 6 by step 607.

Furthermore set j ＝ j+1 as shown in figure 6 step 609 and then loop back to step 605 to repeat for the next column (j+1) .

In some embodiments where there are K information bits and the polar encoding mother code is N the number of frozen bits used in CRC generation can be around K/3 so that these frozen bits can be used to reduce the number of related information bits to generate a specific CRC bit to a very small number.

To reduce the number of related information bits for two CRC bits， the number of frozen bits needed is approximately K/3 + K/3-X， where X is the number of rows of G for the two CRC bits that have a common value 1. The number of frozen bits needed for more CRC bits can be estimated similarly.

In some further embodiments each time all the frozen bits are used to generate the CRC bits.

In some embodiments the F2 mapper 404 is configured such that the information bits and frozen bits are permutated again so that the frozen bits can be directly mapped to the worst subchannels. Thus in such embodiments where there is a one to one mapping based on the index of the frozen bits and subchannels， and the information bits and CRC bits are mapped onto the selected subchannels that are more reliable.

In these embodiments at the receiver side， after the Polar decoding， the reverse or inverse permutation is performed before sending the output into CRC detector.

In some embodiments the F2 mapper 404 is configured to store the index or sequence number of the frozen bits. The frozen bits are then removed from the output of the CRC encoder. The information bits and CRC bits are mapped to the polar code subchannels as usual. At the receiver side in such embodiments， the frozen bits are added based on the stored index or sequence number of the frozen bits to restore them before sending them to the CRC detector.

In one embodiment， a CRC bit is transmitted on the subchannels just after its corresponding information bits from which it is generated， without consideration of the reliability of the subchannels. It is also possible to transmit this CRC bit just before or in the middle of its corresponding information bits.

With respect to the subchannel mapper 405 in some embodiments， subchannel reliability is considered in the transmission of the CRC and information bits. A CRC bit and the corresponding information bits are mapped to the worst subchannels of the polar coder. In some further embodiments， the corresponding information bits are mapped onto the worst channels and the CRC bit is transmitted just before the first corresponding information bit， or just after the last corresponding information bit， or in the middle of the corresponding information bit.

In some embodiments the number m_j for a specific CRC bit j， can be configured as the same value for all the CRC bits. This value may be predefined， e.g. 3 or 4 or 5. This value may also be defined related to the total number of information bits to be encoded by CRC. In some other embodiments， set m_j ＞＝ m_i， for j＞l， and for example m_j＝ j + v， where v is a predefined value， e.g. 1 or 2 or 3 or 4 or 5. In some other embodiments， the value is configured based on the list size. For a larger list size， a larger value is defined. For a smaller list size， a smaller value is defined.

With respect to the F mapper 403 in some embodiments the function F is similar to the known methods for distributing the CRC bits between the information bits. The function F is thus configured to distribute a specific CRC bit to be adjacent to its corresponding information bits， just in front of those corresponding information bits， inside， or just after the corresponding information bits， where the corresponding information bits are those used to generate the CRC bit.

In some embodiments the function F may involve another kind of permutation， where the CRC bits with fewer corresponding information bits are processed first and followed by the CRC bits with more corresponding information bits.

In such embodiments the Polar decoding process， when a CRC bit and all its corresponding information bits are decoded， the CRC may be configured to perform a check on each decoding path. The paths that do not pass the CRC check will be given a penalty (for example any real number) . In some embodiments， the penalty value is an infinite value； in other embodiments， the penalty is 15 or 5 or 3.

The above mentioned operations and parameters may in some embodiments be defined in the communications protocol specification and thus known by both the transmitter and the receiver. In some embodiments the operations and parameters may be signaled， e.g. by using RRC signaling so that they are known by the transmitter and the receiver.

An example of the implementation of the embodiments may define that there are 8 information bits， and 4 CRC bits to be generated. The polar code mother code may output 16 bits so there are 4 frozen bits for manipulation.

The bit sequence to be processed by CRC encoder including frozen bits may be：

[f0 f1 f2 f3 a0 a1 a2 a3 a4 a5 a6 a7]

The CRC generator matrix G for the 12 bits may be：

The parameter m_j， where j ＝ 1： 12， may be configured to be j+1.

A suitable configuration of the frozen rows are as follows， where 1 means the corresponding row is frozen. So row 5， 6， 11 and 12 are frozen.

0 0 0 0 1 1 0 0 0 0 1 1

Then function F1 may be defined as：

mapping [f0 f1 f2 f3 a0 a1 a2 a3 a4 a5 a6 a7]

to [a0 a1 a2 a3 f0 f1 a4 a5 a6 a7 f2 f3]

The output of the CRC encoding may be：

[a0 a1 a2 a3 f0 ft a4 a5 a6 a7 f2 f3 c0 c1 c2 c3]

The CRC bit distribution may be result in：

[a0 a1 c0 a2 a3 c1 f0 f1 a4 a5 c2 a6 a7 c3 f2 f3]

In the code construction in this example， the subchanneis index used for frozen bits are [1 2 3 5] ， where the indexing starts from 1.

The F2 operation may then reshuffle the above bit sequence so that it can be mapped onto the Polar subchannels：

[f0 f1 f2 a0 f3 a1 c0 a2 a3 c1 a4 a5 c2 a6 a7 c3]

Then the above bit sequence is mapped onto the subchannels and which are encoded by Polar encoder.

In the following table a study of the false alarm rate (FAR) of the proposed scheme targeting the polar code (N， K+C) ， where we have mother code size of N， and K information bits to be transmitted and C CRC bits to be generated. The number of error blocks in the simulation is 10000000. From the simulation results in the table it can be seen that with frozen bits taken into account into CRC generation， the performance is similar or even better than the conventional CRC generation scheme. In other words the proposed system results in fewer FAR occurrences.

(N， K+C)	w/o frozen bits	With frozen bits
(64， 24+8)	39025	39143
(64， 16+16)	142	147
(1 28， 48+16)	151	150
(128， 27+16)	150	138
(256， 68+16)	149	138

Furthermore with respect to figure 7 a graph of performance gain is shown for an example transmission scheme of 24 bit information block plus 8 bit CRC. At least 4 information bits are used for each CRC bit generation. The penalty is set to 5dB and there are 2 bits are used for assisting the Polar decoding. The same SCL decoding algorithm is used for both the conventional decoding solution and the proposed solution. It is observed that the proposed scheme 701 can give about 0.4dB gain over the conventional scheme 703. As the information block size is quite small， it is believed that more gain would be observed for larger information blocks. Also the mapping of the CRC bits and information bits does not consider the reliability which when considered achieves a higher performance gain.

Appropriately adapted computer program code product may be used for implementing the embodiments， when loaded to a computer. The program code product for providing the operation may be stored on and provided by means of a carrier medium such as a carrier disc， card or tape. A possibility is to download the program code product via a data network. Implementation may be provided with appropriate software in a server.

Embodiments of the invention may be practiced in various components such as integrated circuit modules. The design of integrated circuits is by and large a highly automated process. Complex and powerful software tools are available for converting a logic level design into a semiconductor circuit design ready to be etched and formed on a semiconductor substrate.

Programs， such as those provided by Synopsys， Inc. of Mountain View， California and Cadence Design， of San Jose， California automatically route conductors and locate components on a semiconductor chip using well established rules of design as well as libraries of pre stored design modules. Once the design for a semiconductor circuit has been completed， the resultant design， in a standardized electronic format (e.g.， Opus， GDSII， or the like) may be transmitted to a semiconductor fabrication facility or ″fab″ for fabrication.

In addition to the modifications explicitly mentioned above， it will be evident to a person skilled in the art that various other modifications of the described embodiment may be made within the scope of the invention.

Claims

A method for encoding a sequence of control information bits， the method comprising：

generating a first sequence of bits comprising a sequence of predetermined bits for an encoder and a sequence of control information bits；

generating a sequence of error detection and/or error correction bits based on the sequence of predetermined bits for the encoder and the sequence of control information bits； and

encoding a redistributed sequence comprising the sequence of predetermined bits for the encoder， the sequence of control information bits and the sequence of error detection and/or error correction bits.
The method as claimed in claim 1， wherein generating a first sequence of bits comprising a sequence of predetermined bits for a polar encoder and a sequence of control information bits comprises concatenating the sequence of predetermined bits and the sequence of control information bits to form the first sequence of bits.
The method as claimed in any of claims 1 and 2， further comprising applying a first permutation mapping to the first sequence of bits to generate a second sequence of bits such that at least one of the sequence of predetermined bits is distributed inside the sequence of information bits.
The method as claimed in claim 3， further comprising generating the first permutation mapping by：

defining a minimum number of information bits m_j to be used to generate a j’th error detection and/or error correction bit；

determine a number of predetermined bits used to generate the error detection and/or error correction bits.

from a part of an error detection and/or error correction generator start， counting the number of the elements from the generator for the associated with the part of the error detection and/or error correction generator equal to 1；

where the number of elements is less than or equal to the number of predetermined bits then set the a part of the permutation mapping defined by the number of elements to be a predetermined bit part；

where the number of elements is greater than the number of predetermined bits set the number of predetermined bits parts of the permutation mapping out of the number of elements to be selected as predetermined；

ensure there are at least the minimum number of information bits left in the part of the permutation mapping；

decrease the number of predetermined bits available to generate the error detection and/or error correction bits by the number of predetermined bit parts defined earlier；

set the parts of the permutation mapping with elements equal to 1 to predetermined bits until there are a number of minimum number of information bit elements left equal to 1 for the parts of the permutation mapping；

repeat for a further part of the permutation mapping.
The method as claimed in claim 4 wherein generating a sequence of error detection and/or error correction bits based on the sequence of predetermined bits for the encoder and the sequence of control information bits comprises applying a generator function to the second sequence of bits.
The method as claimed in claim 5， further comprising concatenating the sequence of error detection and/or error correction bits with the second sequence of bits to generate a third sequence of bits.
The method as claimed in claim 6， further comprising：

generating an index or sequence number for any predetermined bits within the third sequence of bits；

removing any predetermined bits from the third sequence of bits， wherein the index or sequence number is passed to the decoder so to add the predetermined bits based on the stored index or sequence number of the predetermined bits before error detection and/or error correction is applied.
The method as claimed in any of claims 6 and 7， further comprising：

applying a second permutation mapping to the third sequence of bits to generate a fourth sequence of bits； and

applying a third permutation mapping to the fourth sequence of bits to generate a fifth sequence of bits.
The method as claimed in claim 8， wherein one of the third and fourth permutation mapping is configured to distribute the at least one of the error detection and/or error correction bits sequence inside the first sequence bits， and the other of the third and fourth permutation mapping is configured to generate a sequence of bits such that the fifth sequence of bits is suitable for mapping to subchannels for encoding.
The method as claimed in claim 9， wherein the mapping configured to distribute the at least one of the error detection and/or error correction bits sequence inside the first sequence bits function is configured to perform at least one of：

distribute a specific error detection and/or error correction bit to be adjacent to its corresponding information bits；

distribute a specific error detection and/or error correction bit to be just in front of the corresponding information bits；

distribute a specific error detection and/or error correction bit to be inside of the corresponding information bits；

distribute a specific error detection and/or error correction bit to be just after the corresponding information bits， where the corresponding information bits are those used to generate the error detection and/or error correction bit.
The method as claimed in claim 9， wherein the mapping is configured to map the error detection and/or error correction bits with fewer corresponding information bits before the error detection and/or error correction bits with more corresponding information bits.
The method as claimed in any of claims 9 to 11， wherein the other of the third and fourth permutation mapping configured to generate a sequence of bits such that the fifth sequence of bits is suitable for mapping to subchannels for encoding is configured to permutate the information bits and predetermined bits such that the predetermined bits can be directly mapped to the worst subchannels.
The method as claimed in any of claims 6 to 12， further comprising mapping the fifth sequence of bits to subchannels for encoding， wherein the mapping comprises one of：

mapping at least one error detection and/or error correction bit to a subchannel just after a corresponding information bit from which it is generated；

mapping at least one error detection and/or error correction bit just before or in the middle of a corresponding information bit from which it is generated；

mapping at least one error detection and/or error correction bit and a corresponding information bit to the worst sub-channels；

mapping a corresponding information bit onto the worst channels and mapping the error detection and/or error correction bit just before the first corresponding information bit；

mapping a corresponding information bit onto the worst channels and mapping the error detection and/or error correction bit just after the last corresponding information bit； and

mapping a corresponding information bit onto the worst channels and mapping the error detection and/or error correction bit in the middle of the corresponding information bit.
The method as claimed in any of claims 1 to 13， wherein the error detection and/or error correction bit comprises a cyclic redundancy check bit.
The method as claimed in any of claims 1 to 14， wherein the encoding is a polar encoding and the predetermined bits are frozen bits.
An apparatus for encoding a sequence of control information bits， the apparatus comprising： a processor and memory including computer program code， wherein the memory and computer program code are configured to， with the processor， cause the apparatus to：

generate a first sequence of bits comprising a sequence of predetermined bits for an encoder and a sequence of control information bits；

generate a sequence of error detection and/or error correction bits based on the sequence of predetermined bits for the encoder and the sequence of control information bits； and

encode a redistributed sequence comprising the sequence of predetermined bits for the encoder， the sequence of control information bits and the sequence of error detection and/or error correction bits.
An apparatus for encoding a sequence of control information bits， the apparatus comprising：

means for generating a first sequence of bits comprising a sequence of predetermined bits for an encoder and a sequence of control information bits；

means for generating a sequence of error detection and/or error correction bits based on the sequence of predetermined bits for the encoder and the sequence of control information bits； and

means for encoding a redistributed sequence comprising the sequence of predetermined bits for the encoder， the sequence of control information bits and the sequence of error detection and/or error correction bits.