WO2018162746A1

WO2018162746A1 - Power amplifier with stepwise envelope tracking and adaptive load

Info

Publication number: WO2018162746A1
Application number: PCT/EP2018/055972
Authority: WO
Inventors: Pascal PIERRE-CHARLES-FELIX; Vivien KIMON; Hervé GUÉGNAUD; Vikas Vinayak
Original assignee: Acco
Priority date: 2017-03-10
Filing date: 2018-03-09
Publication date: 2018-09-13

Abstract

Circuity for improving linearity and efficiency in mobile device power amplification is provided. The circuitry provides multi-level envelope tracking to divide the input power range of the RF input signal into several discrete steps and to control the supply voltage to the power amplifier accordingly. The circuitry also provides multi- level gate control to add a bias voltage to the RF input signal at each stage of the power amplifier to correct for phase and gain distortions. The circuitry further provides an adaptive load on the power amplifier by measuring the resistive and imaginary parts of the load at the output of the power stage of the power amplifier and adjusting an output matching network that follows the power stage.

Description

Power Amplifier with Stepwise Envelope Tracking and Adaptive Load

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 62/470,031 filed on March 10, 2017 and entitled "Efficiency and Linearization

Improvement with Self Controlled Synchronized Envelope Tracking and Parametric Modification" and also claims priority to U.S. Provisional Patent Application No.

62/469,669 also filed on March 10, 2017 and entitled "Efficiency and Power

Improvement with Adaptive Load Between the PA and the Filtering Function," both of which are incorporated herein by reference.

BACKGROUND

Field of Invention

[0002] The present invention relates generally to mobile communication devices and more particularly to improving the fidelity and efficiency of the power amplifiers therein. Related Art

[0003] Modern mobile devices such as smartphones and tablets enable wireless communications by generating RF signals that are sufficiently powerful to reach other communication devices and equipment. The rate at which information can be coded onto and decoded from the RF signals depends in part upon the fidelity with which the RF signals are generated and amplified. The RF power amplifier handles the largest amount of signal power in the entire wireless communication device, and typically larger signal powers result in greater deviations from fidelity due to distortion. Deviation from fidelity

1 is measured by linearity, in the form of signal measurements such as ACLR (Adjacent Channel Leakage Ratio and Error Vector) and EVM (Error Vector Magnitude). The more linear the response of the RF power amplifier, the less the distortion, and the greater the information rate that can be transmitted.

[0004] The linearity of an RF power amplifier can most easily be increased by increasing its saturated power level. However, this increases the cost and size of the mobile device, and reduces its efficiency. Efficiency is particularly important for mobile devices with limited battery capacity. Both linearity and efficiency are simultaneously desired in an RF power amplifier, however optimization of one at the expense of the other has been the traditional trade-off in RF circuit design.

[0005] Envelope tracking is an example of a technique that has been used to dynamically increase the saturated power of power amplifiers. Envelope tracking is implemented by taking a signal that represents, as closely as possible, the changing RF power requirement, and using that signal to modulate the supply voltage delivered to the power amplifier. Envelope tracking increases the power handling capability of power amplifiers in response to the need to transmit increased RF power. Efficiency is improved because saturated power is increased only when it is required.

[0006] FIG. 1 is a schematic representation of components of a mobile device configured to implement envelope tracking. The components include a baseband chipset 100 in communication with a tracking chip 105 including an envelope detector and both in communication with an RF power amplifier 110. More specifically, the baseband chipset 100 includes a baseband signal generator 115 and an RF signal generator 120 that produce a combined signal comprising a varying RF signal encoding information on top

2 of a baseband signal. This combined signal is the RF input to the power amplifier 110. Baseband chipset 100 also includes a Digital Pre-Distortion (DPD) bloc which is employed in conventional envelope tracking.

[0007] The baseband chipset 100 also includes an RF envelope detector 125 that produces an envelope signal that tracks a time-average of the power level. This signal is used to vary the instantaneous supply voltage to the power amplifier. However, envelope tracking introduces gain and phase distortions, which reduce linearity, therefore, the envelope signal is modified to account for such distortions. Thus, the envelope signal is received by a gain precompensation component 130 of the baseband chipset 100, and the gain precompensation component 130 attempts to add phase and gain changes to the envelope signal such that these added changes will subsequently cancel at the power amplifier 110 the gain and phase distortions that are otherwise introduced. The output signal of the precompensation component 130 becomes the envelope control voltage supplied to a power supply modulator 135 of the tracking chip 105. The power supply modulator 135 then produces a continuously modulated voltage that is the supply voltage applied to the power amplifier 110 and that is meant to faithfully and continuously track the rise and fall of the power level of the input RF signal.

[0008] The envelope tracking technique, however, requires a fast linear power supply modulator 135 that has the bandwidth to respond to quickly changing RF power requirements. Fast linear power supply modulators 135 typically become inefficient with increasing bandwidth, and while this has been the subject of many innovations, the compromise persists. Moreover, having the envelope detector 125 as part of the baseband chipset 100 adds software and hardware overhead, and vendor dependency.

3 [0009] Another approach that has been used is analog predistortion, as illustrated by FIG. 2. In the example of FIG. 2, the baseband chipset 200 does not include the envelope detector 125 or precompensation component 130, and the overall circuitry does not include the tracking chip 105. Instead, the power amplifier 210 includes an envelope detector 220, a gain predistorter 230, and a phase predistorter 240. The RF input to the power amplifier 210 is first measured by the envelope detector 220, then the RF input is received by the gain predistorter 230, and after the gain predistorter 230 by the phase predistorter 240.

[0010] As the RF input power level varies, the gain and phase of the output signal from the RF power amplifier 210 also change. These relationships are called AMAM and AMPM respectively, for the change in gain as a function of power level and the change in phase as a function of power level, and these relationships can be determined experimentally and/or theoretically. Predistorters 230, 240, respectively, are designed to controllably shift the gain and the phase of a received RF input signal in response to an external control voltage such that the gain and phase deviations produced by the predistorters 230, 240 are the inverse of some deviation that will be produced by the power amplifier 210 at the given RF power level. In this way, the gain and phase deviations introduced by the predistorters 230, 240 ideally cancel other gain and phase deviations produced by the power amplifier 210.

[0011] It is noted that the gain predistorter 230 and phase predistorter 240 are different physical circuits. Thus, care has to be taken such that the gain predistorter 230 does not cause phase deviation, and that the phase predistorter 240 does not cause gain deviation. Designing the predistorters 230, 240 with these criteria makes them consume

4 more power, and increases their size which reduces efficiency and increases cost. In addition, there is the disadvantage of having three addition circuits - the envelope detector 220, gain predistorter 230, and phase predistorter 240. Finally, analog predistortion does not provide the same level of efficiency improvement as envelope tracking.

[0012] RF Amplifiers are often multistage. Each stage is made up of an active amplifying element, and provides a certain amount of gain. The amplifying element is usually a transistor having three active nodes. One active node is common to the input and the output of the gain stage, another is the output, and the last is the input. The input node, may either be the gate or the base of the transistor, depending on whether the transistor is a MOSFET or a BJT. The input node receives both the input RF signal as well as a bias voltage. The gain and the phase of the amplifying stage jointly change with this bias voltage as input RF power is varied.

[0013] During the design of linear power amplifiers, dedicated to 3G or 4G modulation, the active area of each transistor is optimized in terms of size and consumption to have the maximum performance under a 50Ω load (see US 9,240,402 issued January 19, 2016 which is incorporated herein by reference). However, in applications such as a mobile phone, the power amplifier is followed by, for example, a duplexer to split the receiving (Rx) and transmission (Tx) paths. Duplexers that employ SAW technology to separate the two frequencies are particularly tailored to the constraints of filtering (e.g., low insertion in Tx path, Tx rejection in Rx path), and as a consequence modify the load seen by the power amplifier. In some instances, the duplexer can present a load with a Voltage Standing Wave Ratio (VSWR) of 2:1,

5 meaning that the magnitude of the load could vary between 25 Ω and 100 Ω for some angles (with reference to the Smith Chart).

[0014] In the case of a high load (Rp above 50 Ω), the power delivered by the power amplifier will be lower (Pout- V Rp), so the linear power will also be lower than for a 50Ω load. On the other hand, in case of low Rp, the delivered power is higher but at the expense of a larger current. The increased current decreases the battery life of the mobile device.

[0015] A few methods exist to compensate for the load variation seen by the power amplifier. One method is to increase the margin in linearity and power during the design phase of the power amplifier. With this over-specification the power amplifier remains linear and delivers enough power even with a poor VSWR due to the duplexer. The cost of this method is increased current consumption and decreased efficiency.

[0016] Secondly, phone makers add some passive matching components before and after the duplexer. The goal here is to reduce the VSWR and to try to put the load seen by the power amplifier as close as possible to a fixed resistance, such as 50Ω. For each manufacturer's phone board, it is necessary to re-tune theses matching components to find a compromise, where the power and the linearity meet the required specifications, but with power consumption as small as possible.

[0017] A similar system, usually called an "antenna tuner" has also be employed. In this system the goal is to keep the load seen by the phone constant, so this system is localized between the last stage of the phone and the antenna and compensates for the VSWR due to the antenna. Of course, an antenna tuner cannot be used in applications

6 where the duplexer would be before this antenna tuner, as changes in the load due to the duplexer would not be compensated by the antenna tuner.

SUMMARY

[0018] The present invention provides high performance RF power amplifiers for mobile handsets and other devices. The present invention simultaneously improves both efficiency and linearity of the power amplifier with a simplified design, all while implementing gain and phase predistortion without requiring any additional gain or phase predistorters. More specifically, the present invention provides multi-level envelope tracking, multi-level gate control, and an adaptive load on the power amplifier. The three can be used in various combinations as well as individually. The present invention can be used by OEM customers to take advantage of higher performance CMOS RF power amplifiers that offer increased efficiency and linearity, while reducing dependence on control signals from the baseband chipset.

[0019] In multi-level envelope tracking, a supply voltage delivered to the RF power amplifier is quantized to a fixed number of levels, each level provided by a separate source. Switching between several fixed sources can be more easily and efficiently implemented than the state of the art envelope tracking that continuously modulates the power supply and reduces bandwidth requirements.

[0020] The quantization of power supply levels in multi-level envelope tracking may, however, produce gain and phase deviations. Multi-level gate control can be applied independently, or in addition to multi-level envelope tracking, to correct for gain and phase deviations. As noted above, traditional predistorters implement painstakingly

7 designed circuits that modify gain but not phase, and those that modify phase but not gain. These increase the circuit size and reduce efficiency. Multi-level gate control solves this by utilizing the gain and phase deviations inherent in the very circuits that it seeks to correct. More specifically, the power amplifier includes an envelope tracker to track the power level of the RF input signal, and also includes two bias circuits that each receive the envelope signal and that, based on the envelope signal, produce bias voltages. One bias circuit applies a bias voltage to the input of a first stage transistor of the power amplifier, while the second bias circuit applies another bias voltage to the input of a second stage transistor of the power amplifier. Each bias circuit can be configured to apply a bias voltage that varies as a function of the envelope signal, where the functional relationship between the applied bias voltage and the amplitude of the envelope signal is different for each bias circuit. When a proper bias voltage is applied at each stage for a given envelope signal level, the gain and phase shifts introduced by the several biases will cancel the gain and phase shifts introduced elsewhere, such as by multi-level envelope tracking.

[0021] The present invention also provides an adaptive load following the power amplifier that serves to maintain a constant load as seen by the last active stage of the power amplifier, regardless of the VSWR seen by the power amplifier. The adaptive load comprises an output matching network that receives the output of the last stage and a circuit that measures the load at the last stage and controls the output matching network to set the correct load.

BRIEF DESCRIPTION OF THE DRAWINGS

8 [0022] FIG. 1 is a schematic representation of mobile device amplifier circuitry implementing instantaneous envelope tracking according to the prior art.

[0023] FIG. 2 is a schematic representation of mobile device amplifier circuitry implementing analog predistortion according to the prior art.

[0024] FIG. 3 is a schematic representation of mobile device amplifier circuitry implementing multi-level envelope tracking according to exemplary embodiments of the present invention.

[0025] FIG. 4 is a schematic representation of mobile device amplifier circuitry implementing multi-level envelope tracking and multi-level gate control according to exemplary embodiments of the present invention.

[0026] FIG. 5 is a schematic representation of mobile device amplifier circuitry 500 implementing multi multi-level gate control according to exemplary embodiments of the present invention.

[0027] FIG. 6 is a graphical representation of an exemplary RF input signal and several signals derived therefrom, according to exemplary embodiments of the present invention.

[0028] FIG. 7 is a schematic representation of mobile device amplifier circuitry implementing an adaptive load according to exemplary embodiments of the present invention.

[0029] FIG. 8 is a schematic representation of mobile device amplifier circuitry implementing an adaptive load according to exemplary embodiments of the present invention.

9 [0030] FIG. 9 is a schematic representation of a logic flow implemented by a controller for providing an adaptive load according to exemplary embodiments of the present invention.

DETAILED DESCRIPTION

[0031] FIG. 3 is a schematic representation of mobile device amplifier circuitry 300 implementing multi-level envelope tracking according to exemplary embodiments of the present invention. The circuitry 300 comprises a baseband chipset 305 including a baseband generator 310 and an RF signal generator 315 that produce a combined signal comprising a varying RF signal encoding information on top of a baseband signal. This combined signal is the RF input to a power amplifier 320. It is noted that the baseband chipset 305 does not include the DPD bloc of FIG. 1 as such is not required with the present invention.

[0032] The power amplifier 320 includes a driver stage transistor 325 and a power stage transistor 330. The driver stage transistor 325 receives the RF input from the baseband chipset 305 and amplifies it using a fixed supply voltage. The amplified output of the driver stage transistor 325 is received by the power stage transistor 330 that receives a step- wise modulated supply voltage. The output of the power stage transistor 330 is the amplified output of the power amplifier 320. The power amplifier 320, in some embodiments is defined in CMOS.

[0033] The power amplifier 320 also includes an envelope detector 335 that continuously measures the power level of the RF input signal to the power amplifier 320 at an input to the power amplifier 320. The envelope detector 335 produces an envelope

10 signal that tracks the measured power level, then provides the envelope signal to a quantization controller 340 which controls a switch 345. The switch 345 is configured to switch between a plurality of supply voltage sources 350, each configured to provide a different DC voltage. In operation, the quantization controller 340 controls the switch 345 to select a supply voltage source 350 that will supply the most appropriate voltage to the power stage transistor 330 for the power level of the RF input signal.

[0034] As noted, there are a plurality of supply voltage sources 350, each configured to provide a different DC voltage. In various embodiments, the number of supply voltage sources 350 is two, three, four, five, six, or seven. The number of supply voltage sources 350 can also be less than 8, less than 10, or less than 25. The more supply voltage sources 350, the finer the spacings between the successive voltage levels and the more the system resembles continuous envelope tracking and losses the advantages of having a small number of discrete voltage steps provided at the power stage transistor 330.

[0035] The quantization controller 340 divides the range of the envelope signal into a number of sub-ranges, where the number of sub-ranges equals the number of supply voltage sources 350. In operation, the quantization controller 340 monitors the level of the envelope signal, which tracks the power level of the RF input signal, and compares the level of the envelope signal to the sub-ranges to control the switch 345 to select different supply voltage sources 350 as the envelope signal moves through the several sub-ranges. To prevent too frequent switching, the quantization controller 340 can average the envelope signal over some time period and only when the average moves from one sub-range to another does the quantization controller 340 control the switch 345 to select a different supply voltage source 350. It should be noted that the while the

11 several sub-ranges collectively span the dynamic range of the envelope signal, the subranges do not have to be equal in their respective spans.

[0036] FIG. 4 is a schematic representation of mobile device amplifier circuitry 400 implementing multi-level envelope tracking and multi-level gate control according to exemplary embodiments of the present invention. The circuitry 400 comprises a baseband chipset 305 including a baseband generator 310 and an RF signal generator 315 that produce a combined signal comprising a varying RF signal encoding information on top of a baseband signal. This combined signal is the RF input to a power amplifier 410.

[0037] The power amplifier 410 includes a driver stage transistor 325, a power stage transistor 330, an envelope detector 335, a quantization controller 340, a switch 345, and a plurality of supply voltage sources 350 all arranged as described with respect to FIG. 3 to provide multi-level envelope tracking. The power amplifier 410 further includes two bias circuits 420, 430 that both also receive the envelope signal from the envelope detector 335. The bias circuit 420 adds a first bias voltage to the RF input signal at the input to the driver stage transistor 325, while the bias circuit 430 adds a second bias voltage to the amplified RF input signal at the input to the power stage transistor 330. The magnitudes of the two bias voltages are dependent on the magnitude of the envelope signal. When a proper bias voltage is applied at each stage for a given envelope signal level, the gain and phase shifts introduced by the several added biases will cancel the gain and phase shifts introduced elsewhere, such as by multi-level envelope tracking.

[0038] Either empirically, or by mathematical modelling, for each input power level, as represented by the magnitude of the envelope signal, a set of bias voltages for the two bias circuits 420, 430 can be determined such that over a wide range of input power

12 levels, the deviation of gain and phase shifts introduced elsewhere are cancelled. By eliminating the requirement to map each control independently to either gain or phase, a jointly optimized approach is created, which does not require the additional of a new circuit. Efficiency is increased because the changing bias levels reduce supply current consumption at lower RF power levels.

[0039] Bias circuits 420, 430 can be implemented such that they vary their applied biases in a continuous fashion, or can be quantized according to the same envelope signal levels as for multi-level envelope tracking, or other quantized differently, or can be a piecewise continuous combination of continuous and quantized, in various embodiments. It is noted that dividing the range into discrete values is simpler to implement., while a continuously variable bias voltage offers finer control over cancelling distortions caused by multi-level envelope tracking.

[0040] FIG. 5 is a schematic representation of mobile device amplifier circuitry 500 implementing multi multi-level gate control according to exemplary embodiments of the present invention. The circuitry 500 comprises a baseband chipset 305 including a baseband generator 310 and an RF signal generator 315 that produce a combined signal comprising a varying RF signal encoding information on top of a baseband signal. This combined signal is the RF input to a power amplifier 510. As compared to the mobile device amplifier circuitry 400 of FIG. 4, this circuitry 500 omits the quantization controller 340, switch 345, and the plurality of supply voltage sources 350.

[0041] FIG. 6 is a graphical representation of an exemplary RF input signal 600 and an envelope signal 610 derived from RF input signal 600. FIG. 6 also shows a multilevel envelope tracking signal 620 derived from the envelope signal 610 according to

13 various embodiments of the present invention. FIG. 6 also shows an output envelop signal 630. Historically, output envelop signal 640 has been obtained by a diode rectifier followed by a low frequency RC circuit. Output envelop signal 640 is not employed by the present invention and is provided for reference only. FIG. 6 also shows a

conventional supply voltage 640 at a fixed value, again for reference.

[0042] FIG. 7 is a schematic representation of mobile device amplifier circuitry 700 implementing an adaptive load according to exemplary embodiments of the present invention. Circuitry 700 comprises an RF power amplifier 705 followed in series by a duplexer 710, an antenna switch module 715, and then an antenna 720. The RF power amplifier 705 receives an RF input signal, such as from a baseband chipset, and amplifies the RF input signal to produce an amplified output signal that is received by the duplexer 710 and passed to the antenna switch module 715 and then to the antenna 720. The antenna switch module 715 consists of multiple input switches in parallel with a common output to the antenna 720, and each input switch is connected to a different duplexer. One duplexer 710 and one input switch of the antenna switch module 715 exists for each band used by the mobile device.

[0043] The RF power amplifier 705 includes at least a power stage transistor 725. The power stage transistor 725, in different embodiments, receives either a fixed or a variable supply voltage, such as one that tracks the envelope, either instantaneously or in a multi-level manner as disclosed herein. The RF power amplifier 705 further comprises an output matching network including a balun 730 followed by filtering components 735. The balun 730 receives the amplified output of the power stage transistor 725 and provides both an impedance transformation and a differential-to-single-ended

14 transformation. The filtering components 735 comprise, for example, an LC circuit, and serves to remove unwanted harmonics. In exemplary embodiments, the inductor of the LC circuit of filtering components 735 is in the range of 0.2nH to ΙΟηΗ, but can be higher as needed for load variation requirements.

[0044] The RF power amplifier 705 also includes switches 740 to select the proper output for the particular frequency band. The output matching network optionally includes the switches 740. As illustrated, the RF power amplifier 705 comprises a differential power amplifier such that the signal received by the balun 730 from the power stage transistor 725 is a differential signal. The balun 730 transforms this differential input signal to single-ended output.

[0045] The RF power amplifier 705 further comprises a controller 745. The controller 745 is coupled to the power stage transistor 725 and is configured to monitor a load value of the power stage transistor 725. Based on the load value, the controller 745 determines an optimal configuration for a pair of variable capacitors 750, 755, then controls the variable capacitors 750, 755 to that configuration. The load value has a resistive and an imaginary part, described by two orthogonal quantities. The quantities used depends of the domain (e.g., analog or RF). By example, Real/Imaginary (Serial model), gamma/phi (Smith Chart), or Rp/Cp (parallel model). The best configuration for the variable capacitors 750, 755 is one that will adjust the resistive component of the load value at the power stage transistor 725 for the given power level to be as close as possible to 50Ω, in some embodiments.

[0046] In some embodiments the load value of the power stage transistor 725 is represented by a VSWR value. The VSWR value can be determined in the Rp/Cp format

15 or the gamma/phi format, in various embodiments. In some embodiments, the controller 745 monitors the load value by monitoring the values for Rp and Cp. The Rp value and Cp value are measured separately.

[0047] The Rp value can be measured by measuring the dynamic ratio of voltage to current at the drain, Vdrain/Idrain, of the power stage transistor 725. To avoid complex calculations and expensive circuitry, in some embodiments, instead of using the instantaneous value of Rp, an integrated value is used. For example, the controller 745 can use the rms for the drain voltage for Vdrain and use the average of the current at the drain for Idrain. In some embodiments, whenever the ratio of Vdrain/Idrain falls below a threshold the controller 745 replaces the ratio with a minimum fixed value for the ratio to avoid errors due to inaccuracy.

[0048] The Cp value can be determined based on a phase difference between internal voltages inside the silicon of the power stage transistor 725. This difference gives a good representation of the variation of the imaginary value of the load value. More specifically, the internal voltage used are the differential input signal of the power stage and the differential output voltage of the power stage. The phase change between these signals can be converted in voltage through a phase comparator within the controller 745.

[0049] The controller 745 implements independent control of Rp and Cp based on the measured values. This implementation is compatible with the output matching network to avoid extra losses. Here, the controller 745 implements a feedback loop such that as excursions from the desired load value are measured, the controller 745 responds by changing Rp and Cp.

16 [0050] One way to vary Rp is to change the imaginary value on the secondary turns of the balun 730. In FIG. 7, this is achieved by varying the capacitances of variable capacitors 750, 755. One way to vary Cp is to include a variable capacitor 760 directly connected to the drain of the power stage transistor 725. The value of the variable capacitor 760 is set by the controller 745. In some embodiments, the variable capacitor 760 comprises a switched capacitor wherein the controller 745 sets the correct switches in order to connect the correct fixed capacitors to set the desired capacitance. It should be noted that the other variable capacitors discussed herein can be implemented in the same manner.

[0051] FIG. 8 shows an alternative embodiment to the one illustrated by FIG. 7. In the circuitry 800 of FIG. 8, an RF power amplifier 810 has a single variable capacitor 820 connected by switches 830 and 840 to the nodes before and after the filtering components 735, instead of the variable capacitors 750, 755 in power amplifier 705. The switches 830 and 840 can both be set to open, in which case the variable capacitor 820 is not part of the circuit, or either of the switches 830, 840 can be closed while the other is open. A controller 850 is configured in this embodiment to control switches 830, 840 as well as to control the variable capacitor 820 and variable capacitor 760.

[0052] In various embodiments the controller 745, 850 responds to the measured VSWR by adjusting the Rp and Cp. The controller 745, 850 can do so, for example, by the logic flow illustrated in FIG. 9. Here, Rp information 910 in analog form, and Cp information 920 in analog form, both determined as described above, are provided to analog to digital converters 930 and 940, respectively, and the digital signals are then provided to logic 950 which implements digital processing or employs a look-up table to

17 find the appropriate settings for Rp and Cp. The embodiment shown in FIG. 9 provides control in the digital domain, but control can also be implemented in the analog domain.

[0053] In the foregoing specification, the invention is described with reference to specific embodiments thereof, but those skilled in the art will recognize that the invention is not limited thereto. Various features and aspects of the above-described invention may be used individually or jointly. Further, the invention can be utilized in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of the specification. The specification and drawings are, accordingly, to be regarded as illustrative rather than restrictive.

[0054] It will be recognized that the terms "comprising," "including," and "having," as used herein, are specifically intended to be read as open-ended terms of art. The term "connect" is differentiated herein from the term "couple" such that when two components are "connected" there are no other components disposed between them, whereas when two components are "coupled" there may be other components disposed between them. "Logic" as used herein can include hardware, firmware and/or software stored on a tangible computer readable medium, other than paper, in combination with a processor for executing the software. The use of the term "means" within a claim of this application is intended to invoke 35 U.S.C. 112(f) only as to the limitation to which the term attaches and not to the whole claim, while the absence of the term "means" from any claim should be understood as excluding that claim from being interpreted under 112(f). As used in the claims of this application, "configured to" and "configured for" are not intended to invoke 35 U.S.C. 112(f).

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Claims

CLAIMS What is claimed is:

1. A circuit comprising:

an RF power amplifier including

an input for receiving an RF input signal,

a power stage transistor having a first input for receiving the RF input signal to be amplified and a second input for receiving a supply voltage,

an envelope detector configured to generate an envelope signal that

represents a continuous measurement of a power level of the RF input signal at the input of the RF power amplifier,

a switch configured to select between a plurality of direct current supplies, each configured to deliver a different voltage, and

a quantizer configured to receive the envelope signal and to control the switch to select between the plurality of direct current supplies according to a magnitude of the envelope signal.

2. The circuit of claim 1 further comprising a baseband chipset including a baseband generator and an RF signal generator, wherein an output of the baseband chipset provides the RF signal at the first input of the power stage transistor.

19

3. The circuit of claim 2 wherein the baseband chipset does not include a digital pre- distortion bloc.

4. The circuit of one of the preceding claims wherein the power amplifier further

comprises a drive stage transistor in series with the power stage transistor.

5. The circuit of claim 4 wherein the power amplifier further comprises

a first bias circuit configured to receive the envelope signal and to add a first bias voltage to the RF signal at an input of the drive stage transistor, a magnitude of the first bias voltage being dependent on the envelope signal, and

a second bias circuit configured to receive the envelope signal and to add a second bias voltage to the RF signal at the input of the power stage transistor, a magnitude of the second bias voltage being dependent on the envelope signal.

6. A circuit comprising:

an RF power amplifier including

an input for receiving an RF input signal,

a power stage transistor having a first input for receiving the RF input signal and a second input for receiving a supply voltage, a drive stage transistor in series with the power stage transistor,

20 an envelope detector configured to generate an envelope signal that

7. The circuit of claim 6 further comprising a baseband chipset including a baseband generator and an RF signal generator, wherein an output of the baseband chipset provides the RF signal at the first input of the power stage transistor.

8. The circuit of claim 7 wherein the baseband chipset does not include a digital pre- distortion bloc.

9. A circuit comprising:

an RF power amplifier transistor having a differential output;

a balun having a differential input coupled to the differential output of the RF power amplifier, and having a single-ended output;

21 an inductor and a capacitor in parallel between a first node and a second node, the first node being coupled to the single-ended output;

a first tunable capacitor coupled between the first node and ground;

a second tunable capacitor coupled between a third node and ground, the third node being disposed between the RF power amplifier transistor and the balun; and

a controller coupled to the differential output of the RF power amplifier transistor and configured to measure the load value at the differential output and vary the first and second tunable capacitors in response thereto.

10. The circuit of claim 9 further comprising a first switch between the first node and the first tunable capacitor and a second switch between the second node and the first tunable capacitor, wherein the controller is configured to control the first and second switches in response to the load value.

11. The circuit of claim 9 or 10 further comprising a third tunable capacitor coupled between the second node and ground, wherein the controller is configured to control the third tunable capacitor in response to the load value.

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