WO2018148864A1

WO2018148864A1 - Clock synchronization method and device

Info

Publication number: WO2018148864A1
Application number: PCT/CN2017/073474
Authority: WO
Inventors: 方李明; 张晓风; 隋猛; 周雷
Original assignee: 华为技术有限公司
Priority date: 2017-02-14
Filing date: 2017-02-14
Publication date: 2018-08-23
Also published as: CN109792376B; CN109792376A

Abstract

Provided are a clock synchronization method and device, which relate to the technical field of communications and solve the problem of user data information being interrupted when an existing CDMA system implements clock synchronization. The method is applied to a code division multiple access system, and comprises: a transmitting end driving a first sequence code by means of sending a clock so as to obtain a signal bearing the clock, wherein the signal bearing the clock is a square wave signal, the first sequence code comprises N symbols, the length of time between any two transition edges of the square wave signal is an integer multiple of the length of time for sending the first sequence code, the length of time of each symbol from among the N symbols is equal, N is an integer greater than or equal to 1, and when N ≥ 2, the N symbols are the same; and the transmitting end sending a transmitting signal to a receiving end, wherein the transmitting signal comprises the signal bearing the clock, and the signal bearing the clock is used for implementing clock synchronization between the receiving end and the transmitting end.

Description

Clock synchronization method and device

Technical field

The present application relates to the field of communications technologies, and in particular, to a clock synchronization method and device.

Background technique

Code division multiple access (CDMA) is a carrier modulation and multiple access connection technology based on spread spectrum communication. The signals used by different user terminals are not based on different frequencies or times. The gaps are distinguished by different, but by different coding sequences. Among them, CDMA is mainly used in wireless communication, and there is a problem that a signal to noise ratio (English: signal to noise ratio, SNR for short) is low when using a CDMA system for data information communication. Therefore, it can be improved by a clock synchronization method. The performance of CDMA systems.

At present, in a CDMA system, a pseudo-random sequence (English: pseudo-noise, PN sequence for short) is usually used to implement clock synchronization, that is, a PN sequence is periodically inserted in data information superimposed by a CDMA system. After receiving the superimposed received signal, the receiving end performs clock synchronization through the good correlation characteristics of the PN sequence, thereby synchronizing the clock frequency and the codeword phase in the CDMA system. For example, the receiving end can realize clock synchronization through the early and late circuit as shown in FIG. 1 for receiving signals, and the early and late circuit includes a PN code generator, a mixer, and a low-pass filter (English: low pass filter, referred to as LPF) ), adder, loop filter (English: loop filter, referred to as: LF) and voltage controlled oscillator (English: voltage controlled oscillator, referred to as: VCO).

However, the above method of implementing clock synchronization in a CDMA system by using a PN sequence requires insertion of an additional overhead, that is, a PN sequence needs to be inserted in each frame included in the data information, thereby causing interruption of the user's data information.

Summary of the invention

The embodiment of the present application provides a clock synchronization method and device, which solves the problem that the existing CDMA system has interrupted data information of the user when implementing clock synchronization.

To achieve the above objective, the embodiment of the present application adopts the following technical solutions:

In a first aspect, a clock synchronization method is provided, which is applied to a code division multiple access system. The method includes: a transmitting end drives a first sequence code by using a transmitting clock to obtain a signal carrying a clock, and the signal carrying the clock is a square wave signal; The first sequence code includes N symbols, and N is an integer greater than or equal to 1. When N≥2, N symbols are the same; the length of time between any two transition edges of the square wave signal is sent. The time length of the first sequence code is an integer multiple, and each of the N symbols has the same length of time; the transmitting end sends a transmitting signal to the receiving end; wherein the transmitting signal includes a signal carrying the clock, and the signal carrying the clock is used. The clock synchronization between the receiving end and the transmitting end is implemented.

In the foregoing technical solution, the transmitting end drives the first sequence code by using a sending clock to obtain a signal carrying a clock, and the length of time between two hop edges of the signal carrying the clock is an integer multiple of a length of time for transmitting the first sequence code. And each of the N symbols has the same length of time, and the receiving end sends a transmission signal including a signal carrying the clock, and the signal carrying the clock is used to implement clock synchronization between the transmitting end and the receiving end, so that the transmitting end sends the separate signal. The clock carrying the clock realizes the clock synchronization of the CDMA system, and does not need to insert the sequence code in the user data information, thereby solving the problem of saving the clock synchronization. The problem of user data interruption is interrupted.

In a possible implementation manner of the first aspect, the duty ratio of the square wave signal is 50%; or the square wave signal is a data signal. In the above possible technical solutions, two possible implementations of the square wave signal are provided, and when the duty ratio of the square wave signal is 50%, or the square wave signal is a data signal, the clock signal can be guaranteed to have better performance. Parameters to improve system performance in CDMA systems.

In a possible implementation manner of the first aspect, the first sequence code is a sequence code in the preset codeword set, the preset sequence code set further includes at least one sequence code, and the first sequence code and the at least one sequence code Orthogonal to each other, each of the at least one sequence code is used to modulate a user data signal; if the transmit signal further includes at least one modulated data signal, before the transmitting end transmits the transmit signal to the receiving end, the method further includes: For a signal of each of the at least one modulated data signal, the transmitting end modulates the user data signal by driving the second serial code to obtain a modulated data signal, and the second serial code is a serial code in the at least one serial code. The transmitting end superimposes the signal carrying the clock and the signal of the at least one modulated data to obtain a transmitting signal. In the above possible technical solution, the transmitting end modulates the user data signal by transmitting a clock to drive the second sequence code orthogonal to the first sequence code, and superimposes the signal carrying the clock signal and the modulated data signal, and sends the signal to the receiving end through a channel. In order to enable the receiving end to demodulate according to the same clock and the second sequence code, the problem that the service data is not interrupted in the transparent transmission system can be solved while providing a clock signal with higher precision.

In a second aspect, a clock synchronization method is provided, which is applied to a code division multiple access system, and the method includes: receiving, by a receiving end, a receiving signal, where the receiving signal is a signal transmitted by a transmitting end and transmitted by a channel; the receiving signal includes a bearer The signal of the clock, and the signal carrying the clock is a square wave signal obtained by the transmitting end by driving the first sequence code by the transmitting clock; the first sequence code includes N symbols, and N is an integer greater than or equal to 1, when N≥2 The N symbols are the same; the length of time between any two hop edges of the square wave signal is an integer multiple of the length of time for transmitting the first sequence code, and the time length of each symbol in the N symbols is equal.

In the above technical solution, when receiving the received signal, the receiving end performs preset processing on the received signal to obtain a clock signal, that is, the receiving end demodulates the received received signal to obtain a separate clock signal, and the clock signal is used for receiving. The clock synchronization between the terminal and the transmitting end realizes clock synchronization of the CDMA system, and does not need to insert a sequence code into the user data information, thereby solving the problem that user data information is interrupted during clock synchronization.

In a possible implementation of the second aspect, the duty cycle of the square wave signal is 50%; or the square wave signal is a data signal. In the above possible technical solutions, two possible implementations of the square wave signal are provided, and when the duty ratio of the square wave signal is 50%, or the square wave signal is a data signal, the clock signal can be guaranteed to have better performance. Parameters to improve system performance in CDMA systems.

In a possible implementation manner of the second aspect, if the CDMA system is a digital signal system, the receiving end performs preset processing on the received signal to obtain a clock signal, including: the receiving end continuously accumulates the received signal or presets sliding. Window accumulating processing, filtering processing, and phase locking processing obtain a clock signal. In the above possible technical solutions, two receiving methods for performing preset processing on the received signals are provided, by continuously accumulating the received signals or presetting the sliding window accumulation. The clock signal with high signal to noise ratio can be obtained.

In a possible implementation manner of the second aspect, the first sequence code is a sequence code in the preset codeword set, the preset sequence code set further includes at least one sequence code, and the first sequence code and the at least one sequence code Orthogonal to each other; each of the at least one sequence code is used to demodulate a data modulated signal; if the received signal further includes at least one modulated data signal, the receiving end performs preset processing on the received signal to obtain a clock signal. The method further includes: the receiving end determines the receiving clock according to the clock signal, the receiving clock is used to drive the at least one sequence code; and for the signal of each of the modulated data in the at least one modulated data signal, the receiving end drives the second sequence by receiving the clock The code demodulates the signal of the modulated data included in the received signal, and performs preset processing on the signal of the modulated modulated data to obtain a user data signal; wherein the second serial code is a serial code in the at least one serial code. In the above possible technical solution, when the receiving end demodulates the signal of the modulated data, the receiving clock determined by the clock signal drives the second sequence code orthogonal to the first sequence code to demodulate the modulated data signal, thereby obtaining User data signal, the method can solve the problem that the service data is not interrupted in the transparent transmission system while providing a higher precision clock signal.

The third aspect provides a transmitting end device, which is applied to a code division multiple access system, where the transmitting end device comprises: driving a first sequence code by using a sending clock to obtain a signal carrying a clock, and the signal carrying the clock is a square wave signal; The first sequence code includes N symbols, N is an integer greater than or equal to 1. When N≥2, N symbols are the same; the length of time between any two transition edges of the square wave signal is the transmission number An integer multiple of a time length of a sequence of codes, and each of the N symbols has an equal length of time; the transmitting unit is configured to send a transmission signal to the receiving end device; wherein the transmitting signal includes a signal carrying a clock; The signal is used to implement clock synchronization between the receiving device and the transmitting device.

In a possible implementation manner of the third aspect, the duty ratio of the square wave signal is 50%; or the square wave signal is a data signal.

In a possible implementation manner of the third aspect, the first sequence code is a sequence code in the preset codeword set, the preset sequence code set further includes at least one sequence code, and the first sequence code and the at least one sequence code Orthogonal to each other; each of the at least one sequence code is used to modulate a user data signal; the modulating unit is further configured to drive the second signal through the transmit clock for the signal of each of the at least one modulated data signal The sequence code modulates the user data signal to obtain a signal for modulating data; wherein the second sequence code is a sequence code in at least one sequence code; and the modulating unit is further configured to superimpose the signal carrying the clock and the signal of the at least one modulated data Processing, get the transmitted signal.

The fourth aspect provides a receiving end device, which is applied to a code division multiple access system, where the receiving end device includes: a receiving unit, configured to receive a received signal; wherein, the received signal is after the transmitting signal sent by the transmitting end device is transmitted through the channel. The received signal includes a signal carrying a clock, and the signal carrying the clock is a square wave signal obtained by the transmitting end device by driving the first serial code by the transmitting clock; the first serial code includes N symbols, and N is greater than or equal to 1 Integer, when N≥2, N symbols are the same; the length of time between any two hop edges of the square wave signal is an integer multiple of the length of time for transmitting the first sequence code, and N symbols The time length of each symbol is equal; the demodulation unit is configured to perform preset processing on the received signal to obtain a clock signal; wherein the clock signal is used to implement clock synchronization between the receiving end device and the transmitting end device.

In a possible implementation manner of the fourth aspect, the duty ratio of the square wave signal is 50%; or the square wave signal is a data signal.

In a possible implementation manner of the fourth aspect, if the CDMA system is a digital signal system, the demodulation unit is specifically configured to: continuously accumulate received signals or preset sliding window accumulation processing, filtering processing, and phase lock processing , get the clock signal.

In a possible implementation manner of the fourth aspect, the first sequence code is a sequence code in the preset codeword set, the preset sequence code set further includes at least one sequence code, and the first sequence code and the at least one sequence code Orthogonal to each other; each of the at least one sequence code is used to demodulate a data modulated signal; the demodulation unit is further configured to determine a receive clock based on the clock signal, the receive clock is used to drive the at least one sequence code; And a unit, configured to, for the signal of each of the at least one modulated data signal, demodulate the signal of the modulated data included in the received signal by the second clock sequence driven by the receiving clock, and signal the demodulated modulated data Performing a preset process to obtain a user data signal; wherein the second sequence code is a sequence code in at least one sequence code.

In a fifth aspect, an apparatus is provided, comprising a processor and a memory, the memory storing code and data, the processor being operable to execute code in the memory, the processor for performing the first aspect or any one of the possible implementations of the first aspect A clock synchronization method provided by the method, or a clock synchronization method provided by the second aspect or any of the possible implementation manners of the second aspect.

According to a sixth aspect, a computer readable storage medium is provided, where computer executed instructions are stored, and when the at least one processor of the device executes the computer to execute an instruction, the device performs the first aspect or the first aspect. A clock synchronization method provided by any of the possible implementations, or a clock synchronization method provided by the second aspect or any of the possible implementations of the second aspect.

In a seventh aspect, a computer program product is provided, the computer program product comprising computer executable instructions stored in a computer readable storage medium; at least one processor of the device can read the computer from a computer readable storage medium Executing an instruction, the at least one processor executing the computer to execute the instruction, causing the device to implement the clock synchronization method provided by the first aspect or any one of the possible implementation manners of the first aspect, or performing the second aspect or the second aspect A clock synchronization method provided by a possible implementation.

According to an eighth aspect, a passive optical network system is provided, where the system includes a transmitting end device and a receiving end device; wherein the transmitting end device is the third aspect, or any possible implementation manner of the third aspect, or the fifth The transmitting end device, and/or the receiving end device provided by the aspect, is the fourth aspect, or any possible implementation manner of the fourth aspect, or the receiving end device provided by the fifth aspect.

It will be understood that any of the above-mentioned devices, computer storage media, computer program products, or both the transmitting device and the receiving device in the system for implementing the clock synchronization method are used to perform the corresponding methods provided above, thus For the beneficial effects that can be achieved, reference may be made to the beneficial effects in the corresponding methods provided above, and details are not described herein again.

DRAWINGS

1 is a schematic structural view of an early circuit;

2 is a schematic diagram of modulating and demodulating user data in a CDMA system according to an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of a CDMA system according to an embodiment of the present disclosure;

4 is a schematic structural diagram of a medium centralized modulation system according to an embodiment of the present application;

FIG. 5 is a flowchart of a CDMA clock synchronization method according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a square wave signal according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a clock signal according to an embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram of a preset process according to an embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of another preset process according to an embodiment of the present disclosure;

FIG. 10 is a schematic structural diagram of still another preset process according to an embodiment of the present disclosure;

FIG. 11 is a schematic diagram of a signal after continuous accumulation processing according to an embodiment of the present disclosure;

FIG. 12 is a schematic diagram of another preset sliding window accumulating processing signal according to an embodiment of the present disclosure;

FIG. 13 is a flowchart of another CDMA clock synchronization method according to an embodiment of the present disclosure;

FIG. 14 is a schematic structural diagram of a device at a transmitting end according to an embodiment of the present disclosure;

FIG. 15 is a schematic structural diagram of another transmitting end device according to an embodiment of the present disclosure;

FIG. 16 is a schematic structural diagram of a receiving end device according to an embodiment of the present disclosure;

FIG. 17 is a schematic structural diagram of another receiving end device according to an embodiment of the present disclosure.

detailed description

"Multiple" as referred to herein means two or more. "and/or", describing the association relationship of the associated objects, indicating that there may be three relationships, for example, A and/or B, which may indicate that there are three cases where A exists separately, A and B exist at the same time, and B exists separately. The symbol "/" generally indicates that the contextual object is an "or" relationship.

Before introducing this application, the technical names involved in this application will be described first.

Clock signal used as the basis for timing logic. For example, taking a central processing unit (CPU) as an example, the clock signal is used as its reference. All signal processing inside the CPU must use the clock signal as a scale, so that the CPU command can be determined by the clock signal. Execution speed. The clock signal may be a square wave signal, the period of the square wave signal may be fixed, or the clock signal is a randomly generated data signal.

Clock synchronization can mean that the clock at the transmitting end and the clock at the receiving end are kept in sync. Wherein, the clock signal can be used to ensure the synchronization of the signal at the transmitting end and the receiving end of the data, and the synchronization can be that the frequency of the data signal received by the receiving end is synchronized with the frequency of the data signal sent by the transmitting end, and the data signal received by the receiving end. The phase is synchronized with the phase of the data signal transmitted by the transmitting end.

CDMA is a carrier modulation and multiple access connection technology based on spread spectrum communication. The basic principle is that the data that the transmitter needs to transmit with a certain signal bandwidth is modulated by a high-speed pseudo-random code with a bandwidth much larger than the signal bandwidth. The signal bandwidth of the data information is expanded, then modulated by the carrier and transmitted. The receiving end uses the identical pseudo-random code, performs correlation processing with the received signal, and converts the received signal into data information to implement information communication between the transmitting end and the receiving end.

For example, as shown in FIG. 2, in a CDMA system, data information of multiple users at a transmitting end can be encoded and modulated by mutually orthogonal sequence codes c1, c2, c3, ..., cn before transmission, and multiple modulated samples. The user's data information is superimposed and transmitted on one channel. The receiving end demodulates the received data information by using the same sequence codes c1, c2, c3, ..., cn, respectively, and performs integral accumulation after demodulation, so that data information of a plurality of users can be recovered.

The basic principle of the embodiment of the present application is that clock synchronization between the transmitting end and the receiving end is implemented by a signal carrying a clock in a CDMA system. Specifically, the transmitting end drives the first sequence code to obtain a signal carrying the clock by transmitting a clock. The first sequence code is a sequence code with the same symbol, and the time length between two hop edges of the signal carrying the clock is the first transmission. An integer multiple of the length of the sequence code, and each of the N symbols has the same length of time. The transmitting end modulates the user data signal by transmitting the clock to drive other serial codes orthogonal to the first sequence code, and superimposes the signal carrying the clock and the modulated modulated data, and transmits the signal to the receiving end through a channel. After receiving the received signal, the receiving end obtains a clock signal through a preset process, and the received clock determined by the clock signal drives other corresponding sequence codes to demodulate the modulated data signal, thereby obtaining a user data signal. The method of the embodiment of the present invention implements clock synchronization between the receiving end and the transmitting end in the CDMA system by setting a separate signal carrying the clock, and ensures that the clock signal has high precision, and does not need to insert the serial code in the user data information. Solved the problem that business data is not interrupted in the transparent transmission system.

FIG. 3 is a schematic structural diagram of a CDMA system according to an embodiment of the present disclosure. Referring to FIG. 3, the CDMA system includes a transmitting end 101 and a receiving end 102. The transmitting end 101 can be configured to send a signal carrying a sending clock and a plurality of user data, where the sending clock and the plurality of user data can be modulated by mutually orthogonal sequence codes, and the transmitting end 101 can perform the modulated carrying clock. The signals of the signal and the modulated data are superimposed and sent to the receiving end through a channel. After receiving the received signal, the receiving end performs corresponding processing on the received signal to obtain a clock signal, and demodulates the other modulated data signals by the orthogonal sequence code corresponding to the receiving drive determined by the clock signal, thereby obtaining a plurality of user data.

The CDMA system shown in FIG. 4 is taken as an example. When the local device in the CDMA system is the transmitting end, the remote device can be the receiving end. When the local device is the receiving end, the remote device can be the transmitting end.

The central office equipment may include a digital signal processing (DSP) resource pool and a CDMA modem, and the DSP resource pool may include a cable (English: Cable) modem, digital subscriber line (English: digital subscriber line, referred to as: DSL) modem and power line (English: Power Line) modulation and demodulation. The remote device can include a CDMA modem and a heterogeneous analog front end. The heterogeneous analog front end includes an amplifier (English: amplifier, AMP for short), a low noise amplifier (LNA), and a hybrid (English: hybrid) interface. The customer premises equipment (English: customer premise equipment, CPE for short) can be divided into Cable CPE, DSL CPE, and shared line (English: party line, PL: CPE) through different connection methods.

Specifically, the transmitting end 101, that is, the transmitting end device, includes:

a modulating unit, configured to drive a first sequence code by using a transmit clock to obtain a signal carrying a clock, where the signal carrying the clock is a square wave signal; wherein the first sequence code includes N symbols; the square wave signal The length of time between any two hop edges is an integer multiple of the length of time at which the first sequence code is transmitted, and the length of time of each of the N symbols is equal; the N is greater than or An integer equal to 1, when the N ≥ 2, the N symbols are the same;

a sending unit, configured to send a transmit signal to the receiving end device, where the transmit signal includes the signal carrying the clock; the signal carrying the clock is used to implement clock synchronization between the receiving end device and the transmitting end device .

Optionally, the duty ratio of the square wave signal is 50%; or the square wave signal is a data signal. number.

Optionally, the first sequence code is a sequence code in a preset codeword set, the preset sequence code set further includes at least one sequence code, and the first sequence code and the at least one sequence code are mutually Orthogonal; each of the at least one sequence code is used to modulate a user data signal;

The modulating unit is further configured to, for the signal of each of the at least one modulated data, modulate the user data signal by driving the second sequence code to obtain a signal of the modulated data; The second sequence code is a sequence code in the at least one sequence code;

The modulating unit is further configured to perform superposition processing on the signal carrying the clock and the signal of the at least one modulated data to obtain the transmitted signal.

The receiving end 102, that is, the receiving end device, includes:

a receiving unit, configured to receive a received signal, where the received signal is a signal transmitted by a transmitting end device and transmitted through a channel; the received signal includes a signal carrying a clock, and the signal carrying the clock is the The transmitting end device transmits a square wave signal obtained by driving the first sequence code by transmitting a clock; the first sequence code includes N symbols, and a length of time between any two transition edges of the square wave signal is An integer multiple of a time length of the first sequence code, and each of the N symbols has an equal length of time; the N is an integer greater than or equal to 1, and when the N≥2, the N The same symbol;

And a demodulation unit, configured to perform preset processing on the received signal to obtain a clock signal, where the clock signal is used to implement clock synchronization between the receiving end device and the transmitting end device.

Further optionally, the duty ratio of the square wave signal is 50%; or the square wave signal is a data signal.

Further, optionally, if the code division multiple access system is a digital signal system, the demodulation unit is specifically configured to:

The clock signal is obtained by continuously accumulating the received signal or presetting a sliding window accumulation process, a filtering process, and a phase lock process.

Further optionally, the first sequence code is a sequence code in a preset codeword set, the preset sequence code set further includes at least one sequence code, and the first sequence code and the at least one sequence code Orthogonal to each other; each of the at least one sequence code is used to demodulate a data modulated signal;

The demodulation unit is further configured to determine a receiving clock according to the clock signal, where the receiving clock is used to drive the at least one sequence code;

The demodulation unit is further configured to: for the signal of each of the at least one modulated data signal, the second sequence code is driven by the receiving clock to demodulate the signal of the modulated data included in the received signal, Predetermining the signal of the demodulated modulated data to obtain a user data signal; wherein the second sequence code is a sequence code in the at least one sequence code.

FIG. 5 is a flowchart of a clock synchronization method according to an embodiment of the present application. The method is applied to a CDMA system. Referring to FIG. 5, the method includes the following steps.

Step 201: The transmitting end drives the first sequence code by using a sending clock to obtain a signal carrying a clock. The signal carrying the clock is a square wave signal. The first sequence code includes N symbols, and N is a positive integer greater than or equal to 1. When N≥2, N symbols are the same. The length of time between two hop edges of the square wave signal is an integer multiple of the length of time at which the first sequence code is transmitted, and the time length of each of the N symbols is equal.

The first sequence code may include N symbols, and when N≥2, the N symbols are the same. For example, the first sequence code may be {1, 1, 1, ..., 1}. The square wave signal can be a periodic signal or a non-periodic signal. When the square wave signal is a periodic signal, the duty ratio of the square wave signal may be any value between 0-1, for example, the duty ratio may be 50%. When the square wave signal is a non-periodic signal, the square wave signal may be a data signal. For example, the data signal is a signal corresponding to a non-return to zero (NRZ) code.

For example, referring to FIG. 6, when the square wave signal is a periodic signal with a duty ratio of 50%, the waveform of the square wave signal can be as shown in FIG. 6(a). When the square wave signal is a data signal, if the NRZ code is [1 1 -1 1 1 1 -1 -1 1 1], the waveform of the square wave signal can be as shown in Fig. 6(b). In Fig. 6, -1 indicates a low level, and +1 indicates a high level.

In addition, the two transition edges of the square wave signal may refer to two hop edges adjacent to the square wave signal, or may be two hop edges that are not adjacent, and the edge includes from high level to low. The falling edge of the level and the rising edge from low to high. The length of time between two hop edges may be an integer multiple of the length of time during which the first sequence code is transmitted, and the length of time of each of the N symbols of the first sequence code is equal. The two hop edges may be aligned with the boundary symbols of the first sequence code, and the boundary symbols are the first symbol and the last symbol of the first sequence code.

For example, as shown in FIG. 7, if the first sequence code can be {1, 1, 1, 1}, when the square wave signal is the periodic signal shown in FIG. 6(a), the first sequence code in the square wave signal The distribution is shown in Figure 7(a). When the square wave signal is the data signal shown in Fig. 6(b), the distribution of the first sequence code in the square wave signal is as shown in Fig. 7(b). In Fig. 7, -1 indicates a low level, +1 indicates a high level, and 2N indicates that the length of time between two hop edges may be twice the length of time at which the first sequence code is transmitted.

When the clock carrying the clock is obtained by transmitting the first sequence code with the same clock driving symbol, the same symbol does not affect the amplitude fluctuation of the signal carrying the clock, and the noise in the signal carrying the clock can be reduced, and the bearer can be improved. The signal-to-noise ratio of the clock's signal, which in turn improves CDMA performance.

Step 202: The transmitting end sends a transmission signal to the receiving end. The transmitting signal includes a signal carrying a clock, and the signal carrying the clock is used to implement clock synchronization between the receiving end and the transmitting end.

After the transmitting end drives the first sequence code to obtain the signal carrying the clock, the transmitting end may send the transmitting signal including the signal carrying the clock to the receiving end through the channel between the transmitting end and the receiving end.

Specifically, when transmitting the transmitting signal, the transmitting end may convert the signal into an optical signal by using the photoelectric conversion module, and send the signal as an optical signal. For example, the photoelectric conversion module may be a laser.

Step 203: When the receiving end receives the received signal, the receiving end performs preset processing on the received signal to obtain a clock signal, where the received signal is a signal transmitted by the transmitting end and transmitted through the channel.

Wherein, when the transmitting end transmits the transmitting signal in the form of an optical signal, the receiving end can convert the optical signal into a corresponding electrical signal through an optical receiver, thereby receiving the received signal.

When the receiving end receives the received signal, the receiving end may filter and lock the received signal into a series of processes to obtain a clock signal. Wherein, when the received signal is filtered, the high frequency part of the received signal can be filtered out, and the direct current component (English: direct current, referred to as DC) is filtered out. For example, When the high frequency portion of the received signal is filtered out, it can be filtered by the low pass filter LPF. In addition, the signal after filtering the high frequency part and the DC component DC can be performed by a phase locked loop (English: phase locked loop, PLL for short) or a clock and data recovery (CDR) circuit. The clock is locked and the clock signal is finally obtained.

It should be noted that the low-pass filtering process at the receiving end can also be replaced by band-pass filtering, and the clock signal can be at the center frequency of the band-pass filter. In addition, the process of performing low-pass filtering processing and filtering DC components at the receiving end may not limit the order.

Specifically, since the CDMA system can be an analog signal system or a digital signal system, and different CDMA systems, the receiving process performed by the receiving end on the received signal is also different, and the following is specifically explained.

If the CDMA system is an analog signal system, as shown in FIG. 8, the receiving end can perform low-pass filtering processing on the received signal through the low-pass filter LPF, and filter out the DC component DC, and then phase through the phase-locked loop PLL or CDR circuit. Lock and convert to a certain clock frequency for output, thus obtaining a clock signal.

If the CDMA system is a digital signal system, as shown in FIG. 9 or FIG. 10, the receiving end may continuously accumulate the received signal or preset the sliding window accumulation processing, and perform low-pass filtering on the processed signal through the low-pass filter LPF. Processing, and filtering out the DC component DC, and then phase-locking through a phase-locked loop PLL or CDR circuit to obtain a clock signal.

9 is a schematic diagram corresponding to the continuous accumulation processing, and the waveform of the signal obtained by the continuous accumulation processing can be as shown in FIG. FIG. 10 is a schematic diagram corresponding to the preset sliding window accumulation processing, and the waveform of the signal obtained by the preset sliding window accumulation processing may be as shown in FIG. 12 .

Further, referring to FIG. 13, if the transmission signal further includes at least one signal of modulated data, the transmitting end transmits a signal for each of the at least one modulated data signal before transmitting the transmission signal to the receiving end through step 202, The method further includes: step 2011-step 2012.

Step 2011: The transmitting end modulates the user data signal by driving the second serial code by the transmitting clock to obtain a signal of the modulated data.

The first sequence code is a sequence code in the preset codeword set, and the preset sequence code set further includes at least one sequence code, and the first sequence code and the at least one sequence code are orthogonal to each other. Each of the at least one sequence code is used to modulate a user data signal, and the second sequence code is a sequence code in at least one of the sequence codes.

That is, the preset sequence code set may include multiple sequence codes, and any two sequence codes in the preset sequence code set are orthogonal to each other, and the first sequence code and the second sequence code are sequence codes in the preset sequence code set. . When the preset sequence code includes a plurality of sequence codes, the first sequence code is used to modulate a signal carrying a clock, at least one sequence code is used to modulate at least one user data signal, and one sequence code is used to modulate a user data signal.

For example, in FIG. 8 and FIG. 9 above, the preset sequence code set may include m sequence codes, m is an integer greater than or equal to 2, the first sequence code may be represented as c1, and at least one sequence code may be represented as c2, c3. , ..., cm, the second serial code may be any one of c2, c3, ..., cm.

Specifically, for the signal of each of the at least one modulated data signal, the transmitting end modulates the user data signal by driving the second serial code to generate a signal of the modulated data. Wherein, when the transmitting end includes multiple user data signals, the transmitting end may separately divide the first sequence by using a preset sequence code set The other sequence codes other than the code respectively modulate the plurality of user data signals according to the above-described step 2011 to obtain signals of a plurality of modulated data, and one user data signal corresponds to one modulated data signal.

Step 2012: The transmitting end superimposes the signal carrying the clock and the signal of the at least one modulated data to obtain the transmitted signal.

Wherein, when the transmitting end modulates the signal carrying the clock and the signal of the at least one modulated data, the transmitting end may superimpose the signal carrying the clock and the signal of the at least one modulated data. For example, the transmitting end may superimpose the signal carrying the clock and the signal of the at least one modulated data through the adder shown in FIG. 8 and FIG. 9 above to obtain the transmitted signal.

Further, when the transmitting signal sent by the transmitting end further includes the signal of the at least one modulated data, the received signal received by the receiving end further includes at least one signal of the modulated data, and after the receiving end obtains the clock signal according to the above step 203, The method also includes: step 204.

Step 204: For each of the modulated data signals of the at least one modulated data signal, the receiving end demodulates the signal of the modulated data included in the received signal by the receiving clock driving the second serial code, and the signal of the modulated data after the demodulation Perform preset processing to obtain user data signals.

The receiving clock is a clock of the receiving end determined by the receiving end according to the clock signal, and the receiving clock is used to drive at least one serial code. Specifically, when the received signal includes a plurality of modulated data signals, the receiving end may separately demodulate the signals of the plurality of modulated data by using the receiving clock to drive the sequence code in the preset sequence code set corresponding to the modulation of the transmitting end. The signal of the demodulated modulated data is subjected to preset processing to obtain a corresponding plurality of user data signals.

In the embodiment of the present application, the device at the transmitting end obtains a signal carrying a clock by driving a first sequence code by sending a clock, where the first sequence code is a sequence code with the same symbol, and between two hop edges of the signal carrying the clock The length of time is an integer multiple of the length of time in which the first sequence code is transmitted, and the length of time of each of the N symbols is equal. The transmitting end modulates the user data by transmitting the clock to drive other serial codes orthogonal to the first sequence code, and superimposes the signal carrying the clock and the modulated data modulated signal, and then transmits the signal to the receiving end device through a channel. After receiving the received signal, the device at the receiving end obtains a clock signal through preset processing, and demodulates the data modulated signal by driving the other corresponding sequence code through the receiving clock determined by the clock signal, thereby obtaining user data. With the method of the embodiment of the present application, the problem that the service data is not interrupted in the transparent transmission system can be solved while providing a clock with higher precision.

The solution provided by the embodiment of the present application is mainly introduced from the perspective of interaction between the devices. It can be understood that each device, such as a transmitting device and a receiving device, etc., in order to implement the above functions, includes hardware structures and/or software modules corresponding to the respective functions. Those skilled in the art will readily appreciate that the present application can be implemented in a combination of hardware or hardware and computer software in conjunction with the network elements and algorithm steps of the various examples described in the embodiments disclosed herein. Whether a function is implemented in hardware or computer software to drive hardware depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present application.

The embodiments of the present application may divide the function modules of the transmitting end device and the receiving end device according to the foregoing method examples. For example, each functional module may be divided according to each function, or two or more functions may be integrated into one processing. In the module. The above integrated modules can be implemented in the form of hardware or It is implemented in the form of a software function module. It should be noted that the division of the module in the embodiment of the present application is schematic, and is only a logical function division, and the actual implementation may have another division manner.

FIG. 14 is a schematic diagram showing a possible structure of a transmitting end device involved in the foregoing embodiment. The transmitting end device 300 includes a modulating unit 301 and a transmitting unit 302. The modulating unit 301 is configured to perform step 201 in FIG. 5 and FIG. 13 and step 2011 and step 2012 in FIG. 13; the transmitting unit 302 is configured to perform step 202 in FIG. 5 and FIG. All the related content of the steps involved in the foregoing method embodiments may be referred to the functional description of the corresponding functional modules, and details are not described herein again.

In hardware implementation, the above modulation unit 301 can be a processor, and the sending unit 302 can be a transmitter, which can form a communication interface with the receiver.

FIG. 15 is a schematic diagram showing a possible logical structure of a transmitting end device 310 involved in the foregoing embodiment provided by the embodiment of the present application. The transmitting device 310 includes a processor 312, a communication interface 313, a memory 311, and a bus 314. The processor 312, the communication interface 313, and the memory 311 are connected to one another via a bus 314. In the embodiment of the present application, the processor 312 is configured to perform control management on the action of the transmitting device 310. For example, the processor 312 is configured to perform step 201 in FIG. 5 or FIG. 13 and steps 2011 and steps in FIG. 2012, and/or other processes for the techniques described herein. The communication interface 313 is used to communicate with the receiving device. The memory 311 is configured to store program codes and data of the transmitting device 310.

The processor 312 can be a central processing unit, a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure. The processor may also be a combination of computing functions, for example, including one or more microprocessor combinations, combinations of digital signal processors and microprocessors, and the like. The bus 314 can be a peripheral component interconnect standard (English: peripheral component interconnect, PCI for short) or an extended industry standard architecture (English: extended industry standard architecture, EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 15, but it does not mean that there is only one bus or one type of bus.

FIG. 16 is a schematic diagram showing a possible structure of the receiving end device involved in the foregoing embodiment. The receiving end device 400 includes: a receiving unit 401 and a demodulating unit 402. . The receiving unit 401 is configured to perform the process of receiving the signal sent by the transmitting end in FIG. 5 and FIG. 13; the demodulating unit 402 is configured to perform step 203 in FIG. 5, FIG. 13, and step 204 in FIG. All the related content of the steps involved in the foregoing method embodiments may be referred to the functional description of the corresponding functional modules, and details are not described herein again.

In hardware implementation, the receiving unit 401 may be a receiver, which may form a communication interface with a transmitter, and the demodulation unit 402 may be a processor.

FIG. 17 is a schematic diagram showing a possible logical structure of the receiving end device 410 involved in the foregoing embodiment provided by the embodiment of the present application. The receiving end device 410 includes a processor 412, a communication interface 413, a memory 411, and a bus 414. The processor 412, the communication interface 413, and the memory 411 are connected to one another via a bus 414. In the embodiment of the present application, the processor 412 is configured to perform control management on the action of the receiving device 410. For example, the processor 412 is configured to perform step 201 in FIG. 5 or FIG. 13 and step 2011 in FIG. 13 and Step 2012, and/or other processes for the techniques described herein. Communication interface 413 is used to communicate with the transmitting device. The memory 411 is configured to store program codes and data of the receiving end device 410.

The processor 412 can be a central processing unit, a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure. The processor may also be a combination of computing functions, for example, including one or more microprocessor combinations, combinations of digital signal processors and microprocessors, and the like. The bus 414 may be a peripheral component interconnect standard (English: interconnected component: PCI) bus or an extended industry standard architecture (English: extended industry standard architecture, EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 17, but it does not mean that there is only one bus or one type of bus.

In another embodiment of the present application, there is provided a computer readable storage medium having stored therein computer executed instructions, when the at least one processor of the device executes the computer to execute an instruction, the device executes the above figure 5. The step of the transmitting end or the step of the receiving end in the clock synchronization method shown in FIG.

In another embodiment of the present application, there is also provided a computer program product comprising computer executed instructions stored in a computer readable storage medium; at least one processor of the device may be The reading storage medium reads the computer execution instructions, and the at least one processor executes the computer execution instructions to cause the device to perform the steps of the transmitting end or the receiving end in the clock synchronization method shown in FIG. 5 or FIG.

In another embodiment of the present application, a passive optical network system is further provided, the system comprising a transmitting end device and a receiving end device. The transmitting device is the transmitting device shown in FIG. 14 or FIG. 15, and/or the receiving device is the receiving device shown in FIG. 16 or FIG. The transmitting end device is configured to perform the step of transmitting end in the clock synchronization method shown in FIG. 5 or FIG. 13; and the receiving end device is configured to perform the step of receiving end in the clock synchronization method shown in FIG. 5 or FIG. 13 .

In the embodiment of the present application, the device at the transmitting end drives the first sequence code by using a sending clock to obtain a signal carrying a clock. The first sequence code is a sequence code with the same symbol, and between two hop edges of the signal carrying the clock. The length of time is an integer multiple of the length of time in which the first sequence code is transmitted, and the length of time of each of the N symbols is equal. The transmitting end modulates the user data by transmitting the clock to drive other serial codes orthogonal to the first sequence code, and superimposes the signal carrying the clock and the modulated data modulated signal, and then transmits the signal to the receiving end device through a channel. After receiving the received signal, the device at the receiving end obtains a clock signal through a preset process, and drives the other corresponding sequence code through the receiving clock determined by the clock signal to demodulate the modulated data signal, thereby obtaining user data. With the method of the embodiment of the present application, the problem that the service data is not interrupted in the transparent transmission system can be solved while providing a clock with higher precision.

Finally, it should be noted that the above description is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be covered in the present application. Within the scope of protection of the application. Therefore, the scope of protection of the present application should be determined by the scope of the claims.

Claims

A clock synchronization method, which is applied to a code division multiple access system, the method comprising:

The transmitting end drives the first sequence code by sending a clock to obtain a signal carrying a clock, and the signal carrying the clock is a square wave signal; wherein the first sequence code includes N symbols; any two of the square wave signals The length of time between the hop edges is an integer multiple of the length of time for transmitting the first sequence code, and the time length of each of the N symbols is equal; the N is greater than or equal to 1. An integer, when the N ≥ 2, the N symbols are the same;

The transmitting end sends a transmitting signal to the receiving end; wherein the transmitting signal includes the signal carrying the clock; and the signal carrying the clock is used to implement clock synchronization between the receiving end and the transmitting end.
The method according to claim 1, wherein the square wave signal has a duty ratio of 50%; or the square wave signal is a data signal.
The method according to claim 1 or 2, wherein the first sequence code is a sequence code in a preset codeword set, the preset sequence code set further includes at least one sequence code, and the a sequence code and the at least one sequence code are orthogonal to each other, each of the at least one sequence code being used to modulate a user data signal;

And the method further includes: before the transmitting end sends the transmitting signal to the receiving end, if the transmitting signal further includes the signal of the at least one modulated data, the method further includes:

And for transmitting, by the transmitting clock, a second sequence code to modulate a user data signal to obtain a signal of modulated data; wherein the second sequence is used for a signal of each of the at least one modulated data signal The code is a sequence code in the at least one sequence code;

The transmitting end superimposes the signal carrying the clock and the signal of the at least one modulated data to obtain the transmitted signal.
A clock synchronization method, which is applied to a code division multiple access system, the method comprising:

The receiving end receives the received signal; wherein the received signal is a signal transmitted by the transmitting end and transmitted by the channel; the received signal includes a signal carrying a clock, and the signal carrying the clock is sent by the transmitting end a clock-driven square wave signal obtained by the first sequence code; the first sequence code includes N symbols, and a length of time between any two transition edges of the square wave signal is a length of transmitting the first sequence code An integer multiple of the length of time, and each of the N symbols has an equal length of time; the N is an integer greater than or equal to 1, and when the N≥2, the N symbols are the same;

The receiving end performs preset processing on the received signal to obtain a clock signal, where the clock signal is used to implement clock synchronization between the receiving end and the transmitting end.
The method according to claim 4, wherein the square wave signal has a duty ratio of 50%; or the square wave signal is a data signal.
The method according to claim 4 or 5, wherein, if the code division multiple access system is a digital signal system, the receiving end performs a preset process on the received signal to obtain a clock signal, including:

The receiving end continuously accumulates the received signal or presets a sliding window accumulation process, a filtering process, and a phase lock process to obtain the clock signal.
The method according to any one of claims 4-6, wherein the first sequence code is a sequence code in a preset codeword set, and the preset sequence code set further includes at least one sequence code, and The first sequence code and the at least one sequence code are orthogonal to each other; each of the at least one sequence code is used to demodulate a data modulated signal;

If the received signal further includes at least one signal of the modulated data, and the receiving end performs a preset process on the received signal to obtain the clock signal, the method further includes:

The receiving end determines a receiving clock according to the clock signal, and the receiving clock is used to drive the at least one sequence code;

For the signal of each of the at least one modulated data signal, the receiving end drives the second sequence code by the receiving clock to demodulate the signal of the modulated data included in the received signal, and after demodulating The signal of the modulated data is subjected to a preset process to obtain a user data signal; wherein the second sequence code is a sequence code in the at least one sequence code.
A transmitting end device is characterized in that it is applied to a code division multiple access system, and the transmitting end device includes:

a modulating unit, configured to drive a first sequence code by using a transmit clock to obtain a signal carrying a clock, where the signal carrying the clock is a square wave signal; wherein the first sequence code includes N symbols; the square wave signal The length of time between any two hop edges is an integer multiple of the length of time at which the first sequence code is transmitted, and the length of time of each of the N symbols is equal; the N is greater than or An integer equal to 1, when the N ≥ 2, the N symbols are the same;

a sending unit, configured to send a transmit signal to the receiving end device, where the transmit signal includes the signal carrying the clock; the signal carrying the clock is used to implement clock synchronization between the receiving end device and the transmitting end device .
The transmitting end device according to claim 8, wherein the square wave signal has a duty ratio of 50%; or the square wave signal is a data signal.
The transmitting end device according to claim 8 or 9, wherein the first sequence code is a sequence code in a preset codeword set, and the preset sequence code set further includes at least one sequence code, and The first sequence code and the at least one sequence code are orthogonal to each other; each of the at least one sequence code is used to modulate a user data signal;

The modulating unit is further configured to, for the signal of each of the at least one modulated data, modulate the user data signal by driving the second sequence code to obtain a signal of the modulated data; The second sequence code is a sequence code in the at least one sequence code;

The modulating unit is further configured to perform superposition processing on the signal carrying the clock and the signal of the at least one modulated data to obtain the transmitted signal.
A receiving end device, which is applied to a code division multiple access system, where the receiving end device includes:

a receiving unit, configured to receive a received signal, where the received signal is a signal transmitted by a transmitting end device and transmitted through a channel; the received signal includes a signal carrying a clock, and the signal carrying the clock is the The transmitting end device transmits a square wave signal obtained by driving the first sequence code by transmitting a clock; the first sequence code includes N symbols, and a length of time between any two transition edges of the square wave signal is An integer multiple of the length of time of the first sequence code, and each of the N symbols The time lengths of the symbol elements are equal; the N is an integer greater than or equal to 1, and when the N≥2, the N symbols are the same;

And a demodulation unit, configured to perform preset processing on the received signal to obtain a clock signal, where the clock signal is used to implement clock synchronization between the receiving end device and the transmitting end device.
The receiving end device according to claim 11, wherein a duty ratio of the square wave signal is 50%; or the square wave signal is a data signal.
The receiving end device according to claim 11 or 12, wherein, if the code division multiple access system is a digital signal system, the demodulating unit is specifically configured to:

The clock signal is obtained by continuously accumulating the received signal or presetting a sliding window accumulation process, a filtering process, and a phase lock process.
The receiving end device according to any one of claims 11 to 13, wherein the first sequence code is a sequence code in a preset codeword set, and the preset sequence code set further includes at least one sequence code. And the first sequence code and the at least one sequence code are orthogonal to each other; each of the at least one sequence code is used to demodulate a data modulated signal;

The demodulation unit is further configured to determine a receiving clock according to the clock signal, where the receiving clock is used to drive the at least one sequence code;

The demodulation unit is further configured to: for the signal of each of the at least one modulated data signal, the second sequence code is driven by the receiving clock to demodulate the signal of the modulated data included in the received signal, Predetermining the signal of the demodulated modulated data to obtain a user data signal; wherein the second sequence code is a sequence code in the at least one sequence code.
An apparatus, comprising: a processor and a memory, the memory storing code and data, the processor being operative to execute code in the memory, the processor for performing claims 1-3 The clock synchronization method according to any one of the preceding claims, or the clock synchronization method according to any one of claims 4-7.
A passive optical network system, characterized in that the system comprises a transmitting end device according to any one of claims 8-10 and a receiving end device according to any one of claims 11-14.