WO2018120780A1

WO2018120780A1 - Method and system for pcie interrupt

Info

Publication number: WO2018120780A1
Application number: PCT/CN2017/093470
Authority: WO
Inventors: 梁康; 朱曦; 肖礼盛; 张琳霞; 刘家家
Original assignee: 深圳开立生物医疗科技股份有限公司
Priority date: 2016-12-27
Filing date: 2017-07-19
Publication date: 2018-07-05
Also published as: CN106681816A

Abstract

Provided are a method and system for a PCIe interrupt. The method comprises: receiving an interrupt request (S110); acquiring a type of an interrupt configured in an FPGA (S120); generating, according to the type of the interrupt, PCIe interrupt data, and determining, according to the type of the interrupt, a transmission interface corresponding to the PCIe interrupt data at a PCIe interface (S130); and transmitting, by means of the transmission interface, the PCIe interrupt data (S140). The method expands compatibility of an FPGA with a processor interrupt. Moreover, respective interrupt functions can be developed and maintained independently, such that the interrupt functions do not interfere with one another and can be developed with less difficulty. Moreover, the present invention facilitates building an FPGA logic platform and ensures building of a platform for a driving layer from a bottom layer.

Description

PCIe interrupt method and system

The present application claims priority to Chinese Patent Application No. PCT Application No. No. No. No. No. No. No. No. No. No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No

Technical field

The embodiments of the present invention relate to the field of communications technologies, and in particular, to a PCIe interrupt method and system.

Background technique

PCIe (Peripheral Component Interconnect Express) is the latest bus and interface standard. This new standard will completely replace the current PCI and AGP, and finally realize the unification of the bus standard.

Pin-based PCI interrupts, also known as INTx interrupts, are often shared between several devices. The core must call every interrupt handler associated with the interrupt, which is less efficient. When the device writes data to the memory and then initiates a pin interrupt, it is possible that the data has not yet reached the memory when the CPU receives the interrupt (the device behind the PCI-PCI bridge is more likely to do so). To ensure that the data has reached memory, the interrupt handler must poll a register of the device that generated the interrupt, and the PCI transaction-preserving rules will ensure that the register will return a value after all data has reached memory.

Each functional device of PCI supports only one pin-based interrupt. The driver often needs to query the device to determine the event that occurs, which reduces the efficiency of interrupt processing. Therefore, the MSI interrupt is used in the PCIe system. The MSI interrupt is not shared, so there is no shared problem in the INTx interrupt. When using MSI, the write operation that generates the interrupt cannot exceed the data write operation, so when the interrupt is generated, the driver can be sure that all data has arrived in memory. The MSI interrupt is implemented by writing a specific value to a specific address, and can support up to 32 interrupt vectors, but the MSI interrupt has a constraint that the interrupt vector number must be consecutive. In order to solve this problem, MSI-X has also been proposed, compared with the MSI Capability register. The MSI-X Capability register uses an array to hold the Message Address field and the Message Data field instead of putting these two fields into the Capability register. Thus, when the PCIE device uses the MSI-X mechanism, each interrupt request can use a separate Message Address field and a Message Data field. MSI-X does not require interrupt vector number continuation and can support up to 2048 interrupt vectors. Different processors have different interpretations of MSI messages sent by PCIE devices. However, when the MCE interrupt request is submitted, the PCIe device writes the Message Data data to the address of the Message Address in the MSI/MSI-X Capability structure to form a memory write TLP, and submits an interrupt request to the processor.

In actual design, the type of interrupt supported by the driver may be one or more of a traditional INTx interrupt, an MSI interrupt, or an MSI-X interrupt. For reasons of ease of development, it is possible that the hardware logic only completes some kind of interrupt that matches it, and discards the other two types of interrupts. This will result in changes in the types of interrupts that may be supported during subsequent driver platform upgrades, resulting in the underlying FPGA developers having to adapt the functions to match the software upgrades, thereby increasing project cycle and maintainability. Conducive to the platform implementation of the project.

Summary of the invention

Embodiments of the present invention provide a PCIe interrupt method and system to extend FPGA compatibility with processor interrupts.

In a first aspect, an embodiment of the present invention provides a PCIe interrupt method, where data communication is implemented between a FPGA and a processor through a PCIe interface, and the method includes:

Receiving an interrupt request;

Obtaining an interrupt type configured in the FPGA, where the interrupt type includes at least one of an INTx interrupt type, an MSI interrupt type, and an MSI-X interrupt type;

Generating PCIe interrupt data according to the interrupt type, and determining, according to the interrupt type, a transport interface corresponding to the PCIe interrupt data on the PCIe interface;

The PCIe interrupt data is transmitted through the transmission interface.

Further, before the step of receiving the interrupt request, the method further includes:

The interrupt type of the FPGA is configured, and the PCIe interface is configured to be a full-type mode, wherein the full-type mode supports all of the interrupt types.

Further, the step of determining, according to the type of the interrupt, the transmission interface corresponding to the PCIe interrupt data includes:

If the interrupt type is MSI-X interrupt, it is determined that the transmission interface is an AXI4-S interface;

If the interrupt type is an MSI interrupt, it is determined that the transport interface is a CFG_INT interface;

If the interrupt type is an INTx interrupt, it is determined that the transport interface is a CFG_INT interface.

Further, when the transmission interface is a CFG_INT interface, the processing timing of sending the PCIe interrupt data through the transmission interface includes: an INTx interrupt execution flow and an MSI interrupt execution flow;

The INTx interrupt execution flow includes:

Set the cfg_interrupt_assert signal and the cfg_interrupt signal of the CFG_INT interface to a high level;

When it is detected that the cfg_interrupt_rdy signal of the CFG_INT interface is set high by the CPU, the cfg_interrupt signal is set to a high level, and the cfg_interrupt_assert signal is set to a low level;

Determining that the CPU responds to the interrupt when the cfg_interrupt_rdy signal is asserted high by the CPU;

The MSI interrupt execution process includes:

Setting the cfg_interrupt signal and the cfg_interrupt_di signal of the CFG_INT interface to the first flag bit;

When the cfg_interrupt_rdy signal of the CFG_INT interface is detected to be set high by the CPU, the cfg_interrupt signal and the cfg_interrupt_di signal are set to the second flag bit as the interrupt request;

When the cfg_interrupt_rdy signal is asserted high by the CPU, it is determined that the CPU responds to the interrupt request.

Further, when the transmission interface is an AXI4-S interface, the processing sequence of sending the PCIe interrupt data through the transmission interface includes:

Set the s_axis_tx_tvalid signal of the AXI4-S interface to a high level, and the s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tlast signals are filled with appropriate data;

When the s_ais_tx_tready signal of the AXI4-S interface is detected to be set high by the CPU, it indicates that the currently transmitted data is received. When s_axis_tx_tlast is set to high level, it indicates that it is the last interrupt data transmission;

When the s_ais_tx_tready signal of the AXI4-S interface is detected to be high by the CPU, indicating that the entire interrupt data transfer is completed, s_axis_tx_tvalid, s_axis_tx_tlast, s_axis_tx_tdata, s_axis_tx_tkeep are set low.

In a second aspect, the embodiment of the present invention further provides a PCIe interrupt system, wherein the FPGA and the processor implement data communication through a PCIe interface, and the system includes: an interrupt control module and a PCIe interface module;

The interrupt control module is configured to receive an interrupt request, acquire an interrupt type configured in the FPGA, generate PCIe interrupt data according to the interrupt type, and determine a transmission interface on the PCIe interface module according to the interrupt type, The interrupt type includes at least one of an INTx interrupt type, an MSI interrupt type, and an MSI-X interrupt type;

The interrupt control module transmits the PCIe interrupt data through the transmission interface.

Further, it also includes:

An interrupt configuration module, configured to configure an interrupt type of the FPGA;

The PCIe interface module is further configured to configure the PCIe interface to be a full-type mode, wherein the full-type mode supports all of the interrupt types.

Further, the interrupt control module is further configured to:

When the interrupt type is an MSI-X interrupt, it is determined that the transmission interface is an AXI4-S interface;

When the interrupt type is an MSI interrupt, determining that the transport interface is a CFG_INT interface;

When the interrupt type is INTx interrupt, it is determined that the transport interface is the CFG_INT interface.

The INTx interrupt execution flow includes:

The MSI interrupt execution process includes:

The embodiment of the invention receives the interrupt request, acquires the configured interrupt type in the FPGA, generates the PCIe interrupt data according to the interrupt type, and determines the transmission interface corresponding to the PCIe interrupt data on the PCIe interface according to the interrupt type; and sends the PCIe interrupt data through the transmission interface. Expanded FPGA compatibility with CPU interrupts. Moreover, each interrupt function can be independently developed and maintained, and has no influence on each other, which reduces the development difficulty, and helps to realize the logical platform construction of the FPGA, and also ensures the platform construction of the driver layer from the bottom layer.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will be implemented BRIEF DESCRIPTION OF THE DRAWINGS The drawings, which are used in the description or the description of the prior art, are briefly described. It is obvious that the drawings in the following description are only some embodiments of the present invention, and no one skilled in the art Other drawings can also be obtained from these drawings.

1 is a flowchart of a PCIe interrupt method according to Embodiment 1 of the present invention;

2 is a schematic structural diagram of a PCIe interrupt system according to Embodiment 1 of the present invention;

3 is a flowchart of a PCIe interrupt method according to Embodiment 2 of the present invention;

4 is a timing diagram of PCIe interrupt processing in Embodiment 2 of the present invention;

FIG. 5 is a timing diagram of PCIe interrupt processing in Embodiment 2 of the present invention; FIG.

6 is a schematic structural diagram of a PCIe interrupt data packet in Embodiment 2 of the present invention;

7 is a schematic structural diagram of a PCIe interrupt system according to Embodiment 3 of the present invention;

FIG. 8 is a schematic structural diagram of a PCIe interrupt system according to another example in Embodiment 3 of the present invention.

detailed description

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. It should also be noted that, for ease of description, only some, but not all, of the structures related to the present invention are shown in the drawings.

Embodiment 1

1 is a flowchart of a method for interrupting a PCIe according to a first embodiment of the present invention. The present embodiment is applicable to a PCIe interrupt. The method may be implemented by a PCIe interrupt system in the embodiment of the present invention. / or hardware implementation. For a system with some kind of function, it usually includes a CPU processor, which is the core device that responds to various computing processing requirements. The system may also include various peripherals such as a keyboard, mouse, display, ultrasound probe or memory, and the like. In the solution of the embodiment of the present invention, an FPGA (Field-Programmable Gate Array) is provided, which is disposed between the peripheral device and the processor CPU, and the auxiliary peripheral device initiates an interrupt request to the CPU, or The FPGA acquires the data in the CPU, sends an interrupt to the CPU, and asks the CPU to perform data processing for itself. Data communication between the FPGA and the CPU is performed through the PCIe interface.

As shown in FIG. 1 , the method specifically includes the following steps:

S110. Receive an interrupt request.

This interrupt request acts as an internal interrupt request for the FPGA and is an operation prompt to start interrupting the data transfer. The normal data is data that needs to be processed by a processor. The specific process is: the peripheral device acquires common data (if the peripheral device is an ultrasonic probe, the ordinary data can be an ultrasonic signal), and the data is transmitted to the FPGA, and the FPGA includes a data transmission module and a receiving module. The receiving module is configured to receive normal data transmitted by the peripheral device, and the data transmission module is configured to send the normal data acquired by the peripheral device to the memory through the AXI4-S interface. The memory and processor belong to the same device, the processor is responsible for computing and processing, and the memory is responsible for data exchange. After the data transmission module transmits all the data to the memory, the data transmission module sends the prompt information that the data has been completely transmitted to the memory, and the receiving module receives the prompt information. The interrupt request in this embodiment refers to the data transmission module transmitting data to the memory. After the data transmission is completed, the receiving module receives the prompt information that the data transmission is completed, that is, the interrupt request.

S120. Acquire an interrupt type configured in the FPGA, where the interrupt type includes at least one of an INTx interrupt type, an MSI interrupt type, and an MSI-X interrupt type.

The interrupt type configured in the FPGA is that the FPGA selects an interrupt type that the processor can process according to an interrupt type that the processor can process. If there is more than one interrupt type that satisfies the interrupt type that the processor can handle, the optimal interrupt type is selected (the MSI-X interrupt type is better than the MSI interrupt type, and the MSI interrupt type is better than the INTx interrupt type). The interrupt type configured in the FPGA may be an INTx interrupt type and an MSI interrupt type, or may be an INTx interrupt type, an MSI interrupt type, and an MSI-X interrupt type, and may also be an INTx interrupt type and an MSI-X interrupt type. This embodiment does not limit this.

S130. Generate PCIe interrupt data according to the interrupt type, and determine, according to the interrupt type, a transport interface corresponding to the PCIe interrupt data on the PCIe interface.

The transmission interface is configured to transmit interrupt data, and the interrupt data is used to notify the processor that normal data transmission is completed. Because the interrupt type is different, the corresponding PCIe interrupt data is also different, so it is necessary to generate corresponding PCIe interrupt data according to the interrupt type. The interrupt data may be the information defined by the device memory PCIe standard, or may be the address of the interrupt vector, which is not limited in this embodiment. The transmission interfaces corresponding to the different types of interrupts are also different. Therefore, the transmission interface corresponding to the PCIe interrupt data on the PCIe interface needs to be determined according to the type of the interrupt. For example, if the interrupt type is INTx interrupt type, the corresponding transport interface is the CFG_INT interface; if the interrupt type For the MSI-X interrupt type, the corresponding transport interface is the AXI4-S interface.

Specifically, the interrupt transmission interfaces corresponding to various interrupt types are as follows:

S140. Send the PCIe interrupt data by using the transmission interface.

The processor starts the interrupt operation after receiving the PCIe interrupt data.

In a specific example, if the peripheral device is an ultrasonic probe, the ultrasonic probe acquires an ultrasonic signal that needs to be processed by the processor, and transmits the ultrasonic signal to the FPGA, and the data transmission unit in the FPGA transmits the ultrasonic signal to the AXI4-S interface. After the data transfer is completed, the data transfer unit sends a prompt message for completing the data transfer to the receiving module, that is, sends an interrupt request to the receiving module of the FPGA. As shown in FIG. 2, the PCIe interrupt system includes an interrupt configuration module and an interrupt processing module. After the FPGA receives the information that the ultrasonic signal has been completely transmitted to the memory, the driver layer acquires the type of interrupt that the processor can handle, and the interrupt configuration module configures the corresponding interrupt type, and the interrupt processing module configures the corresponding transmission interface according to the type of interrupt that the processor can handle. The PCIe interrupt data corresponding to the interrupt type is sent to the PCIe IP core through the corresponding transport interface, and the PCIe IP core sends the data to the PCIe root controller in the processor. In turn, the processor interrupt request is sent to the processor to implement the interrupt operation. The PCIe root controller acts as a hub for connecting CPU/memory and external devices. The root controller is at the core of the entire PCIe architecture. It is the topmost layer of the I/O hierarchy system connected to the CPU/memory system. A root controller can support one or more PCIe ports. Each port defines a separate domain, each domain consisting of a single terminal, or a subsystem containing one or more switches and terminals. At the same time, according to the agreement, the root controller can support the function of packet routing between different domains according to specific choices.

The technical solution of the embodiment receives the internal interrupt request through the FPGA, acquires the configured interrupt type in the FPGA, generates the PCIe interrupt data according to the interrupt type, and determines the transmission interface corresponding to the PCIe interrupt data on the PCIe interface according to the interrupt type; Send PCIe interrupt data. Extends FPGA compatibility with processor interrupts. Moreover, each interrupt function can be independently developed and maintained, and has no influence on each other, which reduces the development difficulty, and helps to realize the logical platform construction of the FPGA, and also ensures the platform construction of the driver layer from the bottom layer.

Embodiment 2

3 is a schematic flowchart of a PCIe interrupt method according to Embodiment 2 of the present invention. On the basis of the foregoing embodiment, before the step of receiving an interrupt request, the method further includes: configuring an interrupt type of the FPGA, and configuring The PCIe interface is a full type mode, wherein the full type mode supports all of the interrupt types.

As shown in FIG. 3, the method in this embodiment specifically includes the following steps:

S210. Configure an interrupt type of the FPGA, and configure the PCIe interface to be a full-type mode, where the full-type mode supports all the interrupt types.

The interrupt type of the FPGA may be an INTx interrupt type, an MSI interrupt type, or an MSI-X interrupt type. The FPGA configures an interrupt type of the FPGA according to an interrupt type that the CPU can process. For example, the interrupt type that the CPU can process is the INTx interrupt type, and the interrupt type of the FPGA is configured as the INTx interrupt type.

Specifically, the full-type mode is a data transmission that can support an INTx interrupt type, an MSI interrupt type data transmission, and an MSI-X interrupt type data transmission.

Specifically, since the INTx interrupt type, the MSI interrupt type, and the MSI-X interrupt type require different transport interfaces, if the FPGA needs to support all interrupt types, multiple transport interfaces need to be configured, in different interrupt types. In case of data transfer using different transport interfaces. This ensures that regardless of whether the interrupt type of the external device is INTx interrupt type, MSI interrupt type or MSI-X interrupt type, the FPGA can provide the corresponding transmission interface as needed.

S220. Receive an interrupt request.

Specifically, first explain the data exchange process between the FPGA and the CPU, taking the most common FPGA upload data to DDR (Double Data Rate, Double Rate Synchronous Dynamic Random Access Memory) as an example. When the FPGA side wants to upload data to the main memory device on the CPU side, in order to reduce the CPU load, the DMU (Direct Memory Unit) module is usually placed on the FPGA side. At the first moment, the DMU is idle, waiting for the CPU configuration. The DMU module, wherein the configuration parameters include information such as transmission data length, destination address, channel number, and interrupt enable. The data transmission module in the FPGA uploads data to the CPU DDR main memory through the PCIe interface through DMA (Direct Memory Access), and the data transmission module sends the data transmission module to the receiving module in the FPGA. Internal interrupt request, the receiving module in the FPGA will receive an internal interrupt request.

S230. Acquire an interrupt type configured in the FPGA, where the interrupt type includes at least one of an INTx interrupt type, an MSI interrupt type, and an MSI-X interrupt type.

S240. Generate PCIe interrupt data according to the interrupt type, and determine, according to the interrupt type, a transport interface corresponding to the PCIe interrupt data on the PCIe interface.

Optionally, the step of determining, according to the type of the interrupt, the transmission interface corresponding to the PCIe interrupt data includes:

The MSI interrupt request is to write the data contained in the Message Data field to the address where the Message Address is located. The MSI-X interrupt mechanism stores a pointer to a set of Message Address and Message Data fields in the MSI-X Capablity structure, so that a PCIe device can support more than 32 MSI-X interrupt requests and does not require an interrupt vector. The number is continuous. The set of Message Address and Message Data fields used by the MSI-X mechanism are stored in the BAR space of the PCIe device, rather than in the configuration space of the PCIe device, so that the number of MSI-X interrupt requests can be determined by the user.

S250. Send the PCIe interrupt data by using the transmission interface.

Specifically, the data transfer completion needs to perform Interrupt interrupt request processing. The interrupt vector table corresponding to the MSI-X interrupt type exists in User Logic, and the User terminal can only be implemented by sending the MWr TLP packet containing the interrupt information, so the MSI-X interrupt must pass. Operate the AXI4-S interface implementation. The MSI interrupt type is stored in the PCIe Capability Structure and can be implemented by sending a MWr TLP packet or by operating the CFG_INT interface. The INTx interrupt type must be implemented by manipulating the CFG_INT interface. The detailed processing flow of Interrupt is as follows: CPU configures the interrupt type; enables the corresponding module according to the configuration type; when the interrupt request comes, the enabled module executes the corresponding interrupt flow; the interrupt execution is completed, the idle state is returned, and the next interrupt is awaited. operating.

Optionally, when the transmission interface is a CFG_INT interface, the processing timing of sending the PCIe interrupt data through the transmission interface includes: an INTx interrupt execution flow and an MSI interrupt execution flow;

The INTx interrupt execution flow includes:

Set the cfg_interrupt_assert signal and cfg_interrupt signal of the CFG_INT interface High level;

Specifically, the interrupt is committed by configuring the interfaces cfg_interrupt and cfg_interrupt_assert. When a valid interrupt is received, cfg_interrupt_rdy is asserted, indicating that the interrupt request is accepted.

Specifically, as shown in FIG. 4, the position shown in 2 in the figure is that the INTx interrupt request is received, and at the rising edge of the clock output, the interrupt set signal (cfg_interrupt_assert signal), the interrupt request signal (cfg_interrupt signal), and the interrupt response signal ( The cfg_interrupt_rdy signal) is high. The position shown in Figure 3 is to release the INTx interrupt request. On the rising edge of the clock output, the interrupt request signal (cfg_interrupt signal) is high, the interrupt set signal (cfg_interrupt_assert signal) is low, and the interrupt response signal (cfg_interrupt_rdy) The signal) is high and it is determined that the CPU responds to the INTx interrupt request.

The MSI interrupt execution process includes:

The cfg_interrupt signal and the cfg_interrupt_di signal of the CFG_INT interface are set to a first flag, and the cfg_interrupt signal is set high and the cfg_interrupt_di signal is set to 01h.

The cfg_interrupt signal and the cfg_interrupt_di signal are set to the second flag bit to set the cfg_interrupt signal and set the cfg_interrupt_di signal to 00h.

Specifically, as shown in FIG. 4, the position shown in FIG. 5 is that the MSI interrupt request is received. On the rising edge of the clock output, the interrupt request signal (cfg_interrupt signal) of the CFG_INT interface is high, and the input data signal is interrupted (cfg_interrupt_di). The signal) is 01h and the interrupt response signal (cfg_interrupt_rdy signal) is high. The position shown in Figure 4 is to release the MSI interrupt request. On the rising edge of the clock output, the interrupt request signal (cfg_interrupt signal) of the CFG_INT interface is high, the interrupt input data signal (cfg_interrupt_di signal) is 00h, and the interrupt response signal ( The cfg_interrupt_rdy signal) is high, and it is determined that the CPU responds to the MSI interrupt request.

Optionally, when the transmission interface is an AXI4-S interface, the processing sequence for sending the PCIe interrupt data by using the transmission interface includes:

Specifically, the ASI4-S complies with the standard AXI4-Stream specification, in which the interrupt address and interrupt data are included in the data packet, and are pre-RC configured to the FPGA internal module. The packet format needs to comply with the PCIe TLP data structure provided by Xilinx.

Specifically, the data transmission between the PCIe core and the PCIe Root Complex is implemented through the AXI4-S interface.

Specifically, as shown in FIG. 5, the position shown in FIG. 1 is the AXI4-S interface data transmission completion. On the rising edge of the clock output, s_axis_tx_tvalid, s_axis_tx_tlast, and s_axis_tx_tready are high, indicating that the transmission is completed.

As shown in Figure 6, the packet format follows the PCIe TLP data structure provided by Xilinx, where the transport type field (TC field) defines the transport type of the message, the TD bit indicates whether the TLP Digest in the TLP is valid, and the EP bit indicates the current TLP. Whether the data in the message is valid, the message model field defines the message Model, the payload of the message (Length), that is, the number of double words (DW) to be read. The first tag consists of eight bits, which determines that the sender can temporarily store 256 TLPs of the same type. The application layer needs to be based on The payload and address of the message, and the completion message is used to return the corresponding data.

In the technical solution of the embodiment, the interrupt type of the FPGA is configured, and the PCIe interface is configured to be a full-type mode, wherein the full-type mode supports all the interrupt types. It can guarantee that no matter what type of CPU (ARM, x86, PowerPC, etc.) is used on the CPU side, no matter which type of interrupt (INTx, MSI, MSI-X) is supported, the FPGA side can support and enhance the FPGA pair. The compatibility of the interrupt type realizes the consistency of the interface and the standardization of the interrupt processing between the CPU and the PCIe, and at the same time, the FPGA platform construction can be improved.

Embodiment 3

FIG. 7 is a schematic structural diagram of a PCIe interrupt system according to Embodiment 3 of the present invention, where the system is configured to execute a PCIe interrupt method. As shown in FIG. 7, the data communication is implemented between the FPGA and the processor through the PCIe interface. The PCIe interrupt system specifically includes an interrupt control module 310 and a PCIe interface module 320.

The interrupt control module 310 is configured to receive an interrupt request, acquire an interrupt type configured in the FPGA, generate PCIe interrupt data according to the interrupt type, and determine the PCIe interface module 320 according to the interrupt type. Transmission interface, wherein the interrupt type includes at least one of an INTx interrupt type, an MSI interrupt type, and an MSI-X interrupt type;

The interrupt control module 310 transmits the PCIe interrupt data through the transmission interface.

Optionally, as shown in FIG. 8, the method further includes: an interrupt configuration module 330, configured to configure an interrupt type of the FPGA. The PCIe interface module is further configured to configure the PCIe interface to be a full-type mode, wherein the full-type mode supports all of the interrupt types.

Optionally, the interrupt control module is further configured to:

The INTx interrupt execution flow includes:

The MSI interrupt execution process includes:

The technical solution of the embodiment receives the interrupt request, acquires the configured interrupt type in the FPGA, generates the PCIe interrupt data according to the interrupt type, and determines the transmission interface corresponding to the PCIe interrupt data on the PCIe interface according to the interrupt type; and sends the PCIe through the transmission interface. Interrupt data. Expanded FPGA compatibility with processor interrupts. And each interrupt function can be independently developed and maintained, and each other There will be no impact between them, which will reduce the development difficulty, and help to realize the logical platform construction of FPGA, and also ensure the platform construction of the driver layer from the bottom.

The above product can perform the method provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

Note that the above are only the preferred embodiments of the present invention and the technical principles applied thereto. Those skilled in the art will appreciate that the invention is not limited to the specific embodiments described herein, and that various modifications, changes and substitutions may be made without departing from the scope of the invention. Therefore, the present invention has been described in detail by the above embodiments, but the present invention is not limited to the above embodiments, and other equivalent embodiments may be included without departing from the inventive concept. The scope is determined by the scope of the appended claims.

Claims

A PCIe interrupt method, the data communication between the FPGA and the processor through the PCIe interface, characterized in that the method comprises the following steps:

Receiving an interrupt request;

Obtaining an interrupt type configured in the FPGA, where the interrupt type includes at least one of an INTx interrupt type, an MSI interrupt type, and an MSI-X interrupt type;

Generating PCIe interrupt data according to the interrupt type, and determining, according to the interrupt type, a transport interface corresponding to the PCIe interrupt data on the PCIe interface;

The PCIe interrupt data is transmitted through the transmission interface.
The method according to claim 1, wherein before the step of receiving the interrupt request, the method further comprises:

The interrupt type of the FPGA is configured, and the PCIe interface is configured to be a full-type mode, wherein the full-type mode supports all of the interrupt types.
The method according to claim 1, wherein the step of determining the transmission interface corresponding to the PCIe interrupt data according to the type of the interrupt comprises:

If the interrupt type is MSI-X interrupt, it is determined that the transmission interface is an AXI4-S interface;

If the interrupt type is an MSI interrupt, it is determined that the transport interface is a CFG_INT interface;

If the interrupt type is an INTx interrupt, it is determined that the transport interface is a CFG_INT interface.
The method according to claim 3, wherein when the transmission interface is a CFG_INT interface, the processing timing of transmitting the PCIe interrupt data through the transmission interface comprises: an INTx interrupt execution flow and an MSI interrupt execution flow;

The INTx interrupt execution flow includes:

Set the cfg_interrupt_assert signal and the cfg_interrupt signal of the CFG_INT interface to a high level;

When it is detected that the cfg_interrupt_rdy signal of the CFG_INT interface is set high by the CPU, the cfg_interrupt signal is set to a high level, and the cfg_interrupt_assert signal is set to a low level;

Determining the CPU response when the cfg_interrupt_rdy signal is asserted high by the CPU The interruption

The MSI interrupt execution process includes:

Setting the cfg_interrupt signal and the cfg_interrupt_di signal of the CFG_INT interface to the first flag bit;

When the cfg_interrupt_rdy signal of the CFG_INT interface is detected to be set high by the CPU, the cfg_interrupt signal and the cfg_interrupt_di signal are set to the second flag bit as the interrupt request;

When the cfg_interrupt_rdy signal is asserted high by the CPU, it is determined that the CPU responds to the interrupt request.
The method according to claim 3, wherein when the transmission interface is an AXI4-S interface, the processing sequence of transmitting the PCIe interrupt data through the transmission interface comprises:

Set the s_axis_tx_tvalid signal of the AXI4-S interface to a high level, and the s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tlast signals are filled with appropriate data;

When the s_ais_tx_tready signal of the AXI4-S interface is detected to be set high by the CPU, it indicates that the currently transmitted data is received. When s_axis_tx_tlast is set to high level, it indicates that it is the last interrupt data transmission;

When the s_ais_tx_tready signal of the AXI4-S interface is detected to be high by the CPU, indicating that the entire interrupt data transfer is completed, s_axis_tx_tvalid, s_axis_tx_tlast, s_axis_tx_tdata, s_axis_tx_tkeep are set low.
A PCIe interrupt system, wherein the FPGA and the processor implement data communication through a PCIe interface, and the method comprises: an interrupt control module and a PCIe interface module;

The interrupt control module is configured to receive an interrupt request, acquire an interrupt type configured in the FPGA, generate PCIe interrupt data according to the interrupt type, and determine a transmission interface on the PCIe interface module according to the interrupt type, The interrupt type includes at least one of an INTx interrupt type, an MSI interrupt type, and an MSI-X interrupt type;

The interrupt control module transmits the PCIe interrupt data through the transmission interface.
The system of claim 6 further comprising:

An interrupt configuration module, configured to configure an interrupt type of the FPGA;

The PCIe interface module is further configured to configure the PCIe interface to be a full-type mode, wherein the full-type mode supports all of the interrupt types.
The system of claim 6 wherein said interrupt control module is further configured to:

When the interrupt type is an MSI-X interrupt, it is determined that the transmission interface is an AXI4-S interface;

When the interrupt type is an MSI interrupt, determining that the transport interface is a CFG_INT interface;

When the interrupt type is INTx interrupt, it is determined that the transport interface is the CFG_INT interface.
The system according to claim 8, wherein when the transmission interface is a CFG_INT interface, the processing timing of transmitting the PCIe interrupt data through the transmission interface comprises: an INTx interrupt execution flow and an MSI interrupt execution flow;

The INTx interrupt execution flow includes:

Set the cfg_interrupt_assert signal and the cfg_interrupt signal of the CFG_INT interface to a high level;

When it is detected that the cfg_interrupt_rdy signal of the CFG_INT interface is set high by the CPU, the cfg_interrupt signal is set to a high level, and the cfg_interrupt_assert signal is set to a low level;

Determining that the CPU responds to the interrupt when the cfg_interrupt_rdy signal is asserted high by the CPU;

The MSI interrupt execution process includes:

Setting the cfg_interrupt signal and the cfg_interrupt_di signal of the CFG_INT interface to the first flag bit;

When the cfg_interrupt_rdy signal of the CFG_INT interface is detected to be set high by the CPU, the cfg_interrupt signal and the cfg_interrupt_di signal are set to the second flag bit as the interrupt request;

When the cfg_interrupt_rdy signal is asserted high by the CPU, it is determined that the CPU responds to the interrupt request.
The system according to claim 8, wherein when the transmission interface is an AXI4-S interface, the processing sequence for transmitting the PCIe interrupt data through the transmission interface comprises:

Set the s_axis_tx_tvalid signal of the AXI4-S interface to high level, s_axis_tx_tdata, The s_axis_tx_tkeep, s_axis_tx_tlast signals are filled with appropriate data;

When the s_ais_tx_tready signal of the AXI4-S interface is detected to be set high by the CPU, it indicates that the currently transmitted data is received. When s_axis_tx_tlast is set to high level, it indicates that it is the last interrupt data transmission;

When the s_ais_tx_tready signal of the AXI4-S interface is detected to be high by the CPU, indicating that the entire interrupt data transfer is completed, s_axis_tx_tvalid, s_axis_tx_tlast, s_axis_tx_tdata, s_axis_tx_tkeep are set low.