WO2018107681A1

WO2018107681A1 - Processing method, device, and computer storage medium for queue operation

Info

Publication number: WO2018107681A1
Application number: PCT/CN2017/088613
Authority: WO
Inventors: 赵培培; 王闯; 闫振林; 孟雄飞
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2016-12-13
Filing date: 2017-06-16
Publication date: 2018-06-21
Also published as: CN108234348B; CN108234348A

Abstract

Embodiments of the present invention disclose a processing method for a queue operation, comprising: obtaining a queue number of a queue including message information to be processed; querying, in a mapping table, storage location information and address information of a queue descriptor corresponding to the queue number; obtaining, according to the storage location information and the address information of the queue descriptor, the queue descriptor, moving the queue descriptor to a register, and updating, in the mapping table, the storage location information and the address information of the queue descriptor corresponding to the queue number; and performing, according to the queue descriptor, a queue operation on the message information to be processed, and updating, according to the storage location information and the address information of the queue descriptor and the updated queue descriptor, the queue descriptor after the queue operation is performed. The present invention further discloses a processing device and computer storage medium for a queue operation.

Description

Processing method, device and computer storage medium in queue operation

Cross-reference to related applications

The present application is filed on the basis of the Chinese Patent Application No. 201611158994.5, the entire disclosure of which is hereby incorporated by reference.

Technical field

The present invention relates to the field of Internet technologies, and in particular, to a processing method and apparatus in a queue operation and a computer storage medium.

Background technique

In a network device, such as a Network Processor (NP), a Fabric Access Processor (FAP), a switch, a bridge, or a traffic management chip, a queue management function is integrated, and packets are processed by a queue. With the growth of the business, the number of queues that the network device needs to support increases exponentially, and the queues that have reached the storage capacity of 512K or more are increased. The difficulty of queue management for a large number of high-density queues increases, and the identifiers of queues and queues increase. That is, the storage of the Queue Descriptor (QD) requires a large amount of storage capacity. Under the premise of ensuring performance, reducing the cost of the chip is a problem that must be considered.

In the prior art, the prior patent documents describe the use of a low-cost, large-capacity, high-density off-chip cache, Dynamic Random Access Memory (DRAM), to compensate for on-chip buffers - static random access memory (SRAM, Static). Random Access Memory) The problem of insufficient storage capacity due to storage of high-density queues and QDs. For example, the patent document US008180966B2 "System and method for operating a packet buffer in an intermediate node" provides a message data buffering method, which uses DRAM bonding. A small-capacity, high-speed on-chip cache (Cache) is used to store queues and QDs, which solves the problem of insufficient Cache storage capacity. Each queue has independent storage space in the Cache. The Cache stores the fragmentation of the first packet of several queues, and the QD is also stored in the Cache. The remaining fragments and tail fragments of the queue are stored in the DRAM. When a new packet is enqueued, the packet fragment is written to the tail of the corresponding queue stored in the DRAM; when the new packet is dequeued, the first packet of the corresponding queue stored in the Cache is read for dequeuing, if stored. If the packets in the Cache are all dequeued, the newly enqueued packets will be stored in the Cache, or the packets stored in the DRAM will be moved to the Cache.

Although the above method compensates for the shortage of storage capacity due to the SRAM storage queue and QD to some extent, for high-density queues, QD storage also needs to consume a large amount of storage space, for example, the number of queues with 1M storage capacity, each The QD storage capacity of the queue needs 80bit, and the SRAM of 80Mbit storage capacity is required. If all the QDs are stored in the Cache, the implementation cost is huge under the existing process. Therefore, in the queue operation, the QD is stored and The processing method needs to be improved. An improved storage processing method for QD is proposed in the patent document US Pat. No. 7,277,990, "Method and apparatus providing efficient queue descriptor memory access". In the improved method, the QD is stored in the Cache or the DRAM, and the Content Addressable Memory (CAM) is triggered by the enqueue request to query whether the QD is stored in the Cache. If the query is obtained, the CAM returns the QD in the Cache. The storage address in the memory reads the QD from the corresponding storage address of the Cache; if not, the QD is read from the DRAM, and the CAM will release a QD tag that is unrelated to the trigger operation, and the vacated QD tag table The item stores the newly moved QD tag, and the discharged QD is moved from the Cache to the DRAM. However, there are three problems in this method. First, the read/write bandwidth of the CAM cannot be arbitrarily expanded. When the CAM is frequently written, the queue number maintained by the CAM frequently changes, which inevitably affects the efficiency of CAM retrieval. Second, The CAM of the same capacity occupies a larger area than the Cache, and the power consumption is larger. The CAM cannot support enough QD tags at the same time, so the number of QDs placed in the Cache It will be affected by CAM capacity. Third, high-speed and high-performance traffic management requires on-chip QD storage with large capacity and large operating bandwidth. Cache cannot support large capacity and large read/write bandwidth at the same time. It can be seen that in the queue operation, the method requires frequent access to the Cache and the DRAM to acquire the QD, thereby resulting in low access efficiency of the QD.

Therefore, in order to solve the problem of low QD access efficiency in queue operations, it is urgent to find a processing method in queue operation.

Summary of the invention

In order to solve the existing problems, the embodiment of the present invention is to provide a processing method, a device, and a computer storage medium in a queue operation, which can improve the access efficiency of the QD in the queue operation and realize the fast access of the QD.

In order to achieve the above object, the technical solution of the present invention is achieved as follows:

An embodiment of the present invention provides a processing method in a queue operation, where the method includes:

Obtain the queue number of the queue to which the packet information to be processed belongs.

Querying, in the mapping table, storage location information and address information of the queue descriptor corresponding to the queue number;

Obtaining a queue descriptor according to the storage location information and the address information of the queue descriptor, moving the queue descriptor to a register, and updating storage location information of the queue descriptor corresponding to the queue number in the mapping table and Address information;

Performing a queue operation on the to-be-processed message information according to the queue descriptor, and after performing the queue operation, according to the queue descriptor, the updated storage location information and the address information of the queue descriptor, The queue descriptor is updated.

In an embodiment, the performing queue operation on the to-be-processed message information according to the queue descriptor includes:

And determining, according to the preset congestion avoidance policy, the packet information to be processed according to the queue descriptor, and the packet information to be processed according to the queue descriptor. Carry in the operation; or,

Dequeuing the packet information to be processed according to the queue descriptor.

In an embodiment, when the queue operation is an enqueue operation, the queue operation is performed according to the queue descriptor, and the queue descriptor is used according to the queue descriptor. And the storage location information and the address information after the queue descriptor is updated, and updating the queue descriptor, including:

Applying a message cache pointer to the dynamic random access memory;

And storing, according to the message buffer pointer, the to-be-processed message information and the message cache pointer into the dynamic random access memory;

Updating the queue descriptor according to the message cache pointer and the message information of the enqueue operation, and storing the updated queue descriptor in the target address, where the target address is updated after the queue descriptor is updated The storage location information and the address determined by the address information.

In an embodiment, when the queue operation is a dequeuing operation, the queue operation is performed according to the queue descriptor, and the queue descriptor is used according to the queue descriptor. And the storage location information and the address information after the queue descriptor is updated, and updating the queue descriptor, including:

Decoding the to-be-processed message information and the next queued message buffer pointer in the dynamic random access memory according to the queue descriptor, and dequeuing the to-be-processed message information;

A message buffer pointer for releasing the dequeued message information;

Updating the queue descriptor according to the next message buffer pointer being queued and the message information of the dequeued operation, and storing the updated queue descriptor in a target address, where the target address is The stored location information and the address determined by the address information after the queue descriptor is updated.

In an embodiment, after the updating the queue descriptor, the method further includes:

Detecting the queue number of the queue corresponding to the queue descriptor before the update;

When the queue number of the queue descriptor corresponding to the updated queue is inconsistent with the queue number of the queue corresponding to all the queue descriptors before the update, the updated queue descriptor stored in the register is moved to the cache memory. ;

The storage location information and the address information of the updated queue descriptor corresponding to the queue number in the mapping table are updated.

In an embodiment, the method further includes:

Detecting the space usage of the cache memory in real time, and obtaining a first detection result;

When the first detection result is greater than the preset first threshold, the queue descriptor of the queue stored in the cache and having the activity less than the preset second threshold is moved to the dynamic random access memory;

A pointer to the queue descriptor that is moved out of the cache is released.

In an embodiment, the method further includes:

Real-time detecting the space usage of the register to obtain a second detection result;

When the second detection result is greater than the preset third threshold, the message descriptor in the to-be-processed message information and the message information to be processed are stopped from being queued until the second detection result is less than the preset. The fourth threshold is restored, and the message descriptor in the to-be-processed message information and the message information to be processed are resumed, and the preset fourth threshold is smaller than the preset third. Threshold.

The embodiment of the present invention further provides a processing device in a queue operation, where the device includes: an obtaining module, a query module, a first moving module, and a first processing module;

The acquiring module is configured to obtain a queue number of a queue to which the packet information to be processed belongs;

The query module is configured to query, in the mapping table, storage location information and address information of the queue descriptor corresponding to the queue number;

The first moving module is configured to store location information and a ground according to the queue descriptor Address information, obtaining a queue descriptor, moving the queue descriptor into a register, and updating storage location information and address information of the queue descriptor corresponding to the queue number in the mapping table;

The first processing module is configured to perform a queue operation on the to-be-processed message information according to the queue descriptor, and after the queue operation, update the storage according to the queue descriptor and the queue descriptor. Location information and address information are updated for the queue descriptor.

In an embodiment, the first processing module is configured to determine, according to the preset congestion avoidance policy, that the to-be-processed packet information is enqueued according to the queue descriptor and the queue number, according to the The queue descriptor performs the enqueue operation on the to-be-processed packet information; or performs the dequeuing operation according to the packet information to be processed according to the queue descriptor.

In an embodiment, when the queue is operated as a queue operation, the first processing module includes: an application unit, a storage unit, and a first update unit;

The application unit is configured to apply for a message cache pointer to the dynamic random access memory;

The storage unit is configured to store the to-be-processed message information and the message cache pointer in the dynamic random access memory according to the message buffer pointer;

The first update unit is configured to update the queue descriptor according to the message cache pointer and the message information of the queued operation, and store the updated queue descriptor in the target address, the target The address is an address determined by the storage location information and the address information after the queue descriptor is updated.

In an embodiment, when the queue operation is a dequeuing operation, the first processing module includes: a reading unit, a releasing unit, and a second updating unit; wherein

The reading unit is configured to read the to-be-processed message information and the next queued message buffer pointer in the dynamic random access memory according to the queue descriptor, and the to-be-processed message information Carry out the team;

The release unit is configured to release a message cache pointer of the dequeued message information;

The second update unit is configured to cache a pointer according to the next queued message And the message information of the dequeued operation, updating the queue descriptor, and storing the updated queue descriptor in a target address, where the target address is updated storage location information of the queue descriptor and The address determined by the address information.

In an embodiment, the device further includes: a first detecting module, a second moving module, and an update mapping table module; wherein

The first detecting module is configured to detect a queue number of a queue corresponding to the queue descriptor before the update;

The second moving module is configured to: when the queue number of the updated queue descriptor corresponding queue is different from the queue number of the queue queue corresponding to all the updated queue descriptors, the updated content stored in the register The queue descriptor is moved to the cache;

The update mapping table module is configured to update storage location information and address information of the updated queue descriptor corresponding to the queue number in the mapping table.

In an embodiment, the device further includes: a second detecting module, a third moving module, and a releasing module; wherein

The second detecting module is configured to detect a space usage of the cache memory in real time, and obtain a first detection result;

The third moving module is configured to: when the first detection result is greater than a preset first threshold, a queue description of a queue that is stored in the cache and whose activity is less than a preset second threshold Move to dynamic random access memory;

The release module is configured to release a pointer that moves out of the cache descriptor of the cache.

In the above device, the device further includes: a third detecting module and a second processing module; wherein

The third detecting module is configured to detect a space usage of the register in real time, and obtain a second detection result;

The second processing module is configured to: when the second detection result is greater than a preset third threshold, And stopping to output the message descriptor in the to-be-processed message information and the message information to be processed, and performing the enqueuing operation until the second detection result is less than the preset fourth threshold, and outputting the to-be-processed report. The message descriptor in the text information and the message information to be processed are enqueued, and the preset fourth threshold is smaller than the preset third threshold.

The processing method, the device, and the computer storage medium in the queue operation provided by the embodiment of the present invention firstly obtain the queue number of the queue to which the packet information to be processed belongs; and then query the mapping table to correspond to the queue number. The storage location information and the address information of the QD; acquiring the QD according to the storage location information and the address information of the QD, moving the QD to a register (Reg), and updating the QD corresponding to the queue number in the Map table And storing the location information and the address information according to the QD, and performing the queue operation on the to-be-processed message information according to the QD, and after the queue operation, according to the QD, the updated storage location information and the address information of the QD Update the QD.

The embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the processing method in the queue operation according to the embodiment of the invention.

It can be seen that, in the embodiment of the present invention, the storage location and the storage address of the QD corresponding to the queue number of the queue to which the packet information to be processed belongs are searched through the Map table; and the QD is obtained according to the storage location and the storage address of the QD, and the QD is obtained. The QD is moved to the Reg, and the storage location of the QD corresponding to the queue number in the Map is Reg and the storage address is the corresponding address in the Reg; the queue is processed according to the QD. After the queue operation, the QD is updated according to the QD, the updated storage location and the storage address of the QD, thereby ensuring the effectiveness of the QD dynamic access in the queue operation, and improving the queue operation. The access efficiency of QD enables fast access of QD and ensures the system performance of integrated queue queuing management function.

DRAWINGS

1 is a schematic diagram of an implementation flow of Embodiment 1 of a processing method in a queue operation according to the present invention;

2 is a schematic diagram of mapping relationships between Reg, Cache, and DRAM in a Map table;

3 is a second schematic diagram of the implementation process of the first embodiment of the processing method in the queue operation according to the present invention;

4 is a third schematic flowchart of the implementation process of the first embodiment of the processing method in the queue operation of the present invention;

5 is a schematic flowchart of an implementation process of a second embodiment of a processing method in a queue operation according to the present invention;

6 is a schematic diagram of a real-time detection process of a Cache usage space;

7 is a schematic diagram showing an implementation flow of moving a QD from a Cache to a DRAM;

FIG. 8a is a schematic diagram of a mapping relationship between a queue number and a QD;

FIG. 8b is a schematic structural diagram of a Cache active linked list;

FIG. 8c is a schematic structural diagram of a Cache idle list;

9 is a schematic diagram of a real-time detection flow of a usage space of Reg;

10 is a schematic diagram of an application scenario of Embodiment 5 of a processing method in a queue operation according to the present invention;

11 is a schematic diagram of a moving process when reading a QD;

FIG. 12 is a second schematic diagram of an application scenario of Embodiment 5 of a processing method in a queue operation according to the present invention;

FIG. 13 is a schematic structural diagram of a first embodiment of a processing apparatus in a queue operation according to the present invention; FIG.

14 is a schematic diagram showing a detailed composition structure of a first processing module in the processing apparatus shown in FIG. 13;

Figure 15 is a second schematic diagram showing the detailed composition of the first processing module in the processing apparatus shown in Figure 13;

16 is a schematic structural diagram of a second embodiment of a processing apparatus in a queue operation according to the present invention;

17 is a schematic diagram of a real-time detection function module of a Cache usage space;

FIG. 18 is a schematic diagram of a real-time detection function module of the usage space of Reg.

detailed description

The processing method in the queue operation provided by the embodiment of the present invention is mainly applied to the system for integrating the queuing management function of the queue, and the storage location and the storage address of the QD corresponding to the queue number of the queue to which the packet information to be processed belongs are searched through the Map table. Obtaining a QD according to the storage location and the storage address of the QD, moving the QD to the Reg, and updating the storage location of the QD corresponding to the queue number in the Map to be Reg and the storage address being in Reg Corresponding address; performing a queue operation on the to-be-processed message information according to the QD, and updating the QD according to the QD, the updated storage location and the storage address of the QD after performing the queue operation, Improve the access efficiency of QD in queue operations and achieve fast access to QD.

The implementation, functional features, and advantages of the present invention will be further described in conjunction with the embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

FIG. 1 is a schematic diagram of an implementation flow of a first embodiment of a processing method in a queue operation according to the present invention. Referring to FIG. 1 , the processing method in the queue operation in this embodiment includes the following steps:

Step 101: Obtain a queue number of a queue to which the packet information to be processed belongs.

Here, the to-be-processed message information includes message data and a message descriptor, and the message descriptor includes a queue number and a message length.

As an implementation manner, the method for obtaining the queue number is different according to the queue operation of the message information to be processed, and the queue operation includes the enqueue operation and the dequeue operation; in this embodiment, in the enqueue operation, Receiving the to-be-processed message information from the network, determining the queue number according to the message descriptor in the message information; in the dequeuing operation, acquiring the port information waiting for scheduling and the queue information waiting to be scheduled, according to the port information and The queue information is calculated by a scheduling algorithm such as a Round-Robin (RR) scheduling algorithm or a Strict Priority (SP) scheduling algorithm.

Step 102: Query a storage location of a queue descriptor corresponding to the queue number in a mapping table. Information and address information;

Here, the Map table is used to store the storage location information and the address information of the QD corresponding to the queue number one by one; FIG. 2 is a schematic diagram of the mapping relationship between the Reg, the Cache and the DRAM in the Map table, as shown in FIG. 2, the Map table Each row represents the storage location information and address information of the QD corresponding to the queue number. For example, the first row number "1" is the queue number, and "in Reg" is the storage location information of the QD corresponding to the queue number 1, indicating The QD corresponding to the queue number 1 is stored in Reg, and the "Reg pointer 5" is the address information of the QD corresponding to the queue number 1, indicating that the QD corresponding to the queue number 1 is stored in the address indicated by the pointer 5 in the Reg; In the example, the storage location information and the address information of the QD corresponding to the queue number are queried in the Map table according to the queue number of the queue to which the packet information to be processed belongs, and the storage location information indicates that the QD corresponding to the queue number is stored. In Reg, in Cache, or in DRAM, or QD display queue is empty, the QD display queue is empty, indicating that there is no QD corresponding to the queue number in Reg, Cache, and DRAM; address information Representation with the queue QD corresponding storage location address.

Step 103: Acquire a queue descriptor according to the storage location information and the address information of the queue descriptor, move the queue descriptor to a register, and update a storage of a queue descriptor corresponding to the queue number in the mapping table. Location information and address information;

Here, a specific address is determined based on the storage location information and the address information of the QD, and the QD is read from the determined specific address; and the QD not stored in the Reg is moved to the QD according to the storage location information of the QD. In the Reg, the storage location information of the QD corresponding to the queue number in the update map table is "in Reg", and the address information of the QD corresponding to the queue number in the Map table is updated as "the address in the storage location Reg". ".

In an embodiment, in the embodiment, determining, according to the storage location information of the QD, whether the QD is stored in the Reg, the Cache, or the DRAM, or the QD display queue is empty; when the QD is When stored in Reg, the address information of the QD is used. The indicated address reads the QD from the Reg. At this time, since the queue description is stored in the Reg, it is not required to perform the moving operation and update the Map table operation; when the QD is stored in the Cache, the The address indicated in the address information of the QD reads the QD from the Cache. At this time, the Reg applies for a free address, moves the QD stored in the Cache to the free address of the Reg, and updates the Map table. The storage location information and the address information of the QD corresponding to the queue number are "in Reg, the address in the storage location Reg"; when the QD is stored in the DRAM, at this time, the address information of the QD is not Meaning, using the queue number to read the QD from the address corresponding to the queue number in the DRAM, applying a free address to the Reg, moving the QD stored in the DRAM to the free address of the Reg, and Updating the storage location information and address information of the QD corresponding to the queue number in the Map table is "in Reg, storing the address in the location Reg"; when the QD display queue is empty, at this time, applying to the Reg Free address, create a new QD at the free address Map table and update the corresponding queue number QD storage location information and address information as "Reg, the storage location address in Reg."

Step 104: Perform a queue operation on the to-be-processed message information according to the queue descriptor, and after the queue operation, according to the queue descriptor, the updated storage location information, and the address information of the queue descriptor, The queue descriptor is updated.

As an implementation manner, in the enqueue operation, the packet information to be queued is received from the network, and the queue number is determined according to the message descriptor in the packet information; or in the dequeuing operation, the port waiting for scheduling is obtained. The information and the queue information waiting for scheduling are calculated according to the port information and the queue information by a scheduling algorithm such as an RR scheduling algorithm or an SP scheduling algorithm, and the queue number is calculated;

Querying, in the Map table, storage location information and address information of the QD corresponding to the queue number;

Determining, according to the storage location information of the QD, whether the QD is stored in the Reg, the Cache, or the DRAM, or the QD display queue is empty; when the QD is stored in the Reg, the address of the QD is adopted. The address indicated in the information reads the QD from the Reg; when the QD is stored in the Cache, the address indicated in the address information of the QD is used from the Cache. Reading the QD, and applying a free address in the Reg, moving the QD in the storage Cache to the free address in the Reg, and updating the storage location information of the QD corresponding to the queue number in the Map table. And the address information is "in Reg, the address in the storage location Reg"; when the QD is stored in the DRAM, at this time, the queue number is used to read the QD from the address corresponding to the queue number in the DRAM, At the same time, applying a free address in the Reg, moving the QD stored in the DRAM to the free address in the Reg, and updating the storage location information and the address information of the QD corresponding to the queue number in the Map table as "In Reg, store the address in the location Reg"; when the QD display queue is empty, apply for a free address to the Reg, create a new QD at the free address, and update the map table corresponding to the queue number The storage location information and address information of the QD is "in Reg, the address in the storage location Reg";

Performing a queue operation on the to-be-processed message information according to the QD, and updating the QD according to the QD, the QD updated storage location information, and address information after performing the queue operation.

It can be understood that, in the queue operation, the storage location information and the address information of the QD corresponding to the queue number are queried according to the Map table, and the QD is obtained according to the storage location information and the address information of the QD; and the QD is moved to the Reg And updating the storage location information and the address information of the QD corresponding to the queue number in the Map table; and updating the QD according to the QD, the updated storage location information of the QD, and the address information to implement the QD The fast access is because: the Map table stores the storage location information and the address information of the QD corresponding to the queue number one by one. In the queue operation, the QD storage corresponding to the queue number can be obtained by querying the Map table. Location and storage address, so when QD is stored in Cache or DRAM, only need to access Cache or DRAM once to get QD, improve QD acquisition efficiency, achieve fast QD acquisition; QD will be stored in Cache or DRAM Moving to the Reg, and updating the storage location information and the address information of the QD corresponding to the queue number in the Map table, after the queue operation, according to the QD, the updated storage location information of the QD, and The address information more QD New, so only need to access Reg when updating the QD, improve the storage efficiency of QD, and achieve fast storage of QD.

Further, FIG. 3 is a schematic diagram of the implementation process of the first embodiment of the processing method in the queue operation according to the present invention. Based on the QD and the queue number, the packet information to be processed is determined according to a preset congestion avoidance policy. The team enters the packet information to be processed according to the QD. Referring to FIG. 3, step 104 specifically includes the following steps:

Step 1041: Apply a message buffer pointer to the dynamic random access memory;

Step 1042: Store the to-be-processed message information and the message cache pointer into the dynamic random access memory according to the message buffer pointer.

Step 1043: Update the queue descriptor according to the packet buffer pointer and the packet information of the enqueue operation, and store the updated queue descriptor in the target address, where the target address is the queue description. The address determined by the updated storage location information and address information.

Here, the QD includes a first pointer of the queue, a tail pointer of the queue, and a queue depth, and the preset congestion avoidance policy may be a weighted random early detection algorithm; in this embodiment, according to the to-be-processed message information. The QD of the queue and the queue number are used to determine whether the to-be-processed message information is queued by using a weighted random early detection algorithm; and when the judgment message information cannot be enqueued, the to-be-processed message information is performed. Discarding; when the message information is entered into the queue, the packet information to be processed is enqueued.

As an implementation manner, according to the QD and the queue number, using a weighted random early detection algorithm to determine that a message cache pointer is directed to the DRAM when the message information is enqueued;

Write the message data in the message information to be processed to the DRAM message data buffer area pointed to by the message buffer pointer, and write the message descriptor in the message information to be processed to the message buffer pointer. DRAM message descriptor buffer area, and write the message buffer pointer to the DRAM message buffer pointer buffer area;

After performing the enqueue operation on the to-be-processed message information, the queue in the QD is The tail pointer is updated to a message buffer pointer, and the queue depth in the QD is updated to the queue depth in the QD plus the message length in the message descriptor, and the updated QD is stored to be updated based on the QD. The storage location information and the address information are determined by the address.

FIG. 4 is a third schematic flowchart of the implementation of the processing method in the queue operation of the present invention. When the queue operation is a dequeuing operation, as shown in FIG. 4, step 104 specifically includes the following steps:

Step 1044: Read, according to the queue descriptor, the to-be-processed message information and the next queued message buffer pointer in the dynamic random access memory, and dequeue the to-be-processed message information;

Step 1045: Release a message buffer pointer of the dequeued message information.

Step 1046: Update the queue descriptor according to the next queued message cache pointer and the message information of the dequeued operation, and store the updated queue descriptor in the target address, The target address is an address determined by the storage location information and the address information after the queue descriptor is updated.

As an implementation manner, the first pointer of the queue in the QD is used to read the message data from the DRAM message data buffer area, and the message data is dequeued, and the first pointer of the queue in the QD is used to cache from the DRAM message descriptor. The area reads the message descriptor, determines the message length, reads the message buffer pointer from the DRAM message buffer pointer buffer area by using the first pointer of the queue in the QD, and uses the first pointer of the queue in the QD to buffer the pointer from the DRAM message. The cache area reads the next queued message buffer pointer;

A message buffer pointer for releasing the dequeued message information;

After performing the dequeuing operation on the to-be-processed message information, updating the first pointer of the queue in the QD to the next queued message buffer pointer, and updating the queue depth in the QD to the QD The queue depth in the packet is subtracted from the message length in the message descriptor, and the updated QD is stored in the address determined based on the updated storage location information and address information of the QD.

FIG. 5 is a schematic flowchart of the implementation of the second embodiment of the processing method in the queue operation according to the present invention. Referring to FIG. 5, the processing method in the queue operation in the embodiment is the first embodiment of the processing method in the queue operation of the present invention. After step 104, the method further includes:

Step 105: Detect a queue number of a queue corresponding to the queue descriptor before the update;

Step 106: When the queue number of the updated queue descriptor corresponding queue is different from the queue number of the queue corresponding to all the updated queue descriptors, the updated queue descriptor stored in the register is moved to the high speed. Buffer memory;

Step 107: Update storage location information and address information of the updated queue descriptor corresponding to the queue number in the mapping table.

Based on the processing method in the queue operation in the first embodiment, in the embodiment, a specific implementation example of the processing method in the enqueue operation is described in detail.

Receiving the to-be-processed message information from the network, determining that the queue number is 2 and the packet length is 128 according to the message descriptor in the to-be-processed message information;

Referring to FIG. 2, the storage location information of the QD corresponding to the queue number 2 is "in the Cache" and the address information is "Cache pointer 1" in the Map table, and the QD is determined according to the storage location information and the address information of the QD. The address 1 pointed to by the pointer pointer 1 stored in the Cache reads the QD from the address, applies a free address 6 in the Reg, moves the QD stored in the Cache to the Reg, and updates the Map table with The storage location information and address information of the QD corresponding to the queue number 2 is "Reg in Reg, 6";

Determining, according to the QD and the outbound port of the queue number 2, a weighted random early detection algorithm, when determining that the message information is enqueued, applying a message buffer pointer to the DRAM;

After the packet information to be processed is queued, the tail pointer of the queue in the QD corresponding to the queue number 2 is updated to the message buffer pointer, and the queue depth in the QD corresponding to the queue number 2 is updated to the queue number. 2 The queue depth in the corresponding QD plus the message length 128, the updated QD is stored in the Address 6 of the Reg;

After updating the QD corresponding to the queue number 2, it is detected that the queue numbers corresponding to the QD before the update are 5 and 10;

Queue number 2 is different from queue number 5 and queue number 10. In this case, a free address 6 is requested in the Cache, and the QD stored in the Reg address 6 is moved to the address 6 of the Cache.

Update the storage location information and address information of the QD corresponding to the queue number 2 in the Map table as "Cache pointer 6 in the Cache".

Further, based on the processing method in the queue operation in the first embodiment, in the embodiment, a specific implementation example of the processing method in the dequeuing operation is described in detail.

Obtaining the port information waiting for scheduling and the queue information waiting for scheduling, according to the port information and the queue information, using the RR scheduling algorithm, the calculated queue number is 65536;

Referring to FIG. 2, in the Map table, the storage location information of the QD corresponding to the queue number 65536 is "in DRAM" and the address information is "Null". At this time, the queue number 65536 is used to read from the address 65536 of the DRAM. Taking QD, applying a free address 7 in Reg, moving the QD stored in the DRAM to Reg, and updating the storage location information and address information of the QD corresponding to the queue number 65536 in the Map table as "at" Reg, Reg pointer 7”;

Reading the message data from the message data buffer area of the DRAM with the first pointer of the queue in the QD, and dequeuing the message data, using the first pointer of the queue in the QD from the DRAM message descriptor The buffer area reads the message descriptor, determines that the message length is 128, and reads the message buffer pointer and the next queued message buffer from the DRAM message buffer pointer buffer area by using the first pointer of the queue in the QD. pointer;

a message buffer pointer for releasing the dequeued message data;

After the dequeuing operation, the first pointer of the queue in the QD corresponding to the queue number 65536 is updated to the next queued message buffer pointer, and the queue depth in the QD corresponding to the queue number 65536 is updated to be the queue number 65536. The queue depth in the corresponding QD is subtracted from the packet length 128, and the updated QD is stored in the Reg address 7;

After updating the QD corresponding to the queue number 65536, it is detected that the queue numbers corresponding to the QD before the update are 4 and 9;

The queue number 65536 is inconsistent with the queue number 4 and the queue number 9. In this case, a free address 7 is requested in the Cache, and the QD stored in the Reg address 7 is moved to the address 7 of the Cache;

Update the storage location information and address information of the QD corresponding to the queue number 65536 in the Map table as "Cache pointer 7 in the Cache".

Further, since the QD that is performing the queue operation processing needs to be moved to the Reg, and the QD that has completed the queue operation processing and stored in the Reg needs to be moved to the Cache, the Cache has sufficient space to store the queue operation. The QD in the process ensures the normal operation of the queue operation. In the third embodiment of the processing method in the queue operation of the present invention, the space of the Cache can be detected in real time.

FIG. 6 is a schematic diagram of a real-time detection process of a Cache usage space. Referring to FIG. 6, the processing method in the queue operation of the present invention further includes:

Step 201: detecting a space usage of the cache memory in real time, and obtaining a first detection result;

Step 202: When the first detection result is greater than a preset first threshold, moving a queue descriptor of a queue stored in the cache and having an activity less than a preset second threshold to a dynamic random access memory Having the space of the cache memory satisfy a preset condition;

The preset first threshold may be set according to actual needs. For example, the value of the first threshold may be a percentage of 90% to 98%; in this embodiment, the first threshold may be 95% is an example for detailed explanation.

When the QD stored in the Reg is moved to the Cache, it indicates that the queue operation process is performed. Therefore, in this embodiment, the activity of the queue may be divided according to the length of time after the QD is stored in the Cache, for example, storage. The QD queue that has not been queued for the longest time in the Cache has the lowest activity, and can be set to 0. When it is detected that QD is moved from the Reg to the Cache, it indicates that the queue is performing queue operation processing. Active, you can set the queue's activity to 10, and the remaining queues can be set to an integer value of 1 to 9.

The preset second threshold may be set according to actual needs. In this embodiment, a second threshold value of 0.5 may be used as an example for detailed description.

In step 203, the pointer of the queue descriptor that is moved out of the cache is released.

As an implementation manner, the space usage of the Cache is detected in real time, and the first detection result is obtained;

When the first detection result is greater than 95%, and the activity of the queue corresponding to the QD stored in the Cache is less than 0.5, the QD is moved to the DRAM;

A pointer to the QD that moves out of the Cache is released.

FIG. 7 is a schematic diagram of an implementation process of moving a QD from a Cache to a DRAM. Referring to FIG. 7, the implementation process of moving the QD from the Cache to the DRAM includes the following steps:

Step 301: Create a doubly linked list of queue numbers corresponding to all QDs stored in the Cache; if there is a trigger event that the QD corresponding to the queue number qN is released from the Reg to the Cache, go to step 302; if there is a queue number qM If the corresponding QD is moved from the Cache to the trigger event in the Reg, step 303 is performed;

Step 302, the queue number qN is added to the end of the linked list, the depth of the linked list is increased by 1, and step 304 is performed;

Step 303, the queue number qM is removed from the linked list, and the upper and lower nodes of the queue number qM are connected;

Step 304: Detect the number of the linked list, that is, the number of queue numbers corresponding to the QD existing in the Cache (ie, The number of queues is determined, whether the depth of the linked list is greater than a preset first threshold, if the depth of the linked list is greater than the preset first threshold, step 305 is performed, otherwise step 307 is performed;

Step 305: Move the QD corresponding to the first queue number in the Cache active linked list to the DRAM.

Step 306, releasing a pointer of the QD that moves out of the Cache;

In step 307, the QD in the Cache is not moved.

To explain the reason why the QD corresponding to the first queue number in the Cache active linked list is moved to the DRAM when the depth of the linked list is greater than the preset first threshold, first, the mapping relationship between the queue number and the QD, the Cache active linked list, and the Cache free linked list. Introduce.

Figure 8a is a schematic diagram of the mapping relationship between the queue number and the QD. As shown in Figure 8a, the Cache Link Table has a depth of 1024, and can store 1024 queue numbers corresponding to the QD. The mapping depth between the queue number qnum and the QD in the Cache is 1024. There is a one-to-one correspondence with the QD in the Cache, as shown in the Cache-qnum table in Figure 8a.

FIG. 8b is a schematic structural diagram of a Cache active linked list. Referring to FIG. 8b, the next hop RAM depth of the Cache active linked list is 1024, and each entry stores the previous node corresponding to the Cache pointer (ie, the previous cache pointer) and the next node. (ie, the next cache pointer), and the Cache active list also contains the first pointer of the active linked list and the tail pointer of the active linked list, indicating the Cache address corresponding to the first and last nodes of the active linked list; in Figure 8b, the number of Cache active linked list nodes is Four, these four nodes represent the connection relationship of Cache addresses 0, 1, 2 and 3.

FIG. 8c is a schematic structural diagram of a Cache free link list. As shown in FIG. 8c, the Cache free list includes a first pointer of the free list and a tail pointer of the free list, indicating a Cache free address corresponding to the first and last nodes of the free list, and a Cache idle list next hop. RAM is used to manage the free address of the Cache.

Then, the event that performs the queue operation processing is called an active event, and the queue of the first queue number in the Cache active linked list is the most long time among the queues of all the queue numbers in the linked list. The queue of the event, that is, the queue with the lowest activity, the queue of the tail queue number in the Cache active list is the queue in which the active event has occurred recently. Therefore, when the depth of the linked list is greater than the preset first threshold, the Cache is active in the linked list. The QD corresponding to the first queue number is moved to the DRAM.

Further, the specific implementation flow of moving the QD from the Cache to the DRAM will be described in detail with reference to FIG. 8a, FIG. 8b and FIG. 8c.

When it is detected that the QD corresponding to the queue number n is moved from the Reg to the Cache event, the address cp is requested from the Cache idle list, the QD is written into the Cache with the cp as the address, and the queue number n is written to the Cache-qnum table. For the next hop RAM of the Cache active linked list, the tail pointer of the Cache active linked list is used as the address, the cp is written to the next node, and the tail pointer of the Cache active linked list is written to the previous node by using cp as the address, and Cp is updated to the tail pointer of the active linked list, and the depth of the linked list is increased by 1;

When it is detected that the QD with the queue number m is moved from the address cp' in the Cache to the Reg event, the QD corresponding to the queue number m is read from the address cp' in the Cache, and the free address is stored in the Reg idle list. The QD in the Cache is moved to the Reg; the next hop RAM of the Cache active list is read by the cp' address, and the last hop x and the next hop y of the queue number m are obtained, and the queue is queued with the queue number x as the address. The number y is written to the next node, and the queue number x is written to the previous node with the queue number y as the address, that is, the queue number m is deleted from the active linked list, and the queue number x and the queue number y are connected, and the Cache is simultaneously The active list depth is reduced by 1;

The number of active queues that are supported in advance is the first threshold value is Cache_th. If the Cache Link Table depth is greater than Cache_th, the first pointer of the Cache active linked list reads the queue number stored in the QD and Cache-qnum table in the Cache. The QD corresponding to the queue number is moved to the DRAM.

Further, in order to ensure that the Reg has enough space to store the QD of the queue operation processing and ensure the normal operation of the queue operation, in the fourth embodiment of the processing method in the queue operation of the present invention, the real space of the Reg can be detected in real time.

FIG. 9 is a schematic diagram of a real-time detection process of the usage space of Reg, as shown in FIG. The processing methods in the queue operation also include:

Step 401: Real-time detection of the space usage of the register, and obtaining a second detection result;

Step 402: When the second detection result is greater than the preset third threshold, stop outputting the message descriptor in the to-be-processed message information and the message information to be processed, and perform the enrollment operation until the first detection result When the threshold is less than the preset fourth threshold, the message descriptor in the message information to be processed and the message information to be processed are restored to be queued, and the preset fourth threshold is smaller than the preset. The third threshold.

Here, the preset third threshold may be set according to actual needs. For example, the value of the third threshold may be a percentage of 90% to 98%; in this embodiment, the third threshold may be 95% is an example for detailed explanation.

The preset fourth threshold may be set according to actual needs. For example, the value of the fourth threshold may be a percentage of 80% to 88%; in this embodiment, the fourth threshold may be 85%. Give an example for a detailed description.

Specifically, the space usage of the Reg is detected in real time, and the second detection result is obtained;

When the second detection result is greater than 95%, the message descriptor in the message information is stopped, and the message information enqueue process is stopped, until the second detection result is less than 85%, and the message in the output message information is restored. Descriptor and resume message information into the team process.

In the fifth embodiment of the processing method in the queue operation of the present invention, in order to explain the practical application of the processing method in the queue operation of the present invention, the processing method in the queue operation of the present invention is described in detail in conjunction with the application scenario diagram.

The processing method of the queue operation of the present invention is mainly applied to the network device queue management system. FIG. 10 is a schematic diagram of an application scenario of the fifth embodiment of the processing method in the queue operation according to the present invention. Referring to FIG. 10, the application scenario includes the inbound direction. a message buffering module, an outgoing packet buffering module, a congestion avoidance module, an enqueue processing module, a queue scheduling module, a dequeue processing module, a message cache management module, a Map table, a QD management module, and a QD cache module; wherein, the QD management Module includes The migration management module, the QD cache module includes DRAM, Reg, and Cache.

First, the moving flow when the QD is read in the queue operation processing will be described with reference to FIG. 10. FIG. 11 is a schematic diagram of the moving flow when the QD is read. Referring to FIG. 11, the moving flow when the QD is read specifically includes the following steps:

Step 501: The Map table receives query request information of the congestion avoidance module or the enqueue module or the dequeue module, where the query request information includes a queue number;

Step 502: Query the storage location information and the address information of the QD corresponding to the queue number in the Map table, and send the information to the QD management module.

Step 503: The moving management module in the QD management module processes the QD according to the storage location information and the address information of the QD queried by the Map table, and when the storage location information of the QD indicates that the QD is stored in the Reg, step 504 is performed; When the storage location information of the QD indicates that the QD is stored in the Cache, step 505 is performed; when the storage location information of the QD indicates that the QD is stored in the DRAM, step 508 is performed;

Step 504, the QD is obtained from the address determined by the QD-based storage location information and the address information, step 5010 is performed;

Step 505, applying for a free pointer to the Reg;

Step 506: Acquire a QD from an address determined by the QD-based storage location information and the address information, and move the QD stored in the Cache to an address pointed to by the Reg idle pointer.

Step 507, the pointer of the QD that has moved out of the Cache is released, and step 5010 is performed;

Step 508, applying a free pointer to the Reg;

Step 509: Acquire a QD from an address determined by the QD-based storage location information and the address information, and move the QD stored in the DRAM to an address pointed to by the Reg idle pointer;

In step 5010, the QD is returned to the congestion avoidance module or the enqueue processing module or the dequeue processing module.

Then, in conjunction with FIG. 10, the process of enqueue operation processing is introduced, and the message information is received from the network, and the information is stored. Sending, to the message buffering module, the message descriptor in the message information to the congestion avoidance module, where the congestion avoidance module determines the queue number of the queue to which the message information belongs according to the message descriptor, and sends the queue number to the queue number The Map table applies for querying a QD corresponding to the queue number;

The Map table receives the query request of the congestion avoidance module, and the query request triggers the Map table to query the storage location information and the address information of the QD corresponding to the queue number, and sends the information to the QD management module;

The QD management module obtains the QD from the address determined by the QD-based storage location information and the address information, and moves the QD stored in the Cache or the DRAM to the Reg by the migration management module in the QD management module; updating the Map table and The storage location information and the address information of the QD corresponding to the queue number, and the QD, the updated storage location information and the address information of the QD are sent to the congestion avoidance module;

After receiving the QD and the updated storage location information and the address information of the QD, the congestion avoidance module reads the egress port of the queue number, and uses the weighted random early according to the QD and the egress port of the queue number. The detection algorithm determines whether the incoming message information can be enqueued, and sends the judgment result, the outbound port of the queue number, the QD, and the message descriptor in the message information to the enqueue processing module through the enrollment operation pipeline; When the result of the judgment indicates that the message information is not in the queue, the congestion avoidance module determines whether the QD stored in the Reg needs to be released according to the queue number. When the queue number is inconsistent with the queue number being processed by the queue operation, the congestion is congested. Avoiding the module decision to release the QD stored in the Reg, at this time, the migration management module moves the QD stored in the Reg corresponding to the queue number to the Cache;

The enqueue processing module receives the decision result, the outbound port of the queue number, the message descriptor in the QD and the message information, and processes the message information according to the judgment result, and the judgment result indicates that the message information does not enter In the team, the enqueue processing module discards the packet data directly after reading the packet data from the incoming packet buffer module; when the judgment result indicates that the packet information is enqueued, the enqueue processing module initiates an inquiry request to the Map table. Obtaining a QD corresponding to the queue number and the updated storage location information and address information of the QD;

The enqueue processing module applies the message buffer pointer to the message buffer management module, and writes the message information into the DRAM pointed to by the message buffer pointer through the enrollment operation pipeline; after the packet information is processed into the queue operation, the enqueue is entered. The processing module updates the QD, and stores the updated QD into an address determined based on the updated storage location information and address information of the QD; after the processing by the enqueue processing module is completed, the packet information of the enqueue is provided. Queue scheduling module scheduling;

The congestion avoidance module determines, according to the queue number, whether the QD corresponding to the queue number stored in the Reg needs to be released. When the queue number is inconsistent with the queue number processed by the queue operation, the congestion avoidance module decides The QD stored in Reg is released. At this time, the migration management module moves the QD corresponding to the queue number stored in Reg to the Cache.

Finally, the queue operation processing flow is introduced in conjunction with FIG. 10, and the queue scheduling module obtains the port information and the queue information waiting for scheduling, and according to the port information and the queue information, calculates a queue number through a scheduling algorithm, and sends a team processing module;

The dequeue processing module sends the queue number to the Map table to query the QD corresponding to the queue number;

The Map table receives the query request of the dequeue processing module, and the query request triggers the Map table to query the storage location information and the address information of the QD corresponding to the queue number, and sends the information to the QD management module;

The QD management module obtains the QD from the address determined by the QD-based storage location information and the address information, and moves the QD stored in the Cache or the DRAM to the Reg by the migration management module in the QD management module; updating the Map table and The storage location information and the address information of the QD corresponding to the queue number, and the QD, the updated storage location information and the address information of the QD are sent to the team processing module;

The dequeue processing module uses the first pointer of the queue in the QD to read the message information in the DRAM, the message buffer pointer, and the next message buffer pointer that is being queued; after the packet information is dequeued, the team is sent out. The processing module updates the QD, and stores the updated QD into an address determined based on the updated storage location information and address information of the QD;

In order to ensure that the Reg and Cache have enough space to store the QD of the queue operation processing, the migration management module detects the space usage of the Reg and the Cache in real time; when the migration management module detects that the usage space of the Cache is greater than the preset first threshold, the Cache is The QD of the queue with the lowest activity is moved to the DRAM, and the pointer of the QD that moves out of the Cache is released. When the migration management module detects that the usage space of the Reg is greater than the preset third threshold, the packet is forwarded to the packet buffer module. The output of the message descriptor is stopped, and the message information enqueuing process is stopped. When the migration management module detects that the usage space of the Reg is less than the preset fourth threshold, the output message descriptor and the message information enqueuing process are resumed.

Further, FIG. 12 is a schematic diagram of the application scenario of the fifth embodiment of the processing method in the queue operation according to the present invention. Referring to FIG. 12, the cell is received from the network, and the port is searched and ported according to the port number carried by the cell. The storage location information and the address information of the corresponding QD, so that the QD is read from the address determined by the QD-based storage location information and the address information, and the tail pointer and the queue depth of the queue are determined according to the QD, wherein the port number is equivalent to the queue Write the Cell to the end of the queue, update the tail pointer of the queue corresponding to the QD to the storage address of the current enqueue Cell, add the queue depth in the QD to the current enqueued Cell length, and write the Cell data to the DRAM. In the Cell data buffer area, the Cell pointer is written to the Cell pointer buffer area in the DRAM. At this time, the enqueue operation is completed; when dequeuing, the output scheduling queue number is selected according to the inter-queue RR scheduling rule, according to the queue number, in the Map table. Querying the storage location information and the address information of the QD corresponding to the queue number, thereby reading the QD from the address determined by the QD-based storage location information and the address information, QD and determines the queue head pointer queue depth, the read data output from the DRAM Cell with the head pointer of the queue, the queue with the pointer at the first reading from a DRAM is being queued Cell Pointer, and update the first pointer of the queue in the QD to the pointer, and update the queue depth in the QD to the queue depth in the QD minus the current dequeued Cell length. At this time, the dequeue operation is completed.

It can be seen that the processing method in the queue operation of the present invention can also be applied to the device in which the cell Cell is managed by the virtual output queue VOQ queue output. Therefore, the application of the processing method in the queue operation of the present invention is not limited to the network device queue management system. It can be applied to all systems or devices that integrate queue queuing management functions.

The present invention also provides a processing device in a queue operation for implementing the specific details of the processing method in the queue operation of the present invention, achieving the same effect.

FIG. 13 is a schematic structural diagram of a first embodiment of a processing apparatus in a queue operation according to the present invention. Referring to FIG. 13, the processing apparatus in the queue operation in the embodiment includes: an obtaining module 61, a querying module 62, and a first moving module 63. And a first processing module 64; wherein

The obtaining module 61 is configured to obtain a queue number of a queue to which the packet information to be processed belongs.

The query module 62 is configured to query, in the mapping table, storage location information and address information of the queue descriptor corresponding to the queue number;

The first moving module 63 is configured to acquire a queue descriptor according to the storage location information and the address information of the queue descriptor, move the queue descriptor into a register, and update the mapping table with the queue number. Storage location information and address information of the corresponding queue descriptor;

The first processing module 64 is configured to perform queue operation on the to-be-processed message information according to the queue descriptor, and update the queue descriptor and the queue descriptor after performing the queue operation. The location descriptor and the address information are stored, and the queue descriptor is updated.

Optionally, the first processing module 64 is configured to determine, according to the preset congestion avoidance policy, that the to-be-processed packet information is enqueued according to the queue descriptor and the queue number, according to the queue. The descriptor performs the enqueue operation on the to-be-processed message information; or performs the dequeuing operation according to the message information to be processed in the queue descriptor.

FIG. 14 is a schematic diagram showing the structure of the refinement of the first processing module in the processing apparatus shown in FIG. 13. Referring to FIG. 14, when the queue operation is a queue operation, the first processing module 64 includes: a unit 641, a storage unit 642, and a first update unit 643; wherein

The application unit 641 is configured to apply for a message cache pointer to the dynamic random access memory;

The storage unit 642 is configured to store the to-be-processed message information and the message cache pointer into the dynamic random access memory according to the message buffer pointer;

The first update unit 643 is configured to update the queue descriptor according to the message cache pointer and the message information of the queued operation, and store the updated queue descriptor in the target address, The target address is an address determined by the storage location information and the address information after the queue descriptor is updated.

FIG. 15 is a second schematic diagram showing the structure of the first processing module in the processing apparatus shown in FIG. 13. Referring to FIG. 15, when the queue operation is a dequeuing operation, the first processing module 64 includes: reading Taking unit 644, a release unit 645 and a second update unit 646; wherein

The reading unit 644 is configured to read, according to the queue descriptor, the to-be-processed message information and the next queued message buffer pointer in the dynamic random access memory, and the to-be-processed message Information is sent out;

The release unit 645 is configured to release a message buffer pointer of the dequeued message information;

The second update unit 646 is configured to update the queue descriptor according to the next message buffer pointer being queued and the message information of the dequeued operation, and store the updated queue descriptor To the target address, the target address is an address determined by the storage location information and the address information after the queue descriptor is updated.

FIG. 16 is a schematic structural diagram of a second embodiment of a processing device in a queue operation according to the present invention. The processing device in the queue operation of the present embodiment includes an obtaining module 61, a query module 62, a first moving module 63, and a first processing module 64. In addition, the first detecting module 65, the second moving module 66, and the update mapping table module 67;

The first detecting module 65 is configured to detect a queue number of a queue corresponding to the queue descriptor before the update;

The second moving module 66 is configured to store the updated directory in the register when the queue number of the updated queue descriptor corresponding queue is different from the queue number of the queue descriptor corresponding to all the updated queue descriptors. The queue descriptor is moved to the cache;

The update mapping table module 67 is configured to update storage location information and address information of the updated queue descriptor corresponding to the queue number in the mapping table.

Because the QD that needs to perform the queue operation processing needs to be moved to the Reg, and the QD that has completed the queue operation processing and stored in the Reg needs to be moved to the Cache, in order to ensure that the Cache has enough space to store the queue operation processing. The QD ensures the normal operation of the queue operation. In the third embodiment of the processing device in the queue operation of the present invention, the space of the Cache can be detected in real time.

Specifically, FIG. 17 is a schematic diagram of a real-time detection function module of the Cache usage space. Referring to FIG. 17, the real-time detection function module of the Cache usage space includes: a second detection module 71, a third migration module 72, and a release module 73; among them,

The second detecting module 71 is configured to detect the space usage of the cache memory in real time, and obtain a first detection result;

The third moving module 72 is configured to queue a queue that is stored in the cache and whose activity is less than a preset second threshold when the first detection result is greater than a preset first threshold. The descriptor is moved to the dynamic random access memory;

The release module 73 is configured to release a pointer that moves out of the cache descriptor of the cache.

In order to ensure that the Reg has enough space to store the QD of the queue operation processing and ensure the normal operation of the queue operation, in the fourth embodiment of the processing apparatus in the queue operation of the present invention, the real space of the Reg can be detected in real time.

Specifically, FIG. 18 is a schematic diagram of a real-time detection function module of the usage space of the Reg. Referring to FIG. 18, the real-time detection function module of the usage space of the Reg includes: a third detection module 81 and a second processing module 82;

The third detecting module 81 is configured to detect the space usage of the register in real time, and obtain a second detection result;

The second processing module 82 is configured to stop outputting the message descriptor in the to-be-processed message information and the message information to be processed when the second detection result is greater than the preset third threshold. After the second detection result is less than the preset fourth threshold, the message descriptor in the to-be-processed message information and the message information to be processed are resumed to be enqueued, and the preset The fourth threshold is less than the preset third threshold.

In an actual application, the obtaining module 61, the querying module 62, the first moving module 63, the first processing module 64, the first detecting module 65, the second moving module 66, the update mapping table module 67, and the second detecting module 71 The third moving module 72, the releasing module 73, the third detecting module 81, the second processing module 82, and the applying unit 641, the storage unit 642, the first updating unit 643, the reading unit 644, the releasing unit 645, and the second update The unit 646 can be configured by a central processing unit (CPU), a microprocessor (MPU, a Micro Processor Unit), a digital signal processor (DSP), or a field programmable gate array (located in the mobile terminal). FPGA, Field Programmable Gate Array) and other implementations.

The embodiment of the invention further describes a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the processing method in the queue operation described in the foregoing embodiments. That is to say, after the computer executable instructions are executed by the processor, the processing method in the queue operation provided by any of the foregoing technical solutions can be implemented.

As an embodiment, an embodiment of the present invention describes a computer storage medium, where the computer storage medium stores one or more programs, and the one or more programs may be Executed by one or more processors to implement the following steps:

As an embodiment, after performing the step of updating the queue descriptor, the one or more programs may also be executed by the one or more processors to implement the following steps:

It should be understood by those skilled in the art that the functions of the programs in the computer storage medium of the present embodiment can be understood by referring to the related description of the processing methods in the queue operations described in the foregoing embodiments.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, such as: multiple units or components may be combined, or Can be integrated into another system, Or some features can be ignored or not executed. In addition, the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.

The units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units, that is, may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing module, or each unit may be separately used as one unit, or two or more units may be integrated into one unit; the above integration The unit can be implemented in the form of hardware or in the form of hardware plus software functional units.

A person skilled in the art can understand that all or part of the steps of implementing the above method embodiments may be completed by using hardware related to the program instructions. The foregoing program may be stored in a computer readable storage medium, and the program is executed when executed. The foregoing storage device includes the following steps: the foregoing storage medium includes: a mobile storage device, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk. A medium that can store program code.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and scope of the present invention are included in the scope of the present invention.

Industrial applicability

The technical solution of the embodiment of the present invention uses the Map table to query the storage location and the storage address of the QD corresponding to the queue number of the queue to which the packet information to be processed belongs, and obtain the QD according to the storage location and the storage address of the QD. The QD is moved to the Reg, and the storage location of the QD corresponding to the queue number in the Map is Reg and the storage address is the corresponding address in the Reg; Performing a queue operation on the to-be-processed message information according to the QD, and updating the QD according to the QD, the updated storage location and the storage address of the QD after performing the queue operation, thereby ensuring the queue The effectiveness of QD dynamic access in operation improves the access efficiency of QD in queue operations, realizes fast access of QD, and ensures the system performance of integrated queue queuing management function.

Claims

A processing method in a queue operation, the method comprising:

Obtain the queue number of the queue to which the packet information to be processed belongs.

Querying, in the mapping table, storage location information and address information of the queue descriptor corresponding to the queue number;

Obtaining a queue descriptor according to the storage location information and the address information of the queue descriptor, moving the queue descriptor to a register, and updating storage location information of the queue descriptor corresponding to the queue number in the mapping table and Address information;

Performing a queue operation on the to-be-processed message information according to the queue descriptor, and after performing the queue operation, according to the queue descriptor, the updated storage location information and the address information of the queue descriptor, The queue descriptor is updated.
The method of claim 1, wherein the performing queue operation on the to-be-processed message information according to the queue descriptor comprises:

And determining, according to the preset congestion avoidance policy, the packet information to be processed according to the queue descriptor and the queue number, and performing the enqueue operation on the to-be-processed packet information according to the queue descriptor. ;or,

Dequeuing the packet information to be processed according to the queue descriptor.
The method according to claim 2, wherein when the queue operation is an enqueue operation, the queued message information is queued according to the queue descriptor, and is performed after the queue operation The queue descriptor, the updated storage location information and the address information of the queue descriptor, update the queue descriptor, including:

Applying a message cache pointer to the dynamic random access memory;

And storing, according to the message buffer pointer, the to-be-processed message information and the message cache pointer into the dynamic random access memory;

Updating the queue description according to the message cache pointer and the message information of the queued operation And storing the updated queue descriptor in the target address, the target address being the address determined by the updated storage location information and the address information of the queue descriptor.
The method according to claim 2, wherein, when the queue operation is a dequeuing operation, the queue operation is performed on the message information to be processed according to the queue descriptor, and after performing a queue operation, according to the method The queue descriptor, the updated storage location information and the address information of the queue descriptor, update the queue descriptor, including:

Decoding the to-be-processed message information and the next queued message buffer pointer in the dynamic random access memory according to the queue descriptor, and dequeuing the to-be-processed message information;

A message buffer pointer for releasing the dequeued message information;

Updating the queue descriptor according to the next message buffer pointer being queued and the message information of the dequeued operation, and storing the updated queue descriptor in a target address, where the target address is The stored location information and the address determined by the address information after the queue descriptor is updated.
The method of claim 1, wherein after the updating the queue descriptor, the method further comprises:

Detecting the queue number of the queue corresponding to the queue descriptor before the update;

When the queue number of the queue descriptor corresponding to the updated queue is inconsistent with the queue number of the queue corresponding to all the queue descriptors before the update, the updated queue descriptor stored in the register is moved to the cache memory. ;

The storage location information and the address information of the updated queue descriptor corresponding to the queue number in the mapping table are updated.
The method of claim 5 wherein the method further comprises:

Detecting the space usage of the cache memory in real time, and obtaining a first detection result;

When the first detection result is greater than a preset first threshold, moving a queue descriptor of a queue stored in the cache and having an activity less than a preset second threshold to a dynamic In random access memory;

A pointer to the queue descriptor that is moved out of the cache is released.
The method of claim 2, wherein the method further comprises:

Real-time detecting the space usage of the register to obtain a second detection result;

When the second detection result is greater than the preset third threshold, the message descriptor in the to-be-processed message information and the message information to be processed are stopped from being queued until the second detection result is less than the preset. The fourth threshold is restored, and the message descriptor in the to-be-processed message information and the message information to be processed are resumed, and the preset fourth threshold is smaller than the preset third. Threshold.
A processing device in a queue operation, the device comprising: an obtaining module, a query module, a first moving module, and a first processing module; wherein

The acquiring module is configured to obtain a queue number of a queue to which the packet information to be processed belongs;

The query module is configured to query, in the mapping table, storage location information and address information of the queue descriptor corresponding to the queue number;

The first moving module is configured to acquire a queue descriptor according to the storage location information and the address information of the queue descriptor, move the queue descriptor to a register, and update the mapping table corresponding to the queue number Storage location information and address information of the queue descriptor;

The first processing module is configured to perform a queue operation on the to-be-processed message information according to the queue descriptor, and after the queue operation, update the storage according to the queue descriptor and the queue descriptor. Location information and address information are updated for the queue descriptor.
The device according to claim 8, wherein the first processing module is configured to determine, according to the preset congestion avoidance policy, that the to-be-processed message information is enqueued based on the queue descriptor and the queue number. And performing the enqueue operation on the to-be-processed packet information according to the queue descriptor; or performing a dequeuing operation according to the packet descriptor to be processed according to the queue descriptor.
The apparatus of claim 9, wherein the first processing module comprises: an application unit, a storage unit, and a first update unit, when the queue is operated as a queue operation;

The application unit is configured to apply for a message cache pointer to the dynamic random access memory;

The storage unit is configured to store the to-be-processed message information and the message cache pointer in the dynamic random access memory according to the message buffer pointer;

The first update unit is configured to update the queue descriptor according to the message cache pointer and the message information of the queued operation, and store the updated queue descriptor in the target address, the target The address is an address determined by the storage location information and the address information after the queue descriptor is updated.
The apparatus of claim 9, wherein the first processing module comprises: a reading unit, a releasing unit, and a second updating unit, when the queue is operated as a dequeue operation;

The reading unit is configured to read the to-be-processed message information and the next queued message buffer pointer in the dynamic random access memory according to the queue descriptor, and the to-be-processed message information Carry out the team;

The release unit is configured to release a message cache pointer of the dequeued message information;

The second update unit is configured to update the queue descriptor according to the next queued message cache pointer and the message information of the dequeued operation, and store the updated queue descriptor to In the target address, the target address is an address determined by the storage location information and the address information after the queue descriptor is updated.
The device according to claim 8, wherein the device further comprises: a first detecting module, a second moving module, and an update mapping table module; wherein

The first detecting module is configured to detect a queue number of a queue corresponding to the queue descriptor before the update;

The second moving module is configured to store, when the queue number of the updated queue descriptor corresponding queue is different from the queue number of the queue corresponding to all the updated queue descriptors, The updated queue descriptor in the register is moved to the cache memory;

The update mapping table module is configured to update storage location information and address information of the updated queue descriptor corresponding to the queue number in the mapping table.
The device according to claim 12, wherein the device further comprises: a second detecting module, a third moving module, and a releasing module; wherein

The second detecting module is configured to detect a space usage of the cache memory in real time, and obtain a first detection result;

The third moving module is configured to: when the first detection result is greater than a preset first threshold, a queue description of a queue that is stored in the cache and whose activity is less than a preset second threshold Move to dynamic random access memory;

The release module is configured to release a pointer that moves out of the cache descriptor of the cache.
The device according to claim 9, wherein the device further comprises: a third detecting module, a second processing module; wherein

The third detecting module is configured to detect a space usage of the register in real time, and obtain a second detection result;

The second processing module is configured to stop outputting the message descriptor in the to-be-processed message information and the message information to be processed to perform the enqueue operation when the second detection result is greater than the preset third threshold. When the second detection result is less than the preset fourth threshold, the message descriptor in the to-be-processed message information and the message information to be processed are restored to perform the enqueue operation, and the preset fourth The threshold is less than the preset third threshold.
A computer storage medium having stored therein computer executable instructions for performing a processing method in a queue operation according to any one of claims 1 to 7.