WO2018076682A1

WO2018076682A1 - Parallel interface time sequence control method and apparatus

Info

Publication number: WO2018076682A1
Application number: PCT/CN2017/085924
Authority: WO
Inventors: 徐超; 周畅; 龚晓亮
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2016-10-28
Filing date: 2017-05-25
Publication date: 2018-05-03
Also published as: CN108011703A; CN108011703B

Abstract

Disclosed in the embodiments of the present invention are a parallel interface time sequence control method and apparatus, the parallel interface time sequence control apparatus comprising: a register configuration module, a rate adaptation module, an interface time sequence control module, and a data and time sequence processing module, used for implementing adaptive configuration of the parallel interface rate.

Description

Parallel interface timing control method and device

Cross-reference to related applications

The present application is based on a Chinese patent application filed on Jan. 28, 2016, the entire disclosure of which is hereby incorporated by reference.

Technical field

The present invention relates to the field of communications, and in particular, to a parallel interface timing control method and apparatus.

Background technique

JESD207 is a radio front-end (Base-to-Plane Integrated Circuit) (RF-based front end integrated circuit (RFIC)). The radio front end-Baseband Digital Parallel (RBDP) interface is mainly used. Transmit RFIC and BBIC digital waveform data, which supports single-antenna and dual-antenna data transmission and reception in Time Division Duplex (TDD) and Frequency Division Duplex (FDD). Figure 1 shows JESD207 data. Interface connection diagram, where MCLK is the associated clock of the data sent by the RFIC to BBIC, FCLK is the associated clock of the data sent by BBIC to RFIC, TXNRX is the data direction indication signal, and ENABLE signal is the start and end indication of data burst transmission The DIQ[11:0] and DIQ[9:0] signals are data bidirectional transmission buses that support transmission in 12-bit and 10-bit data formats, respectively, and can be selected as needed. All data are double data rate (DDR, Double) Data Rate).

The JESD207 data interface has the characteristics of less occupied pin resources, low interface rate, and low design difficulty. Although the FCLK can be regarded as the MCLK homologous clock for the BBIC interface level, the frequency of the clock can be ignored, and only the received MCLK is performed. After the delay, the output can be, but for the latter stage of the BBIC interface, the MCLK clock cycle information is still needed to understand the data communication rate. Therefore, the data communication rate matched with the latter circuit of the BBIC interface is provided to ensure that the data between the RFIC and the BBIC can be correctly transmitted and received. Therefore, when it is necessary to replace different RFICs when testing, it is necessary to meet the requirements of each RFIC. The interface rate is configured to bring inconvenience in testing.

Summary of the invention

In order to solve the existing technical problems, embodiments of the present invention are expected to provide a parallel interface timing control method and apparatus, and implement parallel interface rate adaptive configuration.

The technical solution of the embodiment of the present invention is implemented as follows:

In a first aspect, an embodiment of the present invention provides a parallel interface timing control apparatus, where the parallel interface timing control apparatus includes: a register configuration module, a rate adaptation module, an interface timing control module, and a data and timing processing module, where

The register configuration module is configured to acquire configuration information of the system;

The rate adaptation module is configured to generate an updated data communication rate and an adaptive flag by using period information of the MCLK sent by the peer end when detecting that the first configuration information in the register configuration module is valid, and the updating Data communication rate and adaptive flag are sent to the register configuration module;

The register configuration module is further configured to configure a current data communication rate according to the adaptive flag;

The interface timing control module is configured to generate an interface timing according to the second configuration information and the MCLK information in the register configuration module;

The data and timing processing module is configured to transmit data according to the interface timing, and process data according to the number of channels in the register configuration module and the current data communication rate.

In a second aspect, an embodiment of the present invention provides a parallel interface timing control method, where the method is used for a parallel interface timing control apparatus, where the parallel interface timing control apparatus includes: a register configuration module, a rate adaptation module, and an interface timing control Module and data and timing processing module, The method includes:

The register configuration module acquires configuration information of the system;

When the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module generates an updated data communication rate and an adaptive flag by using period information of the MCLK sent by the peer, and Transmitting the updated data communication rate and the adaptive flag to the register configuration module;

The register configuration module configures a current data communication rate according to the adaptive flag;

The interface timing control module generates an interface timing according to the second configuration information and the MCLK information in the register configuration module;

The data and timing processing module transmits data according to the interface timing, and processes data according to the number of channels in the register configuration module and the current data communication rate.

Embodiments of the present invention provide a parallel interface timing control method and apparatus, the method is used for a parallel interface timing control apparatus, and the parallel interface timing control apparatus includes: a register configuration module, a rate adaptation module, an interface timing control module, and a data and timing processing module, the method comprising: the register configuration module acquiring configuration information of the system; and when the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module Generating an updated data communication rate and an adaptive flag by using the period information of the MCLK sent by the opposite end, and transmitting the updated data communication rate and the adaptive flag to the register configuration module; the register configuration module is configured according to the adaptive flag Configuring a current data communication rate; the interface timing control module generates an interface timing according to the second configuration information and the MCLK information in the register configuration module; the data and timing processing module transmits data according to the interface timing, according to the Register configuration module current data pass Data processing rate, enabling parallel interface rate adaptation configuration.

DRAWINGS

Figure 1 is a JESD207 data interface connection diagram;

2 is a schematic diagram of communication interaction between a parallel interface timing control apparatus and a radio frequency front-end integrated circuit according to an embodiment of the present invention;

FIG. 3 is a timing diagram of data transmission start of JESD 207 according to an embodiment of the present invention;

4 is a timing diagram of data transmission end of JESD 207 according to an embodiment of the present invention;

FIG. 5 is a timing diagram of data reception start of JESD 207 according to an embodiment of the present invention;

FIG. 6 is a timing diagram of data reception end of JESD 207 according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a parallel interface timing control circuit according to an embodiment of the present disclosure;

FIG. 8 is a structural block diagram of a parallel interface timing control apparatus according to an embodiment of the present invention;

FIG. 9 is a structural block diagram of a rate adaptation module according to an embodiment of the present invention;

FIG. 10 is a flowchart of a parallel interface timing control method according to an embodiment of the present invention;

FIG. 11 is a flowchart of generating an updated data communication rate by an adaptive module according to an embodiment of the present invention;

FIG. 12 is a flowchart of processing data by a data and timing processing module according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings in the embodiments.

2 is a schematic diagram of a communication interaction between a parallel interface timing control device and an RFIC according to an embodiment of the present invention. It can be understood that the schematic diagram is only used to explain the technical solution of the embodiment of the present invention, and is not intended to be The embodiment of the invention is arbitrarily limited. As can be seen from the figure, the parallel interface timing control device is located on the BBIC side, and the parallel interface timing control device corresponds to the RBDP related circuit in the BBIC of FIG.

Figures 3 and 4 show the timing of the JESD 207 data transmission operation, and Figures 5 and 6 show the timing of the JESD 207 data reception operation. It can be seen from the above timing diagram that the reception or transmission of the JESD207 interface data uses the paired ENABLE signals as the start and end. The indication, TXNRX signal to indicate the direction of data transmission, high level indicates transmission, low level indicates low reception, and for transmitting data, RFIC uses FCLK for sampling. For receiving data, BBIC uses MCLK for sampling.

Based on the above schematic diagram, an embodiment of the present invention provides a parallel interface timing control method, the parallel interface timing control method is used for a parallel interface timing control device, and FIG. 7 is a schematic structural diagram of a parallel interface timing control circuit, which is implemented by the present invention. In an example, the register configuration module acquires configuration information of the system; when the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module sends the MCLK period through the peer end. Generating an updated data communication rate and an adaptive flag, and transmitting the updated data communication rate and the adaptive flag to a register configuration module; the register configuration module configuring a current data communication rate according to the adaptive flag; The interface timing control module generates an interface timing according to the second configuration information and the MCLK information in the register configuration module; the data and timing processing module transmits data according to the interface timing, and configures a current data communication rate of the module according to the register. Processing data to achieve parallel connection Rate adaptation configuration.

Referring to FIG. 8, a structure of a parallel interface timing control apparatus 80 according to an embodiment of the present invention is shown. The parallel interface timing control apparatus 80 includes: a register configuration module 801, a rate adaptation module 802, and an interface timing control module. 803 and data and timing processing module 804, wherein

The register configuration module 801 is configured to acquire configuration information of the system;

The rate adaptation module 802 is configured to generate an updated data communication rate and an adaptive flag by using period information of the MCLK sent by the peer end when detecting that the first configuration information in the register configuration module is valid, and The updated data communication rate and the adaptive flag are sent to the register configuration module;

The register configuration module 801 is further configured to configure a current data communication rate according to the adaptive flag;

The interface timing control module 803 is configured to perform a second according to the register configuration module Configuration information and MCLK information generation interface timing;

The data and timing processing module 804 is configured to transmit data according to the interface timing, and process data according to the number of channels in the register configuration module and the current data communication rate.

For the register configuration module 801, the configuration information includes: interface module enable, channel number, default data communication rate, TDD mode subframe type, adaptive function enable, adaptive successful detection times, and adaptive failure detection times. ;

The adaptive function is enabled to correspond to the first configuration information, where the first configuration information is effective to enable the adaptive function in the register configuration module to be valid, for example, the adaptive function is enabled when the high level is enabled; and the TDD mode is used. Corresponding to the second configuration information.

For the rate adaptation module 802, the period information of the MCLK sent by the opposite end refers to the period information of the MCLK sent by the RFIC;

The adaptive flag includes an adaptive success flag and an adaptive failure flag.

The block diagram of the rate adaptation module 802 is as shown in FIG. 9. The rate adaptation module 802 includes: an MCLK period detection sub-module 8021, an MCLK clock stability detection sub-module 8022, a rate adaptive failure detection sub-module 8023, and Rate adaptive information update submodule 8024;

For the rate adaptation module 802, wherein

The MCLK period detecting sub-module 8021 is configured to acquire the period information of the MCLK through the working clock, and send the period information of the MCLK to the MCLK clock stability detecting sub-module 8022 and the rate adaptive information updating sub-module 8024 in real time; The working clock is not less than 2 times the MCLK clock frequency and is an integer multiple of the MCLK clock frequency;

The MCLK clock stability detection sub-module 8022 is configured to trigger the rate adaptive information update sub-module 8024 to generate an updated data communication rate when detecting that the number of consecutive times of the MCLK periodic information coincides with the preset adaptive success value. Sended to the register configuration module 801;

And, configured to trigger the rate adaptive information update sub-module 8024 to turn off the adaptive function when the number of times of inconsistency of the periodic information of the MCLK that is detected twice consecutive times satisfies the value of the adaptive failure. Yes; among them,

The MCLK clock stability detection submodule 8022 is configured to

When the period information of the MCLK consecutively detected is the same, the internal clock stabilization counter performs an accumulation count to obtain a first accumulated count value; and, when the first accumulated count value reaches a pre-configured adaptive success value, Generating a rate adaptive success flag; and transmitting the rate adaptive success flag to the rate adaptive information update sub-module 8024 and the register configuration module 801.

The rate adaptive information update sub-module 8024 is configured to convert the period information of the MCLK into a data communication rate when the rate adaptive success flag is detected; and to use the data communication rate converted by the period information of the MCLK as the updated data. The communication rate is sent to the register configuration module 801.

It should be noted that, when the period information of the MCLKs that are consecutively detected twice is consistent, the MCLK clock stability detection sub-module 8022 and the rate adaptive information update sub-module 8024 are configured to implement an updated data communication rate, and send the information to the The process of register configuration module 801.

The MCLK clock stability detection sub-module 8022 is further configured to trigger the rate adaptive information update sub-module 8024 to turn off the adaptive function when detecting that the number of times of the inconsistency of the periodic information of the MCLKs of the two consecutive times meets the adaptive failure value;

The MCLK clock stability detection sub-module 8022 is further configured to

When detecting that the period information of the MCLK consecutive times is inconsistent, the internal clock stabilization counter performs an accumulation count clearing to generate an MCLK change flag; and, the MCLK change flag is sent to the rate adaptive failure detection submodule 8023.

The rate adaptive fail detection sub-module 8023 is configured to, when detecting the MCLK change flag, perform an accumulative counting operation on the internal clock change counter to obtain a second accumulated count value; and, when the second accumulated count value Upon reaching the pre-configured adaptive failure value, a rate adaptive failure flag is generated; and the rate adaptive failure flag is sent to the rate adaptive information update sub-module 8024 and the register configuration module 801.

The rate adaptive information update sub-module 8024 is further configured to turn off the rate adaptation function when the rate adaptation failure flag is detected.

It should be noted that, when the period information of the MCLK that is detected twice consecutive times is inconsistent, the MCLK clock stability detection sub-module 8022, the rate adaptive failure detection sub-module 8023, and the rate adaptive information update sub-module 8024 are configured to implement the shutdown. The process of adapting to functions.

The register configuration module 801 is further configured to: configure a current data communication rate according to the adaptive success flag as the updated data communication rate; configure a current data communication rate according to the adaptive failure flag to be configured to be sent by the system to the register Configure the module's default data communication rate.

For the interface timing control module 803, the communication type includes: uplink communication and downlink communication;

The interface timing refers to an interface timing that meets the requirements of the JESD207 protocol;

In other embodiments of the present invention, the interface timing control module 803 is configured to

When the data communication type in the TDD mode subframe type in the register configuration module is uplink data communication, configured to generate an interface timing corresponding to the uplink data communication;

When the data communication type in the TDD mode subframe type in the register configuration module is downlink data communication, configured to generate an interface timing corresponding to the downlink data communication, and generate the same FCLK timing as the MCLK timing according to the MCLK information delay .

The data and timing processing module 804 is configured to receive uplink data transmitted by the interface timing control module 803 according to an interface timing corresponding to the uplink data communication when the data communication type is uplink data communication, according to the register configuration module 801. The number of channels in the current data communication rate and the current data communication rate are sent to the BBIC's subsequent stage circuit;

In other embodiments of the present invention, the interface timing control module 803 sends data to the data and timing processing module 804, that the interface timing control module 803 corresponds to TXNRX, ENABLE timing signals, and MCLK timing according to uplink data communication. Receiving data of the DDR sent by the peer end through the DIQ interface, the interface timing control module 803 converting the data of the DDR The data for the single data rate (SDR) is sent to the data and timing processing module 804 for data processing, and the data and timing processing module 804 finally corresponds to the TXNRX, ENABLE timing signal and MCLK timing according to the uplink data communication. The processed SDR data is sent to the BBIC's subsequent stage circuit;

And, when the data communication type is downlink data communication, receiving downlink data transmitted by the BBIC subsequent circuit according to the interface timing corresponding to the downlink data communication, according to the number of channels in the register configuration module 801 and the current data communication rate. The downlink data is sent to the interface timing control module 803;

In other embodiments of the present invention, the data sent by the subsequent circuit of the BBIC to the data and timing processing module 804 is SDR data, and the subsequent circuit of the BBIC corresponds to the TXNRX and ENABLE timings according to the downlink data communication. The signal and MCLK timings send SDR data to the data and timing processing module 804, and the data of the SDR processed by the data and timing processing module 804 is finally converted to DDR data by the interface timing control module 803. The data of the DDR is sent by the interface timing control module 803 to the opposite end according to the downlink data communication corresponding TXNRX, ENABLE timing signal and FCLK through the DIQ interface.

In addition, the present embodiment also uses the rate adaptation module 802 to generate a rate adaptive fail flag off rate adaptation function for the problem that the MCLK frequent jitter causes frequent update of the data communication rate information. In other embodiments of the present invention, when the MCLK clock stability detection sub-module 8022 detects that the MCLK frequent jitter number satisfies the pre-configured off-rate adaptive dithering number, a rate adaptive invalidation flag is generated and sent to the register configuration module 801. And a rate adaptive information update sub-module 8024, the rate adaptive information update sub-module 8024 detects the rate adaptive invalidation flag and then turns off the rate adaptation function.

The embodiment provides a parallel interface timing control device, the register configuration module 801 is configured to acquire configuration information of the system, and the rate adaptation module 802 is configured to detect the first configuration in the register configuration module. When the information is valid, the updated data communication rate and the adaptive flag are generated by the period information of the MCLK sent by the opposite end, and the updated data communication speed is The rate and the adaptive flag are sent to a register configuration module, the register configuration module 801 is configured to configure a current data communication rate according to the adaptive flag, and the interface timing control module 803 is configured to be configured according to the register Second configuration information and MCLK information generation interface timing, the data and timing processing module 804 is configured to transmit data according to the interface timing, process data according to a current data communication rate of the register configuration module, thereby implementing a parallel interface rate Adaptive configuration.

Referring to FIG. 10, a parallel interface timing control method according to an embodiment of the present invention is shown. The method periodically detects the period information of the MCLK clock of the host RFIC and combines the channel configuration information to obtain the slave BBIC and the host. The communication rate of the RFIC; thus, the interface of the slave sends the timing signal required by the host RFIC at the detected rate to complete the communication between the two devices; since the periodic detection is performed, when the host RFIC clock MCLK changes, the communication is changed. Rate to ensure normal communication between the two devices. The method is used for a parallel interface timing control device, and the parallel interface timing control device comprises: a register configuration module, a rate adaptation module, an interface timing control module, and a data and timing processing module, the method comprising:

S1001: The register configuration module acquires configuration information of the system;

S1002: When the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module generates an updated data communication rate and an adaptive flag by using period information of the MCLK sent by the peer end, And transmitting the updated data communication rate and the adaptive flag to the register configuration module;

S1003: The register configuration module configures a current data communication rate according to the adaptive flag.

S1004: The interface timing control module generates an interface timing according to the second configuration information and the MCLK information in the register configuration module.

S1005: The data and timing processing module transmits data according to the interface timing, and processes data according to the number of channels in the register configuration module and the current data communication rate.

For the step S1001, the configuration information includes: interface module enable, number of channels, default Data communication rate, TDD mode subframe type, adaptive function enable, adaptive successful detection times, adaptive failure detection times;

For the step S1002, the rate adaptation module includes: an MCLK period detection submodule, an MCLK clock stability detection submodule, a rate adaptive failure detection submodule, and a rate adaptive information update submodule;

The period information of the MCLK sent by the peer end refers to the period information of the MCLK sent by the RFIC;

For step S1002, FIG. 11 is a flowchart of the adaptive module generating an updated data communication rate. When the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module passes The period information of the MCLK sent by the terminal generates an updated data communication rate and an adaptive flag, and sends the updated data communication rate and the adaptive flag to the register configuration module, including:

S10021: The rate adaptation module acquires period information of the MCLK by using an operating clock; the working clock is not less than twice the MCLK clock frequency and is an integer multiple of the MCLK clock frequency;

S10022: When the rate adaptation module detects that the number of coincidences of the periodic information of the two consecutive MCLKs meets the preset adaptive success value, step S10023 to step S10027 are performed; when the MCLK clock stability detection submodule detects two consecutive When the number of times of inconsistency of the periodicity information of the MCLK meets the adaptive failure value, step S10028 to step S100212 are performed;

S10023: The clock stabilization counter inside the rate adaptation module performs an accumulation count, and the rate adaptation module obtains a first accumulated count value;

S10024: When the first accumulated count value reaches a pre-configured adaptive success value of the rate adaptation module, the rate adaptation module generates a rate adaptive success flag;

S10025: The rate adaptation module sends the rate adaptive success flag to the registration Device configuration module;

S10026: When the rate adaptation module detects the rate adaptation success flag, the rate adaptation module converts the period information of the MCLK into a data communication rate;

S10027: The rate adaptation module sends a data communication rate of the cycle information conversion of the MCLK to the register configuration module as an updated data communication rate.

It should be noted that, in step S10023 to step S10027, when the rate adaptation module detects that the number of coincidences of the periodic information of the two consecutive times of MCLK meets the preset adaptive success value, an updated data communication rate is generated and sent to the The implementation process of the register configuration module.

S10028: The clock stabilization counter inside the rate adaptation module performs an accumulation count clearing, and the rate adaptation module generates an MCLK change flag.

S10029: When the rate adaptation module detects the MCLK change flag, the clock change counter in the rate adaptation module performs an accumulation count operation, and the rate adaptation module obtains a second accumulated count value;

S100210: The rate adaptation module generates a rate adaptation failure flag when the second accumulated count value reaches a pre-configured adaptive failure value of the rate adaptation module;

S100211: The rate adaptation module sends the rate adaptation failure flag to the register configuration module.

S100212: When the rate adaptation module detects the rate adaptation failure flag, the rate adaptation module turns off the rate adaptation function.

It should be noted that step S10028 to step S100212 is an implementation process for turning off the adaptive function when the rate adaptation module detects that the number of times of coincidence of the periodic information of the MCLKs that are consecutive two times satisfies the adaptive failure value.

For step S1003, the register configuration module configures a current data communication rate according to the adaptive flag, including:

The register configuration module configures a current data communication rate as the updated data communication rate according to an adaptive success flag;

The register configuration module configures a current data communication rate according to an adaptive failure flag to configure a default data communication rate that the system sends to the register configuration module.

For the step S1004, the communication type includes: uplink communication and downlink communication;

In other embodiments of the present invention, the interface timing control module generates an interface timing according to the second configuration information and the MCLK information in the register configuration module, including:

When the data communication type in the TDD mode subframe type in the register configuration module is uplink data communication, the interface timing control module generates an interface timing corresponding to the uplink data communication;

When the data communication type in the TDD mode subframe type in the register configuration module is downlink data communication, the interface timing control module generates an interface timing corresponding to the downlink data communication, and the interface timing control module according to the MCLK information The delay generates the same FCLK timing as the MCLK timing.

For step S1005, the data includes uplink receiving data and downlink sending data;

For step S1005, FIG. 12 is a flowchart of processing data by the data and timing processing module, the data and timing processing module transmits data according to the interface timing, and processes according to the number of channels in the register configuration module and the current data communication rate. Data, including:

S10051: when the data communication type is uplink data communication, the data and timing processing module receives uplink data transmitted by the interface timing control module according to an interface timing corresponding to the uplink data communication, where the data and timing processing module is configured according to the register Configuring the number of channels in the module and the current data communication rate to send the uplink data to the subsequent circuit of the BBIC;

S10052: When the data communication type is downlink data communication, the data and timing processing module receives downlink data transmitted by the BBIC subsequent circuit according to an interface timing corresponding to the downlink data communication, where the data and timing processing module is configured according to the register The number of channels in the module and the current data communication rate send the downlink data to the interface timing control module.

In other embodiments of the present invention, for step S10051, the interface timing control module The data sent to the data and the timing processing module means that the interface timing control module receives the data of the DDR sent by the opposite end through the DIQ interface according to the uplink data communication corresponding to the TXNRX, the ENABLE timing signal and the MCLK timing, and the interface timing control module Data for converting DDR data into SDR is sent to the data and timing processing module for data processing, and the data and timing processing module finally responds to the TXNRX, ENABLE timing signal and MCLK sequence processed SDR data according to the uplink data communication. Send to the rear stage circuit of BBIC;

In other embodiments of the present invention, for the step S10052, the data sent by the subsequent circuit of the BBIC to the data and the timing processing module is data of the SDR, and the subsequent circuit of the BBIC corresponds to the TXNRX according to the downlink data communication. The ENDR timing signal and the MCLK timing send the SDR data to the data and timing processing module, and the data of the SDR processed by the data and the timing processing module is finally converted into the data of the DDR by the interface timing control module, The data of the DDR is sent to the opposite end by the interface timing control module through the DIQ interface according to the downlink data communication corresponding to the TXNRX, ENABLE timing signal and FCLK.

In addition, in this embodiment, the rate adaptation module generates a rate adaptive failure flag off rate adaptation function for the problem that the MCLK frequent jitter causes the data communication rate information to be frequently updated. In other embodiments of the present invention, when the MCLK clock stability detection sub-module detects that the MCLK frequent jitter number satisfies a pre-configured off-rate adaptive dither count, a rate adaptive fail flag is generated and sent to the register configuration module and the rate adaptation. The information update sub-module, the rate adaptive information update sub-module detects the rate adaptive invalidation flag and then turns off the rate adaptation function.

The embodiment provides a parallel interface timing control method, the register configuration module acquires configuration information of the system, and when the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate is self-determined. The adaptation module generates an updated data communication rate and an adaptive flag by using the period information of the MCLK sent by the peer end, and sends the updated data communication rate and the adaptive flag to the register configuration module, where the register configuration module is configured according to the Adapting the flag to configure a current data communication rate, the interface timing control module according to the registration The second configuration information in the configuration module selects a timing signal required for the communication type and the communication type, the data and timing processing module transmits data according to the interface timing, and processes data according to the current data communication rate of the register configuration module. Thereby achieving parallel interface rate adaptive configuration.

Those skilled in the art will appreciate that embodiments of the present invention can provide a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.

The invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the program diagrams and/or block diagrams, and combinations and/or combinations of flowcharts and/or block diagrams can be implemented by computer program instructions. Processors that provide such computer program instructions to a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device are susceptible to generating a machine that is executed by a processor or other programmable data processing device. Means for implementing the functions specified in one or more flows of the flowchart or in a block or blocks of the flowchart.

These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computing and readable memory produce an article of manufacture comprising the instruction device. The instruction means implements the functions specified in one or more blocks of the flow or processes and/or block diagrams in the flowchart.

These computer program instructions can also be loaded on a computer or other programmable processing device such that instructions executed on a computer or other programmable device are provided for implementation in a flow or a block diagram of a flow or a block diagram or The steps of the function specified in multiple boxes.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Industrial applicability

In the embodiment of the present invention, the register configuration module acquires configuration information of the system; when the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module sends the information through the peer end. The cycle information of the MCLK generates an updated data communication rate and an adaptive flag, and sends the updated data communication rate and the adaptive flag to the register configuration module; the register configuration module configures the current data communication according to the adaptive flag Rate; the interface timing control module generates an interface timing according to the second configuration information and the MCLK information in the register configuration module; the data and timing processing module transmits data according to the interface timing, according to the register configuration module current The data communication rate processes the data to enable parallel interface rate adaptive configuration.

Claims

A parallel interface timing control device, the parallel interface timing control device includes: a register configuration module, a rate adaptation module, an interface timing control module, and a data and timing processing module, wherein

The register configuration module is configured to acquire configuration information of the system;

The rate adaptation module is configured to generate an updated data communication rate and an adaptive flag by using period information of the MCLK sent by the peer end when detecting that the first configuration information in the register configuration module is valid, and the updating Data communication rate and adaptive flag are sent to the register configuration module;

The register configuration module is further configured to configure a current data communication rate according to the adaptive flag;

The interface timing control module is configured to generate an interface timing according to the second configuration information and the MCLK information in the register configuration module;

The data and timing processing module is configured to transmit data according to the interface timing, and process data according to the number of channels in the register configuration module and the current data communication rate.
The apparatus according to claim 1, wherein the configuration information comprises: interface module enable, number of channels, default data communication rate, TDD mode subframe type, adaptive function enable, adaptive successful detection times, and adaptation The number of failure detections; wherein the adaptive function is enabled to correspond to the first configuration information, and the TDD mode subframe type corresponds to the second configuration information.
The apparatus of claim 1, wherein the adaptive flag comprises an adaptive success flag and an adaptive failure flag.
The apparatus according to claim 1, wherein the rate adaptation module comprises: an MCLK period detection sub-module, an MCLK clock stability detection sub-module, a rate adaptive failure detection sub-module, and a rate adaptive information update sub-module; ,

The MCLK period detection submodule is configured to acquire a week of MCLK through an operating clock Period information, the cycle information of the MCLK is sent to the MCLK clock stability detection sub-module and the rate adaptive information update sub-module in real time;

The MCLK clock stability detection sub-module is configured to trigger the rate adaptive information update sub-module to generate an updated data communication rate when detecting that the number of consecutive times of the MCLK periodic information coincides with the preset adaptive success value And transmitting the updated data communication rate to the register configuration module;

The MCLK clock stability detection sub-module is further configured to trigger the rate adaptive information update sub-module to disable the adaptive function when detecting that the number of times of inconsistency of the periodic information of the two consecutive MCLKs meets the adaptive failure value.
The apparatus according to claim 4, wherein said MCLK clock stability detection submodule is configured to

When the period information of the MCLK consecutively detected is consistent, the internal clock stabilization counter performs an accumulation count to obtain a first accumulated count value;

And generating a rate adaptive success flag when the first accumulated count value reaches a pre-configured adaptive success value;

And transmitting the rate adaptive success flag to the rate adaptive information update submodule and the register configuration module;

The rate adaptive information update submodule is configured to convert the period information of the MCLK into a data communication rate when the rate adaptive success flag is detected;

And, the data communication rate converted by the cycle information of the MCLK is sent to the register configuration module as an updated data communication rate.
The apparatus according to claim 4, wherein the MCLK clock stability detection submodule is further configured to

When the period information of the MCLK detected twice consecutive times is inconsistent, the internal clock stabilization counter performs an accumulated count clearing to generate an MCLK change flag;

And transmitting the MCLK change flag to the rate adaptive failure detection submodule Piece;

The rate adaptive fail detection sub-module is configured to perform an accumulative counting operation on the internal clock change counter when the MCLK change flag is detected, to obtain a second accumulated count value;

And generating a rate adaptation failure flag when the second accumulated count value reaches a pre-configured adaptive failure value;

And transmitting the rate adaptive failure flag to the rate adaptive information update submodule and the register configuration module;

The rate adaptive information update submodule is further configured to turn off the rate adaptation function when the rate adaptation failure flag is detected.
The apparatus of claim 1, wherein the register configuration module is further configured to

Configuring a current data communication rate according to an adaptive success flag as the updated data communication rate;

And configuring a current data communication rate according to the adaptive failure flag to configure a default data communication rate that the system sends to the register configuration module.
The apparatus of claim 1, wherein the interface timing control module is configured to

When the data communication type in the TDD mode subframe type in the register configuration module is uplink data communication, configured to generate an interface timing corresponding to the uplink data communication;

When the data communication type in the TDD mode subframe type in the register configuration module is downlink data communication, configured to generate an interface timing corresponding to the downlink data communication, and generate the same FCLK timing as the MCLK timing according to the MCLK information delay .
The apparatus of claim 1, wherein the data and timing processing module is configured to

When the data communication type is uplink data communication, according to the interface corresponding to the uplink data communication Receiving, by the terminal, the uplink data transmitted by the interface timing control module, and transmitting the uplink data to the subsequent circuit of the BBIC according to the number of channels in the register configuration module and the current data communication rate;

And, when the data communication type is downlink data communication, receiving downlink data transmitted by the BBIC subsequent circuit according to the interface timing corresponding to the downlink data communication, according to the number of channels in the register configuration module and the current data communication rate. The downlink data is sent to the interface timing control module.
A parallel interface timing control method, the method is used for a parallel interface timing control device, the parallel interface timing control device includes: a register configuration module, a rate adaptation module, an interface timing control module, and a data and timing processing module, Methods include:

The register configuration module acquires configuration information of the system;

When the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module generates an updated data communication rate and an adaptive flag by using period information of the MCLK sent by the peer, and Transmitting the updated data communication rate and the adaptive flag to the register configuration module;

The register configuration module configures a current data communication rate according to the adaptive flag;

The interface timing control module generates an interface timing according to the second configuration information and the MCLK information in the register configuration module;

The data and timing processing module transmits data according to the interface timing, and processes data according to the number of channels in the register configuration module and the current data communication rate.
The method according to claim 10, wherein the configuration information comprises: interface module enable, number of channels, default data communication rate, time division duplex TDD mode subframe type, adaptive function enable, adaptive success detection times The number of times of the adaptive failure detection; wherein the adaptive function is enabled to correspond to the first configuration information, and the TDD mode subframe type corresponds to the second configuration information.
The method of claim 10 wherein said adaptive flag comprises: Adapt to success flags and adaptive failure flags.
The method according to claim 10, wherein said rate adaptation module transmits period information of MCLK transmitted by the opposite end when said first configuration information in said register configuration module is valid Generating an updated data communication rate and an adaptive flag, and transmitting the updated data communication rate and the adaptive flag to the register configuration module, including:

The rate adaptation module acquires period information of the MCLK by using an operating clock;

When the rate adaptation module detects that the number of coincidences of the cycle information of the two consecutive MCLKs meets the preset adaptive success value, generates an updated data communication rate, and sends the updated data communication rate to the register configuration Module

When the rate adaptation module detects that the number of times of inconsistency of the period information of the MCLK consecutively meets the adaptive failure value, the adaptive function is turned off.
The method according to claim 13, wherein when the rate adaptation module detects that the number of coincidences of the period information of the two consecutive MCLKs satisfies a preset adaptive success value, an updated data communication rate is generated, and The updated data communication rate is sent to the register configuration module, including:

When the rate adaptation module detects that the period information of the two consecutive MCLKs is consistent, the clock stabilization counter inside the rate adaptation module performs an accumulation count, and the rate adaptation module obtains a first accumulated count value;

The rate adaptation module generates a rate adaptive success flag when the first accumulated count value reaches a pre-configured adaptive success value of the rate adaptation module;

When the rate adaptation module detects the rate adaptation success flag, the rate adaptation module converts the period information of the MCLK into a data communication rate;

The rate adaptation module transmits the data communication rate of the cycle information conversion of the MCLK to the register configuration module as an updated data communication rate.
The method of claim 13 wherein said MCLK clock stability The detecting submodule detects that the number of times of inconsistency of the period information of the MCLK that is consecutively two times meets the value of the adaptive failure, and triggers the rate adaptive information update submodule to turn off the adaptive function, including:

When the rate adaptation module detects that the period information of the two consecutive MCLKs is inconsistent, the clock stabilization counter inside the rate adaptation module performs an accumulation count clearing, and the rate adaptation module generates an MCLK change flag;

When the rate adaptation module detects the MCLK change flag, the clock change counter in the rate adaptation module performs an accumulation count operation, and the rate adaptation module obtains a second accumulated count value;

The rate adaptation module generates a rate adaptation failure flag when the second accumulated count value reaches a pre-configured adaptive failure value of the rate adaptation module;

The rate adaptation module sends the rate adaptation failure flag to the register configuration module;

The rate adaptation module turns off the rate adaptation function when the rate adaptation module detects the rate adaptation failure flag.
The method of claim 10, wherein the register configuration module configures a current data communication rate based on the adaptive flag, comprising:

The register configuration module configures a current data communication rate as the updated data communication rate according to an adaptive success flag;

The register configuration module configures a current data communication rate according to an adaptive failure flag to configure a default data communication rate that the system sends to the register configuration module.
The method of claim 10, wherein the interface timing control module generates an interface timing according to the second configuration information and the MCLK information in the register configuration module, including:

When the data communication type in the TDD mode subframe type in the register configuration module is uplink data communication, the interface timing control module generates an interface timing corresponding to the uplink data communication;

When the data communication type in the TDD mode subframe type in the register configuration module is downlink data communication, the interface timing control module generates an interface timing corresponding to the downlink data communication, and the interface timing control module according to the MCLK information The delay generates the same FCLK timing as the MCLK timing.
The method of claim 10, wherein the data and timing processing module transmits data according to the interface timing, and processes data according to the number of channels in the register configuration module and the current data communication rate, including:

When the data communication type is uplink data communication, the data and timing processing module receives uplink data transmitted by the interface timing control module according to an interface timing corresponding to the uplink data communication, and the data and timing processing module according to the register configuration module The number of channels in the current data communication rate and the current data communication rate are sent to the BBIC's subsequent stage circuit;

When the data communication type is downlink data communication, the data and timing processing module receives the downlink data transmitted by the subsequent circuit of the BBIC according to the interface timing corresponding to the downlink data communication, and the data and timing processing module is configured according to the register configuration module. The number of channels and the current data communication rate send the downlink data to the interface timing control module.