WO2018055838A1 - Semiconductor element manufacturing method and semiconductor substrate - Google Patents

Semiconductor element manufacturing method and semiconductor substrate Download PDF

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Publication number
WO2018055838A1
WO2018055838A1 PCT/JP2017/020355 JP2017020355W WO2018055838A1 WO 2018055838 A1 WO2018055838 A1 WO 2018055838A1 JP 2017020355 W JP2017020355 W JP 2017020355W WO 2018055838 A1 WO2018055838 A1 WO 2018055838A1
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substrate
layer
single crystal
semiconductor element
crystal layer
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PCT/JP2017/020355
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French (fr)
Japanese (ja)
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光治 加藤
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株式会社テンシックス
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Priority to JP2018540631A priority Critical patent/JP6930746B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • the present invention relates to a method for manufacturing a semiconductor element and a semiconductor substrate. Specifically, the present invention relates to a semiconductor element manufacturing method for manufacturing a semiconductor element having a high thickness and a high breakdown voltage by using a temporary substrate, and a semiconductor substrate on which the high breakdown voltage semiconductor element is formed.
  • FIG. 16A shows a cross-sectional structure of a general vertical structure Schottky diode (91) made of SiC.
  • An active layer 902 is formed by epitaxial growth on a support substrate 901 made of a single crystal, and P-type impurity layers 911 and 912 serving as a guard ring and a Schottky electrode 913 are formed in the active layer 902 region.
  • the current i flows between the Schottky electrode 913 and the back electrode 903 formed on the bottom surface of the support substrate 901.
  • FIG. 2B shows the cross-sectional structure of a general vertical MOSFET (92) made of SiC.
  • An active layer 902 is formed by epitaxial growth on a support substrate 901 made of a single crystal, and a source 921, a drain 922, and a gate 923 are formed in the region of the active layer 902.
  • the conduction and interruption of the current between the source 921 and the drain 922 are controlled by the gate 923.
  • the drain current i during conduction flows between the drain 922 and the back electrode 903 formed on the bottom surface of the support substrate 901.
  • FIG. 6C shows a cross-sectional structure of a MOSFET (94) provided with a single crystal buffer layer 904 having a high nitrogen concentration in the initial stage of forming the active layer 902 by epitaxial growth.
  • the single crystal buffer layer 904 is formed in order to reduce the crystal defect density of the epitaxial layer as compared with the crystal defect density of the support substrate 901.
  • the support substrate 901 is a region where current flows in the vertical direction (vertical direction in the drawing), and has a low resistivity of 20 m ⁇ ⁇ cm or less.
  • the active layer 902 requires a high voltage withstand voltage, and therefore has a resistivity that is two to three orders of magnitude higher than that of the support substrate 901. Since a semiconductor element using SiC has a large band gap width, the thickness of the active layer 902 can be reduced to about 5 to 10 ⁇ m.
  • the active layer 902 is formed on the support substrate 901 by epitaxial growth, the crystallinity of the active layer 902 depends on the base support substrate 901. For this reason, the SiC crystal quality of the support substrate 901 is important.
  • the thickness of the support substrate 901 is required to be about 300 ⁇ m in the case of a 6-inch substrate in order to prevent cracking when handling the single crystal substrate. Then, after forming the element on the front surface side of the substrate, in order to reduce the resistance of the support substrate portion, the back surface is ground and the thickness is reduced to 100 ⁇ m or less.
  • the support substrate 901 which is the base of the active layer 902 to be epitaxially grown.
  • the support substrate 901 is an N-type semiconductor by adding high-concentration nitrogen in order to reduce the resistivity.
  • the resistance of the support substrate layer is further reduced by processing the support substrate 901 thinly.
  • an expensive single crystal substrate is used as a substrate for a semiconductor element, and the thickness of the single crystal substrate is not increased for the active layer, but is increased for handling the substrate in the element formation process. Has been. Further, after the element is formed, the substrate is processed thinly, and a large part of the single crystal substrate is currently removed by grinding.
  • the substrate of the semiconductor element made of SiC only the surface active layer may be a single crystal.
  • the supporting substrate layer may be monocrystalline, polycrystalline, or amorphous regardless of crystallinity.
  • a substrate manufacturing method in which a single crystal active layer and a non-single crystal support substrate layer are bonded.
  • a substrate manufacturing method in which amorphous silicon is deposited on a polycrystalline SiC support, the polycrystalline SiC support and a single crystal SiC substrate are joined, and integrated by direct bonding see Patent Document 1).
  • An example in which substrates are bonded by a surface activation method is also disclosed (see Patent Document 3).
  • a thin film layer made of a single crystal is formed as an active layer on a support substrate (support layer) having a certain thickness.
  • the active layer is manufactured by epitaxial growth. Since this support substrate may be a single crystal or a polycrystal, a method of bonding a thin single crystal layer and an inexpensive polycrystalline semiconductor substrate by a bonding technique has been proposed (Patent Documents 1, 2, 3, etc.). .
  • Patent Documents 1, 2, 3, etc. a method of bonding a thin single crystal layer and an inexpensive polycrystalline semiconductor substrate by a bonding technique has been proposed (Patent Documents 1, 2, 3, etc.).
  • the bonding substrate made of different materials has a large amount of warpage due to a difference in thermal expansion coefficient and non-uniformity of crystals, and there are many problems in practical use.
  • a thick single crystal SiC substrate of about 350 ⁇ m is used for handling during processing, and the thickness of the support layer is finally reduced to about 100 ⁇ m in order to obtain good device characteristics.
  • this has a problem that an expensive single crystal substrate is not fully utilized.
  • the support layer is thinned after forming the element, it is conceivable to use a thin substrate as the element substrate.
  • the thickness of the substrate is sufficient for the thickness of the epitaxial layer portion of the surface layer even for a high voltage element. You can pay attention.
  • a thin substrate is easy to bend and warpage increases.
  • the single crystal buffer layer 904 is provided as shown in FIG. 16C to reduce the crystal defects of the epitaxial layer 902, the phenomenon that the crystal defects increase due to the influence of minority carriers during the operation of the MOSFET element is known. ing. For this reason, it is preferable to remove the single crystal buffer layer 904 after the element is formed, but it is impossible to remove the single crystal buffer layer 904 which is the base of the epitaxial layer 902 on which the MOSFET element is formed with a general structure. It is.
  • the present invention has been made in view of the above situation, and a semiconductor device manufacturing method for manufacturing a semiconductor device having a thin thickness and a high breakdown voltage by using a temporary substrate, and a high breakdown voltage semiconductor element formed.
  • An object of the present invention is to provide a semiconductor substrate.
  • the present invention is as follows. 1. A second film forming step of forming a second single crystal layer made of a single crystal of a second semiconductor material on a second substrate to be a temporary support substrate; and forming a semiconductor element on the second single crystal layer An element forming step, a second bonding step of bonding a third substrate on the second single crystal layer on which the semiconductor element is formed, and removing the second substrate after bonding the third substrate And a substrate removing step for performing a semiconductor device manufacturing method. 2. A bonding step of bonding one plane of the first substrate made of a single crystal of the first semiconductor material and the second substrate; and the first substrate at a predetermined depth from the bonding surface of the second substrate.
  • the first single crystal layer is formed on the first single crystal layer formed on the second substrate.
  • the first single crystal layer is formed on the surface thin film layer formed on the second substrate by separating the first substrate with the hydrogen injection layer in the separation step.
  • the second film forming step leaves a multi-layer substrate in which the surface thin film layer, the first single crystal layer, and the second single crystal layer are sequentially stacked on the second substrate, and the substrate is removed.
  • the surface thin film layer is further removed.
  • the second single crystal layer is formed after forming a single crystal buffer layer made of a single crystal of the second semiconductor material.
  • the substrate removing step the single crystal buffer layer is formed Further removing the above 1.
  • the manufacturing method of the semiconductor element in any one of. 6). 6. The method of manufacturing a semiconductor element according to claim 2, further comprising a silicide layer forming step of forming a silicide layer on the one plane of the first substrate. 7).
  • the silicon oxide film or the compound semiconductor film containing Ga is formed on the one surface of the second substrate as the surface thin film layer.
  • the buffer layer made of a semiconductor material is further formed on the one plane side of the second substrate as the surface thin film layer.
  • the polycrystalline SiC film made of SiC polycrystal is formed on the other plane of the second substrate as the surface thin film layer.
  • the second substrate is a light transmitting substrate, and the surface thin film layer is a semiconductor material containing Ga.
  • Ga is deposited by irradiating a laser beam from the second substrate side. Removing the second substrate by To 5.
  • the first substrate is a substrate made of sapphire or SiC.
  • the manufacturing method of the semiconductor element in any one of. 12 The second substrate is a substrate made of carbon, and in the first film formation step, the surface thin film layer is formed so as to cover a side surface side of the second substrate.
  • the first substrate is a metal substrate.
  • the third substrate is a substrate made of one of alkali-free glass, sapphire, and Si. To 12.
  • the through-hole is formed in a tapered shape that expands toward the surface side of the third substrate.
  • the first semiconductor material is one of SiC, GaN and gallium oxide
  • the second semiconductor material is one of SiC, GaN and gallium oxide.
  • a first single crystal layer made of a single crystal of a first semiconductor material is provided on the second single crystal layer, and the back electrode layer is formed on the first single crystal layer or on the first single crystal layer.
  • the above-mentioned 20 provided on a buffer layer made of a semiconductor material provided on the substrate.
  • the first semiconductor material is one of SiC, GaN, and gallium oxide
  • the second semiconductor material is one of SiC, GaN, and gallium oxide.
  • the method for manufacturing a semiconductor device of the present invention includes a second film forming step of forming a second single crystal layer made of a single crystal of a second semiconductor material on a second substrate to be a temporary support substrate, And an element formation step of forming a semiconductor element in the second single crystal layer. For this reason, a multi-layer substrate on which the second single crystal layer is formed using the second substrate as a base is obtained, and can be a substrate for element formation that can withstand high temperatures and has less warpage. Thus, in the element formation step, a semiconductor element can be formed in the second single crystal layer using a general-purpose photolithography apparatus or the like.
  • the method for manufacturing a semiconductor device of the present invention includes a second bonding step of bonding a third substrate on the second single crystal layer on which the semiconductor device is formed, and a substrate removal step of removing the second substrate. And. For this reason, after joining the 3rd board
  • a multilayer substrate in which layers are stacked is obtained, and the amount of the first substrate made of a single crystal of the first semiconductor material (for example, SiC) can be minimized.
  • a single crystal SiC substrate having a high concentration of N-type and having a thickness of about 350 ⁇ m is used as a support layer, and a single crystal having a thickness of about 5 ⁇ m is formed thereon by epitaxial growth.
  • a SiC layer (low-concentration N-type layer) is formed.
  • the substrate is polished and thinned to about 100 ⁇ m in order to reduce the resistance value of the support layer portion, and then the electrode is processed on the back surface of the substrate. .
  • an N-type layer is constituted by the first single crystal layer, and the thickness thereof can be reduced to about 0.5 ⁇ m.
  • a second single crystal layer having a necessary thickness and a necessary impurity concentration can be formed by epitaxial growth or MOCVD (Metal Organic Chemical Vapor Deposition) in terms of the breakdown voltage of the semiconductor element.
  • MOCVD Metal Organic Chemical Vapor Deposition
  • the first single crystal layer is formed on the surface thin film layer formed on the second substrate by separating the first substrate with the hydrogen injection layer in the separation step.
  • the second film forming step leaves a multi-layer substrate in which the surface thin film layer, the first single crystal layer, and the second single crystal layer are sequentially stacked on the second substrate, and the substrate is removed.
  • the substrate when the surface thin film layer is further removed, The substrate can be easily bonded to the second substrate which surface thin film layer is formed.
  • the first substrate can be easily separated in the hydrogen injection layer, and the first single crystal layer having a small thickness can be left on the second substrate. Then, since the surface thin film layer is removed in the substrate removal step, the back electrode of the semiconductor element can be provided on the surface of the first single crystal layer exposed thereby.
  • the second single crystal layer is formed after forming a single crystal buffer layer made of a single crystal of the second semiconductor material.
  • the substrate removing step the single crystal buffer layer is formed In the case of further removal, the crystal defect density of the second single crystal layer formed on the single crystal buffer layer can be lowered.
  • the second substrate used for forming the semiconductor element is removed, and the single crystal buffer layer is also removed. Even if a forward current flows through the PN junction, it is possible to suppress an increase in defects due to minority carrier recombination.
  • the first film formation step when a compound semiconductor film containing a silicon oxide film or Ga is formed on the one plane of the second substrate as the surface thin film layer, the first substrate in the bonding step , Removal of the second substrate in the substrate removal step, and removal of the surface thin film layer after removal of the second substrate can be facilitated. Further, the surface thin film layer and the second single crystal layer laminated thereon can be combined to form a substrate for an element that can withstand high temperatures and has less warpage as a multilayer substrate.
  • a silicon oxide film or a compound semiconductor film containing Ga can be formed as a two-layer surface thin film layer with the first layer as the first layer and the buffer layer as the second layer.
  • the surface thin film layer is used to form the second substrate.
  • the entire surface can be covered, and the second substrate can be protected from high-temperature processing or the like when forming the semiconductor element.
  • the stress on both sides can be balanced, so that a thin multilayer substrate with less warpage can be obtained.
  • the surface thin film layer is formed so that the thickness is uniform up to the plate end on the plane of the second substrate. A film can be formed and bonded to the first substrate without polishing its surface.
  • the second substrate is a light transmitting substrate, and the surface thin film layer is a semiconductor material containing Ga.
  • Ga is deposited by irradiating a laser beam from the second substrate side.
  • the second substrate can be easily removed by laser light irradiation.
  • the removed second substrate can be reused after the residue of the material containing Ga is removed.
  • the second substrate is a substrate made of sapphire or SiC
  • it can be a substrate for element formation that can withstand high temperatures and has less warpage as the base of the multilayer substrate.
  • the second substrate is a substrate made of carbon.
  • the first film formation step when the surface thin film layer is formed so as to cover the side surface of the second substrate, the entire carbon substrate is formed. Since the surface is covered with the surface thin film layer, carbon that burns out in an environment where oxygen exists at a high temperature can be protected. This makes it possible to perform high-temperature heat treatment, film formation containing high-density oxygen, or the like in the element formation process. Further, even if the thickness of the carbon substrate is reduced, the stress on both sides can be balanced, so that a thin multilayer substrate with less warpage can be obtained.
  • the metal substrate serving as a support substrate for the semiconductor element can be used as an electrode terminal for external connection as it is.
  • the metal substrate can be an anode electrode, and the cathode electrode can be formed on the surface from which the second substrate is removed.
  • the semiconductor element is a MOSFET
  • the metal substrate can be used as it is as the source electrode. In these cases, it becomes easy to mount the metal substrate on the mounting substrate after element division.
  • the third substrate is a substrate made of one of alkali-free glass, sapphire, and Si, it is easy to join and is suitable as a support substrate for a semiconductor element.
  • the surface exposed after removing the second substrate first single crystal layer, A back electrode layer can be provided on the buffer layer or the second single crystal layer.
  • an electrode wiring for mounting the semiconductor element is provided in the case where the third substrate is provided with an opening step for forming a through hole to be an electrode portion of the semiconductor element. Can be made easier.
  • the opening step when the through hole is formed in a tapered shape that expands toward the surface side of the third substrate, wiring such as aluminum may be formed on the wall surface of the through hole that becomes a slope.
  • electrical wiring can be formed on the surface of the third substrate.
  • the first semiconductor material is one of SiC, GaN, and gallium oxide
  • the second semiconductor material is one of SiC, GaN, and gallium oxide
  • the first semiconductor material having a large band gap is used. Since the second single crystal layer made of the second semiconductor material having a large band gap is formed on the single crystal layer, SiC elements, GaN elements, gallium oxide elements, etc. suitable for high power applications Can be manufactured. For example, if the first semiconductor material and the second semiconductor material are SiC, a single crystal SiC layer is stacked, which is more preferable.
  • the support substrate is made of one of an insulating material, a semiconductor material, and a metal, and is formed of a single crystal of the second semiconductor material laminated on the support substrate with a bonding layer interposed therebetween.
  • a second single crystal layer is provided, a semiconductor element is formed on the second single crystal layer, and a back electrode layer of the semiconductor element is provided on the second single crystal layer. Since the back surface electrode layer of the semiconductor element is directly formed on the second single crystal layer, it has excellent conductivity. If the buffer layer is formed of a polycrystalline layer containing a high nitrogen concentration, a lower ohmic contact can be obtained.
  • the thickness of the first single crystal layer made of the single crystal of the first semiconductor material is minimized. Therefore, a low-cost semiconductor substrate can be obtained.
  • the second single crystal layer having a necessary thickness and a necessary impurity concentration is formed from the surface of the withstand voltage of the semiconductor element, and the supporting substrate which is a permanent supporting layer of the semiconductor substrate may have an arbitrary thickness. it can.
  • the back electrode layer is provided on the first single crystal layer or on the buffer layer made of a semiconductor material provided on the first single crystal layer. It has excellent thermal conductivity and is suitable for semiconductor devices for high power applications.
  • the first semiconductor material is one of SiC, GaN, and gallium oxide
  • the second semiconductor material is one of SiC, GaN, and gallium oxide
  • the first semiconductor material having a large band gap is used. Since the second single crystal layer made of the second semiconductor material having a large band gap is formed on the single crystal layer, an SiC element, a GaN element, a gallium oxide element, etc. suitable for high power applications The semiconductor substrate on which is formed.
  • Typical sectional drawing which shows the process of removing the 1st layer of a 2nd board
  • Schematic sectional view showing the manufacturing process of Schottky diode Schematic cross-sectional view showing the manufacturing process of MOSFET
  • Typical sectional drawing which shows the manufacturing process of the semiconductor substrate (MOSFET element) using a metal support substrate
  • Schematic cross-sectional view showing the basic structure of a semiconductor substrate Schematic sectional view showing the structure of a semiconductor substrate
  • the semiconductor element manufacturing method uses a semiconductor element suitable for high power applications by using, for example, a carbon substrate, an SiC substrate, or the like as a temporary support substrate (second substrate (2)).
  • a carbon substrate, an SiC substrate, or the like As a temporary support substrate (second substrate (2)).
  • Carbon substrates and SiC substrates have a feature that they can withstand high temperatures with little warping.
  • the carbon substrate (2) or the like is used as a temporary support layer, and a single crystal layer such as SiC (first single crystal layer (11) is provided on one surface of the carbon substrate (2) via a silicon oxide film or the like (41). ))
  • a thin film layer (second single crystal layer (5)) made of a single crystal such as SiC for forming a semiconductor element is formed (see FIGS. 2A and 2B).
  • a polycrystalline film made of SiC or the like can be formed on the other surface of the carbon substrate (2).
  • a semiconductor element can be formed in the second single crystal layer (5) using the multilayer substrate (6) formed on the basis of the carbon substrate (2) or the like in this way. Then, after the formation of the semiconductor element, a substrate (third substrate (3)) to be a final support layer is bonded, and the carbon substrate (2) and the like which are temporary substrates are removed. Thus, a semiconductor substrate in which the third substrate (3) is a permanent support layer and a semiconductor element is formed on the second single crystal layer (5) laminated thereon can be manufactured.
  • a back electrode layer to be a back electrode of the semiconductor element can be formed on the back surface of the semiconductor element (the surface from which the carbon substrate or the like has been removed and the silicon oxide film has been removed).
  • the carbon substrate (2) can have a thermal expansion coefficient substantially the same as that of the second single crystal layer (5) made of SiC and the polycrystalline SiC film (42) made of SiC. If the thickness of the carbon substrate (2) is several mm, a multilayer substrate (6) having high rigidity and no warpage can be obtained.
  • the thickness of the second single crystal layer (5) made of SiC laminated on one surface of the carbon substrate (2) and the thickness of the polycrystalline SiC film (42) formed on the other surface should be made substantially the same. For example, even if the thickness of the carbon substrate (2) is 1 mm or less, a multilayer substrate (6) with little warpage can be obtained.
  • the carbon substrate (2) is formed from the formation of a silicon oxide film or the like (41), the formation of a polycrystalline SiC film (42), the bonding of the first single crystal layer (11), the second single crystal layer (5). It serves as a foundation from film formation to formation of the semiconductor element.
  • the third substrate (3) is bonded to the multilayer substrate (6), the carbon substrate (2) and the silicon oxide film (41) are removed, so that the back surface of the multilayer substrate (6) is removed.
  • the first single crystal layer (11) is exposed, and the back electrode of the semiconductor element can be formed.
  • the third substrate (3) plays the role of the support substrate as a base.
  • the conventional structure see FIG.
  • a single crystal layer for forming a semiconductor element is provided on a thick support substrate made of a single crystal, and the thickness of the support substrate is further reduced.
  • the conventional support substrate can be eliminated, and the thinning step can be eliminated.
  • a high-quality second single crystal layer (5) serving as an active layer of a semiconductor element can be formed on the first single crystal layer (11) made of a single crystal with good crystallinity.
  • a single crystal single crystal buffer layer (52) containing high-concentration nitrogen is formed on a first single crystal layer (11) formed using a carbon substrate (2) or the like as a base, and then a second single crystal layer ( 5) may be formed.
  • the single crystal buffer layer (52) can reduce the crystal defects in the second single crystal layer (5) more than the crystal defects in the first single crystal layer (11).
  • the carbon substrate (2), the silicon oxide film (41), etc. are removed, and the first single crystal layer is further removed.
  • the second single crystal (5) is exposed on the back surface of the multilayer substrate (6), and the back electrode of the semiconductor element is formed on the back surface. be able to.
  • the third substrate (3) that will be the final support layer of the semiconductor element is bonded, and the second substrate (2), which was a temporary substrate, is removed.
  • the third substrate (3) is a metal substrate
  • the third substrate (3) can be used as an electrode terminal for external connection of a semiconductor element.
  • the semiconductor element is a Schottky diode
  • the anode electrode can be used.
  • the source electrode can be used.
  • the second substrate (2) for example, a substrate that transmits laser light, such as a SiC substrate (25) or a sapphire substrate (26), can be used.
  • a substrate that transmits laser light such as a SiC substrate (25) or a sapphire substrate (26)
  • a surface thin film layer for example, a GaN film (413)
  • a semiconductor material containing Ga for example, GaN film (413)
  • the SiC substrate or the sapphire substrate can be repeatedly used as the second substrate (2) after removing the Ga-based thin film.
  • the method of manufacturing a semiconductor device according to this embodiment has a predetermined depth from one plane 101 of the first substrate 1 made of a single crystal of a first semiconductor material. Then, a hydrogen layer forming step for forming the hydrogen injection layer 15 and a first thin film layer 4 made of one or more thin films of an insulating material or a semiconductor material are formed on at least one plane of the second substrate 2. A film forming process, a bonding process for bonding one flat surface 101 of the first substrate 1 and the surface of the surface thin film layer 4 formed on the second substrate 2, and the first substrate 1 to the hydrogen injection layer 15.
  • a second bonding step for bonding the third substrate 3 to the surface of the multilayer substrate 6 on which the semiconductor element is formed, and a substrate removing step for removing the second substrate 2 are provided.
  • the surface thin film layer 41 can be formed on one flat surface 201 of the second substrate 2.
  • the surface thin film layer 42 can be formed on the other plane 202 of the second substrate 2.
  • the second film forming step after forming a single crystal buffer layer 52 made of a single crystal of a second semiconductor material on the surface of the first single crystal layer 11, the second single crystal layer 5 is formed, and the substrate In the removing step, the single crystal buffer layer 52 can be removed after removing the second substrate 2.
  • the single crystal buffer layer 52 can be formed of, for example, a single crystal of a second semiconductor material containing nitrogen at a high concentration.
  • the first substrate 1 is a single crystal SiC substrate.
  • a carbon substrate is used as the second substrate 2
  • the surface thin film layer 41 formed on one surface 201 is a silicon oxide film (SiO 2 ).
  • the material of the surface thin film layer 42 formed on the other surface 202 is preferably the same as that of the second semiconductor material, and the crystallinity thereof is not limited. In the following, it is assumed that the surface thin film layer 42 is a polycrystalline SiC film made of polycrystalline SiC.
  • FIG. 1A is a top view and a side view showing an example of a single crystal SiC substrate 1 that is a base material for the carbon substrate 2, the silicon oxide film 41, the polycrystalline SiC film 42, and the first single crystal layer 11.
  • One plane of the carbon substrate 2 is an upper surface 201
  • the other plane is a lower surface (or back surface) 202
  • the entire side surface is a side surface 203.
  • the silicon oxide film 41 is formed on the upper surface 201 and the side surface 203 of the carbon substrate 2 (the side surface 203 portion is not shown), and the polycrystalline SiC film 42 is formed on the lower surface 202 and the side surface 203 of the carbon substrate 1.
  • the shape of the carbon substrate 2 and the single crystal SiC substrate 1 is not limited, but is preferably a disc-shaped or columnar substrate.
  • the sizes of the carbon substrate 2 and the single crystal SiC substrate 1 are not limited, but the carbon substrate 2 is made slightly larger than the single crystal SiC substrate 1 in terms of handling.
  • the diameter of the carbon substrate 2 is preferably about 1 to 10 mm larger than the diameter of the single crystal SiC substrate 1. For example, when the single crystal SiC substrate 1 has an outer diameter of 6 inches (about 150 mm), the carbon substrate 2 may have an outer diameter of about 160 mm.
  • the surface of the silicon oxide film 41 provided on the surface 201 of the carbon substrate 2 and the lower surface 101 of the single crystal SiC substrate 1 are bonded.
  • FIG. 1B shows an example in which a SiC substrate (or sapphire substrate) 25 is used as the second substrate, and a GaN film 413 is formed as a surface thin film layer on one surface 201 thereof. Since SiC is stable in an atmosphere such as oxygen, it is not necessary to form a surface thin film layer on the lower surface 202. In the bonding step, the surface of the GaN film 413 formed on the SiC substrate 25 and the lower surface 101 of the single crystal SiC substrate 1 are bonded.
  • the diameter of SiC substrate 25 is preferably about 1 mm larger than the diameter of single crystal SiC substrate 1.
  • FIG. 2A and 2B show a surface thin film layer 41, a first single crystal layer (single crystal SiC layer) 11, and a second single crystal layer (single crystal SiC layer) on one surface 201 of the carbon substrate 2.
  • FIG. FIG. 5 is a schematic cross-sectional view showing a multilayer substrate 6 in which 5 and 5 are sequentially stacked.
  • the multilayer substrate 6 (6a) shown in FIG. 2A has a silicon oxide film 41, a first single crystal layer 11, and a second single crystal layer 5 as a surface thin film layer on the upper surface 201 of the carbon substrate 2.
  • the polycrystalline SiC film 42 is formed on the other surface (lower surface) 202 of the carbon substrate 2.
  • the silicon oxide film 41 is formed on the upper surface 201 and the side surface 203 of the carbon substrate 2, and then the polycrystalline SiC film 42 is formed on the lower surface 202 and the side surface 203 of the carbon substrate 2. Be filmed. Then, the carbon substrate 2 and the first single crystal layer 11 (single crystal SiC substrate 1) are bonded via the silicon oxide film 41, and further, an SiC layer (covering the upper surface 201 side and the side surface 203 side of the carbon substrate 2). 5, 51) are formed to form the multilayer substrate 6a.
  • the diameter of the first substrate 1 is smaller than the diameter of the carbon substrate 2, so that the second surface made of single crystal is formed on the upper surface of the first single crystal layer 11.
  • the single crystal layer 5 is formed, and a polycrystal layer (on the outer peripheral portion exceeding the diameter of the first single crystal layer 11 (that is, the diameter of the first substrate 1) and the side surface 203 side of the carbon substrate 2 ( The second polycrystalline layer) 51 is formed.
  • the surface thin film layer formed on one surface 201 of the second substrate 2 can be composed of two thin films.
  • the multilayer substrate 6 (6b) shown in FIG. 2 (b) is different from the multilayer substrate 6a shown in FIG. 2 (a) in that the surface thin film layer formed on the upper surface 201 of the carbon substrate 2 consists of two layers. Different.
  • a silicon oxide film 41 is formed as a first layer on the upper surface 201 of the carbon substrate 2
  • a SiC layer is formed as a second layer (buffer layer made of a semiconductor material) thereon. .
  • This SiC layer is made of polycrystal.
  • the multilayer substrate 6b provided with the buffer layer is formed on the upper surface 201 of the carbon substrate 2 with a buffer layer 412 made of a silicon oxide film 41 and SiC polycrystal as a surface thin film layer, a first single crystal layer 11 and a second single crystal.
  • the layer 5 is sequentially formed, and the polycrystalline SiC film 42 is formed on the other surface (lower surface) 202 of the carbon substrate 2.
  • the side surface 203 side of the carbon substrate 2 is covered with a silicon oxide film 41, a buffer layer 412 made of SiC polycrystal, and a polycrystalline SiC film 42.
  • the buffer layer 412 may be a high-concentration polycrystalline SiC layer.
  • a polycrystalline SiC layer having a high nitrogen concentration By using a polycrystalline SiC layer having a high nitrogen concentration, ohmic contractability can be improved when a back electrode is formed later.
  • a potential barrier is generated between the polycrystalline SiC layer having a high nitrogen concentration and the first single crystal layer 11 due to a difference in the bandwidth, thereby hindering ohmic connection.
  • a very thin surface layer of the first single crystal layer 11 may be set to a high nitrogen concentration before bonding.
  • FIG. 2C shows a multi-layer substrate 6 (6c) in which a SiC substrate (or sapphire substrate) 25 is used as the second substrate and a GaN film 413 is formed as a surface thin film layer on one surface 201 thereof. Is shown.
  • the multilayer substrate 6 c is configured by forming a GaN film 413, the first single crystal layer 11, and the second single crystal layer 5 in this order on the upper surface 201 of the SiC substrate 25.
  • the second single crystal layer 5 is formed, the second polycrystalline layer 51 is formed at the periphery.
  • a single crystal buffer layer 52 made of SiC single crystal containing nitrogen at a high concentration is formed in the multilayer substrate 6 (6a, 6b, 6c).
  • a single crystal buffer layer 52 made of SiC single crystal containing nitrogen at a high concentration is formed in the multilayer substrate 6 (6a, 6b, 6c).
  • FIG. 2D a single crystal buffer layer 52 made of a single crystal of the second semiconductor material is formed on the surface of the first single crystal layer 11, and then the second single crystal layer 5 is formed.
  • a layer substrate 6 (6d) is shown.
  • FIG. 2E shows a GaN film 413, a high nitrogen concentration polycrystalline SiC layer 53 as a buffer layer, the first single crystal layer 11, and the second single crystal layer 5 on the upper surface 201 of the SiC substrate 25. Shows a multilayer substrate 6 (6e) that is formed in order.
  • the ohmic contractability can be improved when the back electrode is formed later.
  • a potential barrier is generated between the polycrystalline SiC layer 53 having a high nitrogen concentration and the first single crystal layer 11 due to the difference in the bandwidth, thereby hindering ohmic connection.
  • a very thin surface layer of the first single crystal layer 11 may be set to a high nitrogen concentration before bonding.
  • the first substrate 1 is made of a single crystal of a first semiconductor material.
  • the first semiconductor material is not limited to SiC, and, for example, SiC, GaN, gallium oxide, or the like can be employed.
  • the first semiconductor material is the material of the second single crystal layer 5. It is preferably the same as a certain second semiconductor material or SiC.
  • the hydrogen layer forming step is a step of forming the hydrogen injection layer 15 at a predetermined depth from the lower surface 101 of the first substrate 1.
  • the hydrogen implantation layer 15 can be formed by implanting hydrogen ions at the predetermined depth (for example, a depth of about 0.2 to 1.5 ⁇ m, preferably about 0.5 ⁇ m).
  • a silicide layer can be formed in advance on the surface of the first single crystal layer 11 on the second substrate side.
  • a silicide layer is formed on the lower surface 101 of the first substrate 1 before bonding to the second substrate. In this way, the silicidation process when the second substrate is removed later to form the back electrode layer of the semiconductor element can be omitted.
  • the first film forming step is a step of forming a surface thin film layer 4 made of a thin film of an insulating material or a semiconductor material on at least one plane of the second substrate 2.
  • the insulating material or the semiconductor material to be used may be appropriately selected according to the bonding property with the first substrate 1 and the necessity of protection of the second substrate 2, for example, silicon oxide (SiO 2 ), SiC, GaN, etc. can be mentioned.
  • SiO 2 silicon oxide
  • SiC SiC
  • GaN GaN
  • the silicon oxide film 41 or the buffer layer 412 made of the silicon oxide film 41 and SiC is formed on the one plane 201 of the carbon substrate 2 as the surface thin film layer 4. To be able to.
  • a polycrystalline SiC film (42) can be formed on the other flat surface 202 of the carbon substrate 2. Any of the surface thin film layers 41, 412 and 42 may be formed first. When the surface thin film layers (41, 412, and 42) are formed, the same thin film layers (41, 412, and 41) are also formed on the side surface 203 side of the second substrate 2. When a sapphire substrate is used as the second substrate 2, a GaN film or a silicon oxide film can be formed on the one surface 201 as the surface thin film layer 4. Since the sapphire substrate does not need to be protected from the heat treatment in the element formation process, it is not necessary to form the surface thin film layer 4 on the other plane 202 and side surface 203.
  • a semiconductor layer for example, a GaN film or a Ga oxide film
  • Ga can be formed as the surface thin film layer 4 on one plane 201 of the SiC substrate 25. Since it is not necessary to protect the SiC substrate 25 from the heat treatment in the element formation process, it is not necessary to form the surface thin film layer 4 on the other plane 202 and the side surface 203. Further, the sapphire substrate and the SiC substrate are rigid and warpage is suppressed.
  • a process of raising the temperature to about 1700 ° C. is necessary to activate impurities such as nitrogen, phosphorus, and aluminum.
  • a carbon substrate can be used as the second substrate 2 as a base for forming the semiconductor element.
  • Carbon is a material that can withstand such high temperatures in an inert gas. However, carbon burns out at 400 ° C. or higher when oxygen is present. In order to protect such carbon, a method of covering the entire surface of the carbon substrate 2 can be employed.
  • the polycrystalline SiC film 42 is formed so as to cover the upper surface 201 and the side surface 203 of the carbon substrate 2 with the silicon oxide film 41 and cover the lower surface 202 and the side surface 203 side of the carbon substrate 2. It is preferable to form a film. Further, in the subsequent process, the upper surface 201 side and the side surface 203 side of the carbon substrate 2 are covered with a thin film layer (second single crystal layer 5 and second polycrystalline layer 51) made of the second semiconductor material. In this way, the entire surface of the carbon substrate 2 is covered with the polycrystalline SiC film 42, the second single crystal layer 5, the second polycrystalline layer 51, etc., and the carbon substrate 2 is not exposed to the outside. The existing high temperature processing can be performed.
  • the warp of the carbon substrate 2 can be extremely reduced.
  • the thickness of the polycrystalline SiC film 42 formed on the back surface 202 of the carbon substrate 2 is formed on the upper surface 201 side of the carbon substrate 2 for the purpose of covering the carbon substrate 2 and reducing warpage of the multilayer substrate 6.
  • a thickness necessary for balancing so as not to cause warpage for example, about 1 to 10 ⁇ m
  • the thickness of the carbon substrate 2 can be set to a minimum thickness (for example, about 250 to 1000 ⁇ m) necessary for suppressing warpage and facilitating handling.
  • FIG. 3 is a cross-sectional image of the edge of the substrate when the carbon substrate 2 is covered with the silicon oxide film 41 and the polycrystalline SiC film 42.
  • the silicon oxide film 41 is formed on the upper surface 201 of the carbon substrate 2 using a thermal CVD apparatus, the silicon oxide film 41 is also formed on the side surface 203 side of the carbon substrate 2.
  • the polycrystalline SiC film 42 is formed on the lower surface 202 of the carbon substrate 2 from above with the silicon oxide film 41 face down, the polycrystalline SiC film 42 is also formed on the side surface 203 side of the carbon substrate 2.
  • a boundary 43 between the polycrystalline SiC film 42 and the silicon oxide film 41 is indicated by a broken line.
  • the corner of the end of the carbon substrate 2 is chamfered (beveled). It is preferable that the thickness and thickness of the silicon oxide film 41 and the polycrystalline SiC film 42 be uniform until reaching the end of the carbon substrate 2 by appropriately determining the shape and size of the chamfer.
  • the bonding step the lower surface 101 of the first substrate (single crystal SiC substrate) 1 and the surface of the surface thin film layer 4 (silicon oxide film 41) formed on the second substrate (carbon substrate) 2 are bonded. It is a process.
  • the bonding method is not particularly limited, and for example, both surfaces can be activated and bonded with an argon beam or the like.
  • the surface thin film layer 4 the silicon oxide film 41 and the buffer layer 412 made of SiC
  • the second substrate is the SiC substrate 25 (or sapphire substrate) and the GaN film 413 is formed as the surface thin film layer 4, the lower surface 101 of the first substrate 1 and the SiC substrate 25 are formed on the bonding step.
  • the surface of the GaN film 413 formed on the surface is joined.
  • the bonding method is not particularly limited, and for example, both surfaces can be activated and bonded with an argon beam or the like.
  • the separation step separates the first substrate at a predetermined depth from the bonding surface with the second substrate, that is, the lower surface 101 of the first substrate, so that the lower surface side of the first substrate becomes the first single crystal.
  • the first substrate (single crystal SiC substrate) 1 can be separated by the hydrogen injection layer 15.
  • the lower surface 101 side of the separated first substrate 1 is left as the first single crystal layer 11 on the surface thin film layer 4 (silicon oxide film 41) formed on the second substrate (carbon substrate) 2. be able to.
  • Separation in the hydrogen injection layer 15 is possible by raising the temperature of the bonded substrate.
  • the first substrate 1 is a single crystal SiC substrate
  • blisters are generated in the hydrogen injection layer 15 at 900 to 1000 ° C., and the single crystal SiC substrate 1 is separated with the hydrogen injection layer 15 as a boundary.
  • the second substrate is the SiC substrate 25 (or sapphire substrate) and the GaN film 413 is formed as the surface thin film layer 4.
  • the second film forming step is a step of forming a second single crystal layer 5 made of a single crystal of a second semiconductor material on a second substrate which is a temporary support substrate. Specifically, the second single crystal layer 5 made of a single crystal of the second semiconductor material is formed on the surface of the first single crystal layer 11 formed on the second substrate 2 (25). Can do.
  • the second semiconductor material is not particularly limited, and for example, one of SiC, GaN, gallium oxide, and the like can be employed.
  • a single crystal SiC layer (second single crystal layer) formed by forming a silicon oxide film 41 and a single crystal SiC layer (first single crystal layer) 11 on the carbon substrate (second substrate) 2 is formed.
  • a multilayer substrate 6 in which a crystal layer 5) is laminated in order can be obtained.
  • the single crystal layer 5 of the second semiconductor material is formed on the first single crystal layer 11, and the portion where the first single crystal layer 11 does not exist (that is, the second substrate 2).
  • the polycrystalline layer 51 of the second semiconductor material is formed on the outer peripheral portion where the first single crystal layer 11 is not present on the upper surface 201 side and on the side surface 203 side of the second substrate 2.
  • the first single crystal layer 11 having good crystallinity is suitable as a base for the second single crystal layer 5 formed thereon.
  • a specific film forming method of the second single crystal layer 5 is not particularly limited.
  • the second single crystal layer 5 can be formed on the first single crystal layer 11 by epitaxial growth.
  • the film can be formed by the MOCVD method. Since the second single crystal layer 5 is formed on the first single crystal layer 11 having good crystallinity, the second single crystal layer 5 can be a high-quality single crystal layer and is suitable for forming a semiconductor element. The thickness of the second single crystal layer 5 only needs to be a thickness necessary for forming an active layer of a semiconductor element (about 5 to 10 ⁇ m when the second semiconductor material is SiC). Through the above steps, the multilayer substrate 6 shown in FIG. 2 is formed.
  • a single crystal single crystal buffer layer 52 containing nitrogen at a high concentration is formed on the first single crystal layer 11, and then the second single crystal layer 5 having a low nitrogen concentration is epitaxially grown. You can also.
  • the element forming step is a step of forming the semiconductor element 7 on the second single crystal layer 5 which is the surface layer of the multilayer substrate 6 obtained by the second film forming step.
  • the process of forming the semiconductor element is a process of forming an impurity region, an insulator region, a surface electrical wiring region, and the like necessary for configuring the target semiconductor device 7 such as a Schottky diode, MOSFET, JFET, and the like. (See FIGS. 11 and 12). Since the multilayer substrate 6 is prevented from being bent or warped by the thickness of the carbon substrate 2 or the balance of the thin films formed on both surfaces thereof, the semiconductor element 7 can be formed using a general-purpose photolithography apparatus. When the second substrate is a SiC substrate or a sapphire substrate, bending and warping of the multilayer substrate 6 are suppressed by the rigidity of the SiC substrate or sapphire substrate itself.
  • the second bonding step is a step of bonding the third substrate 3 to the surface of the multilayer substrate 6 on which the semiconductor element 7 is formed in the element forming step on the second single crystal layer 5 side.
  • the bonding method of the third substrate 3 is not particularly limited, and for example, the third substrate 3 and the surface of the second single crystal layer 5 on which the semiconductor element 7 is formed are connected through an appropriately selected adhesive layer 34 or the like. (See FIGS. 6 and 8).
  • a substrate (31) made of an insulating material such as non-alkali glass or sapphire can be used.
  • a substrate using a semiconductor material such as a Si substrate (32) can also be used.
  • an adhesive layer 34 coated with a photocurable adhesive is provided on the surface of the second single crystal layer 5 in which the element forming process has been completed, and on that, The third substrate 31 can be bonded and bonded by ultraviolet curing.
  • a TEOS oxide film Tetra Ethyl Ortho Silicate oxide film
  • Bonding is possible by plasma activation or the like.
  • the bonding layer 34 and the metal bonding layer 38 are provided on the surface of the second single crystal layer 5 on which the semiconductor element 7 is formed, and the metal substrate 33 is bonded thereon. (See FIG. 6C and FIG. 8C).
  • the metal bonding layer 38 may be formed by sputtering a metal such as Ni, forming a thick plating layer, and flattening the thick plating layer and then bonding the metal substrate 33 to the metal. When the metal substrate 33 is used, the following opening process is not necessary.
  • an opening step of forming a through hole that becomes an electrode portion of the semiconductor element 7 in the third substrate 3 can be provided.
  • the opening step is a step of forming through holes (36, 37) in the third substrate 3 after bonding the multilayer substrate 6 and the third substrate 3 (31, 32) in the second bonding step. (See FIGS. 6 and 8).
  • the third substrate 3 is made of alkali-free glass, sapphire, or the like, a through hole can be provided in a necessary portion as an electrode portion by photolithography.
  • the third substrate 3 is a semiconductor material such as Si, a through hole can be provided by photolithography.
  • a taper having an angle of 54 degrees can be formed by setting the surface orientation of Si to 100 and etching with KOH liquid. If this taper is used to form an electrode on the surface of the Si substrate later, the electrode of the semiconductor element can be guided to the surface of the Si substrate. This opening step can also be performed after removing the second substrate 2 from the multilayer substrate 6.
  • the substrate removing step is a step of removing the second substrate (carbon substrate) 2 from the multilayer substrate 6 bonded to the third substrate 3 (see FIGS. 9 and 10).
  • a specific method for removing the substrate is not particularly limited. For example, when the lower surface 202 of the carbon substrate 2 is covered with the polycrystalline SiC film 42, first, the peripheral portion of the multilayer substrate 6 (at least the second polycrystalline layer 51 formed on the side surface 203 side of the carbon substrate 2). Then, the silicon oxide film 41 and the polycrystalline SiC film 42) are cut and removed to expose the side surface portion 203 ′ of the carbon substrate 2. Thereafter, the carbon substrate 2 is removed by incineration or the like. Carbon can be easily incinerated by raising the temperature to about 500 ° C. After the carbon substrate 2 is removed, the remaining surface thin film layer (silicon oxide film) 41 can be removed by acid or dry etching.
  • the substrate removal step when the second substrate 2 is a sapphire substrate or a SiC substrate 25 and the surface thin film layer is a GaN film 413, the GaN film is irradiated by irradiating laser light from the second substrate 2 side. Ga can be deposited from 413 and the second substrate 2 can be easily removed. The removed second substrate 2 can be reused as the second substrate 2 after the surface thin film layer is removed by etching or the like.
  • the surface thin film layer 4 remaining after the removal of the second substrate 2 carbon substrate, SiC substrate, etc.
  • the first single crystal layer 11 may be further removed.
  • the second substrate 2 and the surface thin film layer 41 are removed. Then, the first single crystal layer 11 is exposed on the back side of the semiconductor element 7. In this case, the first single crystal layer 11 and the single crystal buffer layer 52 may be removed.
  • the specific removal method is not particularly limited, and can be removed by polishing such as CMP.
  • the back electrode forming step is a step of forming the back electrode layer 8 (81, 82) on the back surface of the semiconductor element 7, that is, the surface from which the second substrate 2 and the surface thin film layer 41 are removed (see FIG. 9). .
  • the first single crystal layer 11 is exposed on the back surface side of the semiconductor element 7.
  • a metal thin film for silicide such as Ni is formed on the back surface of the semiconductor element 7 and then silicidation is performed at the interface between the first single crystal layer 11 and the metal such as Ni at a high temperature.
  • the silicide layer 81 can be formed.
  • the metal layer 82 can be formed by copper plating or silver plating.
  • the silicide layer 81 and the metal layer 82 can be formed even if the substrate is warped.
  • the silicidation process may be performed before the element formation process (silicide layer formation process). That is, an ultrathin Ni thin film is formed on one surface 101 of the first substrate 1 before bonding to the second substrate 2. Then, heat treatment is performed to form a silicide layer on one surface 101 of the first substrate 1, and then the Ni thin film layer is removed. Thereafter, one surface 101 of the first substrate 1 whose surface is silicided and the second substrate 2 are bonded. Through the subsequent steps, the silicide layer on one surface 101 of the first substrate 1 is exposed in a state where the second substrate 2 and the surface thin film layer 41 are removed after the bonding of the third substrate 3. A metal layer 82 can be formed on the exposed silicide layer by copper plating or silver plating in the back electrode forming step.
  • the back electrode layer 8 includes the second single crystal layer 5 exposed by removing the single crystal buffer layer 52. Formed on the surface.
  • a carbon substrate 2 having a thickness of about 0.5 mm is used as the second substrate, and the thermal expansion coefficient thereof is adjusted to be approximately the same as that of polycrystalline SiC.
  • the coefficient of thermal expansion of carbon can be adjusted by adjusting the density and firing temperature.
  • the carbon substrate 2 is a high-purity material with a metal density as an impurity being as low as 10 10 / cm 3 or less.
  • the first substrate is a single crystal SiC substrate 1.
  • FIG. 4 shows a manufacturing process of the multilayer substrate 6 shown in FIG.
  • the first substrate 1 is made of single crystal SiC
  • the second single crystal layer 5 is also made of SiC.
  • FIG. 4A shows the substrate 61 in which the silicon oxide film 41 is formed on the upper surface 201 and the side surface 203 of the carbon substrate 2 and the polycrystalline SiC film 42 is formed on the lower surface 202 and the side surface 203 side of the carbon substrate 2.
  • FIG. 2B shows a state in which the hydrogen implantation layer 15 is formed by implanting hydrogen ions from the lower surface 101 of the single crystal SiC substrate 1 to a depth of 0.5 ⁇ m.
  • the amount of hydrogen ions is about 1 ⁇ 10 17 / cm 2
  • the hydrogen density of the hydrogen injection layer 15 is a high concentration of about 1 ⁇ 10 22 / cm 3 .
  • the plane 101 side from the hydrogen injection layer 15 becomes the first single crystal layer 11 made of single crystal SiC.
  • FIG. 2C shows a state where the substrate 61 and the single crystal SiC substrate 1 are bonded.
  • the surface of the silicon oxide film 41 formed on the surface of the carbon substrate 2 and the flat surface 101 of the single crystal SiC substrate 1 are joined after activating both surfaces.
  • FIG. 4D shows a state in which the single-crystal SiC substrate 1 is separated with the hydrogen injection layer 15 as a boundary by bringing the bonded substrates to a high temperature of about 1000 ° C.
  • the base material side of the SiC substrate 1 is not shown.
  • the first single crystal layer 11 is laminated on the surface of the silicon oxide film 41 formed on the carbon substrate 2 to form a substrate 62.
  • the second single crystal layer 5 is formed by epitaxially growing single crystal SiC on the surface of the first single crystal layer 11 of the substrate 62. Simultaneously with the formation of the second single crystal layer 5, a polycrystal grows on the peripheral portion on the silicon oxide film 41 where the first single crystal layer 11 does not exist and on the side surface side (on the polycrystalline SiC film 42) of the carbon substrate 2. Then, the second polycrystalline layer 51 having the same thickness as the second single crystal layer 5 is formed.
  • the thickness of the second single crystal layer 5 varies depending on the material and application, and in the case of SiC, is approximately 5 ⁇ m (withstand voltage of 600 V) to 10 ⁇ m (withstand voltage of 1500 V).
  • a single crystal buffer layer 52 may be formed after the substrate 62 shown in FIG. 6D is formed and before the second single crystal 5 is epitaxially grown (see FIG. 2D).
  • FIG. 5 shows an example in which a Schottky diode 71 is formed as the semiconductor element 7 in the second single crystal layer 5.
  • FIG. 4A shows only one element portion (A portion) formed on the multilayer substrate 6, and FIG. 5B is an enlarged view of the one element portion.
  • FIG. 7 shows an example in which a MOSFET 75 is formed as the semiconductor element 7 in the second single crystal layer 5.
  • FIG. 4A shows only one element portion (A portion) formed on the multilayer substrate 6, and FIG. 5B is an enlarged view of the one element portion. 5 and 7, the detailed structure of the element portion is omitted.
  • FIGS. 5A and 5B show examples in which the carbon substrate 2 is used as the second substrate and the surface thin film layers 41 and 42 are formed.
  • FIG. 5C shows an example in which the SiC substrate 25 is used as the second substrate, and the Schottky diode 71 is formed with the surface thin film layer as the GaN film 413.
  • FIGS. 7A and 7B show an example in which the carbon substrate 2 is used as the second substrate and the surface thin film layers 41 and 42 are formed.
  • FIG. 7C shows an example in which the SiC substrate 25 is used as the second substrate, and the MOSFET 75 is formed with the surface thin film layer as the GaN film 413. The illustrated through electrode 85 will be described later.
  • the third substrate 3 serving as a permanent support substrate for the semiconductor element 7 is bonded to the surface of the multilayer substrate 6 on the second single crystal layer 5 side.
  • an insulating material such as alkali-free glass or sapphire, or a semiconductor material such as Si can be used.
  • an opening process for forming a through hole for forming the electrode portion of the semiconductor element 7 in the third substrate 3 can be performed.
  • FIG. 6 shows a second bonding step and an opening step in the case where an alkali-free glass substrate 31 is used as the third substrate 3.
  • a photo-curing adhesive layer 34 is coated as a bonding layer on the surface of the multilayer substrate 6 (see FIG. 5) on the second single crystal layer 5 side where a Schottky diode 71 is formed in the A part.
  • attached the alkali free glass substrate 31 through the joining layer is shown.
  • the photocurable adhesive layer 34 is cured by irradiation with ultraviolet light.
  • FIG. 2B shows a state in which a through-hole 36 for forming an electrode portion of a semiconductor element is provided in the alkali-free glass substrate 31.
  • the through hole 36 can be formed by photolithography.
  • the surface electrode of the Schottky diode 71 can be electrically connected to an external package through the through hole 36 by wire bonding or the like.
  • a metal substrate 33 can be used as the third substrate 3.
  • This figure shows an example in which the SiC substrate 25 (or sapphire substrate) is used as the second substrate and the surface thin film layer is the GaN film 413, but the carbon substrate 2 is used and the surface thin film layers 41, 42 are used. May be formed.
  • the element surface of the Schottky diode 71 is protected by a silicon oxide film, the anode electrode part is opened by photolithography, a nickel thin film is formed on the entire surface, and if necessary, the film is increased by plating to form a metal bonding layer 38 is formed.
  • the metal substrate 33 can be used as an anode electrode for external connection.
  • FIG. 8 shows a second bonding step and an opening step when the Si substrate 32 is used as the third substrate 3.
  • a TEOS oxide film 35 is formed as a bonding layer on the surface of the second single crystal layer 5 side of the multilayer substrate 6 (see FIG. 7) in which the MOSFET 75 is formed in the A part, and the TEOS oxide film 35 is formed thereon.
  • the state which joined Si substrate 32 is shown.
  • the TEOS oxide film 35 and the Si substrate 32 can be bonded after the surfaces to be bonded are planarized and activated by plasma irradiation.
  • FIG. 4B shows a state in which a through hole 37 for forming an electrode portion of a semiconductor element is provided in the Si substrate 32.
  • the through hole 37 can be formed by photolithography.
  • the through hole 37 is formed with a taper angle of 54 degrees.
  • the wall surface of the through-hole 37 can be a gentle slope with an inclination angle of 54 degrees.
  • an electrode can be formed on the surface of the Si substrate 32. It is also possible to provide a heat sink on the upper surface of the Si substrate 32.
  • a metal substrate 33 can be used as the third substrate 3.
  • This figure shows an example in which a SiC substrate (or sapphire substrate) 25 is used as the second substrate, and the surface thin film layer is a GaN film 413.
  • the surface thin film layers 41 and 42 may be formed using the carbon substrate 2.
  • An interconnection layer 36 for performing necessary electrical wiring is formed on the element surface of the MOSFET 75.
  • the interconnect layer 36 also serves as the bonding layer 34.
  • a metal junction layer 38 electrically connected to the source of the MOSFET 75 is formed on the surface of the interconnect layer 36.
  • FIG. 9 shows a process of forming the back electrode layer 8 (81, 82) to be the back electrode of the semiconductor element 7 after forming the semiconductor element 7 on the multilayer substrate 6 and bonding the third substrate 3.
  • FIG. 9A is the same view as FIG. 6B, and the portion A shows a portion corresponding to one semiconductor element.
  • the outer peripheries of the circular single crystal layers 11 and 5 in a top view are represented by boundaries z1-z1 ′ and z2-z2 ′, and the boundary is defined by performing a circle cut along these boundaries. Remove excess substrate periphery.
  • FIG. 9B shows a state in which the outer peripheral portion has been removed by performing a circle cut along the boundary.
  • the side surface 203 ′ of the cut carbon substrate 2 is exposed. If the carbon substrate 2 is removed by incineration in an oxygen atmosphere and the silicon oxide film 41 is removed by etching, the back surface of the first single crystal layer (single crystal SiC layer) 11 is exposed. Therefore, as shown in FIG. 3C, Ni is deposited on the exposed surface of the single crystal SiC layer 11 in an extremely thin manner, and silicide is formed by siliciding the interface between Ni and the single crystal SiC layer by laser annealing. Layer 81 is formed. Then, a metal layer 82 to be a back electrode can be formed on the silicide layer 81 by plating. In addition, when the silicide layer 81 is formed in advance on the surface of the first single crystal layer 11 on the second substrate 2 side, the metal layer 82 serving as the back electrode can be formed by direct plating.
  • FIG. 10 removes the second substrate 2 and the first layer 41 of the surface thin film layer from the multilayer substrate 6 (6b) shown in FIG. 2B, and forms the back electrode layer 8 (81, 81) on the buffer layer 412. 82).
  • a silicon oxide film 41 and a buffer layer 412 made of SiC are formed as a surface thin film layer on the upper surface of the carbon 2.
  • FIG. 10A shows the semiconductor element 7 formed on the multilayer substrate 6 (6b), the third substrate 3 is bonded, and the outer periphery along the boundaries z1-z1 ′ and z2-z2 ′ as in the previous figure. This shows a state in which the outer peripheral portion of the substrate beyond the boundary is removed by circle cutting. A part corresponds to one semiconductor element.
  • the side surface 203 'of the cut carbon substrate 2 is exposed.
  • the buffer layer 412 made of SiC polycrystal is exposed. Therefore, as shown in FIG. 6B, Ni is deposited on the exposed buffer layer 412 to be extremely thin, and the silicide layer 81 is formed by siliciding between the Ni and the single crystal SiC layer 11 by laser annealing. Form. Then, a metal layer 82 to be a back electrode can be formed on the silicide layer 81 by plating.
  • the buffer layer 412 made of SiC polycrystal formed as the surface thin film layer becomes a thermal buffer layer to the aluminum electrode of the semiconductor element 7 when the electrode interface becomes high temperature by laser annealing.
  • the silicide layer 81 can be formed by siliciding the interface between the first single crystal layer 5 and the second single crystal layer 5.
  • the silicide layer 81 and the metal layer 82 serving as the back electrode can be formed.
  • the metal substrate 33 is used as the third substrate 3 (see, for example, FIG. 6C)
  • the silicide layer 81 and the metal layer 82 to be the back electrode can be formed in the same manner.
  • the surface of the single-crystal SiC layer 11 to be silicided may be ion-implanted immediately before it to obtain a high nitrogen concentration.
  • a very thin high nitrogen concentration layer may be provided in advance on the surface layer.
  • an extremely thin high nitrogen concentration layer can be formed on the lower surface 101 of the first substrate 1 before being bonded to the second substrate 2 in the bonding step.
  • a semiconductor substrate for forming a vertical element for high power use vertical electrical conductivity and thermal conductivity are important.
  • the resistance between the first single crystal layer 11 and the metal layer 82 serving as the back electrode is important, but this resistance is eliminated by silicidation. .
  • the carbon substrate 2 is removed, the electric resistance of the support layer is substantially minimized. The same applies to thermal conductivity, and the carbon substrate 2 is removed to form only the metal layer 82, so that thermal conduction is not hindered.
  • FIG. 11 shows a process of forming the Schottky diode element 71 on the second single crystal layer 5 formed on the surface layer of the multilayer substrate 6.
  • the first substrate 1 is single crystal SiC.
  • FIG. 11A shows the multilayer substrate 6 shown in FIG. 2 in a simplified manner, and the first single crystal layer 11 and the polycrystalline SiC layer 51 are not shown.
  • a portion in the figure is a region corresponding to one semiconductor element in the multilayer substrate 6.
  • the A portion is shown in an enlarged manner, and represents a process of forming one element.
  • an SiO 2 film is formed on the surface of the N-type second single crystal layer 5, and a mask 701 is formed by opening necessary portions by photolithography.
  • P-type impurities are ion-implanted into the opening of the mask 701 while being heated to about 500 ° C., and then the mask 701 is removed.
  • a P-type impurity region 711 is formed in the surface layer portion of the second single crystal layer 5 as shown in FIG.
  • a SiO 2 film is formed on the surface of the second single crystal layer 5, and a mask 702 is formed by opening necessary portions by photolithography.
  • a SiO 2 film having a thickness of about 1 ⁇ m is formed on the surface of the second single crystal layer 5 by thermal CVD, and a portion to be an electrode is removed by etching and opened.
  • an SiO 2 interlayer insulating film 713 is formed on the second single crystal layer 5 as shown in FIG.
  • the electrode film 714 is formed by patterning. In this state, a Schottky interface is formed by instantaneously raising the temperature to over 1000 ° C. by lamp annealing or the like.
  • the electrode film 714 can be further increased using aluminum or the like.
  • a multilayer substrate on which the main part of the Schottky diode 71 is formed is obtained.
  • the back electrode is formed on the surface of the first single crystal layer 11 exposed by removing the carbon substrate 2 and the silicon oxide film 41 in the same manner as the example shown in FIG.
  • a Schottky diode 71 having a vertical structure can be formed.
  • the bonding layer 34 and the metal bonding are formed on the surface of the second single crystal layer 5 on which the semiconductor element 71 is formed.
  • a layer 38 can be provided on which the metal substrate 33 can be bonded.
  • the metal bonding layer 38 can be formed by forming a thick plating layer on a metal such as Ni by sputtering and planarizing the surface of the plating layer.
  • the metal bonding layer 38 and the metal substrate 33 can be directly bonded by intermetal bonding.
  • FIG. 12 shows a step of forming the MOSFET element 75 on the second single crystal layer 5 formed on the surface layer of the multilayer substrate 6.
  • the first substrate 1 is single crystal SiC.
  • FIG. 12A shows the multilayer substrate 6 shown in FIG. 2 in a simplified manner, and the first single crystal layer 11 and the polycrystalline SiC layer 51 are not shown.
  • a portion in the figure is a region corresponding to one semiconductor element in the multilayer substrate 6.
  • the A portion is shown in an enlarged manner, and represents a process of forming one element.
  • a SiO 2 film is formed on the surface of the N-type second single crystal layer 5, and a mask is formed by opening necessary portions by photolithography.
  • FIG. 5B shows a state in which a P well 751, a source part 752, a drain part 753, and the like are formed.
  • an annealing process is performed at a high temperature to activate these impurities.
  • the second single crystal layer 5 is SiC
  • annealing is performed at about 1700 ° C.
  • a SiO 2 film having a thickness of about 1 ⁇ m is formed on the surface of the second single crystal layer 5 by thermal CVD, and a portion to be an electrode is removed by etching and opened.
  • the insulating film is partially removed by etching around the gate portion 755.
  • an interlayer insulating film 754 is formed on the second single crystal layer 5 as shown in FIG. The figure shows a state before the generation of the gate oxide film.
  • a gate oxide film 756 is formed as shown in FIG.
  • the gate oxide film 756 can be formed in an oxygen atmosphere because the carbon substrate 2 is completely covered with the polycrystalline SiC layers 42 and 51.
  • the contact portion is opened.
  • a gate metal is formed in a region where the gate oxide film 756 between the source portion 752 and the drain portion 753 becomes the gate portion 755 (not shown).
  • FIG. 5E shows a structure in which an electrode film 758, a wiring layer 759, and the like are further formed. As described above, a multilayer substrate in which the main part of the MOSFET 75 is formed is obtained. Subsequently, in the same manner as in the example shown in FIG.
  • FIG. 12 shows a structural example of a MOSFET having a planar structure, a MOSFET having a trench structure can also be formed by modifying the element formation process described above.
  • FIG. 13 shows a step of forming the MOSFET element 76 on the second single crystal layer 5 formed on the surface layer of the multilayer substrate 6.
  • a semiconductor substrate 66 (MOSFET element 76) shown in FIG. 5E uses a metal substrate 33 as a third substrate (support substrate) 3 and is made of a single second semiconductor material layered on the metal substrate 33 in order.
  • a second single crystal layer 5 made of crystals, a semiconductor element is formed on the second single crystal layer 5, and a back electrode layer 82 is provided on the upper side of the second single crystal layer 5 (see FIG. 13).
  • the metal substrate 33 is drawn on the upper side and the back electrode layer 82 is on the lower side.
  • the back electrode layer 82 may be formed on the first single crystal layer 11 made of a single crystal of the first semiconductor material provided on the second single crystal layer 5, and further, the first single crystal layer 11 may be formed on a buffer layer made of a semiconductor material provided on the substrate 11. That is, the configuration of the multilayer substrate 6 forming the MOSFET element 76 may be any of the multilayer substrates 6a, 6b, 6c, 6d, and 6e shown in FIG. FIG. 13 shows an example in which a SiC substrate 25 is used as the second substrate 2 and the second semiconductor material (and the first semiconductor material) is SiC. Each drawing in FIG.
  • FIG. 13 represents a region corresponding to one semiconductor element, and the single crystal buffer layer 52, the first single crystal layer 11, the buffer layers (41, 412, 413), and the like are omitted.
  • FIG. 6A shows a P well 751, a source portion 752, a drain portion 753, an interlayer insulating film 754, and a gate oxide film formed on the second single crystal layer 5 by the same process as the case of the MOSFET element 75 shown in FIG. 756, an electrode film 758, a wiring layer 759, and the like are formed.
  • the SiC substrate 25 does not need to be covered with the polycrystalline SiC layer 42 or the like.
  • FIG. 13B shows a state in which a through hole 851 penetrating the second single crystal layer 5 is formed.
  • the through hole 851 can be formed by a trench structure.
  • the inner wall surface of the through hole 851 is covered with an insulating film 852, and a through electrode 85 is formed by evaporating metal or the like.
  • the through hole 851 can be tapered.
  • the metal bonding layer 38 shows a state in which the interconnection layer 36 and the metal bonding layer 38 are provided on the element, and the metal substrate 33 is bonded as a support substrate on the metal bonding layer 38.
  • the gate portion 755, which is a metal film portion on the gate oxide film, and the through electrode 85 are electrically connected.
  • the metal bonding layer 38 is electrically connected to the source portion 752 by the interconnection layer 36, and the metal substrate 33 becomes the source electrode S for external connection.
  • the metal bonding layer 38 can be formed by forming a thick plating layer on a metal such as Ni by sputtering and planarizing the surface of the plating layer.
  • the metal bonding layer 38 and the metal substrate 33 can be directly bonded by intermetal bonding.
  • SiC substrate 25 bonded to the lower surface side of second single crystal layer 5 is removed.
  • the SiC substrate 25 can be removed by irradiating the laser beam.
  • the first single crystal layer 11, the single crystal buffer layer 52, and the like can be removed by polishing or the like.
  • a back insulating layer 83 is selectively formed on the surface of the second single crystal layer 5 exposed by removing the SiC substrate 25 and the like, and further, a back electrode layer 82 is selectively formed. Shows the state.
  • the back electrode layer 82 part in contact with the lower surface side (back drain part) of the second single crystal layer 5 becomes the drain electrode D for external connection
  • the back electrode layer 82 part in contact with the through electrode 85 is the gate for external connection. It becomes the electrode G.
  • the thickness of the interconnect layer 36 is preferably thin.
  • the region of the second single crystal layer 5 under the gate wiring portion in the interconnection layer 36 is arranged to have a source or P well potential close to the gate potential. It is preferable to do.
  • the length from the surface of the second single crystal layer 5 where the source portion and the P well portion exist to the metal substrate 33 is short, and the wiring area is increased. It is preferable to do.
  • the through electrode 85 is formed before the metal substrate 33 is bonded. However, after the metal substrate 33 is bonded, the through electrode 85 can be formed by performing trench processing from the back surface side. It is.
  • the MOSFET manufacturing process of this example can be applied to a MOSFET having a trench structure by modifying the element forming process.
  • the second substrate 2 is a carbon substrate and the first semiconductor material and the second semiconductor material are SiC has been mainly described.
  • the thermal expansion coefficient can be adjusted by the density, the size of crystal grains, and the like.
  • the thermal expansion coefficient of the carbon substrate can be matched according to the thermal expansion coefficients of the first semiconductor material and the second semiconductor material.
  • the crystal defects of the second single crystal layer 5 formed on the first single crystal layer 11 can be reduced.
  • the second semiconductor material is GaN, gallium oxide, gallium oxide, or the like.
  • the material of the second substrate 2 is sapphire or SiC, it is preferable to form a compound semiconductor film containing Ga as the surface thin film layer 4.
  • Examples of the compound semiconductor film containing Ga include GaN, gallium oxide, and GaAs.
  • GaN gallium oxide
  • GaAs GaAs
  • the first semiconductor material and the second semiconductor material are SiC and a semiconductor element having a vertical structure is formed has been described, even when a semiconductor element having a horizontal structure is formed using GaN or the like, It can be manufactured similarly.
  • a silicon oxide film 41 is formed on the second substrate 2, the first substrate 1 is bonded thereon, and a GaN layer is formed as the second single crystal layer 5 to form a lateral element.
  • the second substrate 2 can be removed after the third substrate 3 is bonded.
  • the internal stress of the GaN layer is minimized by matching the thermal expansion coefficient of the carbon substrate, which is the second substrate 2 as a base, to GaN. It is possible. This is because the thermal expansion coefficient of the carbon substrate can be adjusted depending on the density and the size of the crystal grains.
  • the multilayer substrate 6 (6a, 6b, 6c, 6d, 6e) shown in FIG. 2 is suitable as a semiconductor substrate for forming an element for high power use.
  • a semiconductor substrate on which a semiconductor element is formed can be formed based on the multilayer substrate 6.
  • 14 and 15 show a semiconductor substrate 65 using a multilayer substrate 6 and using a substrate made of one of an insulating material, a semiconductor material, and a metal as the support substrate 3 (the third substrate 3). ing.
  • a semiconductor element 7 is formed on the semiconductor substrate 65.
  • FIG. 14 and 15 are drawn with the support substrate 3 on the bottom and the back electrode layer 8 on the top.
  • the 14 has a support substrate 3 (31, 32 or 33) made of one of an insulating material, a semiconductor material, and a metal, and a bonding layer 34 (35, 36) sandwiched on the support substrate 3. And a second single crystal layer 5 made of a single crystal of the second semiconductor material laminated.
  • the semiconductor element 7 is formed on the second single crystal layer 5, and the back electrode layer 8 (81, 82) of the semiconductor element 7 is provided on the second single crystal layer 5.
  • the Schottky diode 71 and the MOSFETs 75 and 76 described above can be used.
  • FIG. 15 shows another form (65a, 65b, 65c) of the semiconductor substrate 65.
  • the semiconductor substrate (65a, 65b, 65c) includes a first single crystal layer 11 made of a single crystal of a first semiconductor material on the second single crystal layer 5, and the back electrode layer 8 (81, 82) is It is provided on the first single crystal layer 11 or on the buffer layer 412 made of a semiconductor material provided on the first single crystal layer 11. That is, the second single crystal layer 5 and the first single crystal layer 11 are provided on the support substrate 3 (31, 32, or 33) with the bonding layer 34 (35, 36) interposed therebetween.
  • a semiconductor element 7 is formed on the substrate.
  • FIG. 5A shows an example of a semiconductor substrate 65 a provided with the back electrode layer 8 of the semiconductor element 7 on the first single crystal layer 11.
  • the back electrode layer 8 may be provided on the first single crystal layer 11 via a buffer layer 412 made of a semiconductor material, as shown in FIG.
  • a substrate made of alkali-free glass, sapphire, Si, or the like can be used as the support substrate 3.
  • the support substrate 3 may be formed with through holes 3 (36, 37) serving as electrode portions of the semiconductor element 7.
  • FIG. 3C shows a semiconductor substrate 65 c in which a metal substrate 33 is bonded as a support substrate 3 via a metal bonding layer 38. If the metal substrate 33 is used, a power semiconductor having excellent thermal conductivity can be obtained.
  • the first semiconductor material used for the semiconductor substrate is preferably one of SiC, GaN, and gallium oxide
  • the second semiconductor material is preferably one of SiC, GaN, and gallium oxide.
  • the semiconductor substrate since the thickness of the first single crystal layer 11 may be thin (about 0.5 to 1 ⁇ m), the first substrate 1 made of a single crystal of the first semiconductor material is used. Only a small amount is used.
  • the second substrate 2 is a sapphire substrate or a SiC substrate 25, and can be repeatedly used as the second substrate 2 if it is removed by laser lift-off. As described above, since the number of members consumed in the manufacturing process is extremely small, the semiconductor substrate 65 of this embodiment can be extremely low in cost.
  • Power-based compound semiconductor elements using SiC and the like are becoming increasingly important with the spread of hybrid cars and electric cars in cars.
  • the role of power-based compound semiconductor devices becomes important for home appliance control and energy management with the spread of smart grids at home.
  • the amount of SiC single crystal, which is an expensive material can be greatly reduced, and an inexpensive power semiconductor element can be manufactured.

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Abstract

This semiconductor element manufacturing method includes: a second film-forming step for film-forming a second single crystal layer 5 on a second substrate 2, i.e., a temporary supporting substrate, said second single crystal layer being formed of the single crystal of a second semiconductor material; an element forming step for forming a semiconductor element 7 on the second single crystal layer; a second bonding step for bonding a third substrate 3 on the second single crystal layer having the semiconductor element formed thereon; and a substrate removing step for removing the second substrate after bonding the third substrate.

Description

半導体素子の製造方法及び半導体基板Semiconductor device manufacturing method and semiconductor substrate
　本発明は、半導体素子の製造方法及び半導体基板に関する。詳しくは、暫定的な基板を使用することにより厚さが薄く且つ高耐圧の半導体素子を製造する半導体素子の製造方法、及び高耐圧半導体素子が形成された半導体基板に関する。 The present invention relates to a method for manufacturing a semiconductor element and a semiconductor substrate. Specifically, the present invention relates to a semiconductor element manufacturing method for manufacturing a semiconductor element having a high thickness and a high breakdown voltage by using a temporary substrate, and a semiconductor substrate on which the high breakdown voltage semiconductor element is formed.
　高電圧用途の半導体素子の基板として、バンドギャップ幅が大きい炭化ケイ素（ＳｉＣ）半導体基板が着目されている。図１６（ａ）は、ＳｉＣからなる一般的な縦型構造のショットキーダイオード（９１）の断面構造を示している。単結晶からなる支持基板９０１上に能動層９０２がエピタキシャル成長により形成されており、その能動層９０２の領域にガードリングとなるＰ型不純物層９１１、９１２、及びショットキー電極９１３が形成されている。電流ｉは、ショットキー電極９１３と支持基板９０１の底面に形成されている裏面電極９０３との間で流れる。
　また、同図（ｂ）は、ＳｉＣからなる一般的な縦型構造のＭＯＳＦＥＴ（９２）の断面構造を示している。単結晶からなる支持基板９０１上に能動層９０２がエピタキシャル成長により形成されており、その能動層９０２の領域にソース９２１、ドレイン９２２及びゲート９２３が形成されている。ソース９２１、ドレイン９２２間の電流の導通と遮断はゲート９２３により制御される。導通時のドレイン電流ｉは、ドレイン９２２と支持基板９０１の底面に形成されている裏面電極９０３との間で流れる。
　また、同図（ｃ）は、エピタキシャル成長により能動層９０２を成膜する初期に、高い窒素濃度の単結晶バッファ層９０４を設けたＭＯＳＦＥＴ（９４）の断面構造を示している。単結晶バッファ層９０４は、エピタキシャル層の結晶欠陥密度を支持基板９０１の結晶欠陥密度と比べて低くするために形成される。
　上記支持基板９０１は、電流が縦方向（図の上下方向）に流れる領域であり、２０ｍΩ・ｃｍ以下の低い抵抗率とされる。一方、上記能動層９０２は、高電圧の耐圧が必要であるため、支持基板９０１と比べて２～３桁高い抵抗率とされている。ＳｉＣを用いる半導体素子はバンドギャップ幅が大きいため、能動層９０２の厚さを５～１０μｍ程度と薄くできることが特徴である。能動層９０２は、支持基板９０１の上にエピタキシャル成長によって形成されるため、その結晶性は下地となる支持基板９０１に依存する。このため、支持基板９０１のＳｉＣの結晶品質が重要となる。支持基板９０１の厚さは、単結晶基板の取り扱い時の割れ防止等のため、６インチサイズの基板の場合、３００μｍ程度が必要とされる。そして、基板の表面側に素子形成後、支持基板部の抵抗を低くするために、裏面を研削して厚さは１００μｍ以下まで薄くされる。 A silicon carbide (SiC) semiconductor substrate having a large band gap is attracting attention as a substrate for a semiconductor element for high voltage applications. FIG. 16A shows a cross-sectional structure of a general vertical structure Schottky diode (91) made of SiC. An active layer 902 is formed by epitaxial growth on a support substrate 901 made of a single crystal, and P- type impurity layers 911 and 912 serving as a guard ring and a Schottky electrode 913 are formed in the active layer 902 region. The current i flows between the Schottky electrode 913 and the back electrode 903 formed on the bottom surface of the support substrate 901.
FIG. 2B shows the cross-sectional structure of a general vertical MOSFET (92) made of SiC. An active layer 902 is formed by epitaxial growth on a support substrate 901 made of a single crystal, and a source 921, a drain 922, and a gate 923 are formed in the region of the active layer 902. The conduction and interruption of the current between the source 921 and the drain 922 are controlled by the gate 923. The drain current i during conduction flows between the drain 922 and the back electrode 903 formed on the bottom surface of the support substrate 901.
FIG. 6C shows a cross-sectional structure of a MOSFET (94) provided with a single crystal buffer layer 904 having a high nitrogen concentration in the initial stage of forming the active layer 902 by epitaxial growth. The single crystal buffer layer 904 is formed in order to reduce the crystal defect density of the epitaxial layer as compared with the crystal defect density of the support substrate 901.
The support substrate 901 is a region where current flows in the vertical direction (vertical direction in the drawing), and has a low resistivity of 20 mΩ · cm or less. On the other hand, the active layer 902 requires a high voltage withstand voltage, and therefore has a resistivity that is two to three orders of magnitude higher than that of the support substrate 901. Since a semiconductor element using SiC has a large band gap width, the thickness of the active layer 902 can be reduced to about 5 to 10 μm. Since the active layer 902 is formed on the support substrate 901 by epitaxial growth, the crystallinity of the active layer 902 depends on the base support substrate 901. For this reason, the SiC crystal quality of the support substrate 901 is important. The thickness of the support substrate 901 is required to be about 300 μm in the case of a 6-inch substrate in order to prevent cracking when handling the single crystal substrate. Then, after forming the element on the front surface side of the substrate, in order to reduce the resistance of the support substrate portion, the back surface is ground and the thickness is reduced to 100 μm or less.
　ＳｉＣは格子定数の異なる炭素とシリコンとからなる化合物であるので、素子基板には結晶欠陥が多く発生する。特にパワー素子用途では結晶欠陥は致命的となるため、結晶欠陥の低減に種々の工夫がなされているが、そのため素子基板のコストが高くなっている。このため、エピタキシャル成長される能動層９０２の下地である支持基板９０１の結晶欠陥の低減とコストの低減とを両立させることが課題となっている。また、図１６に示すような縦型構造の素子の場合には、支持基板９０１は抵抗率を低くするため高濃度の窒素が添加されてＮ型半導体とされている。その上で、素子形成後には、支持基板９０１を薄く加工することによって支持基板層の抵抗の更なる低減を図っている。
　このように、半導体素子の基板として高価格な単結晶基板が使用され、その単結晶基板の厚さは、能動層のために厚くされるのではなく、素子形成工程における基板の取り扱いのために厚くされている。さらに、素子形成後には基板は薄く加工され、単結晶基板の多くの部分は、研削により除去されているのが現状である。 Since SiC is a compound composed of carbon and silicon having different lattice constants, many crystal defects are generated in the element substrate. In particular, since crystal defects are fatal in power device applications, various attempts have been made to reduce crystal defects, but the cost of the device substrate is therefore high. For this reason, it is an issue to achieve both reduction of crystal defects and cost reduction of the support substrate 901 which is the base of the active layer 902 to be epitaxially grown. In the case of an element having a vertical structure as shown in FIG. 16, the support substrate 901 is an N-type semiconductor by adding high-concentration nitrogen in order to reduce the resistivity. In addition, after the element is formed, the resistance of the support substrate layer is further reduced by processing the support substrate 901 thinly.
Thus, an expensive single crystal substrate is used as a substrate for a semiconductor element, and the thickness of the single crystal substrate is not increased for the active layer, but is increased for handling the substrate in the element formation process. Has been. Further, after the element is formed, the substrate is processed thinly, and a large part of the single crystal substrate is currently removed by grinding.
　また、ＳｉＣからなる半導体素子の基板としては、表層の能動層だけが単結晶であればよい。支持基板層は結晶性を問わず、単結晶でも多結晶でも非晶質でもよい。従来、単結晶の能動層と単結晶ではない支持基板層とを接合する基板製造方法がある。例えば、非晶質シリコンを多結晶ＳｉＣ支持体上に蒸着し、その多結晶ＳｉＣ支持体と単結晶ＳｉＣ基板とを接合し、直接ボンディングにより一体化する基板製造方法がある（特許文献１を参照）。また、表面活性化手法により基板の貼り合せを行う例も開示されている（特許文献３を参照）。 Also, as the substrate of the semiconductor element made of SiC, only the surface active layer may be a single crystal. The supporting substrate layer may be monocrystalline, polycrystalline, or amorphous regardless of crystallinity. Conventionally, there is a substrate manufacturing method in which a single crystal active layer and a non-single crystal support substrate layer are bonded. For example, there is a substrate manufacturing method in which amorphous silicon is deposited on a polycrystalline SiC support, the polycrystalline SiC support and a single crystal SiC substrate are joined, and integrated by direct bonding (see Patent Document 1). ). An example in which substrates are bonded by a surface activation method is also disclosed (see Patent Document 3).
特表２００４－５０３９４２号Special table 2004-503942 特開２００２－２８０５３１号Japanese Patent Laid-Open No. 2002-280531 特開２０１５－１５４０１号JP2015-15401
　前記のとおり、従来、高電圧用途の半導体素子の基板は、一定の厚さの支持基板（支持層）上に、単結晶からなる薄膜層が能動層として形成されている。能動層はエピタキシャル成長させることにより製造されている。この支持基板は単結晶でもよいし多結晶でもよいので、薄い単結晶層と安価な多結晶半導体基板とを接合技術により貼り合せする手法も提案されてきた（特許文献１、２、３等）。しかし、異種の材料からなる接合基板は熱膨張係数の違いや結晶の不均一さにより反りが大きくなってしまい、実用上は課題が多い。 As described above, conventionally, in a substrate of a semiconductor element for high voltage use, a thin film layer made of a single crystal is formed as an active layer on a support substrate (support layer) having a certain thickness. The active layer is manufactured by epitaxial growth. Since this support substrate may be a single crystal or a polycrystal, a method of bonding a thin single crystal layer and an inexpensive polycrystalline semiconductor substrate by a bonding technique has been proposed ( Patent Documents 1, 2, 3, etc.). . However, the bonding substrate made of different materials has a large amount of warpage due to a difference in thermal expansion coefficient and non-uniformity of crystals, and there are many problems in practical use.
　また、従来、加工時の取り扱いのため３５０μｍ程度の厚い単結晶ＳｉＣ基板を使用し、最終的には良好な素子特性を得るために支持層の厚さを１００μｍ程度まで薄くしている。しかし、これでは高価な単結晶基板がフルに利用されないという問題がある。素子形成後に支持層を研削して薄くしていることを考慮すれば、素子基板としてそもそも薄い基板を使用することが考えられる。例えば、ＳｉＣ素子用基板の場合には、バンドギャップ幅が大きい材料であるため、高電圧素子とするにも、基板の厚さは表層のエピタキシャル層の部分の厚さだけで十分であることに注目することができる。しかし、薄い基板は曲がり易く、反りも大きくなるという問題がある。 Conventionally, a thick single crystal SiC substrate of about 350 μm is used for handling during processing, and the thickness of the support layer is finally reduced to about 100 μm in order to obtain good device characteristics. However, this has a problem that an expensive single crystal substrate is not fully utilized. Considering that the support layer is thinned after forming the element, it is conceivable to use a thin substrate as the element substrate. For example, in the case of a substrate for an SiC element, since the material has a large band gap width, the thickness of the substrate is sufficient for the thickness of the epitaxial layer portion of the surface layer even for a high voltage element. You can pay attention. However, there is a problem that a thin substrate is easy to bend and warpage increases.
　また、図１６（ｃ）のように単結晶バッファ層９０４を設けてエピタキシャル層９０２の結晶欠陥を低減しても、ＭＯＳＦＥＴ素子動作中に少数キャリアの影響で結晶欠陥が増加するという現象が知られている。このため、素子形成後に単結晶バッファ層９０４を除去することが好ましいが、ＭＯＳＦＥＴ素子が形成されたエピタキシャル層９０２の下地である単結晶バッファ層９０４を除去することは、一般的な構造では不可能である。 Further, even when the single crystal buffer layer 904 is provided as shown in FIG. 16C to reduce the crystal defects of the epitaxial layer 902, the phenomenon that the crystal defects increase due to the influence of minority carriers during the operation of the MOSFET element is known. ing. For this reason, it is preferable to remove the single crystal buffer layer 904 after the element is formed, but it is impossible to remove the single crystal buffer layer 904 which is the base of the epitaxial layer 902 on which the MOSFET element is formed with a general structure. It is.
　本発明は、上記現状に鑑みてなされたものであり、暫定的な基板を使用することにより厚さが薄く且つ高耐圧の半導体素子を製造する半導体素子の製造方法、及び高耐圧半導体素子が形成された半導体基板を提供することを目的とする。 The present invention has been made in view of the above situation, and a semiconductor device manufacturing method for manufacturing a semiconductor device having a thin thickness and a high breakdown voltage by using a temporary substrate, and a high breakdown voltage semiconductor element formed. An object of the present invention is to provide a semiconductor substrate.
　本発明は、以下の通りである。
　１．仮支持基板とするための第２の基板上に第２の半導体材料の単結晶からなる第２単結晶層を成膜する第２成膜工程と、前記第２単結晶層に半導体素子を形成する素子形成工程と、前記半導体素子が形成された前記第２単結晶層上に第３の基板を接合する第２接合工程と、前記第３の基板を接合した後に前記第２の基板を除去する基板除去工程と、を含むことを特徴とする半導体素子の製造方法。
　２．第１の半導体材料の単結晶からなる第１の基板の一方の平面と前記第２の基板とを接合する接合工程と、前記第２の基板との接合面から所定の深さにおいて前記第１の基板を分離することにより、前記第１の基板の前記一方の平面側を第１単結晶層として前記第２の基板上に残す分離工程と、を含み、前記第２成膜工程において、前記第２単結晶層は前記第２の基板上に形成された前記第１単結晶層上に成膜される前記１．記載の半導体素子の製造方法。
　３．前記基板除去工程において、前記第１単結晶層を更に除去する前記２．記載の半導体素子の製造方法。
　４．前記第１の基板の前記一方の平面から所定の深さに水素注入層を形成する水素層形成工程と、前記第２の基板の少なくとも１つの平面上に絶縁材料又は半導体材料の１層以上の薄膜からなる表面薄膜層を成膜する第１成膜工程と、を含み、前記接合工程において、前記第１の基板の前記一方の平面と前記第２の基板上に形成された前記表面薄膜層の表面とを接合し、前記分離工程において、前記第１の基板を前記水素注入層で分離することにより、前記第１単結晶層を前記第２の基板に形成された前記表面薄膜層上に残し、前記第２成膜工程により、前記第２の基板上に前記表面薄膜層と前記第１単結晶層と前記第２単結晶層とが順に積層された複層基板が形成され、基板除去工程において、更に前記表面薄膜層を除去する前記２．又は３．に記載の半導体素子の製造方法。
　５．前記第２成膜工程において、前記第２の半導体材料の単結晶からなる単結晶バッファ層を形成した後に前記第２単結晶層を成膜し、前記基板除去工程において、前記単結晶バッファ層を更に除去する前記１．乃至４．のいずれかに記載の半導体素子の製造方法。
　６．前記第１の基板の前記一方の平面上にシリサイド層を形成するシリサイド層形成工程を含む請求項２乃至５のいずれかに記載の半導体素子の製造方法。
　７．前記第１成膜工程において、前記表面薄膜層として前記第２の基板の一方の平面にシリコン酸化膜又はＧａを含む化合物半導体膜を成膜する前記４．乃至６．のいずれかに記載の半導体素子の製造方法。
　８．前記第１成膜工程において、前記表面薄膜層として前記第２の基板の前記一方の平面側に更に半導体材料からなるバッファ層を成膜する前記４．乃至７．のいずれかに記載の半導体素子の製造方法。
　９．前記第１成膜工程において、前記表面薄膜層として前記第２の基板の他方の平面にＳｉＣの多結晶からなる多結晶ＳｉＣ膜を成膜する前記４．乃至８．のいずれかに記載の半導体素子の製造方法。
　１０．前記第２の基板は光を透過する基板であり、前記表面薄膜層はＧａを含む半導体材料であり、前記基板除去工程において、前記第２の基板側からレーザ光を照射してＧａを析出させることによって前記第２の基板を除去する前記１．乃至５．のいずれかに記載の半導体素子の製造方法。
　１１．前記第２の基板はサファイア又はＳｉＣからなる基板である前記１．乃至１０．のいずれかに記載の半導体素子の製造方法。
　１２．前記第２の基板はカーボンからなる基板であり、前記第１成膜工程において、前記表面薄膜層は前記第２の基板の側面側を覆うように成膜される前記１．乃至９．のいずれかに記載の半導体素子の製造方法。
　１３．前記第３の基板は金属基板である前記１．乃至１２．のいずれかに記載の半導体素子の製造方法。
　１４．前記第３の基板は、無アルカリガラス、サファイア及びＳｉのうちの１つからなる基板である前記１．乃至１２．のいずれかに記載の半導体素子の製造方法。
　１５．前記基板除去工程により露出された面上に、前記半導体素子の裏面電極層を形成する裏面電極形成工程を備える前記１．乃至１４．のいずれかに記載の半導体素子の製造方法。
　１６．前記第２接合工程又は前記基板除去工程の後、前記第３の基板に前記半導体素子の電極部となる貫通孔を形成する開孔工程を備える前記１４．又は１５．に記載の半導体素子の製造方法。
　１７．前記開孔工程において、前記貫通孔は前記第３の基板の表面側に向けて拡がるテーパ状に形成される前記１６．記載の半導体素子の製造方法。
　１８．前記第１の半導体材料はＳｉＣ、ＧａＮ及び酸化ガリウムのうちの１つであり、前記第２の半導体材料はＳｉＣ、ＧａＮ及び酸化ガリウムのうちの１つである前記１．乃至１７．のいずれかに記載の半導体素子の製造方法。
　２０．絶縁材料、半導体材料及び金属のうちの１つからなる支持基板と、前記支持基板上に接合層を挟んで積層された第２の半導体材料の単結晶からなる第２単結晶層を備え、前記第２単結晶層に半導体素子が形成されており、前記第２単結晶層の上に前記半導体素子の裏面電極層を備えることを特徴とする半導体基板。
　２１．前記第２単結晶層上に第１の半導体材料の単結晶からなる第１単結晶層を備え、前記裏面電極層は、前記第１単結晶層の上に、又は前記第１単結晶層上に設けられた半導体材料からなるバッファ層の上に備えられている前記２０．記載の半導体基板。
　２２．前記第１の半導体材料はＳｉＣ、ＧａＮ及び酸化ガリウムのうちの１つであり、前記第２の半導体材料はＳｉＣ、ＧａＮ及び酸化ガリウムのうちの１つである前記２０．又は２１．に記載の半導体基板。 The present invention is as follows.
1. A second film forming step of forming a second single crystal layer made of a single crystal of a second semiconductor material on a second substrate to be a temporary support substrate; and forming a semiconductor element on the second single crystal layer An element forming step, a second bonding step of bonding a third substrate on the second single crystal layer on which the semiconductor element is formed, and removing the second substrate after bonding the third substrate And a substrate removing step for performing a semiconductor device manufacturing method.
2. A bonding step of bonding one plane of the first substrate made of a single crystal of the first semiconductor material and the second substrate; and the first substrate at a predetermined depth from the bonding surface of the second substrate. Separating the first substrate to leave the one planar side of the first substrate as a first single crystal layer on the second substrate, and in the second film-forming step, The first single crystal layer is formed on the first single crystal layer formed on the second substrate. The manufacturing method of the semiconductor element of description.
3. In the substrate removing step, the first single crystal layer is further removed. The manufacturing method of the semiconductor element of description.
4). A hydrogen layer forming step of forming a hydrogen injection layer at a predetermined depth from the one plane of the first substrate; and at least one layer of an insulating material or a semiconductor material on at least one plane of the second substrate A first film forming step of forming a surface thin film layer made of a thin film, wherein the surface thin film layer formed on the one plane of the first substrate and the second substrate in the bonding step The first single crystal layer is formed on the surface thin film layer formed on the second substrate by separating the first substrate with the hydrogen injection layer in the separation step. The second film forming step leaves a multi-layer substrate in which the surface thin film layer, the first single crystal layer, and the second single crystal layer are sequentially stacked on the second substrate, and the substrate is removed. In the step, the surface thin film layer is further removed. Or 3. The manufacturing method of the semiconductor element of description.
5). In the second film forming step, the second single crystal layer is formed after forming a single crystal buffer layer made of a single crystal of the second semiconductor material. In the substrate removing step, the single crystal buffer layer is formed Further removing the above 1. To 4. The manufacturing method of the semiconductor element in any one of.
6). 6. The method of manufacturing a semiconductor element according to claim 2, further comprising a silicide layer forming step of forming a silicide layer on the one plane of the first substrate.
7). In the first film forming step, the silicon oxide film or the compound semiconductor film containing Ga is formed on the one surface of the second substrate as the surface thin film layer. To 6. The manufacturing method of the semiconductor element in any one of.
8). In the first film forming step, the buffer layer made of a semiconductor material is further formed on the one plane side of the second substrate as the surface thin film layer. To 7. The manufacturing method of the semiconductor element in any one of.
9. In the first film forming step, the polycrystalline SiC film made of SiC polycrystal is formed on the other plane of the second substrate as the surface thin film layer. To 8. The manufacturing method of the semiconductor element in any one of.
10. The second substrate is a light transmitting substrate, and the surface thin film layer is a semiconductor material containing Ga. In the substrate removing step, Ga is deposited by irradiating a laser beam from the second substrate side. Removing the second substrate by To 5. The manufacturing method of the semiconductor element in any one of.
11. The first substrate is a substrate made of sapphire or SiC. To 10. The manufacturing method of the semiconductor element in any one of.
12 The second substrate is a substrate made of carbon, and in the first film formation step, the surface thin film layer is formed so as to cover a side surface side of the second substrate. To 9. The manufacturing method of the semiconductor element in any one of.
13. The first substrate is a metal substrate. To 12. The manufacturing method of the semiconductor element in any one of.
14 The third substrate is a substrate made of one of alkali-free glass, sapphire, and Si. To 12. The manufacturing method of the semiconductor element in any one of.
15. 1. the back electrode forming step of forming a back electrode layer of the semiconductor element on the surface exposed by the substrate removing step; To 14. The manufacturing method of the semiconductor element in any one of.
16. 14. The opening step of forming a through hole that becomes an electrode portion of the semiconductor element in the third substrate after the second bonding step or the substrate removing step. Or 15. The manufacturing method of the semiconductor element of description.
17. In the opening step, the through-hole is formed in a tapered shape that expands toward the surface side of the third substrate. The manufacturing method of the semiconductor element of description.
18. The first semiconductor material is one of SiC, GaN and gallium oxide, and the second semiconductor material is one of SiC, GaN and gallium oxide. To 17. The manufacturing method of the semiconductor element in any one of.
20. A support substrate made of one of an insulating material, a semiconductor material, and a metal, and a second single crystal layer made of a single crystal of a second semiconductor material laminated on the support substrate with a bonding layer interposed therebetween, A semiconductor substrate, wherein a semiconductor element is formed in a second single crystal layer, and a back electrode layer of the semiconductor element is provided on the second single crystal layer.
21. A first single crystal layer made of a single crystal of a first semiconductor material is provided on the second single crystal layer, and the back electrode layer is formed on the first single crystal layer or on the first single crystal layer. 20. The above-mentioned 20. provided on a buffer layer made of a semiconductor material provided on the substrate. The semiconductor substrate as described.
22. 20. The first semiconductor material is one of SiC, GaN, and gallium oxide, and the second semiconductor material is one of SiC, GaN, and gallium oxide. Or 21. A semiconductor substrate according to 1.
　本発明の半導体素子の製造方法は、仮支持基板とするための第２の基板上に第２の半導体材料の単結晶からなる第２単結晶層を成膜する第２成膜工程と、前記第２単結晶層に半導体素子を形成する素子形成工程と、を備えている。このため、第２の基板を土台として第２単結晶層が成膜された複層基板が得られ、高温に耐えることができ且つ反りが少ない素子形成用の基板となすことができる。これにより、素子形成工程では、汎用のフォトリソグラフィ装置等を用いて、第２単結晶層内に半導体素子を形成することができる。特に、高電力用途に向いたＳｉＣ等の半導体は不純物拡散係数が小さいため、Ｎ型不純物、Ｐ型不純物共に熱拡散によるドーピングが困難である。また、Ｓｉ半導体の製造プロセスのような熱拡散によるセルフアライメント処理が不可能である。そのため、Ｎ型不純物、Ｐ型不純物の添加位置を決めるにはステッパのように高精度の露光機が必要とされ、半導体基板の反りや曲がりは２０μｍ程度以下に抑えることが求められる。前記複層基板は、第２の基板により反りや曲がりが小さく抑えられるため、ステッパを用いて第２単結晶層内に不純物領域等からなる半導体素子を形成することができる。
　また、本発明の半導体素子の製造方法は、半導体素子が形成された前記第２単結晶層上に第３の基板を接合する第２接合工程と、前記第２の基板を除去する基板除去工程と、を備えている。このため、半導体素子の最終的な支持基板となる第３の基板を接合した後、半導体素子を形成するために使用した第２の基板を除去することができる。これによって露出した裏面上に半導体素子の裏面電極を設けることが可能になる。 The method for manufacturing a semiconductor device of the present invention includes a second film forming step of forming a second single crystal layer made of a single crystal of a second semiconductor material on a second substrate to be a temporary support substrate, And an element formation step of forming a semiconductor element in the second single crystal layer. For this reason, a multi-layer substrate on which the second single crystal layer is formed using the second substrate as a base is obtained, and can be a substrate for element formation that can withstand high temperatures and has less warpage. Thus, in the element formation step, a semiconductor element can be formed in the second single crystal layer using a general-purpose photolithography apparatus or the like. In particular, since semiconductors such as SiC suitable for high power applications have a small impurity diffusion coefficient, doping by thermal diffusion is difficult for both N-type impurities and P-type impurities. Further, self-alignment processing by thermal diffusion as in the Si semiconductor manufacturing process is impossible. Therefore, in order to determine the addition position of the N-type impurity and the P-type impurity, a high-precision exposure machine such as a stepper is required, and it is required to suppress the warp or bend of the semiconductor substrate to about 20 μm or less. Since the multi-layer substrate is suppressed from being warped or bent by the second substrate, a semiconductor element including an impurity region or the like can be formed in the second single crystal layer using a stepper.
The method for manufacturing a semiconductor device of the present invention includes a second bonding step of bonding a third substrate on the second single crystal layer on which the semiconductor device is formed, and a substrate removal step of removing the second substrate. And. For this reason, after joining the 3rd board | substrate used as the final support substrate of a semiconductor element, the 2nd board | substrate used in order to form a semiconductor element can be removed. This makes it possible to provide the back electrode of the semiconductor element on the exposed back surface.
　第１の半導体材料の単結晶からなる第１の基板の一方の平面と前記第２の基板とを接合する接合工程と、前記第２の基板との接合面から所定の深さにおいて前記第１の基板を分離することにより、前記第１の基板の前記一方の平面側を第１単結晶層として前記第２の基板上に残す分離工程と、を含み、前記第２成膜工程において、前記第２単結晶層は前記第２の基板上に形成された前記第１単結晶層上に成膜される場合には、第２の基板を土台として薄い第１単結晶層及び第２単結晶層が積層された複層基板が得られ、第１の半導体材料（例えば、ＳｉＣ）の単結晶からなる第１の基板の使用量を必要最小限とすることが可能となる。従来、一般的な高電力用途の半導体基板として、高濃度Ｎ型とされた厚さ３５０μｍ程度の単結晶ＳｉＣ基板が支持層として用いられており、その上にエピタキシャル成長により厚さ５μｍ程度の単結晶ＳｉＣ層（低濃度のＮ型層）が形成されている。そして、その単結晶ＳｉＣ層に半導体素子を形成した後、支持層部分の抵抗値を小さくするために基板を研磨して厚さ１００μｍ程度まで薄肉化した上で基板裏面に電極加工をしている。本発明の半導体素子の製造方法によれば、第１単結晶層によりＮ型層が構成され、その厚さを０．５μｍ程度と薄くすることができる。その上に、半導体素子の耐圧の面から必要な厚さ及び必要な不純物濃度の第２単結晶層を、エピタキシャル成長或いはＭＯＣＶＤ（Metal Organic Chemical Vapor Deposition）によって形成することができる。
　前記基板除去工程において、前記第１単結晶層を更に除去する場合には、露出した前記第２単結晶層の表面上に半導体素子の裏面電極を設けることができる。 A bonding step of bonding one plane of the first substrate made of a single crystal of the first semiconductor material and the second substrate; and the first substrate at a predetermined depth from the bonding surface of the second substrate. Separating the first substrate to leave the one planar side of the first substrate as a first single crystal layer on the second substrate, and in the second film-forming step, When the second single crystal layer is formed on the first single crystal layer formed on the second substrate, the thin first single crystal layer and the second single crystal are based on the second substrate. A multilayer substrate in which layers are stacked is obtained, and the amount of the first substrate made of a single crystal of the first semiconductor material (for example, SiC) can be minimized. Conventionally, as a general semiconductor substrate for high power use, a single crystal SiC substrate having a high concentration of N-type and having a thickness of about 350 μm is used as a support layer, and a single crystal having a thickness of about 5 μm is formed thereon by epitaxial growth. A SiC layer (low-concentration N-type layer) is formed. Then, after forming a semiconductor element on the single crystal SiC layer, the substrate is polished and thinned to about 100 μm in order to reduce the resistance value of the support layer portion, and then the electrode is processed on the back surface of the substrate. . According to the method for manufacturing a semiconductor element of the present invention, an N-type layer is constituted by the first single crystal layer, and the thickness thereof can be reduced to about 0.5 μm. In addition, a second single crystal layer having a necessary thickness and a necessary impurity concentration can be formed by epitaxial growth or MOCVD (Metal Organic Chemical Vapor Deposition) in terms of the breakdown voltage of the semiconductor element.
In the substrate removing step, when the first single crystal layer is further removed, a back electrode of a semiconductor element can be provided on the exposed surface of the second single crystal layer.
　前記第１の基板の前記一方の平面から所定の深さに水素注入層を形成する水素層形成工程と、前記第２の基板の少なくとも１つの平面上に絶縁材料又は半導体材料の１層以上の薄膜からなる表面薄膜層を成膜する第１成膜工程と、を含み、前記接合工程において、前記第１の基板の前記一方の平面と前記第２の基板上に形成された前記表面薄膜層の表面とを接合し、前記分離工程において、前記第１の基板を前記水素注入層で分離することにより、前記第１単結晶層を前記第２の基板に形成された前記表面薄膜層上に残し、前記第２成膜工程により、前記第２の基板上に前記表面薄膜層と前記第１単結晶層と前記第２単結晶層とが順に積層された複層基板が形成され、基板除去工程において、更に前記表面薄膜層を除去する場合には、第１の基板を表面薄膜層が形成された第２の基板に容易に接合することができる。また、水素注入層において第１の基板を容易に分離することができ、厚さの薄い第１単結晶層を第２の基板上に残すことができる。そして、基板除去工程において表面薄膜層は除去されるため、それによって露出した第１単結晶層の表面上に半導体素子の裏面電極を設けることができる。 A hydrogen layer forming step of forming a hydrogen injection layer at a predetermined depth from the one plane of the first substrate; and at least one layer of an insulating material or a semiconductor material on at least one plane of the second substrate A first film forming step of forming a surface thin film layer made of a thin film, wherein the surface thin film layer formed on the one plane of the first substrate and the second substrate in the bonding step The first single crystal layer is formed on the surface thin film layer formed on the second substrate by separating the first substrate with the hydrogen injection layer in the separation step. The second film forming step leaves a multi-layer substrate in which the surface thin film layer, the first single crystal layer, and the second single crystal layer are sequentially stacked on the second substrate, and the substrate is removed. In the process, when the surface thin film layer is further removed, The substrate can be easily bonded to the second substrate which surface thin film layer is formed. In addition, the first substrate can be easily separated in the hydrogen injection layer, and the first single crystal layer having a small thickness can be left on the second substrate. Then, since the surface thin film layer is removed in the substrate removal step, the back electrode of the semiconductor element can be provided on the surface of the first single crystal layer exposed thereby.
　前記第２成膜工程において、前記第２の半導体材料の単結晶からなる単結晶バッファ層を形成した後に前記第２単結晶層を成膜し、前記基板除去工程において、前記単結晶バッファ層を更に除去する場合には、単結晶バッファ層上に形成される第２単結晶層の結晶欠陥密度を低くすることができる。そして、半導体素子の支持基板となる第３の基板を接合した後、半導体素子を形成するために使用した第２の基板が除去され、単結晶バッファ層も除去されるため、半導体素子の動作時にＰＮ接合部に順方向電流が流れても、少数キャリアの再結合により欠陥が増加することを抑制することができる。 In the second film forming step, the second single crystal layer is formed after forming a single crystal buffer layer made of a single crystal of the second semiconductor material. In the substrate removing step, the single crystal buffer layer is formed In the case of further removal, the crystal defect density of the second single crystal layer formed on the single crystal buffer layer can be lowered. Then, after joining the third substrate which is a supporting substrate of the semiconductor element, the second substrate used for forming the semiconductor element is removed, and the single crystal buffer layer is also removed. Even if a forward current flows through the PN junction, it is possible to suppress an increase in defects due to minority carrier recombination.
　前記第１の基板の前記一方の平面上にシリサイド層を形成するシリサイド層形成工程を含む場合には、後に金属により半導体素子の裏面電極層を形成する際のシリサイド化処理を不要とすることができ、裏面電極形成時の熱処理を簡素化することができる。 In the case of including a silicide layer forming step of forming a silicide layer on the one plane of the first substrate, it is not necessary to perform a silicidation process when forming a back electrode layer of a semiconductor element with a metal later. It is possible to simplify the heat treatment when forming the back electrode.
　前記第１成膜工程において、前記表面薄膜層として前記第２の基板の一方の平面にシリコン酸化膜又はＧａを含む化合物半導体膜を成膜する場合には、前記接合工程における第１の基板との接合、基板除去工程における第２の基板の除去、及び第２の基板除去後の表面薄膜層の除去を容易にすることができる。また、表面薄膜層とその上に積層される第２単結晶層とを合わせて、複層基板として高温度に耐えることができ且つ反りが少ない素子用の基板となすことができる。 In the first film formation step, when a compound semiconductor film containing a silicon oxide film or Ga is formed on the one plane of the second substrate as the surface thin film layer, the first substrate in the bonding step , Removal of the second substrate in the substrate removal step, and removal of the surface thin film layer after removal of the second substrate can be facilitated. Further, the surface thin film layer and the second single crystal layer laminated thereon can be combined to form a substrate for an element that can withstand high temperatures and has less warpage as a multilayer substrate.
　前記第１成膜工程において、前記表面薄膜層として前記第２の基板の前記一方の平面側に更に半導体材料からなるバッファ層を成膜する場合には、シリコン酸化膜又はＧａを含む化合物半導体膜を第１層とし、バッファ層を第２層とする２層からなる表面薄膜層を形成することができる。 In the first film forming step, when a buffer layer made of a semiconductor material is further formed on the one plane side of the second substrate as the surface thin film layer, a silicon oxide film or a compound semiconductor film containing Ga Can be formed as a two-layer surface thin film layer with the first layer as the first layer and the buffer layer as the second layer.
　前記第１成膜工程において、前記表面薄膜層として前記第２の基板の他方の平面にＳｉＣの多結晶からなる多結晶ＳｉＣ膜を成膜する場合には、表面薄膜層により第２の基板の表面を全て覆うことが可能になり、半導体素子形成時の高温処理等から第２の基板を保護することができる。また、多結晶ＳｉＣ層の膜厚を調整することによって、第２の基板の厚さを薄くしてもその両面での応力のバランスがとれるため、反りが少なく薄い複層基板とすることができる。
　以上のような第１成膜工程において、第２の基板の端部の面取りをしておけば、第２の基板の平面上において厚さが板端まで均一となるように表面薄膜層を成膜することができ、その表面を研磨することなく前記第１の基板と接合させることができる。 In the first film forming step, when a polycrystalline SiC film made of SiC polycrystal is formed on the other plane of the second substrate as the surface thin film layer, the surface thin film layer is used to form the second substrate. The entire surface can be covered, and the second substrate can be protected from high-temperature processing or the like when forming the semiconductor element. In addition, by adjusting the thickness of the polycrystalline SiC layer, even if the thickness of the second substrate is reduced, the stress on both sides can be balanced, so that a thin multilayer substrate with less warpage can be obtained. .
In the first film formation step as described above, if the end portion of the second substrate is chamfered, the surface thin film layer is formed so that the thickness is uniform up to the plate end on the plane of the second substrate. A film can be formed and bonded to the first substrate without polishing its surface.
　前記第２の基板は光を透過する基板であり、前記表面薄膜層はＧａを含む半導体材料であり、前記基板除去工程において、前記第２の基板側からレーザ光を照射してＧａを析出させることによって前記第２の基板を除去する場合には、レーザ光の照射により容易に第２の基板を除去することができる。除去された第２の基板は、Ｇａを含む材料の残渣を除去した後に再利用することが可能である。 The second substrate is a light transmitting substrate, and the surface thin film layer is a semiconductor material containing Ga. In the substrate removing step, Ga is deposited by irradiating a laser beam from the second substrate side. Thus, when the second substrate is removed, the second substrate can be easily removed by laser light irradiation. The removed second substrate can be reused after the residue of the material containing Ga is removed.
　前記第２の基板がサファイア又はＳｉＣからなる基板である場合には、前記複層基板の土台として、高温に耐えることができ且つ反りが少ない素子形成用の基板となすことができる。
　前記第２の基板はカーボンからなる基板であり、前記第１成膜工程において、前記表面薄膜層は前記第２の基板の側面側を覆うように成膜される場合には、カーボン基板の全表面が表面薄膜層により覆われるため、高温で酸素が存在する環境において焼損が生じるカーボンを保護することができる。これにより、素子形成工程において高温の熱処理や高密度の酸素を含有する成膜等が可能になる。また、カーボン基板の厚さを薄くしても両面での応力のバランスがとれるため、反りが少ない薄い複層基板とすることができる。 In the case where the second substrate is a substrate made of sapphire or SiC, it can be a substrate for element formation that can withstand high temperatures and has less warpage as the base of the multilayer substrate.
The second substrate is a substrate made of carbon. In the first film formation step, when the surface thin film layer is formed so as to cover the side surface of the second substrate, the entire carbon substrate is formed. Since the surface is covered with the surface thin film layer, carbon that burns out in an environment where oxygen exists at a high temperature can be protected. This makes it possible to perform high-temperature heat treatment, film formation containing high-density oxygen, or the like in the element formation process. Further, even if the thickness of the carbon substrate is reduced, the stress on both sides can be balanced, so that a thin multilayer substrate with less warpage can be obtained.
　前記第３の基板が金属基板である場合には、半導体素子の支持基板となる金属基板をそのまま外部接続用の電極端子とすることができる。例えば、半導体素子がショットキーダイオードである場合には、金属基板をアノ－ド電極とし、第２の基板を除去した面にカソード電極を形成することができる。また、半導体素子がＭＯＳＦＥＴである場合には、金属基板をそのままソース電極とすることができる。これらの場合、素子分割後に金属基板を実装基板に搭載することが容易となる。 When the third substrate is a metal substrate, the metal substrate serving as a support substrate for the semiconductor element can be used as an electrode terminal for external connection as it is. For example, when the semiconductor element is a Schottky diode, the metal substrate can be an anode electrode, and the cathode electrode can be formed on the surface from which the second substrate is removed. When the semiconductor element is a MOSFET, the metal substrate can be used as it is as the source electrode. In these cases, it becomes easy to mount the metal substrate on the mounting substrate after element division.
　前記第３の基板は無アルカリガラス、サファイア及びＳｉのうちの１つからなる基板である場合には、接合が容易であると共に、半導体素子の支持基板として好適である。
　前記基板除去工程により露出された面上に、前記半導体素子の裏面電極層を形成する裏面電極形成工程を備える場合には、第２の基板を除去した後に露出した面（第１単結晶層、バッファ層又は第２単結晶層）上に裏面電極層を設けることができる。 When the third substrate is a substrate made of one of alkali-free glass, sapphire, and Si, it is easy to join and is suitable as a support substrate for a semiconductor element.
In the case of providing a back electrode forming step for forming a back electrode layer of the semiconductor element on the surface exposed by the substrate removing step, the surface exposed after removing the second substrate (first single crystal layer, A back electrode layer can be provided on the buffer layer or the second single crystal layer.
　前記第２接合工程又は前記基板除去工程の後、前記第３の基板に前記半導体素子の電極部となる貫通孔を形成する開孔工程を備える場合には、半導体素子を実装する際の電極配線を容易にすることができる。
　前記開孔工程において、前記貫通孔は前記第３の基板の表面側に向けて拡がるテーパ状に形成される場合には、斜面となった貫通孔の壁面にアルミ等の配線を形成することができ、第３の基板の表面に電気配線を形成することが可能になる。 After the second bonding step or the substrate removing step, an electrode wiring for mounting the semiconductor element is provided in the case where the third substrate is provided with an opening step for forming a through hole to be an electrode portion of the semiconductor element. Can be made easier.
In the opening step, when the through hole is formed in a tapered shape that expands toward the surface side of the third substrate, wiring such as aluminum may be formed on the wall surface of the through hole that becomes a slope. In addition, electrical wiring can be formed on the surface of the third substrate.
　前記第１の半導体材料はＳｉＣ、ＧａＮ及び酸化ガリウムのうちの１つであり、前記第２の半導体材料はＳｉＣ、ＧａＮ及び酸化ガリウムのうちの１つである場合には、バンドギャップの大きい第１単結晶層上に、バンドギャップの大きい材料である第２の半導体材料からなる第２単結晶層が成膜されるため、高電力用途に適したＳｉＣ素子、ＧａＮ素子、酸化ガリウム素子等を製造することができる。例えば、第１の半導体材料及び第２の半導体材料がＳｉＣであれば、単結晶ＳｉＣ層が積層されることになるため、より好適である。 When the first semiconductor material is one of SiC, GaN, and gallium oxide, and the second semiconductor material is one of SiC, GaN, and gallium oxide, the first semiconductor material having a large band gap is used. Since the second single crystal layer made of the second semiconductor material having a large band gap is formed on the single crystal layer, SiC elements, GaN elements, gallium oxide elements, etc. suitable for high power applications Can be manufactured. For example, if the first semiconductor material and the second semiconductor material are SiC, a single crystal SiC layer is stacked, which is more preferable.
　本発明の半導体基板によれば、絶縁材料、半導体材料及び金属のうちの１つからなる支持基板と、前記支持基板上に接合層を挟んで積層された第２の半導体材料の単結晶からなる第２単結晶層を備え、前記第２単結晶層に半導体素子が形成されており、前記第２単結晶層の上に前記半導体素子の裏面電極層を備える。半導体素子の裏面電極層が第２単結晶層上に直接形成されているため、導電性に優れる。また、高窒素濃度を含む多結晶層によりバッファ層が形成されていれば、一層低いオーミックコンタクトを得ることができる。 According to the semiconductor substrate of the present invention, the support substrate is made of one of an insulating material, a semiconductor material, and a metal, and is formed of a single crystal of the second semiconductor material laminated on the support substrate with a bonding layer interposed therebetween. A second single crystal layer is provided, a semiconductor element is formed on the second single crystal layer, and a back electrode layer of the semiconductor element is provided on the second single crystal layer. Since the back surface electrode layer of the semiconductor element is directly formed on the second single crystal layer, it has excellent conductivity. If the buffer layer is formed of a polycrystalline layer containing a high nitrogen concentration, a lower ohmic contact can be obtained.
　前記第２単結晶層上に第１の半導体材料の単結晶からなる第１単結晶層を備える場合には、第１の半導体材料の単結晶からなる第１単結晶層の厚さを必要最小限とし、低コストの半導体基板とすることができる。また、半導体素子の耐圧の面から必要な厚さ及び必要な不純物濃度の第２単結晶層が形成されており、半導体基板の恒久的な支持層である支持基板は任意の厚さとすることができる。そして、前記裏面電極層は、第１単結晶層の上に、又は第１単結晶層上に設けられた半導体材料からなるバッファ層の上に備えられているため、縦方向の電気伝導性及び熱伝導性に優れ、高電力用途の半導体素子に好適である。
　前記第１の半導体材料はＳｉＣ、ＧａＮ及び酸化ガリウムのうちの１つであり、前記第２の半導体材料はＳｉＣ、ＧａＮ及び酸化ガリウムのうちの１つである場合には、バンドギャップの大きい第１単結晶層上に、バンドギャップの大きい材料である第２の半導体材料からなる第２単結晶層が成膜されているため、高電力用途に適したＳｉＣ素子、ＧａＮ素子、酸化ガリウム素子等が形成された半導体基板となる。 In the case where the first single crystal layer made of a single crystal of the first semiconductor material is provided on the second single crystal layer, the thickness of the first single crystal layer made of the single crystal of the first semiconductor material is minimized. Therefore, a low-cost semiconductor substrate can be obtained. Further, the second single crystal layer having a necessary thickness and a necessary impurity concentration is formed from the surface of the withstand voltage of the semiconductor element, and the supporting substrate which is a permanent supporting layer of the semiconductor substrate may have an arbitrary thickness. it can. The back electrode layer is provided on the first single crystal layer or on the buffer layer made of a semiconductor material provided on the first single crystal layer. It has excellent thermal conductivity and is suitable for semiconductor devices for high power applications.
When the first semiconductor material is one of SiC, GaN, and gallium oxide, and the second semiconductor material is one of SiC, GaN, and gallium oxide, the first semiconductor material having a large band gap is used. Since the second single crystal layer made of the second semiconductor material having a large band gap is formed on the single crystal layer, an SiC element, a GaN element, a gallium oxide element, etc. suitable for high power applications The semiconductor substrate on which is formed.
第１の基板及び第２の基板を示す模式的な上面図及び側面図Schematic top view and side view showing a first substrate and a second substrate 素子形成用の複層基板の構成を表す模式的断面図Typical sectional view showing composition of multilayer substrate for element formation 表面薄膜層で被覆された第２の基板（カーボン基板）の端部の断面画像Cross-sectional image of the edge of the second substrate (carbon substrate) covered with the surface thin film layer 両面に表面薄膜層が形成された第２の基板を土台として複層基板を形成する工程を示す模式的断面図Typical sectional drawing which shows the process of forming a multilayer substrate on the 2nd board | substrate with which the surface thin film layer was formed in both surfaces as a foundation 複層基板を構成する第２単結晶層に形成された半導体素子を示す模式的断面図Schematic sectional view showing a semiconductor element formed in a second single crystal layer constituting a multilayer substrate 半導体素子形成後に第３の基板を接合し、貫通孔を形成する工程を示す模式的断面図Typical sectional drawing which shows the process of joining a 3rd substrate after forming a semiconductor element, and forming a penetration hole 複層基板を構成する第２単結晶層に形成された別の半導体素子を示す模式的断面図Typical sectional drawing which shows another semiconductor element formed in the 2nd single crystal layer which comprises a multilayer substrate 別の半導体素子形成後に第３の基板を接合し、テーパ形状の貫通孔を形成する工程を示す模式的断面図Typical sectional drawing which shows the process of joining a 3rd substrate after forming another semiconductor element, and forming a taper-shaped penetration hole 第３の基板を接合した複層基板から第２の基板を除去し、裏面電極となる裏面電極層を形成する工程を示す模式的断面図Typical sectional drawing which shows the process of removing a 2nd board | substrate from the multilayer substrate which joined the 3rd board | substrate, and forming the back surface electrode layer used as a back surface electrode. 第３の基板を接合した複層基板から第２の基板及び表面薄膜層の第１層を除去し、バッファ層上に裏面電極層を形成する工程を示す模式的断面図Typical sectional drawing which shows the process of removing the 1st layer of a 2nd board | substrate and a surface thin film layer from the multilayer substrate which joined the 3rd board | substrate, and forming a back surface electrode layer on a buffer layer. ショットキーダイオードの製造工程を示す模式的断面図Schematic sectional view showing the manufacturing process of Schottky diode ＭＯＳＦＥＴの製造工程を示す模式的断面図Schematic cross-sectional view showing the manufacturing process of MOSFET 金属の支持基板を用いる半導体基板（ＭＯＳＦＥＴ素子）の製造工程を示す模式的断面図Typical sectional drawing which shows the manufacturing process of the semiconductor substrate (MOSFET element) using a metal support substrate 半導体基板の基本構造を示す模式的断面図Schematic cross-sectional view showing the basic structure of a semiconductor substrate 半導体基板の構造を示す模式的断面図Schematic sectional view showing the structure of a semiconductor substrate 一般的な縦型構造の半導体素子の構造を示す模式的断面図Schematic sectional view showing the structure of a general vertical semiconductor device
　本実施形態に係る半導体素子の製造方法は、例えば、カーボン基板、ＳｉＣ基板等を暫定的な支持基板（第２の基板（２））として使用することによって、高電力用途に適した半導体素子を製造するものである。カーボン基板やＳｉＣ基板は、反りが少なく高温まで耐えられるという特徴がある。本実施形態においては、そのカーボン基板（２）等を暫定的な支持層として、その一方の表面にシリコン酸化膜等（４１）を介してＳｉＣ等の単結晶層（第１単結晶層（１１））を接合し、更に半導体素子を形成するためのＳｉＣ等の単結晶からなる薄膜層（第２単結晶層（５））を形成する（図２（ａ）、（ｂ）参照）。また、カーボン基板（２）の他方の面には、ＳｉＣ等からなる多結晶膜（多結晶ＳｉＣ膜（４２））を形成することができる。このようにカーボン基板（２）等を土台として形成される複層基板（６）を用いて、第２単結晶層（５）に半導体素子を形成することができる。そして、半導体素子形成後に、最終的な支持層となる基板（第３の基板（３））を接合し、暫定的な基板であったカーボン基板（２）等が除去される。これによって、上記第３の基板（３）を恒久的な支持層とし、それに積層された第２単結晶層（５）に半導体素子が形成された半導体基板を製造することができる。更に、この半導体素子の裏面（カーボン基板等が除去され、更にシリコン酸化膜が除去された面）には、半導体素子の裏面電極となる裏面電極層を形成することができる。これによって、高電力用途に適した半導体素子及び半導体基板を製造することが可能になる。
　カーボン基板（２）は、その熱膨張係数をＳｉＣからなる上記第２単結晶層（５）及びＳｉＣからなる上記多結晶ＳｉＣ膜（４２）の熱膨張係数とほぼ同じにすることができる。また、カーボン基板（２）の厚さを数ｍｍとすれば、剛性が高く、反りの無い複層基板（６）を得ることができる。更に、カーボン基板（２）の一方の面に積層するＳｉＣからなる第２単結晶層（５）の厚さと、他方の面に形成する多結晶ＳｉＣ膜（４２）の厚さとをほぼ同じにすれば、カーボン基板（２）の厚さが１ｍｍ以下であっても、反りの少ない複層基板（６）を得ることができる。 The semiconductor element manufacturing method according to the present embodiment uses a semiconductor element suitable for high power applications by using, for example, a carbon substrate, an SiC substrate, or the like as a temporary support substrate (second substrate (2)). To manufacture. Carbon substrates and SiC substrates have a feature that they can withstand high temperatures with little warping. In the present embodiment, the carbon substrate (2) or the like is used as a temporary support layer, and a single crystal layer such as SiC (first single crystal layer (11) is provided on one surface of the carbon substrate (2) via a silicon oxide film or the like (41). )) And a thin film layer (second single crystal layer (5)) made of a single crystal such as SiC for forming a semiconductor element is formed (see FIGS. 2A and 2B). Also, a polycrystalline film (polycrystalline SiC film (42)) made of SiC or the like can be formed on the other surface of the carbon substrate (2). A semiconductor element can be formed in the second single crystal layer (5) using the multilayer substrate (6) formed on the basis of the carbon substrate (2) or the like in this way. Then, after the formation of the semiconductor element, a substrate (third substrate (3)) to be a final support layer is bonded, and the carbon substrate (2) and the like which are temporary substrates are removed. Thus, a semiconductor substrate in which the third substrate (3) is a permanent support layer and a semiconductor element is formed on the second single crystal layer (5) laminated thereon can be manufactured. Furthermore, a back electrode layer to be a back electrode of the semiconductor element can be formed on the back surface of the semiconductor element (the surface from which the carbon substrate or the like has been removed and the silicon oxide film has been removed). This makes it possible to manufacture a semiconductor element and a semiconductor substrate suitable for high power applications.
The carbon substrate (2) can have a thermal expansion coefficient substantially the same as that of the second single crystal layer (5) made of SiC and the polycrystalline SiC film (42) made of SiC. If the thickness of the carbon substrate (2) is several mm, a multilayer substrate (6) having high rigidity and no warpage can be obtained. Further, the thickness of the second single crystal layer (5) made of SiC laminated on one surface of the carbon substrate (2) and the thickness of the polycrystalline SiC film (42) formed on the other surface should be made substantially the same. For example, even if the thickness of the carbon substrate (2) is 1 mm or less, a multilayer substrate (6) with little warpage can be obtained.
　カーボン基板（２）は、シリコン酸化膜等（４１）の成膜、多結晶ＳｉＣ膜（４２）の成膜から、第１単結晶層（１１）の接合、第２単結晶層（５）の成膜、上記半導体素子の形成に至るまでの土台の役割を果たす。そして、複層基板（６）に第３の基板（３）を張り合わせた後には、カーボン基板（２）及びシリコン酸化膜等（４１）を除去することにより、複層基板（６）の裏面には第１単結晶層（１１）が露出し、半導体素子の裏面電極を形成することができる。これ以降、土台である支持基板の役割は第３の基板（３）が担うこととなる。従来の構造（図１６参照）においては、単結晶からなる厚い支持基板上に半導体素子を形成するための単結晶層が設けられ、更に支持基板の厚さを薄くする加工が施されていた。本発明の製造方法によれば、従来の支持基板を無くすことができ、薄肉化工程も不要とすることができる。また、結晶性の良い単結晶からなる第１単結晶層（１１）上に、半導体素子の能動層となる高品質な第２単結晶層（５）を成膜することができる。このように各層の特徴を活かすことによって、半導体素子の形成を容易にすると共に、コスト低減を図ることが可能になる。 The carbon substrate (2) is formed from the formation of a silicon oxide film or the like (41), the formation of a polycrystalline SiC film (42), the bonding of the first single crystal layer (11), the second single crystal layer (5). It serves as a foundation from film formation to formation of the semiconductor element. After the third substrate (3) is bonded to the multilayer substrate (6), the carbon substrate (2) and the silicon oxide film (41) are removed, so that the back surface of the multilayer substrate (6) is removed. The first single crystal layer (11) is exposed, and the back electrode of the semiconductor element can be formed. Thereafter, the third substrate (3) plays the role of the support substrate as a base. In the conventional structure (see FIG. 16), a single crystal layer for forming a semiconductor element is provided on a thick support substrate made of a single crystal, and the thickness of the support substrate is further reduced. According to the manufacturing method of the present invention, the conventional support substrate can be eliminated, and the thinning step can be eliminated. In addition, a high-quality second single crystal layer (5) serving as an active layer of a semiconductor element can be formed on the first single crystal layer (11) made of a single crystal with good crystallinity. By utilizing the characteristics of each layer in this way, it is possible to facilitate the formation of a semiconductor element and to reduce the cost.
　カーボン基板（２）等を土台として形成された第１単結晶層（１１）上に、高濃度窒素を含む単結晶の単結晶バッファ層（５２）を形成し、その後に第２単結晶層（５）を形成してもよい。単結晶バッファ層（５２）により、第２単結晶層（５）内の結晶欠陥を第１単結晶層（１１）内の結晶欠陥より低減することができる。このように形成された複層基板（６）に第３の基板（３）を張り合わせた後には、カーボン基板（２）及びシリコン酸化膜等（４１）等を除去し、更に第１単結晶層（１１）及び単結晶バッファ層（５２）を除去することにより、複層基板（６）の裏面には第２単結晶（５）が露出し、その裏面上に半導体素子の裏面電極を形成することができる。 A single crystal single crystal buffer layer (52) containing high-concentration nitrogen is formed on a first single crystal layer (11) formed using a carbon substrate (2) or the like as a base, and then a second single crystal layer ( 5) may be formed. The single crystal buffer layer (52) can reduce the crystal defects in the second single crystal layer (5) more than the crystal defects in the first single crystal layer (11). After the third substrate (3) is bonded to the multilayer substrate (6) thus formed, the carbon substrate (2), the silicon oxide film (41), etc. are removed, and the first single crystal layer is further removed. By removing (11) and the single crystal buffer layer (52), the second single crystal (5) is exposed on the back surface of the multilayer substrate (6), and the back electrode of the semiconductor element is formed on the back surface. be able to.
　半導体素子形成後に、半導体素子の最終的な支持層となる第３の基板（３）が接合され、暫定的な基板であった第２の基板（２）が除去される。第３の基板（３）が金属基板である場合には、第３の基板（３）を半導体素子の外部接続用の電極端子とすることができる。例えば、半導体素子がショットキーダイオードである場合には、そのアノ－ド電極とすることができる。また、ＭＯＳＦＥＴである場合には、そのソース電極とすることができる。 After the formation of the semiconductor element, the third substrate (3) that will be the final support layer of the semiconductor element is bonded, and the second substrate (2), which was a temporary substrate, is removed. When the third substrate (3) is a metal substrate, the third substrate (3) can be used as an electrode terminal for external connection of a semiconductor element. For example, when the semiconductor element is a Schottky diode, the anode electrode can be used. In the case of a MOSFET, the source electrode can be used.
　第２の基板（２）として、例えば、ＳｉＣ基板（２５）やサファイア基板（２６）のように、レーザ光を透過する基板を用いることができる。その場合、Ｇａを含む半導体材料で表面薄膜層（例えば、ＧａＮ膜（４１３））を形成することが好ましい。そのようにすれば、レーザ光を照射することによりＧａを析出させ、容易に第２基板（２）を除去することができる。ＳｉＣ基板やサファイア基板は、Ｇａ系薄膜を除去した後に、繰り返し第２の基板（２）として利用することができる。 As the second substrate (2), for example, a substrate that transmits laser light, such as a SiC substrate (25) or a sapphire substrate (26), can be used. In that case, it is preferable to form a surface thin film layer (for example, a GaN film (413)) with a semiconductor material containing Ga. By so doing, it is possible to easily remove the second substrate (2) by depositing Ga by irradiating the laser beam. The SiC substrate or the sapphire substrate can be repeatedly used as the second substrate (2) after removing the Ga-based thin film.
　以下、図面を参照しつつ本発明の実施形態に係る半導体素子の製造方法を説明する。
　本実施形態に係る半導体素子の製造方法は、図１、２、４、６等に示すように、第１の半導体材料の単結晶からなる第１の基板１の一方の平面１０１から所定の深さに水素注入層１５を形成する水素層形成工程と、第２の基板２の少なくとも１つの平面上に絶縁材料又は半導体材料の１層以上の薄膜からなる表面薄膜層４を成膜する第１成膜工程と、第１の基板１の一方の平面１０１と第２の基板２上に形成された表面薄膜層４の表面とを接合する接合工程と、第１の基板１を水素注入層１５で分離することにより、分離された第１の基板１の一方の平面１０１側を第１単結晶層１１として第２の基板２に形成された表面薄膜層４上に残す分離工程と、を備えている。そして、第１単結晶層１１の表面上に第２の半導体材料の単結晶からなる第２単結晶層５を成膜することにより、第２の基板２上に表面薄膜層４と第１単結晶層１１と第２単結晶層５とが順に積層された複層基板６を得る第２成膜工程と、複層基板６の第２単結晶層５に半導体素子を形成する素子形成工程と、を備えている。更に、前記半導体素子が形成された複層基板６の表面に第３の基板３を接合する第２接合工程と、第２の基板２を除去する基板除去工程と、を備えている。
　前記第１成膜工程においては、第２の基板２の一方の平面２０１に表面薄膜層４１を成膜するようにすることができる。また、第２の基板２の他方の平面２０２に、表面薄膜層４２を成膜するようにすることができる。 Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
As shown in FIGS. 1, 2, 4, 6 and the like, the method of manufacturing a semiconductor device according to this embodiment has a predetermined depth from one plane 101 of the first substrate 1 made of a single crystal of a first semiconductor material. Then, a hydrogen layer forming step for forming the hydrogen injection layer 15 and a first thin film layer 4 made of one or more thin films of an insulating material or a semiconductor material are formed on at least one plane of the second substrate 2. A film forming process, a bonding process for bonding one flat surface 101 of the first substrate 1 and the surface of the surface thin film layer 4 formed on the second substrate 2, and the first substrate 1 to the hydrogen injection layer 15. A separation step of leaving the one plane 101 side of the separated first substrate 1 on the surface thin film layer 4 formed on the second substrate 2 as the first single crystal layer 11 ing. Then, by forming a second single crystal layer 5 made of a single crystal of the second semiconductor material on the surface of the first single crystal layer 11, the surface thin film layer 4 and the first single crystal layer 5 are formed on the second substrate 2. A second film forming step for obtaining a multilayer substrate 6 in which the crystal layer 11 and the second single crystal layer 5 are sequentially laminated; and an element forming step for forming a semiconductor element on the second single crystal layer 5 of the multilayer substrate 6; It is equipped with. Furthermore, a second bonding step for bonding the third substrate 3 to the surface of the multilayer substrate 6 on which the semiconductor element is formed, and a substrate removing step for removing the second substrate 2 are provided.
In the first film forming step, the surface thin film layer 41 can be formed on one flat surface 201 of the second substrate 2. Further, the surface thin film layer 42 can be formed on the other plane 202 of the second substrate 2.
　前記第２成膜工程は、第１単結晶層１１の表面上に第２の半導体材料の単結晶からなる単結晶バッファ層５２を形成した後に第２単結晶層５を成膜し、前記基板除去工程は、第２の基板２を除去した後に単結晶バッファ層５２を除去するようにすることができる。単結晶バッファ層５２は、例えば、窒素を高濃度に含む第２の半導体材料の単結晶により形成することができる。 In the second film forming step, after forming a single crystal buffer layer 52 made of a single crystal of a second semiconductor material on the surface of the first single crystal layer 11, the second single crystal layer 5 is formed, and the substrate In the removing step, the single crystal buffer layer 52 can be removed after removing the second substrate 2. The single crystal buffer layer 52 can be formed of, for example, a single crystal of a second semiconductor material containing nitrogen at a high concentration.
　以下では、第１の半導体材料及び第２の半導体材料として、ＳｉＣを例として説明する。すなわち、第１の基板１は単結晶ＳｉＣ基板とする。また、第２の基板２としてカーボン基板を使用し、その一方の面２０１に成膜する表面薄膜層４１はシリコン酸化膜（ＳｉＯ２）とする。また、他方の面２０２に成膜する表面薄膜層４２の材料は第２の半導体材料と同じであることが好ましく、その結晶性は問わない。以下では、表面薄膜層４２は、ＳｉＣの多結晶からなる多結晶ＳｉＣ膜であるとする。
　図１（ａ）は、カーボン基板２、シリコン酸化膜４１、多結晶ＳｉＣ膜４２及び第１単結晶層１１の母材となる単結晶ＳｉＣ基板１の例を示す上面図及び側面図である。カーボン基板２の一方の平面を上面２０１、他方の平面を下面（又は裏面）２０２、その側面全体を側面２０３とする。本図では、シリコン酸化膜４１がカーボン基板２の上面２０１と側面２０３に形成され（側面２０３部は図示せず）、多結晶ＳｉＣ膜４２がカーボン基板１の下面２０２と側面２０３に形成されており（側面２０３部は図示せず）、単結晶ＳｉＣ基板１の下面１０１から所定の深さに水素注入層１５が形成された状態を表している。カーボン基板２及び単結晶ＳｉＣ基板１の形状は問わないが、好ましくは円板状又は円柱状の基板である。また、カーボン基板２及び単結晶ＳｉＣ基板１のサイズも限定されないが、取扱性の上でカーボン基板２が単結晶ＳｉＣ基板１より一回り大きくされている。カーボン基板２の直径が、単結晶ＳｉＣ基板１の直径よりも１～１０ｍｍ程度大きいことが好ましい。例えば、単結晶ＳｉＣ基板１が外径６インチ（約１５０ｍｍ）である場合には、カーボン基板２は外径１６０ｍｍ程度とすればよい。
　前記接合工程において、カーボン基板２の表面２０１上に設けられたシリコン酸化膜４１の表面と、単結晶ＳｉＣ基板１の下面１０１とが接合される。 Hereinafter, SiC will be described as an example of the first semiconductor material and the second semiconductor material. That is, the first substrate 1 is a single crystal SiC substrate. Further, a carbon substrate is used as the second substrate 2, and the surface thin film layer 41 formed on one surface 201 is a silicon oxide film (SiO 2 ). The material of the surface thin film layer 42 formed on the other surface 202 is preferably the same as that of the second semiconductor material, and the crystallinity thereof is not limited. In the following, it is assumed that the surface thin film layer 42 is a polycrystalline SiC film made of polycrystalline SiC.
FIG. 1A is a top view and a side view showing an example of a single crystal SiC substrate 1 that is a base material for the carbon substrate 2, the silicon oxide film 41, the polycrystalline SiC film 42, and the first single crystal layer 11. One plane of the carbon substrate 2 is an upper surface 201, the other plane is a lower surface (or back surface) 202, and the entire side surface is a side surface 203. In this figure, the silicon oxide film 41 is formed on the upper surface 201 and the side surface 203 of the carbon substrate 2 (the side surface 203 portion is not shown), and the polycrystalline SiC film 42 is formed on the lower surface 202 and the side surface 203 of the carbon substrate 1. (Side part 203 is not shown), and shows a state in which the hydrogen injection layer 15 is formed at a predetermined depth from the lower surface 101 of the single crystal SiC substrate 1. The shape of the carbon substrate 2 and the single crystal SiC substrate 1 is not limited, but is preferably a disc-shaped or columnar substrate. The sizes of the carbon substrate 2 and the single crystal SiC substrate 1 are not limited, but the carbon substrate 2 is made slightly larger than the single crystal SiC substrate 1 in terms of handling. The diameter of the carbon substrate 2 is preferably about 1 to 10 mm larger than the diameter of the single crystal SiC substrate 1. For example, when the single crystal SiC substrate 1 has an outer diameter of 6 inches (about 150 mm), the carbon substrate 2 may have an outer diameter of about 160 mm.
In the bonding step, the surface of the silicon oxide film 41 provided on the surface 201 of the carbon substrate 2 and the lower surface 101 of the single crystal SiC substrate 1 are bonded.
　図１（ｂ）は、第２の基板としてＳｉＣ基板（又はサファイア基板）２５を使用し、その一方の面２０１に表面薄膜層としてＧａＮ膜４１３を成膜する例を示している。ＳｉＣは、酸素等の雰囲気において安定であるため、下面２０２に表面薄膜層を形成する必要はない。前記接合工程において、ＳｉＣ基板２５上に形成されたＧａＮ膜４１３の表面と単結晶ＳｉＣ基板１の下面１０１とが接合されることとなる。ＳｉＣ基板２５の直径は、単結晶ＳｉＣ基板１の直径よりも１ｍｍ程度大きいことが好ましい。 FIG. 1B shows an example in which a SiC substrate (or sapphire substrate) 25 is used as the second substrate, and a GaN film 413 is formed as a surface thin film layer on one surface 201 thereof. Since SiC is stable in an atmosphere such as oxygen, it is not necessary to form a surface thin film layer on the lower surface 202. In the bonding step, the surface of the GaN film 413 formed on the SiC substrate 25 and the lower surface 101 of the single crystal SiC substrate 1 are bonded. The diameter of SiC substrate 25 is preferably about 1 mm larger than the diameter of single crystal SiC substrate 1.
　図２（ａ）及び（ｂ）は、カーボン基板２の一方の面２０１上に表面薄膜層４１と第１単結晶層（単結晶ＳｉＣ層）１１と第２単結晶層（単結晶ＳｉＣ層）５とが順に積層された複層基板６を表す模式的な断面図である。図２（ａ）に示す複層基板６（６ａ）は、カーボン基板２の上面２０１上に、表面薄膜層としてシリコン酸化膜４１と、第１単結晶層１１と第２単結晶層５とが順に形成され、カーボン基板２の他方の面（下面）２０２に多結晶ＳｉＣ膜４２が形成されて構成されている。この複層基板６の製造工程においては、先ずカーボン基板２の上面２０１及び側面２０３にシリコン酸化膜４１が成膜され、次にカーボン基板２の下面２０２及び側面２０３に多結晶ＳｉＣ膜４２が成膜される。そして、シリコン酸化膜４１を介してカーボン基板２と第１単結晶層１１（単結晶ＳｉＣ基板１）とが接合され、更にカーボン基板２の上面２０１側及び側面２０３側を覆うようにＳｉＣ層（５、５１）が成膜されて、複層基板６ａが構成される。ＳｉＣからなる第２単結晶層５を成膜する際に、第１の基板１の径はカーボン基板２の径よりも小さいため、第１単結晶層１１の上面には単結晶からなる第２単結晶層５が成膜されるが、第１単結晶層１１の径（即ち第１の基板１の径）を超える外周部及びカーボン基板２の側面２０３側には、多結晶からなる層（第２多結晶層）５１が形成される。 2A and 2B show a surface thin film layer 41, a first single crystal layer (single crystal SiC layer) 11, and a second single crystal layer (single crystal SiC layer) on one surface 201 of the carbon substrate 2. FIG. FIG. 5 is a schematic cross-sectional view showing a multilayer substrate 6 in which 5 and 5 are sequentially stacked. The multilayer substrate 6 (6a) shown in FIG. 2A has a silicon oxide film 41, a first single crystal layer 11, and a second single crystal layer 5 as a surface thin film layer on the upper surface 201 of the carbon substrate 2. The polycrystalline SiC film 42 is formed on the other surface (lower surface) 202 of the carbon substrate 2. In the manufacturing process of the multilayer substrate 6, first, the silicon oxide film 41 is formed on the upper surface 201 and the side surface 203 of the carbon substrate 2, and then the polycrystalline SiC film 42 is formed on the lower surface 202 and the side surface 203 of the carbon substrate 2. Be filmed. Then, the carbon substrate 2 and the first single crystal layer 11 (single crystal SiC substrate 1) are bonded via the silicon oxide film 41, and further, an SiC layer (covering the upper surface 201 side and the side surface 203 side of the carbon substrate 2). 5, 51) are formed to form the multilayer substrate 6a. When forming the second single crystal layer 5 made of SiC, the diameter of the first substrate 1 is smaller than the diameter of the carbon substrate 2, so that the second surface made of single crystal is formed on the upper surface of the first single crystal layer 11. The single crystal layer 5 is formed, and a polycrystal layer (on the outer peripheral portion exceeding the diameter of the first single crystal layer 11 (that is, the diameter of the first substrate 1) and the side surface 203 side of the carbon substrate 2 ( The second polycrystalline layer) 51 is formed.
　第２の基板２の一方の面２０１上に成膜する表面薄膜層は、２層の薄膜により構成することができる。図２（ｂ）に示す複層基板６（６ｂ）は、カーボン基板２の上面２０１上に形成する表面薄膜層が２層からなる点で、同図（ａ）に示した複層基板６ａと異なる。複層基板６ｂは、カーボン基板２の上面２０１上に第１層としてシリコン酸化膜４１が成膜され、その上に第２層（半導体材料からなるバッファ層）としてＳｉＣ層が成膜されている。このＳｉＣ層は多結晶からなる。バッファ層を設けた複層基板６ｂは、カーボン基板２の上面２０１上に、表面薄膜層としてシリコン酸化膜４１及びＳｉＣ多結晶からなるバッファ層４１２と、第１単結晶層１１と第２単結晶層５とが順に形成され、カーボン基板２の他方の面（下面）２０２に多結晶ＳｉＣ膜４２が形成されて構成されている。カーボン基板２の側面２０３側は、シリコン酸化膜４１、ＳｉＣ多結晶からなるバッファ層４１２及び多結晶ＳｉＣ膜４２により覆われる。 The surface thin film layer formed on one surface 201 of the second substrate 2 can be composed of two thin films. The multilayer substrate 6 (6b) shown in FIG. 2 (b) is different from the multilayer substrate 6a shown in FIG. 2 (a) in that the surface thin film layer formed on the upper surface 201 of the carbon substrate 2 consists of two layers. Different. In the multi-layer substrate 6b, a silicon oxide film 41 is formed as a first layer on the upper surface 201 of the carbon substrate 2, and a SiC layer is formed as a second layer (buffer layer made of a semiconductor material) thereon. . This SiC layer is made of polycrystal. The multilayer substrate 6b provided with the buffer layer is formed on the upper surface 201 of the carbon substrate 2 with a buffer layer 412 made of a silicon oxide film 41 and SiC polycrystal as a surface thin film layer, a first single crystal layer 11 and a second single crystal. The layer 5 is sequentially formed, and the polycrystalline SiC film 42 is formed on the other surface (lower surface) 202 of the carbon substrate 2. The side surface 203 side of the carbon substrate 2 is covered with a silicon oxide film 41, a buffer layer 412 made of SiC polycrystal, and a polycrystalline SiC film 42.
　バッファ層４１２は、高窒素濃度の多結晶ＳｉＣ層であってもよい。高窒素濃度の多結晶ＳｉＣ層とすることにより、後の裏面電極形成時にオーミックコントクト性を良くすることができる。尚、高窒素濃度の多結晶ＳｉＣ層と第１単結晶層１１との間では、バンド幅の違いにより電位障壁が生じてオーミック接続の障害となる可能性がある。その場合には、接合前に第１単結晶層１１の極く薄い表層を高窒素濃度にしておいてもよい。 The buffer layer 412 may be a high-concentration polycrystalline SiC layer. By using a polycrystalline SiC layer having a high nitrogen concentration, ohmic contractability can be improved when a back electrode is formed later. In addition, there is a possibility that a potential barrier is generated between the polycrystalline SiC layer having a high nitrogen concentration and the first single crystal layer 11 due to a difference in the bandwidth, thereby hindering ohmic connection. In that case, a very thin surface layer of the first single crystal layer 11 may be set to a high nitrogen concentration before bonding.
　図２（ｃ）は、第２の基板としてＳｉＣ基板（又はサファイア基板）２５を使用し、その一方の面２０１に表面薄膜層としてＧａＮ膜４１３を成膜した場合の複層基板６（６ｃ）を示している。複層基板６ｃは、ＳｉＣ基板２５の上面２０１上に、ＧａＮ膜４１３と第１単結晶層１１と第２単結晶層５とが順に形成されて構成されている。図示されていないが、第２単結晶層５を成膜する際に周縁部には第２多結晶層５１が形成される。
　上記複層基板６（６ａ、６ｂ、６ｃ）において、ＳｉＣからなる第２単結晶層５を成膜する前に、窒素を高濃度に含むＳｉＣの単結晶からなる単結晶バッファ層５２が形成されてもよい。図２（ｄ）は、第１単結晶層１１の表面上に第２の半導体材料の単結晶からなる単結晶バッファ層５２が形成され、その後に第２単結晶層５が成膜された複層基板６（６ｄ）を示している。
　図２（e）は、ＳｉＣ基板２５の上面２０１上に、ＧａＮ膜４１３と、バッファ層として高窒素濃度の多結晶ＳｉＣ層５３と、第１単結晶層１１と、第２単結晶層５とが順に形成されて構成された複層基板６（６ｅ）を示している。高窒素濃度の多結晶ＳｉＣ層５３を形成することにより、後の裏面電極形成時にオーミックコントクト性を良くすることができる。尚、高窒素濃度の多結晶ＳｉＣ層５３と第１単結晶層１１との間では、バンド幅の違いにより電位障壁が生じてオーミック接続の障害となる可能性がある。その場合には、接合前に第１単結晶層１１の極く薄い表層を高窒素濃度にしておいてもよい。 FIG. 2C shows a multi-layer substrate 6 (6c) in which a SiC substrate (or sapphire substrate) 25 is used as the second substrate and a GaN film 413 is formed as a surface thin film layer on one surface 201 thereof. Is shown. The multilayer substrate 6 c is configured by forming a GaN film 413, the first single crystal layer 11, and the second single crystal layer 5 in this order on the upper surface 201 of the SiC substrate 25. Although not shown, when the second single crystal layer 5 is formed, the second polycrystalline layer 51 is formed at the periphery.
In the multilayer substrate 6 (6a, 6b, 6c), before the second single crystal layer 5 made of SiC is formed, a single crystal buffer layer 52 made of SiC single crystal containing nitrogen at a high concentration is formed. May be. In FIG. 2D, a single crystal buffer layer 52 made of a single crystal of the second semiconductor material is formed on the surface of the first single crystal layer 11, and then the second single crystal layer 5 is formed. A layer substrate 6 (6d) is shown.
FIG. 2E shows a GaN film 413, a high nitrogen concentration polycrystalline SiC layer 53 as a buffer layer, the first single crystal layer 11, and the second single crystal layer 5 on the upper surface 201 of the SiC substrate 25. Shows a multilayer substrate 6 (6e) that is formed in order. By forming the polycrystalline SiC layer 53 with a high nitrogen concentration, the ohmic contractability can be improved when the back electrode is formed later. In addition, there is a possibility that a potential barrier is generated between the polycrystalline SiC layer 53 having a high nitrogen concentration and the first single crystal layer 11 due to the difference in the bandwidth, thereby hindering ohmic connection. In that case, a very thin surface layer of the first single crystal layer 11 may be set to a high nitrogen concentration before bonding.
　（水素層形成工程）
　第１の基板１は、第１の半導体材料の単結晶からなる。第１の半導体材料はＳｉＣに限定されず、例えば、ＳｉＣ、ＧａＮ、酸化ガリウム等を採用することができる。後の工程において、第１の基板１から分離された第１単結晶層１１上に第２単結晶層５が形成されるため、第１の半導体材料は、第２単結晶層５の材料である第２の半導体材料と同じか又はＳｉＣとすることが好ましい。
　前記水素層形成工程は、第１の基板１の下面１０１から所定の深さに水素注入層１５を形成する工程である。水素注入層１５は、上記所定の深さ（例えば、０．２～１．５μｍ、好ましくは０．５μｍ程度の深さ）に水素イオンを注入することにより形成することができる。 (Hydrogen layer formation process)
The first substrate 1 is made of a single crystal of a first semiconductor material. The first semiconductor material is not limited to SiC, and, for example, SiC, GaN, gallium oxide, or the like can be employed. In the subsequent process, since the second single crystal layer 5 is formed on the first single crystal layer 11 separated from the first substrate 1, the first semiconductor material is the material of the second single crystal layer 5. It is preferably the same as a certain second semiconductor material or SiC.
The hydrogen layer forming step is a step of forming the hydrogen injection layer 15 at a predetermined depth from the lower surface 101 of the first substrate 1. The hydrogen implantation layer 15 can be formed by implanting hydrogen ions at the predetermined depth (for example, a depth of about 0.2 to 1.5 μm, preferably about 0.5 μm).
　（シリサイド層形成工程）
　図２に示した複層基板６（６ａ、６ｂ、６ｃ、６ｄ、６ｅ）において、第２の基板側となる第１単結晶層１１の表面に予めシリサイド層を形成しておくことができる。例えば、第２の基板と接合する前に、第１の基板１の下面１０１にシリサイド層を形成する。このようにすれば、後に第２の基板を除去して半導体素子の裏面電極層を形成する際のシリサイド化処理を省略することができる。 (Silicide layer formation process)
In the multilayer substrate 6 (6a, 6b, 6c, 6d, 6e) shown in FIG. 2, a silicide layer can be formed in advance on the surface of the first single crystal layer 11 on the second substrate side. For example, a silicide layer is formed on the lower surface 101 of the first substrate 1 before bonding to the second substrate. In this way, the silicidation process when the second substrate is removed later to form the back electrode layer of the semiconductor element can be omitted.
　（第１成膜工程）
　前記第１成膜工程は、第２の基板２の少なくとも１つの平面上に絶縁材料又は半導体材料の薄膜からなる表面薄膜層４を成膜する工程である。使用する絶縁材料又は半導体材料は、第１の基板１との接合性や第２の基板２の保護の必要性等に応じて適宜選択されればよく、例えば、シリコン酸化物（ＳｉＯ２）、ＳｉＣ、ＧａＮ等を挙げることができる。
　第２の基板２にカーボン基板を用いる場合には、表面薄膜層４として、カーボン基板２の一方の平面２０１に、シリコン酸化膜４１、又はシリコン酸化膜４１及びＳｉＣからなるバッファ層４１２を成膜するようにすることができる。また、それに加えて、カーボン基板２の他方の平面２０２に多結晶ＳｉＣ膜（４２）を成膜するようにすることができる。表面薄膜層４１、４１２及び４２の成膜は、いずれを先に行ってもよい。表面薄膜層（４１、４１２、４２）を成膜する際には、第２の基板２の側面２０３側にも同じ薄膜層（４１、４１２、４１）が形成される。
　第２の基板２にサファイア基板を用いる場合には、表面薄膜層４として、一方の平面２０１にＧａＮ膜又はシリコン酸化膜を成膜するようにすることができる。サファイア基板は素子形成工程の熱処理から保護する必要はないため、他方の平面２０２及び側面２０３には、表面薄膜層４を形成する必要はない。 (First film formation step)
The first film forming step is a step of forming a surface thin film layer 4 made of a thin film of an insulating material or a semiconductor material on at least one plane of the second substrate 2. The insulating material or the semiconductor material to be used may be appropriately selected according to the bonding property with the first substrate 1 and the necessity of protection of the second substrate 2, for example, silicon oxide (SiO 2 ), SiC, GaN, etc. can be mentioned.
When a carbon substrate is used as the second substrate 2, the silicon oxide film 41 or the buffer layer 412 made of the silicon oxide film 41 and SiC is formed on the one plane 201 of the carbon substrate 2 as the surface thin film layer 4. To be able to. In addition, a polycrystalline SiC film (42) can be formed on the other flat surface 202 of the carbon substrate 2. Any of the surface thin film layers 41, 412 and 42 may be formed first. When the surface thin film layers (41, 412, and 42) are formed, the same thin film layers (41, 412, and 41) are also formed on the side surface 203 side of the second substrate 2.
When a sapphire substrate is used as the second substrate 2, a GaN film or a silicon oxide film can be formed on the one surface 201 as the surface thin film layer 4. Since the sapphire substrate does not need to be protected from the heat treatment in the element formation process, it is not necessary to form the surface thin film layer 4 on the other plane 202 and side surface 203.
　第２の基板２として光透過性のあるＳｉＣ基板２５を用いる場合も同様である。ＳｉＣ基板２５の一方の平面２０１に表面薄膜層４としてＧａを含む半導体層（例えば、ＧａＮ膜、酸化Ｇａ膜）を成膜することができる。ＳｉＣ基板２５もまた素子形成工程の熱処理から保護する必要はないため、他方の平面２０２及び側面２０３に表面薄膜層４を形成する必要はない。また、サファイア基板やＳｉＣ基板は剛性があり、反りも抑制される。 The same applies to the case where a light-transmitting SiC substrate 25 is used as the second substrate 2. A semiconductor layer (for example, a GaN film or a Ga oxide film) containing Ga can be formed as the surface thin film layer 4 on one plane 201 of the SiC substrate 25. Since it is not necessary to protect the SiC substrate 25 from the heat treatment in the element formation process, it is not necessary to form the surface thin film layer 4 on the other plane 202 and the side surface 203. Further, the sapphire substrate and the SiC substrate are rigid and warpage is suppressed.
　高電力用途の半導体素子を形成するには、窒素、リン、アルミニウム等の不純物の活性化のために１７００℃程度の高温とする工程が必要である。その半導体素子を形成する土台となる第２の基板２として、カーボン基板を使用することができる。カーボンは、不活性ガス中においては上記のような高温に耐える材料である。しかし、カーボンは、酸素が存在する場合には４００℃以上で焼損する。このようなカーボンを保護するために、カーボン基板２の全表面を被覆する方法を採用することができる。具体的には、第１成膜工程において、カーボン基板２の上面２０１及び側面２０３をシリコン酸化膜４１で覆い、カーボン基板２の下面２０２及び側面２０３側を覆うように多結晶ＳｉＣ膜４２を成膜することが好ましい。更に、後の工程において、カーボン基板２の上面２０１側及び側面２０３側は、第２の半導体材料からなる薄膜層（第２単結晶層５及び第２多結晶層５１）により覆われる。このようにすれば、カーボン基板２の全ての表面が多結晶ＳｉＣ膜４２、第２単結晶層５、第２多結晶層５１等により被覆され、カーボン基板２が外部に露出しないので、酸素が存在する高温での加工を行うことができる。また、カーボン基板２の両面に形成されるこれら各薄膜の厚さのバランスをとることにより、カーボン基板２の反りを極めて小さくすることができる。カーボン基板２の裏面２０２に形成される多結晶ＳｉＣ膜４２の厚さは、カーボン基板２を覆うこと及び複層基板６の反りを減らすことを目的として、カーボン基板２の上面２０１側に形成されるシリコン酸化膜４１等、第１単結晶層１１及び第２単結晶層５の各厚さに対応して、反りが生じないようバランスさせるのに必要な厚さ（例えば、１～１０μｍ程度）とすることが可能である。その場合、カーボン基板２の厚さは、反りを抑制しハンドリングを容易にするために最低限必要な厚さ（例えば、２５０～１０００μｍ程度）とすることが可能である。 In order to form a semiconductor element for high power use, a process of raising the temperature to about 1700 ° C. is necessary to activate impurities such as nitrogen, phosphorus, and aluminum. A carbon substrate can be used as the second substrate 2 as a base for forming the semiconductor element. Carbon is a material that can withstand such high temperatures in an inert gas. However, carbon burns out at 400 ° C. or higher when oxygen is present. In order to protect such carbon, a method of covering the entire surface of the carbon substrate 2 can be employed. Specifically, in the first film forming step, the polycrystalline SiC film 42 is formed so as to cover the upper surface 201 and the side surface 203 of the carbon substrate 2 with the silicon oxide film 41 and cover the lower surface 202 and the side surface 203 side of the carbon substrate 2. It is preferable to form a film. Further, in the subsequent process, the upper surface 201 side and the side surface 203 side of the carbon substrate 2 are covered with a thin film layer (second single crystal layer 5 and second polycrystalline layer 51) made of the second semiconductor material. In this way, the entire surface of the carbon substrate 2 is covered with the polycrystalline SiC film 42, the second single crystal layer 5, the second polycrystalline layer 51, etc., and the carbon substrate 2 is not exposed to the outside. The existing high temperature processing can be performed. Further, by balancing the thicknesses of these thin films formed on both surfaces of the carbon substrate 2, the warp of the carbon substrate 2 can be extremely reduced. The thickness of the polycrystalline SiC film 42 formed on the back surface 202 of the carbon substrate 2 is formed on the upper surface 201 side of the carbon substrate 2 for the purpose of covering the carbon substrate 2 and reducing warpage of the multilayer substrate 6. Corresponding to the thickness of each of the first single crystal layer 11 and the second single crystal layer 5 such as the silicon oxide film 41 and the like, a thickness necessary for balancing so as not to cause warpage (for example, about 1 to 10 μm) Is possible. In this case, the thickness of the carbon substrate 2 can be set to a minimum thickness (for example, about 250 to 1000 μm) necessary for suppressing warpage and facilitating handling.
　図３は、カーボン基板２をシリコン酸化膜４１及び多結晶ＳｉＣ膜４２で被覆したときの基板端部の断面画像である。カーボン基板２の上面２０１に熱ＣＶＤ装置を用いてシリコン酸化膜４１を形成すると、カーボン基板２の側面２０３側にもシリコン酸化膜４１が成膜される。その後、シリコン酸化膜４１面を下にして、上方からカーボン基板２の下面２０２に多結晶ＳｉＣ膜４２を成膜すると、カーボン基板２の側面２０３側にも多結晶ＳｉＣ膜４２が形成される。図３において、多結晶ＳｉＣ膜４２とシリコン酸化膜４１の境界部４３を破線にて示している。このように、カーボン基板２の端部においては不均一が発生し、膜厚が一定とはならないため、カーボン基板２の板端の角部は、面取り処理（べベル処理）がされている。面取りの形状や大きさを適宜定めることにより、カーボン基板２の板端に至るまでシリコン酸化膜４１及び多結晶ＳｉＣ膜４２の厚さが均一となるようにすることが好ましい。 FIG. 3 is a cross-sectional image of the edge of the substrate when the carbon substrate 2 is covered with the silicon oxide film 41 and the polycrystalline SiC film 42. When the silicon oxide film 41 is formed on the upper surface 201 of the carbon substrate 2 using a thermal CVD apparatus, the silicon oxide film 41 is also formed on the side surface 203 side of the carbon substrate 2. Thereafter, when the polycrystalline SiC film 42 is formed on the lower surface 202 of the carbon substrate 2 from above with the silicon oxide film 41 face down, the polycrystalline SiC film 42 is also formed on the side surface 203 side of the carbon substrate 2. In FIG. 3, a boundary 43 between the polycrystalline SiC film 42 and the silicon oxide film 41 is indicated by a broken line. As described above, nonuniformity occurs at the end of the carbon substrate 2 and the film thickness is not constant. Therefore, the corner of the end of the carbon substrate 2 is chamfered (beveled). It is preferable that the thickness and thickness of the silicon oxide film 41 and the polycrystalline SiC film 42 be uniform until reaching the end of the carbon substrate 2 by appropriately determining the shape and size of the chamfer.
　（接合工程）
　前記接合工程は、第１の基板（単結晶ＳｉＣ基板）１の下面１０１と第２の基板（カーボン基板）２上に形成された表面薄膜層４（シリコン酸化膜４１）の表面とを接合する工程である。接合方法は特に問わず、例えば、両表面をアルゴンビーム等で活性化して接合することが可能である。カーボン基板２上に２層からなる表面薄膜層４（シリコン酸化膜４１及びＳｉＣからなるバッファ層４１２）が形成されている場合も、同様に接合することができる。 (Joining process)
In the bonding step, the lower surface 101 of the first substrate (single crystal SiC substrate) 1 and the surface of the surface thin film layer 4 (silicon oxide film 41) formed on the second substrate (carbon substrate) 2 are bonded. It is a process. The bonding method is not particularly limited, and for example, both surfaces can be activated and bonded with an argon beam or the like. When the surface thin film layer 4 (the silicon oxide film 41 and the buffer layer 412 made of SiC) having two layers is formed on the carbon substrate 2, the bonding can be similarly performed.
　第２の基板がＳｉＣ基板２５（又はサファイア基板）であり、表面薄膜層４としてＧａＮ膜４１３が形成されている場合には、接合工程において、第１の基板１の下面１０１とＳｉＣ基板２５上に形成されたＧａＮ膜４１３の表面とが接合される。接合方法は特に問わず、例えば、両表面をアルゴンビーム等で活性化して接合することが可能である。 When the second substrate is the SiC substrate 25 (or sapphire substrate) and the GaN film 413 is formed as the surface thin film layer 4, the lower surface 101 of the first substrate 1 and the SiC substrate 25 are formed on the bonding step. The surface of the GaN film 413 formed on the surface is joined. The bonding method is not particularly limited, and for example, both surfaces can be activated and bonded with an argon beam or the like.
　（分離工程）
　前記分離工程は、第２の基板との接合面、即ち第１の基板の下面１０１から所定の深さにおいて第１の基板を分離することにより、第１の基板の下面側を第１単結晶層として第２の基板上に残す工程である。すなわち、第２の基板上に、前記所定の深さに相当する厚さの第１単結晶層が残される。
　例えば、第１の基板（単結晶ＳｉＣ基板）１を水素注入層１５で分離することができる。これにより、第２の基板（カーボン基板）２に形成された表面薄膜層４（シリコン酸化膜４１）上に、分離された第１の基板１の下面１０１側を第１単結晶層１１として残すことができる。水素注入層１５における分離は、接合された基板を高温とすることによって可能である。例えば、第１の基板１が単結晶ＳｉＣ基板である場合には、９００～１０００℃で水素注入層１５にてブリスタが発生し、水素注入層１５を境界として単結晶ＳｉＣ基板１が分離される。
　第２の基板がＳｉＣ基板２５（又はサファイア基板）であり、表面薄膜層４としてＧａＮ膜４１３が形成されている場合も同様である。 (Separation process)
The separation step separates the first substrate at a predetermined depth from the bonding surface with the second substrate, that is, the lower surface 101 of the first substrate, so that the lower surface side of the first substrate becomes the first single crystal. A step of leaving the layer on the second substrate. That is, the first single crystal layer having a thickness corresponding to the predetermined depth is left on the second substrate.
For example, the first substrate (single crystal SiC substrate) 1 can be separated by the hydrogen injection layer 15. Thus, the lower surface 101 side of the separated first substrate 1 is left as the first single crystal layer 11 on the surface thin film layer 4 (silicon oxide film 41) formed on the second substrate (carbon substrate) 2. be able to. Separation in the hydrogen injection layer 15 is possible by raising the temperature of the bonded substrate. For example, when the first substrate 1 is a single crystal SiC substrate, blisters are generated in the hydrogen injection layer 15 at 900 to 1000 ° C., and the single crystal SiC substrate 1 is separated with the hydrogen injection layer 15 as a boundary. .
The same applies to the case where the second substrate is the SiC substrate 25 (or sapphire substrate) and the GaN film 413 is formed as the surface thin film layer 4.
　（第２成膜工程）
　前記第２成膜工程は、仮支持基板である第２の基板上に第２の半導体材料の単結晶からなる第２単結晶層５を成膜する工程である。具体的には、第２の基板２（２５）上に形成された第１単結晶層１１の表面上に、第２の半導体材料の単結晶からなる第２単結晶層５を成膜することができる。第２の半導体材料は特に限定されず、例えば、ＳｉＣ、ＧａＮ、酸化ガリウム等のうち１つを採用することができる。第２成膜工程により、例えば、カーボン基板（第２の基板）２上にシリコン酸化膜４１と単結晶ＳｉＣ層（第１単結晶層）１１と成膜された単結晶ＳｉＣ層（第２単結晶層）５とが順に積層された複層基板６を得ることができる。第２成膜工程においては、第１単結晶層１１上には第２の半導体材料の単結晶層５が成膜され、第１単結晶層１１が存在しない部分（即ち、第２の基板２の上面２０１側において第１単結晶層１１が無い外周部分、及び第２の基板２の側面２０３側）には、第２の半導体材料の多結晶層５１が形成される。
　結晶性の良い第１単結晶層１１は、その上に形成される第２単結晶層５の下地として好適である。第２単結晶層５の具体的な成膜方法は特に限定されない。例えば、第１単結晶層１１上に、エピタキシャル成長により第２単結晶層５を成膜することができる。第２の半導体材料の種類によっては、ＭＯＣＶＤ手法により成膜することも可能である。第２単結晶層５は、結晶性の良い第１単結晶層１１上に成膜されるため高品質な単結晶層とすることができ、半導体素子を形成するために好適である。第２単結晶層５の厚さは、半導体素子の能動層とするために必要な厚さ（第２の半導体材料がＳｉＣである場合、５～１０μｍ程度）だけがあればよい。
　以上の工程によって、図２に示した複層基板６が形成される。 (Second film formation step)
The second film forming step is a step of forming a second single crystal layer 5 made of a single crystal of a second semiconductor material on a second substrate which is a temporary support substrate. Specifically, the second single crystal layer 5 made of a single crystal of the second semiconductor material is formed on the surface of the first single crystal layer 11 formed on the second substrate 2 (25). Can do. The second semiconductor material is not particularly limited, and for example, one of SiC, GaN, gallium oxide, and the like can be employed. In the second film formation step, for example, a single crystal SiC layer (second single crystal layer) formed by forming a silicon oxide film 41 and a single crystal SiC layer (first single crystal layer) 11 on the carbon substrate (second substrate) 2 is formed. A multilayer substrate 6 in which a crystal layer 5) is laminated in order can be obtained. In the second film formation step, the single crystal layer 5 of the second semiconductor material is formed on the first single crystal layer 11, and the portion where the first single crystal layer 11 does not exist (that is, the second substrate 2). The polycrystalline layer 51 of the second semiconductor material is formed on the outer peripheral portion where the first single crystal layer 11 is not present on the upper surface 201 side and on the side surface 203 side of the second substrate 2.
The first single crystal layer 11 having good crystallinity is suitable as a base for the second single crystal layer 5 formed thereon. A specific film forming method of the second single crystal layer 5 is not particularly limited. For example, the second single crystal layer 5 can be formed on the first single crystal layer 11 by epitaxial growth. Depending on the type of the second semiconductor material, the film can be formed by the MOCVD method. Since the second single crystal layer 5 is formed on the first single crystal layer 11 having good crystallinity, the second single crystal layer 5 can be a high-quality single crystal layer and is suitable for forming a semiconductor element. The thickness of the second single crystal layer 5 only needs to be a thickness necessary for forming an active layer of a semiconductor element (about 5 to 10 μm when the second semiconductor material is SiC).
Through the above steps, the multilayer substrate 6 shown in FIG. 2 is formed.
　第２成膜工程においては、第１単結晶層１１上に窒素を高濃度に含む単結晶の単結晶バッファ層５２を形成して、その後に窒素濃度の低い第２単結晶層５をエピタキシャル成長させることもできる。 In the second film forming step, a single crystal single crystal buffer layer 52 containing nitrogen at a high concentration is formed on the first single crystal layer 11, and then the second single crystal layer 5 having a low nitrogen concentration is epitaxially grown. You can also.
　（素子形成工程）
　前記素子形成工程は、第２成膜工程によって得られた複層基板６の表層である第２単結晶層５に半導体素子７を形成する工程である。半導体素子を形成する工程は、ショットキーダイオード、ＭＯＳＦＥＴ、ＪＦＥＴ等、目的とする半導体素子７を構成するために必要な不純物領域、絶縁物領域、表面の電気的配線領域等を形成する工程である（図１１、１２参照）。複層基板６は、カーボン基板２の厚みやその両面に形成された薄膜のバランスにより曲がりや反りが抑制されるため、汎用のフォトリソグラフィ装置を使用して半導体素子７を形成することができる。
　第２の基板がＳｉＣ基板又はサファイア基板である場合には、ＳｉＣ基板又はサファイア基板自体の剛性により複層基板６の曲がりや反りが抑制される。 (Element formation process)
The element forming step is a step of forming the semiconductor element 7 on the second single crystal layer 5 which is the surface layer of the multilayer substrate 6 obtained by the second film forming step. The process of forming the semiconductor element is a process of forming an impurity region, an insulator region, a surface electrical wiring region, and the like necessary for configuring the target semiconductor device 7 such as a Schottky diode, MOSFET, JFET, and the like. (See FIGS. 11 and 12). Since the multilayer substrate 6 is prevented from being bent or warped by the thickness of the carbon substrate 2 or the balance of the thin films formed on both surfaces thereof, the semiconductor element 7 can be formed using a general-purpose photolithography apparatus.
When the second substrate is a SiC substrate or a sapphire substrate, bending and warping of the multilayer substrate 6 are suppressed by the rigidity of the SiC substrate or sapphire substrate itself.
　（第２接合工程）
　前記第２接合工程は、素子形成工程により半導体素子７が形成された複層基板６の第２単結晶層５側表面に第３の基板３を接合する工程である。第３の基板３の接合方法は特に問わず、例えば、第３の基板３と、半導体素子７が形成された第２単結晶層５の表面とを、適宜選択される接着層３４等を介して接合することができる（図６、８参照）。
　第３の基板３としては、無アルカリガラスやサファイアのように絶縁材料からなる基板（３１）を用いることができる。また、第３の基板３として、Ｓｉ基板（３２）等のような半導体材料を用いた基板を用いることもできる。無アルカリガラス、サファイア等の非半導体材料を用いる場合には、例えば、素子形成工程が完了した第２単結晶層５の表面に光硬化型接着剤をコートした接着層３４を設け、その上に第３の基板３１を貼り合せ、紫外線硬化により接合することが可能である。Ｓｉ基板等を用いる場合には、例えば、素子形成工程が完了した第２単結晶層５の表面上にＴＥＯＳ酸化膜（Tetra Ethyl Ortho Silicate酸化膜）を形成し、平坦化した後にＳｉ基板３２と接合することができる。接合はプラズマ活性化等により可能である。 (Second joining process)
The second bonding step is a step of bonding the third substrate 3 to the surface of the multilayer substrate 6 on which the semiconductor element 7 is formed in the element forming step on the second single crystal layer 5 side. The bonding method of the third substrate 3 is not particularly limited, and for example, the third substrate 3 and the surface of the second single crystal layer 5 on which the semiconductor element 7 is formed are connected through an appropriately selected adhesive layer 34 or the like. (See FIGS. 6 and 8).
As the third substrate 3, a substrate (31) made of an insulating material such as non-alkali glass or sapphire can be used. Further, as the third substrate 3, a substrate using a semiconductor material such as a Si substrate (32) can also be used. In the case of using a non-semiconductor material such as alkali-free glass or sapphire, for example, an adhesive layer 34 coated with a photocurable adhesive is provided on the surface of the second single crystal layer 5 in which the element forming process has been completed, and on that, The third substrate 31 can be bonded and bonded by ultraviolet curing. In the case of using a Si substrate or the like, for example, a TEOS oxide film (Tetra Ethyl Ortho Silicate oxide film) is formed on the surface of the second single crystal layer 5 where the element formation process is completed, and after planarization, the Si substrate 32 and Can be joined. Bonding is possible by plasma activation or the like.
　第３の基板３として金属基板３３を用いる場合には、半導体素子７が形成された第２単結晶層５の表面に接合層３４、金属接合層３８を設け、その上に金属基板３３を接合することができる（図６（ｃ）、図８（ｃ）参照）。金属接合層３８は、Ｎｉ等の金属をスパッタで形成した上に厚膜のメッキ層を形成し、厚膜のメッキ層を平坦化した後に金属基板３３と金属間接合をしてもよい。金属基板３３を用いる場合には、下記開孔工程は不要である。 When the metal substrate 33 is used as the third substrate 3, the bonding layer 34 and the metal bonding layer 38 are provided on the surface of the second single crystal layer 5 on which the semiconductor element 7 is formed, and the metal substrate 33 is bonded thereon. (See FIG. 6C and FIG. 8C). The metal bonding layer 38 may be formed by sputtering a metal such as Ni, forming a thick plating layer, and flattening the thick plating layer and then bonding the metal substrate 33 to the metal. When the metal substrate 33 is used, the following opening process is not necessary.
　（開孔工程）
　前記第２接合工程の後、又は基板除去工程の後、第３の基板３に半導体素子７の電極部となる貫通孔を形成する開孔工程を備えることができる。開孔工程は、第２接合工程により複層基板６と第３の基板３（３１、３２）とを接合した後に、第３の基板３に貫通孔（３６、３７）を形成する工程である（図６、８参照）。第３の基板３が無アルカリガラス、サファイア等の場合には、フォトリソグラフィにより電極部として必要な部分に貫通孔を設けることができる。また、第３の基板３がＳｉ等の半導体材料の場合にも、フォトリソグラフィにより貫通孔を設けることができる。その場合、Ｓｉの面方位を１００面とし、エッチングをＫＯＨ液で行うことにより、５４度の角度を持つテーパを形成することができる。このテーパを利用し、後にＳｉ基板の表面に電極を形成すれば、半導体素子の電極をＳｉ基板表面に導くことが可能となる。この開孔工程は、複層基板６から第２の基板２を除去した後に行うようにすることもできる。 (Opening process)
After the second bonding step or after the substrate removing step, an opening step of forming a through hole that becomes an electrode portion of the semiconductor element 7 in the third substrate 3 can be provided. The opening step is a step of forming through holes (36, 37) in the third substrate 3 after bonding the multilayer substrate 6 and the third substrate 3 (31, 32) in the second bonding step. (See FIGS. 6 and 8). When the third substrate 3 is made of alkali-free glass, sapphire, or the like, a through hole can be provided in a necessary portion as an electrode portion by photolithography. Also, when the third substrate 3 is a semiconductor material such as Si, a through hole can be provided by photolithography. In that case, a taper having an angle of 54 degrees can be formed by setting the surface orientation of Si to 100 and etching with KOH liquid. If this taper is used to form an electrode on the surface of the Si substrate later, the electrode of the semiconductor element can be guided to the surface of the Si substrate. This opening step can also be performed after removing the second substrate 2 from the multilayer substrate 6.
　（基板除去工程）
　前記基板除去工程は、第３の基板３と接合された複層基板６から第２の基板（カーボン基板）２を除去する工程である（図９、１０参照）。具体的な基板の除去方法は特に問わない。例えば、カーボン基板２の下面２０２が多結晶ＳｉＣ膜４２により覆われている場合、先ず、複層基板６の周縁部（少なくともカーボン基板２の側面２０３側に形成されている第２多結晶層５１、シリコン酸化膜４１及び多結晶ＳｉＣ膜４２）を切断除去して、カーボン基板２の側面部２０３’を露出させる。その後、焼却等によりカーボン基板２を除去する。カーボンは、５００℃程度の高温とすることによって容易に焼却することができる。カーボン基板２を除去した後、残存する表面薄膜層（シリコン酸化膜）４１は、酸により又はドライエッチング等により、除去することができる。 (Substrate removal process)
The substrate removing step is a step of removing the second substrate (carbon substrate) 2 from the multilayer substrate 6 bonded to the third substrate 3 (see FIGS. 9 and 10). A specific method for removing the substrate is not particularly limited. For example, when the lower surface 202 of the carbon substrate 2 is covered with the polycrystalline SiC film 42, first, the peripheral portion of the multilayer substrate 6 (at least the second polycrystalline layer 51 formed on the side surface 203 side of the carbon substrate 2). Then, the silicon oxide film 41 and the polycrystalline SiC film 42) are cut and removed to expose the side surface portion 203 ′ of the carbon substrate 2. Thereafter, the carbon substrate 2 is removed by incineration or the like. Carbon can be easily incinerated by raising the temperature to about 500 ° C. After the carbon substrate 2 is removed, the remaining surface thin film layer (silicon oxide film) 41 can be removed by acid or dry etching.
　基板除去工程においては、第２の基板２がサファイア基板又はＳｉＣ基板２５であり、表面薄膜層がＧａＮ膜４１３である場合には、第２の基板２側からレーザ光を照射することによりＧａＮ膜４１３からＧａを析出させ、第２の基板２を容易に除去することができる。除去された第２の基板２は、表面薄膜層をエッチング等により除去した後に第２の基板２として再利用が可能である。
　また、基板除去工程においては、第２の基板２（カーボン基板、ＳｉＣ基板等）の除去後に残存する表面薄膜層４を除去し、更に第１単結晶層１１を除去してもよい。
　また、第２単結晶層５を成膜する前に単結晶バッファ層５２が形成されている場合（図２（ｄ）参照）には、第２の基板２及び表面薄膜層４１が除去されると、半導体素子７の裏面側には第１単結晶層１１が露出する。この場合、第１単結晶層１１と単結晶バッファ層５２を除去してもよい。具体的な除去方法は特に問わず、例えばＣＭＰ等研磨により除去することができる。 In the substrate removal step, when the second substrate 2 is a sapphire substrate or a SiC substrate 25 and the surface thin film layer is a GaN film 413, the GaN film is irradiated by irradiating laser light from the second substrate 2 side. Ga can be deposited from 413 and the second substrate 2 can be easily removed. The removed second substrate 2 can be reused as the second substrate 2 after the surface thin film layer is removed by etching or the like.
In the substrate removal step, the surface thin film layer 4 remaining after the removal of the second substrate 2 (carbon substrate, SiC substrate, etc.) may be removed, and the first single crystal layer 11 may be further removed.
When the single crystal buffer layer 52 is formed before the second single crystal layer 5 is formed (see FIG. 2D), the second substrate 2 and the surface thin film layer 41 are removed. Then, the first single crystal layer 11 is exposed on the back side of the semiconductor element 7. In this case, the first single crystal layer 11 and the single crystal buffer layer 52 may be removed. The specific removal method is not particularly limited, and can be removed by polishing such as CMP.
　（裏面電極形成工程）
　裏面電極形成工程は、半導体素子７の裏面、即ち第２の基板２及び表面薄膜層４１が除去された面に、裏面電極層８（８１、８２）を形成する工程である（図９参照）。基板除去工程により第２の基板２及び表面薄膜層４１が除去されると、半導体素子７の裏面側には第１単結晶層１１が露出することとなる。裏面電極形成工程においては、この半導体素子７の裏面にＮｉ等のシリサイド用金属薄膜を形成し、その後、高温で第１単結晶層１１とＮｉ等の金属との界面にシリサイド化処理を行うことにより、シリサイド層８１を形成することができる。シリサイド化処理は、レーザアニールのように表層だけを高温度にする手法を用いることが望ましい。その上で銅メッキや銀メッキにより金属層８２を形成することが可能である。シリサイド層８１の形成や金属層８２の形成は、基板に反りが生じていても可能である。なお、第２の基板２の表面薄膜層にバッファ層４１２を設けた場合（図２（ｂ）参照）、基板除去工程により第２の基板２及び表面薄膜層４１が除去されると、半導体素子７の裏面側にはバッファ層４１２が露出することとなる。この場合の裏面電極層８の形成については後述する。 (Back electrode forming process)
The back electrode forming step is a step of forming the back electrode layer 8 (81, 82) on the back surface of the semiconductor element 7, that is, the surface from which the second substrate 2 and the surface thin film layer 41 are removed (see FIG. 9). . When the second substrate 2 and the surface thin film layer 41 are removed by the substrate removing step, the first single crystal layer 11 is exposed on the back surface side of the semiconductor element 7. In the back surface electrode forming step, a metal thin film for silicide such as Ni is formed on the back surface of the semiconductor element 7 and then silicidation is performed at the interface between the first single crystal layer 11 and the metal such as Ni at a high temperature. Thus, the silicide layer 81 can be formed. For the silicidation treatment, it is desirable to use a technique in which only the surface layer is brought to a high temperature, such as laser annealing. Then, the metal layer 82 can be formed by copper plating or silver plating. The silicide layer 81 and the metal layer 82 can be formed even if the substrate is warped. When the buffer layer 412 is provided on the surface thin film layer of the second substrate 2 (see FIG. 2B), when the second substrate 2 and the surface thin film layer 41 are removed by the substrate removal step, the semiconductor element 7, the buffer layer 412 is exposed. The formation of the back electrode layer 8 in this case will be described later.
　シリサイド化処理は、素子形成工程の前に行うようにすることも可能である（前記シリサイド層形成工程）。即ち、第２の基板２と接合する前に、第１の基板１の一方の表面１０１上に極薄のＮｉ薄膜を形成する。そして熱処理をして第１の基板１の一方の表面１０１にシリサイド層を形成し、その後Ｎｉ薄膜層を除去する。その後、表面がシリサイド化された第１の基板１の一方の表面１０１と第２の基板２とが接合される。その後の工程を経て、第３の基板３の接合後に第２の基板２及び表面薄膜層４１が除去された状態で、第１の基板１の一方の表面１０１のシリサイド層が露出する。露出したシリサイド層上に、裏面電極形成工程において銅メッキや銀メッキにより金属層８２を成膜することができる。 The silicidation process may be performed before the element formation process (silicide layer formation process). That is, an ultrathin Ni thin film is formed on one surface 101 of the first substrate 1 before bonding to the second substrate 2. Then, heat treatment is performed to form a silicide layer on one surface 101 of the first substrate 1, and then the Ni thin film layer is removed. Thereafter, one surface 101 of the first substrate 1 whose surface is silicided and the second substrate 2 are bonded. Through the subsequent steps, the silicide layer on one surface 101 of the first substrate 1 is exposed in a state where the second substrate 2 and the surface thin film layer 41 are removed after the bonding of the third substrate 3. A metal layer 82 can be formed on the exposed silicide layer by copper plating or silver plating in the back electrode forming step.
　前記基板除去工程において、第１単結晶層１１及び単結晶バッファ層５２が除去されている場合には、裏面電極層８は、単結晶バッファ層５２が除去されて露出した第２単結晶層５の面に形成される。 In the substrate removing step, when the first single crystal layer 11 and the single crystal buffer layer 52 are removed, the back electrode layer 8 includes the second single crystal layer 5 exposed by removing the single crystal buffer layer 52. Formed on the surface.
　以下、本実施形態に係る半導体素子の製造工程を具体的に説明する。本例では第２の基板として厚さ約０．５ｍｍのカーボン基板２を使用し、その熱膨張係数は多結晶ＳｉＣの熱膨張係数と同程度となるように合わせてある。カーボンは、その密度、焼成温度を調整することにより熱膨張係数を調整することが可能である。また、カーボン基板２は、不純物となる金属の密度が１０１０／ｃｍ３以下と少なく、純度の高い素材である。また、本例において第１の基板は単結晶ＳｉＣ基板１とする。 Hereinafter, the manufacturing process of the semiconductor device according to this embodiment will be described in detail. In this example, a carbon substrate 2 having a thickness of about 0.5 mm is used as the second substrate, and the thermal expansion coefficient thereof is adjusted to be approximately the same as that of polycrystalline SiC. The coefficient of thermal expansion of carbon can be adjusted by adjusting the density and firing temperature. The carbon substrate 2 is a high-purity material with a metal density as an impurity being as low as 10 10 / cm 3 or less. In this example, the first substrate is a single crystal SiC substrate 1.
（複層基板６の製造工程）
　図４は、図２で示した複層基板６の製造工程を示している。第１の基板１は単結晶ＳｉＣからなり、第２単結晶層５もＳｉＣからなる。
　図４（ａ）は、シリコン酸化膜４１がカーボン基板２の上面２０１及び側面２０３に形成され、多結晶ＳｉＣ膜４２がカーボン基板２の下面２０２及び側面２０３側に形成されている基板６１を表している。同図（ｂ）は、単結晶ＳｉＣ基板１の下面１０１から０．５μｍの深さに水素イオンを注入することによって水素注入層１５が形成された状態を表している。水素イオンの量は、１×１０１７／ｃｍ２程度であり、水素注入層１５の水素密度は１×１０２２／ｃｍ３程度の高濃度となる。水素注入層１５から平面１０１側が、単結晶ＳｉＣからなる第１単結晶層１１になる。
　同図（ｃ）は、上記基板６１と上記単結晶ＳｉＣ基板１とを接合した状態を表している。カーボン基板２の表面に形成されたシリコン酸化膜４１の表面と単結晶ＳｉＣ基板１の平面１０１とを、両表面を活性化した後に接合する。
　同図（ｄ）は、上記接合された基板を約１０００℃の高温にすることにより、単結晶ＳｉＣ基板１が水素注入層１５を境界として分離された状態を表している（分離された単結晶ＳｉＣ基板１の母材側は図示せず）。カーボン基板２に形成されたシリコン酸化膜４１の表面上に第１単結晶層１１が積層されて、基板６２が構成されている。
　同図（ｅ）に示す複層基板６は、上記基板６２の第１単結晶層１１の表面上に単結晶ＳｉＣをエピタキシャル成長させることによって、第２単結晶層５が形成されている。第２単結晶層５の成膜と同時に、第１単結晶層１１が存在しないシリコン酸化膜４１上の周縁部やカーボン基板２の側面側（多結晶ＳｉＣ膜４２上）には多結晶が成長し、第２単結晶層５と同じ厚さの第２多結晶層５１が成膜される。複層基板６において、第２単結晶層５の厚さはその材料及び用途により異なり、ＳｉＣの場合には概ね５μｍ（耐圧６００Ｖの場合）から１０μｍ（耐圧１５００Ｖの場合）の程度である。
　同図（ｄ）に示した基板６２を形成した後、第２単結晶５をエピタキシャル成長させる前に、単結晶バッファ層５２が形成されてもよい（図２（ｄ）参照）。 (Manufacturing process of multilayer substrate 6)
FIG. 4 shows a manufacturing process of the multilayer substrate 6 shown in FIG. The first substrate 1 is made of single crystal SiC, and the second single crystal layer 5 is also made of SiC.
FIG. 4A shows the substrate 61 in which the silicon oxide film 41 is formed on the upper surface 201 and the side surface 203 of the carbon substrate 2 and the polycrystalline SiC film 42 is formed on the lower surface 202 and the side surface 203 side of the carbon substrate 2. ing. FIG. 2B shows a state in which the hydrogen implantation layer 15 is formed by implanting hydrogen ions from the lower surface 101 of the single crystal SiC substrate 1 to a depth of 0.5 μm. The amount of hydrogen ions is about 1 × 10 17 / cm 2 , and the hydrogen density of the hydrogen injection layer 15 is a high concentration of about 1 × 10 22 / cm 3 . The plane 101 side from the hydrogen injection layer 15 becomes the first single crystal layer 11 made of single crystal SiC.
FIG. 2C shows a state where the substrate 61 and the single crystal SiC substrate 1 are bonded. The surface of the silicon oxide film 41 formed on the surface of the carbon substrate 2 and the flat surface 101 of the single crystal SiC substrate 1 are joined after activating both surfaces.
FIG. 4D shows a state in which the single-crystal SiC substrate 1 is separated with the hydrogen injection layer 15 as a boundary by bringing the bonded substrates to a high temperature of about 1000 ° C. (separated single crystals The base material side of the SiC substrate 1 is not shown). The first single crystal layer 11 is laminated on the surface of the silicon oxide film 41 formed on the carbon substrate 2 to form a substrate 62.
In the multilayer substrate 6 shown in FIG. 5E, the second single crystal layer 5 is formed by epitaxially growing single crystal SiC on the surface of the first single crystal layer 11 of the substrate 62. Simultaneously with the formation of the second single crystal layer 5, a polycrystal grows on the peripheral portion on the silicon oxide film 41 where the first single crystal layer 11 does not exist and on the side surface side (on the polycrystalline SiC film 42) of the carbon substrate 2. Then, the second polycrystalline layer 51 having the same thickness as the second single crystal layer 5 is formed. In the multilayer substrate 6, the thickness of the second single crystal layer 5 varies depending on the material and application, and in the case of SiC, is approximately 5 μm (withstand voltage of 600 V) to 10 μm (withstand voltage of 1500 V).
A single crystal buffer layer 52 may be formed after the substrate 62 shown in FIG. 6D is formed and before the second single crystal 5 is epitaxially grown (see FIG. 2D).
　（半導体素子の形成工程）
　複層基板６に成膜された第２単結晶層５には、図５及び７に示すように、目的とする半導体素子７を形成することができる。
　図５は、第２単結晶層５に半導体素子７としてショットキーダイオード７１を形成した例を示している。同図（ａ）は、複層基板６に形成された１つの素子部（Ａ部）のみを示しており、同図（ｂ）はその１つの素子部を拡大して描いた図である。
　また、図７は、第２単結晶層５に半導体素子７としてＭＯＳＦＥＴ７５を形成した例を示している。同図（ａ）は、複層基板６に形成された１つの素子部（Ａ部）のみを示しており、同図（ｂ）はその１つの素子部を拡大して描いた図である。
　なお、図５及び７では素子部の詳細構造は省略している。 (Semiconductor element formation process)
A target semiconductor element 7 can be formed on the second single crystal layer 5 formed on the multilayer substrate 6 as shown in FIGS.
FIG. 5 shows an example in which a Schottky diode 71 is formed as the semiconductor element 7 in the second single crystal layer 5. FIG. 4A shows only one element portion (A portion) formed on the multilayer substrate 6, and FIG. 5B is an enlarged view of the one element portion.
FIG. 7 shows an example in which a MOSFET 75 is formed as the semiconductor element 7 in the second single crystal layer 5. FIG. 4A shows only one element portion (A portion) formed on the multilayer substrate 6, and FIG. 5B is an enlarged view of the one element portion.
5 and 7, the detailed structure of the element portion is omitted.
　図５(ａ)、（ｂ）は、第２の基板としてカーボン基板２を使用し、表面薄膜層４１、４２が形成されている例を表している。図５(ｃ)は、第２の基板としてＳｉＣ基板２５を使用し、表面薄膜層をＧａＮ膜４１３としてショットキーダイオード７１を形成した例を示している。
　図７(ａ)、（ｂ）は、第２の基板としてカーボン基板２を使用し、表面薄膜層４１、４２が形成されている例を表している。図７(ｃ)は、第２の基板としてＳｉＣ基板２５を使用し、表面薄膜層をＧａＮ膜４１３としてＭＯＳＦＥＴ７５を形成した例を示している。図示されている貫通電極８５については後述する。 FIGS. 5A and 5B show examples in which the carbon substrate 2 is used as the second substrate and the surface thin film layers 41 and 42 are formed. FIG. 5C shows an example in which the SiC substrate 25 is used as the second substrate, and the Schottky diode 71 is formed with the surface thin film layer as the GaN film 413.
FIGS. 7A and 7B show an example in which the carbon substrate 2 is used as the second substrate and the surface thin film layers 41 and 42 are formed. FIG. 7C shows an example in which the SiC substrate 25 is used as the second substrate, and the MOSFET 75 is formed with the surface thin film layer as the GaN film 413. The illustrated through electrode 85 will be described later.
　（第３の基板の接合工程）
　半導体素子７の形成後、第２接合工程において、複層基板６の第２単結晶層５側の表面に、半導体素子７の恒久的な支持基板となる第３の基板３が接合される。第３の基板３の材料として、無アルカリガラスやサファイア等の絶縁材料、Ｓｉ等の半導体材料を用いることができる。この第３の基板３の接合後、第３の基板３に半導体素子７の電極部を形成するための貫通孔を形成する開孔工程を行うことができる。
　図６は、第３の基板３として無アルカリガラス基板３１を用いる場合の第２接合工程と開孔工程を示している。同図（ａ）は、Ａ部にショットキーダイオード７１を形成した複層基板６（図５参照）の第２単結晶層５側の表面に、接合層として光硬化型接着層３４をコートし、その接合層を介して無アルカリガラス基板３１を接着した状態を示す。光硬化型接着層３４は、紫外光の照射により硬化がなされる。
　同図（ｂ）は、無アルカリガラス基板３１に半導体素子の電極部を形成するための貫通孔３６を設けた状態を表している。貫通孔３６は、フォトリソグラフィにより形成することができる。半導体素子の実装時に、この貫通孔３６を通して、ワイアボンディング等によりショットキーダイオード７１の表面電極を外部のパッケージに電気的に接続することができる。 (Third substrate bonding step)
After the formation of the semiconductor element 7, in the second bonding step, the third substrate 3 serving as a permanent support substrate for the semiconductor element 7 is bonded to the surface of the multilayer substrate 6 on the second single crystal layer 5 side. As the material of the third substrate 3, an insulating material such as alkali-free glass or sapphire, or a semiconductor material such as Si can be used. After the bonding of the third substrate 3, an opening process for forming a through hole for forming the electrode portion of the semiconductor element 7 in the third substrate 3 can be performed.
FIG. 6 shows a second bonding step and an opening step in the case where an alkali-free glass substrate 31 is used as the third substrate 3. In FIG. 5A, a photo-curing adhesive layer 34 is coated as a bonding layer on the surface of the multilayer substrate 6 (see FIG. 5) on the second single crystal layer 5 side where a Schottky diode 71 is formed in the A part. The state which adhere | attached the alkali free glass substrate 31 through the joining layer is shown. The photocurable adhesive layer 34 is cured by irradiation with ultraviolet light.
FIG. 2B shows a state in which a through-hole 36 for forming an electrode portion of a semiconductor element is provided in the alkali-free glass substrate 31. The through hole 36 can be formed by photolithography. When the semiconductor element is mounted, the surface electrode of the Schottky diode 71 can be electrically connected to an external package through the through hole 36 by wire bonding or the like.
　また、図６（ｃ）に示すように、第３の基板３として金属基板３３を用いることができる。本図は、第２の基板としてＳｉＣ基板２５（又はサファイア基板）を使用し、表面薄膜層をＧａＮ膜４１３とした例を示しているが、カーボン基板２を使用し、表面薄膜層４１、４２が形成されていてもよい。ショットキーダイオード７１の素子表面をシリコン酸化膜により保護し、フォトリソグラフィによりアノ－ド電極部を開孔して、全面にニッケル薄膜を形成し、必要に応じてメッキで増膜して金属接合層３８を形成する。その金属接合層３８に金属基板３３を直接接合することにより、金属基板３３を外部接続用のアノ－ド電極とすることができる。 Further, as shown in FIG. 6C, a metal substrate 33 can be used as the third substrate 3. This figure shows an example in which the SiC substrate 25 (or sapphire substrate) is used as the second substrate and the surface thin film layer is the GaN film 413, but the carbon substrate 2 is used and the surface thin film layers 41, 42 are used. May be formed. The element surface of the Schottky diode 71 is protected by a silicon oxide film, the anode electrode part is opened by photolithography, a nickel thin film is formed on the entire surface, and if necessary, the film is increased by plating to form a metal bonding layer 38 is formed. By directly bonding the metal substrate 33 to the metal bonding layer 38, the metal substrate 33 can be used as an anode electrode for external connection.
　図８は、第３の基板３としてＳｉ基板３２を用いる場合の第２接合工程と開孔工程を示している。同図（ａ）は、Ａ部にＭＯＳＦＥＴ７５を形成した複層基板６（図７参照）の第２単結晶層５側の表面に、接合層としてＴＥＯＳ酸化膜３５を成膜し、その上にＳｉ基板３２を接合した状態を示す。ＴＥＯＳ酸化膜３５とＳｉ基板３２とは、接合する両面を平坦化し、プラズマ照射により活性化した後に接合することができる。
　同図（ｂ）は、Ｓｉ基板３２に半導体素子の電極部を形成するための貫通孔３７を設けた状態を表している。貫通孔３７は、フォトリソグラフィにより形成することができる。本例においては、貫通孔３７は５４度のテーパ角をつけて形成されている。面方位（１００）のＳｉ基板３２を用いてテーパエッチングすることにより、貫通孔３７の壁面は５４度の傾斜角でなだらかな斜面とすることができる。この斜面にアルミ配線を形成することにより、Ｓｉ基板３２の表面に電極を形成することが可能である。また、Ｓｉ基板３２の上面にヒートシンクを設けることも可能である。 FIG. 8 shows a second bonding step and an opening step when the Si substrate 32 is used as the third substrate 3. In FIG. 6A, a TEOS oxide film 35 is formed as a bonding layer on the surface of the second single crystal layer 5 side of the multilayer substrate 6 (see FIG. 7) in which the MOSFET 75 is formed in the A part, and the TEOS oxide film 35 is formed thereon. The state which joined Si substrate 32 is shown. The TEOS oxide film 35 and the Si substrate 32 can be bonded after the surfaces to be bonded are planarized and activated by plasma irradiation.
FIG. 4B shows a state in which a through hole 37 for forming an electrode portion of a semiconductor element is provided in the Si substrate 32. The through hole 37 can be formed by photolithography. In this example, the through hole 37 is formed with a taper angle of 54 degrees. By taper-etching using the Si substrate 32 with the plane orientation (100), the wall surface of the through-hole 37 can be a gentle slope with an inclination angle of 54 degrees. By forming aluminum wiring on this slope, an electrode can be formed on the surface of the Si substrate 32. It is also possible to provide a heat sink on the upper surface of the Si substrate 32.
　また、図８（ｃ）に示すように、第３の基板３として金属基板３３を用いることができる。本図は、第２の基板としてＳｉＣ基板（又はサファイア基板）２５を使用し、表面薄膜層をＧａＮ膜４１３とした例を示しているが、図８(ａ)、（ｂ）に表されているように、カーボン基板２を使用し、表面薄膜層４１、４２が形成されていてもよい。ＭＯＳＦＥＴ７５の素子表面上に必要な電気配線を行う相互配線層３６が形成されている。相互配線層３６は接合層３４を兼ねている。相互配線層３６の表面にはＭＯＳＦＥＴ７５のソースと電気的に接続された金属接合層３８が形成されている。この金属接合層３８に金属基板３３を直接接合することにより、金属基板３３を外部接続用のソース電極とすることができる。 Further, as shown in FIG. 8C, a metal substrate 33 can be used as the third substrate 3. This figure shows an example in which a SiC substrate (or sapphire substrate) 25 is used as the second substrate, and the surface thin film layer is a GaN film 413. This is shown in FIGS. 8 (a) and 8 (b). As shown, the surface thin film layers 41 and 42 may be formed using the carbon substrate 2. An interconnection layer 36 for performing necessary electrical wiring is formed on the element surface of the MOSFET 75. The interconnect layer 36 also serves as the bonding layer 34. A metal junction layer 38 electrically connected to the source of the MOSFET 75 is formed on the surface of the interconnect layer 36. By directly bonding the metal substrate 33 to the metal bonding layer 38, the metal substrate 33 can be used as a source electrode for external connection.
　（裏面電極の形成）
　図９は、複層基板６に半導体素子７を形成し、第３の基板３を接合した後に、半導体素子７の裏面電極となる裏面電極層８（８１、８２）を形成する工程を示している。図９（ａ）は、図６（ｂ）と同じ図であり、Ａ部は１つの半導体素子に当たる部分を示す。図９（ａ）において、上面視で円形の単結晶層１１及び５の外周を境界ｚ１－ｚ１’及びｚ２－ｚ２’で表わしており、この境界に沿ってサークルカットをすることによって、境界を超える基板の外周部を除去する。図９（ｂ）は、上記境界に沿ってサークルカットすることにより外周部を除去した状態を示す。この状態で、切断されたカーボン基板２の側面２０３’が露出する。カーボン基板２を酸素雰囲気中で焼却により除去し、シリコン酸化膜４１をエッチングにより除去すれば、第１単結晶層（単結晶ＳｉＣ層）１１の裏面が露出する。そこで、同図（ｃ）に示すように、単結晶ＳｉＣ層１１の露出した面にＮｉを極薄に成膜し、レーザアニールによりＮｉと単結晶ＳｉＣ層との界面をシリサイド化することによってシリサイド層８１を形成する。そして、シリサイド層８１上にメッキにより裏面電極となる金属層８２を成膜することができる。また、予め第２の基板２側の第１単結晶層１１の表面にシリサイド層８１が形成されている場合には、直接メッキにより裏面電極となる金属層８２を成膜することができる。 (Formation of back electrode)
FIG. 9 shows a process of forming the back electrode layer 8 (81, 82) to be the back electrode of the semiconductor element 7 after forming the semiconductor element 7 on the multilayer substrate 6 and bonding the third substrate 3. Yes. FIG. 9A is the same view as FIG. 6B, and the portion A shows a portion corresponding to one semiconductor element. In FIG. 9A, the outer peripheries of the circular single crystal layers 11 and 5 in a top view are represented by boundaries z1-z1 ′ and z2-z2 ′, and the boundary is defined by performing a circle cut along these boundaries. Remove excess substrate periphery. FIG. 9B shows a state in which the outer peripheral portion has been removed by performing a circle cut along the boundary. In this state, the side surface 203 ′ of the cut carbon substrate 2 is exposed. If the carbon substrate 2 is removed by incineration in an oxygen atmosphere and the silicon oxide film 41 is removed by etching, the back surface of the first single crystal layer (single crystal SiC layer) 11 is exposed. Therefore, as shown in FIG. 3C, Ni is deposited on the exposed surface of the single crystal SiC layer 11 in an extremely thin manner, and silicide is formed by siliciding the interface between Ni and the single crystal SiC layer by laser annealing. Layer 81 is formed. Then, a metal layer 82 to be a back electrode can be formed on the silicide layer 81 by plating. In addition, when the silicide layer 81 is formed in advance on the surface of the first single crystal layer 11 on the second substrate 2 side, the metal layer 82 serving as the back electrode can be formed by direct plating.
　図１０は、図２（ｂ）に示した複層基板６（６ｂ）から第２の基板２及び表面薄膜層の第１層４１を除去し、バッファ層４１２上に裏面電極層８（８１，８２）を形成する工程を示す。本例においては、カーボン２の上面に表面薄膜層としてシリコン酸化膜４１及びＳｉＣからなるバッファ層４１２が形成されている。図１０（ａ）は、複層基板６（６ｂ）に半導体素子７を形成し、第３の基板３を接合した後に、前図同様に外周を境界ｚ１－ｚ１’及びｚ２－ｚ２’に沿ってサークルカットをすることによって、境界を超える基板の外周部を除去した状態を示している。Ａ部は１つの半導体素子に当たる部分である。この状態で、切断されたカーボン基板２の側面２０３’が露出する。そして、カーボン基板２を酸素雰囲気中で焼却により除去し、シリコン酸化膜４１をエッチングにより除去すれば、ＳｉＣ多結晶からなるバッファ層４１２が露出する。そこで、同図（ｂ）に示すように、露出したバッファ層４１２上にＮｉを極薄に成膜し、レーザアニールによりＮｉと単結晶ＳｉＣ層１１との間をシリサイド化することによってシリサイド層８１を形成する。そして、シリサイド層８１の上にメッキにより裏面電極となる金属層８２を成膜することができる。表面薄膜層として形成したＳｉＣ多結晶からなるバッファ層４１２は、レーザアニールで電極界面が高温度になる場合に、半導体素子７のアルミ電極への熱的なバッファ層となる。 10 removes the second substrate 2 and the first layer 41 of the surface thin film layer from the multilayer substrate 6 (6b) shown in FIG. 2B, and forms the back electrode layer 8 (81, 81) on the buffer layer 412. 82). In this example, a silicon oxide film 41 and a buffer layer 412 made of SiC are formed as a surface thin film layer on the upper surface of the carbon 2. FIG. 10A shows the semiconductor element 7 formed on the multilayer substrate 6 (6b), the third substrate 3 is bonded, and the outer periphery along the boundaries z1-z1 ′ and z2-z2 ′ as in the previous figure. This shows a state in which the outer peripheral portion of the substrate beyond the boundary is removed by circle cutting. A part corresponds to one semiconductor element. In this state, the side surface 203 'of the cut carbon substrate 2 is exposed. Then, if the carbon substrate 2 is removed by incineration in an oxygen atmosphere and the silicon oxide film 41 is removed by etching, the buffer layer 412 made of SiC polycrystal is exposed. Therefore, as shown in FIG. 6B, Ni is deposited on the exposed buffer layer 412 to be extremely thin, and the silicide layer 81 is formed by siliciding between the Ni and the single crystal SiC layer 11 by laser annealing. Form. Then, a metal layer 82 to be a back electrode can be formed on the silicide layer 81 by plating. The buffer layer 412 made of SiC polycrystal formed as the surface thin film layer becomes a thermal buffer layer to the aluminum electrode of the semiconductor element 7 when the electrode interface becomes high temperature by laser annealing.
　以上において、単結晶ＳｉＣ層１１上に単結晶バッファ層５２が形成されている場合には、それらを除去した後に露出する第２単結晶層５の面にＮｉを極薄に成膜し、Ｎｉと第２単結晶層５との界面をシリサイド化することによってシリサイド層８１を形成することができる。
　以上のように、複層基板６の構成（図２（ａ）～（e））に関わらず、シリサイド層８１及び裏面電極となる金属層８２を形成することができる。また、第３の基板３として金属基板３３を使用する場合（例えば図６（ｃ）参照）も、同様にシリサイド層８１及び裏面電極となる金属層８２を形成することができる。シリサイド化する単結晶ＳｉＣ層１１の表面には、その直前に高窒素濃度とするためのイオン注入をしてもよい。または、予め表層に極く薄い高窒素濃度層を設けておいてもよい。例えば、接合工程において第２の基板２と接合する前に、第１の基板１の下面１０１に極く薄い高窒素濃度層を形成しておくことができる。 In the above, in the case where the single crystal buffer layer 52 is formed on the single crystal SiC layer 11, Ni is deposited on the surface of the second single crystal layer 5 exposed after removing them, and Ni The silicide layer 81 can be formed by siliciding the interface between the first single crystal layer 5 and the second single crystal layer 5.
As described above, regardless of the configuration of the multilayer substrate 6 (FIGS. 2A to 2E), the silicide layer 81 and the metal layer 82 serving as the back electrode can be formed. Further, when the metal substrate 33 is used as the third substrate 3 (see, for example, FIG. 6C), the silicide layer 81 and the metal layer 82 to be the back electrode can be formed in the same manner. The surface of the single-crystal SiC layer 11 to be silicided may be ion-implanted immediately before it to obtain a high nitrogen concentration. Alternatively, a very thin high nitrogen concentration layer may be provided in advance on the surface layer. For example, an extremely thin high nitrogen concentration layer can be formed on the lower surface 101 of the first substrate 1 before being bonded to the second substrate 2 in the bonding step.
　高電力用途の縦型素子を形成するための半導体基板においては、縦方向の電気伝導性と熱伝導性が重要である。本実施形態において、半導体基板としての電気伝導性については、第１単結晶層１１と裏面電極となる金属層８２との間の抵抗が重要になるが、この抵抗はシリサイド化により解消されている。また、支持層の電気抵抗は、カーボン基板２が除去されているので、実質的には極小化されている。熱伝導性についても同様であり、カーボン基板２が除去されて金属層８２だけとされているため、熱伝導を妨げない。 In a semiconductor substrate for forming a vertical element for high power use, vertical electrical conductivity and thermal conductivity are important. In the present embodiment, for electrical conductivity as a semiconductor substrate, the resistance between the first single crystal layer 11 and the metal layer 82 serving as the back electrode is important, but this resistance is eliminated by silicidation. . Moreover, since the carbon substrate 2 is removed, the electric resistance of the support layer is substantially minimized. The same applies to thermal conductivity, and the carbon substrate 2 is removed to form only the metal layer 82, so that thermal conduction is not hindered.
　（ショットキーダイオード素子の形成）
　図１１は、複層基板６の表層に形成されている第２単結晶層５にショットキーダイオード素子７１を形成する工程を示している。第１の基板１は単結晶ＳｉＣである。図１１（ａ）は、図２に示した複層基板６を簡略化して表しており、第１単結晶層１１及び多結晶ＳｉＣ層５１は図示していない。図中のＡ部は、複層基板６において１つの半導体素子に相当する領域である。以下の図（ｂ）～（ｇ）においては、そのＡ部を拡大して図示しており、１つの素子の形成工程を表している。
　先ず、図（ｂ）に示すように、Ｎ型とした第２単結晶層５の表面にＳｉＯ２膜を形成し、フォトリソグラフィにより必要な部分を開口させてマスク７０１を形成する。そして、約５００℃に加熱をした状態でマスク７０１の開口部にＰ型不純物をイオン注入し、その後マスク７０１を除去する。これにより、同図（ｃ）に示すように、第２単結晶層５の表層部にＰ型不純物領域７１１が形成される。
　次に、同図（ｄ）に示すように、第２単結晶層５の表面にＳｉＯ２膜を形成し、フォトリソグラフィにより必要な部分を開口させてマスク７０２を形成する。そして、約５００℃に加熱をした状態でマスク７０２の開口部に別の濃度のＰ型不純物をイオン注入し、その後マスク７０２を除去する。これにより、同図（ｅ）に示すように、第２単結晶層５の表層部に別のＰ型不純物領域７１２が形成される。Ｐ型不純物領域７１１及び別のＰ型不純物領域７１２が形成された後、これらの不純物の活性化のために高温にてアニール処理がされる。第２単結晶層５がＳｉＣである場合には、約１７００℃にてアニール処理がされる。
　その後、熱ＣＶＤにより第２単結晶層５の表面上に厚さ１μｍ程度のＳｉＯ２膜を形成し、電極となる部分をエッチングにより除去して開口させる。これにより、同図（ｆ）に示すように、第２単結晶層５上にＳｉＯ２の層間絶縁膜７１３が形成される。
　そして、同図（ｇ）に示すように、ニッケルなどの金属を蒸着した後、パターニングすることによって電極膜７１４を形成する。この状態でランプアニール等により瞬間的に１０００℃を越える高温とすることによって、ショットキー界面が形成される。電極膜７１４は、更にアルミニウム等を用いて増膜することも可能である。以上の工程によって、ショットキーダイオード７１の主要部を形成した複層基板が得られる。
　引き続き、第３の基板を接合した後、図９に示した例と同様にして、カーボン基板２及びシリコン酸化膜４１を除去することによって露出される第１単結晶層１１の面に、裏面電極層８を形成することによって、縦型構造のショットキーダイオード７１を形成することができる。 (Formation of Schottky diode element)
FIG. 11 shows a process of forming the Schottky diode element 71 on the second single crystal layer 5 formed on the surface layer of the multilayer substrate 6. The first substrate 1 is single crystal SiC. FIG. 11A shows the multilayer substrate 6 shown in FIG. 2 in a simplified manner, and the first single crystal layer 11 and the polycrystalline SiC layer 51 are not shown. A portion in the figure is a region corresponding to one semiconductor element in the multilayer substrate 6. In the following drawings (b) to (g), the A portion is shown in an enlarged manner, and represents a process of forming one element.
First, as shown in FIG. 2B, an SiO 2 film is formed on the surface of the N-type second single crystal layer 5, and a mask 701 is formed by opening necessary portions by photolithography. Then, P-type impurities are ion-implanted into the opening of the mask 701 while being heated to about 500 ° C., and then the mask 701 is removed. As a result, a P-type impurity region 711 is formed in the surface layer portion of the second single crystal layer 5 as shown in FIG.
Next, as shown in FIG. 4D, a SiO 2 film is formed on the surface of the second single crystal layer 5, and a mask 702 is formed by opening necessary portions by photolithography. Then, another concentration of P-type impurity is ion-implanted into the opening of the mask 702 while being heated to about 500 ° C., and then the mask 702 is removed. As a result, another P-type impurity region 712 is formed in the surface layer portion of the second single crystal layer 5 as shown in FIG. After the P-type impurity region 711 and another P-type impurity region 712 are formed, annealing treatment is performed at a high temperature to activate these impurities. When the second single crystal layer 5 is SiC, annealing is performed at about 1700 ° C.
Thereafter, a SiO 2 film having a thickness of about 1 μm is formed on the surface of the second single crystal layer 5 by thermal CVD, and a portion to be an electrode is removed by etching and opened. As a result, an SiO 2 interlayer insulating film 713 is formed on the second single crystal layer 5 as shown in FIG.
And as shown in the figure (g), after depositing metals, such as nickel, the electrode film 714 is formed by patterning. In this state, a Schottky interface is formed by instantaneously raising the temperature to over 1000 ° C. by lamp annealing or the like. The electrode film 714 can be further increased using aluminum or the like. Through the above steps, a multilayer substrate on which the main part of the Schottky diode 71 is formed is obtained.
Subsequently, after bonding the third substrate, the back electrode is formed on the surface of the first single crystal layer 11 exposed by removing the carbon substrate 2 and the silicon oxide film 41 in the same manner as the example shown in FIG. By forming the layer 8, a Schottky diode 71 having a vertical structure can be formed.
　また、第３の基板３として金属基板３３を用いる場合には、図６（ｃ）に示したように、半導体素子７１が形成された第２単結晶層５の表面に接合層３４、金属接合層３８を設け、その上に金属基板３３を接合することができる。金属接合層３８は、Ｎｉ等の金属をスパッタで形成した上に厚膜のメッキ層を形成し、そのメッキ層の表面を平坦化して形成することができる。金属接合層３８と金属基板３３とは、金属間接合により直接に接合することができる。 Further, when the metal substrate 33 is used as the third substrate 3, as shown in FIG. 6C, the bonding layer 34 and the metal bonding are formed on the surface of the second single crystal layer 5 on which the semiconductor element 71 is formed. A layer 38 can be provided on which the metal substrate 33 can be bonded. The metal bonding layer 38 can be formed by forming a thick plating layer on a metal such as Ni by sputtering and planarizing the surface of the plating layer. The metal bonding layer 38 and the metal substrate 33 can be directly bonded by intermetal bonding.
　（ＭＯＳＦＥＴ素子の形成）
　図１２は、複層基板６の表層に形成されている第２単結晶層５にＭＯＳＦＥＴ素子７５を形成する工程を示している。第１の基板１は単結晶ＳｉＣである。図１２（ａ）は、図２に示した複層基板６を簡略化して表しており、第１単結晶層１１及び多結晶ＳｉＣ層５１は図示していない。図中のＡ部は、複層基板６において１つの半導体素子に相当する領域である。以下の図（ｂ）～（ｅ）においては、そのＡ部を拡大して図示しており、１つの素子の形成工程を表している。
　先ず、Ｎ型とした第２単結晶層５の表面にＳｉＯ２膜を形成し、フォトリソグラフィにより必要な部分を開口させてマスクを形成する。そして、約５００℃に加熱をした状態で前記マスクの開口部にＰ型不純物をイオン注入し、その後マスクを除去する。これにより、同図（ｂ）に示すように、第２単結晶層５の表層部にＰウェル７５１が形成される。続いて、同様にＳｉＯ２膜のパターンをマスクとして不純物を注入することにより、Ｎ＋領域を形成することができる。これによって、ソース部、ドレイン部等が形成される。同図（ｂ）は、Ｐウェル７５１、ソース部７５２、ドレイン部７５３等が形成された状態を示している。Ｐ型不純物からなるＰウェル、Ｎ＋不純物からなるソース、ドレインが形成された後に、これらの不純物の活性化のために高温にてアニール処理がされる。第２単結晶層５がＳｉＣである場合には、約１７００℃にてアニール処理がされる。
　その後、熱ＣＶＤにより第２単結晶層５の表面に厚さ１μｍ程度のＳｉＯ２膜を形成し、電極となる部分をエッチングにより除去して開口させる。続いて、ゲート部７５５を中心として部分的に絶縁膜をエッチングにより除去する。これにより、同図（ｃ）に示すように、第２単結晶層５上に層間絶縁膜７５４が形成される。図はゲート酸化膜生成前の状態を示している。次に、同図（ｄ）に示すように、ゲート酸化膜７５６を形成する。ゲート酸化膜７５６は、カーボン基板２が多結晶ＳｉＣ層４２及び５１で完全に被覆されているため、酸素雰囲気で成膜できる。ゲート酸化膜７５６を形成した後に、コンタクト部が開口される。尚、ソース部７５２とドレイン部７５３の間のゲート酸化膜７５６上がゲート部７５５となる領域で、ゲート金属が形成されている（図示せず）。
　同図（ｅ）は、更に電極膜７５８、配線層７５９等を形成した構造を示している。以上によってＭＯＳＦＥＴ７５の主要部を形成した複層基板が得られる。引き続き、図９に示した例と同様にして、カーボン基板２及びシリコン酸化膜４１を除去することによって露出される第１単結晶層１１の面に、裏面電極層８を形成することによって、縦型構造のＭＯＳＦＥＴ７５を形成することができる。
　なお、図１２においてはプレーナ構造のＭＯＳＦＥＴの構造例を示したが、トレンチ構造のＭＯＳＦＥＴも、以上に説明した素子形成工程を変形することにより形成することが可能である。 (Formation of MOSFET elements)
FIG. 12 shows a step of forming the MOSFET element 75 on the second single crystal layer 5 formed on the surface layer of the multilayer substrate 6. The first substrate 1 is single crystal SiC. FIG. 12A shows the multilayer substrate 6 shown in FIG. 2 in a simplified manner, and the first single crystal layer 11 and the polycrystalline SiC layer 51 are not shown. A portion in the figure is a region corresponding to one semiconductor element in the multilayer substrate 6. In the following drawings (b) to (e), the A portion is shown in an enlarged manner, and represents a process of forming one element.
First, a SiO 2 film is formed on the surface of the N-type second single crystal layer 5, and a mask is formed by opening necessary portions by photolithography. Then, P-type impurities are ion-implanted into the opening of the mask while being heated to about 500 ° C., and then the mask is removed. As a result, a P well 751 is formed in the surface layer portion of the second single crystal layer 5 as shown in FIG. Subsequently, an N + region can be formed by implanting impurities using the pattern of the SiO 2 film as a mask. Thereby, a source part, a drain part, etc. are formed. FIG. 5B shows a state in which a P well 751, a source part 752, a drain part 753, and the like are formed. After the P well made of P-type impurities and the source and drain made of N + impurities are formed, an annealing process is performed at a high temperature to activate these impurities. When the second single crystal layer 5 is SiC, annealing is performed at about 1700 ° C.
Thereafter, a SiO 2 film having a thickness of about 1 μm is formed on the surface of the second single crystal layer 5 by thermal CVD, and a portion to be an electrode is removed by etching and opened. Subsequently, the insulating film is partially removed by etching around the gate portion 755. As a result, an interlayer insulating film 754 is formed on the second single crystal layer 5 as shown in FIG. The figure shows a state before the generation of the gate oxide film. Next, a gate oxide film 756 is formed as shown in FIG. The gate oxide film 756 can be formed in an oxygen atmosphere because the carbon substrate 2 is completely covered with the polycrystalline SiC layers 42 and 51. After forming the gate oxide film 756, the contact portion is opened. Note that a gate metal is formed in a region where the gate oxide film 756 between the source portion 752 and the drain portion 753 becomes the gate portion 755 (not shown).
FIG. 5E shows a structure in which an electrode film 758, a wiring layer 759, and the like are further formed. As described above, a multilayer substrate in which the main part of the MOSFET 75 is formed is obtained. Subsequently, in the same manner as in the example shown in FIG. 9, by forming the back electrode layer 8 on the surface of the first single crystal layer 11 exposed by removing the carbon substrate 2 and the silicon oxide film 41, the vertical electrode layer 8 is formed. A MOSFET 75 having a mold structure can be formed.
Although FIG. 12 shows a structural example of a MOSFET having a planar structure, a MOSFET having a trench structure can also be formed by modifying the element formation process described above.
　図１３は、複層基板６の表層に形成されている第２単結晶層５にＭＯＳＦＥＴ素子７６を形成する工程を示している。同図（ｅ）に示す半導体基板６６（ＭＯＳＦＥＴ素子７６）は、第３の基板（支持基板）３として金属基板３３を使用し、金属基板３３上に順に積層された第２の半導体材料の単結晶からなる第２単結晶層５と、を備え、第２単結晶層５に半導体素子が形成されており、第２単結晶層５の上側に裏面電極層８２を備えている（図１３は、金属基板３３を上側、裏面電極層８２を下側にして描いてある。）。裏面電極層８２は、第２単結晶層５上に設けられた第１の半導体材料の単結晶からなる第１単結晶層１１上に形成されていてもよいし、更に、第１単結晶層１１上に設けられた半導体材料からなるバッファ層の上に形成されていてもよい。すなわち、ＭＯＳＦＥＴ素子７６を形成する複層基板６の構成は、図２に示した複層基板６ａ、６ｂ、６ｃ、６ｄ、６ｅのいずれであってもよい。
　図１３においては、第２の基板２としてＳｉＣ基板２５を使用し、第２の半導体材料（及び第１の半導体材料）はＳｉＣである例を示している。図１３の各図は、１つの半導体素子に相当する領域を表しており、単結晶バッファ層５２、第１単結晶層１１、バッファ層（４１、４１２、４１３）等は省略している。
　同図（ａ）は、図１２に示したＭＯＳＦＥＴ素子７５の場合と同様の工程によって、第２単結晶層５にＰウェル７５１、ソース部７５２、ドレイン部７５３、層間絶縁膜７５４、ゲート酸化膜７５６、電極膜７５８、配線層７５９等が形成された状態を表している。ＳｉＣ基板２５は多結晶ＳｉＣ層４２等によって被覆される必要はない。尚、ソース部７５２とドレイン部７５３の間のゲート酸化膜７５６上がゲート部７５５となる領域で、ゲート金属が形成されている（図示せず）。
　図１３（ｂ）は、第２単結晶層５を貫通する貫通孔８５１を形成した状態を表す。貫通孔８５１はトレンチ構造により形成することができる。そして、同図（ｃ）に示すように、貫通孔８５１の内壁面を絶縁膜８５２で覆い、金属を蒸着する等して貫通電極８５を形成する。金属層の接続性を高めるために貫通孔８５１をテーパ状とすることもできる。
　同図（ｄ）は、素子上に相互配線層３６及び金属接合層３８を設け、金属接合層３８の上に支持基板として金属基板３３を接合した状態を表している。相互配線層３６において、ゲート酸化膜上の金属膜部であるゲート部７５５と貫通電極８５とが電気的に接続される。また、相互配線層３６により金属接合層３８はソース部７５２と電気的に接続されており、金属基板３３は外部接続用のソース電極Ｓとなる。金属接合層３８は、Ｎｉ等の金属をスパッタで形成した上に厚膜のメッキ層を形成し、そのメッキ層の表面を平坦化して形成することができる。金属接合層３８と金属基板３３とは、金属間接合により直接に接合することができる。
　そして、第２単結晶層５の下面側に接合されていたＳｉＣ基板２５を除去する。前記のとおり、ＳｉＣ基板２５の表面にＧａＮ膜４１３が形成されている場合には、レーザ光を照射することによりＳｉＣ基板２５を除去することができる。また、前記のとおり、第１単結晶層１１や単結晶バッファ層５２等は、研磨等により除去することができる。
　同図（ｅ）は、ＳｉＣ基板２５等を除去して露出された第２単結晶層５の面に、選択的に裏面絶縁層８３を形成し、更に、選択的に裏面電極層８２を形成した状態を示している。これにより、第２単結晶層５の下面側（裏面ドレイン部）に接する裏面電極層８２部は外部接続用のドレイン電極Ｄとなり、貫通電極８５と接する裏面電極層８２部は外部接続用のゲート電極Ｇとなる。以上のような工程により、ＭＯＳＦＥＴ素子７６が形成されている半導体基板６６を得ることができる。 FIG. 13 shows a step of forming the MOSFET element 76 on the second single crystal layer 5 formed on the surface layer of the multilayer substrate 6. A semiconductor substrate 66 (MOSFET element 76) shown in FIG. 5E uses a metal substrate 33 as a third substrate (support substrate) 3 and is made of a single second semiconductor material layered on the metal substrate 33 in order. A second single crystal layer 5 made of crystals, a semiconductor element is formed on the second single crystal layer 5, and a back electrode layer 82 is provided on the upper side of the second single crystal layer 5 (see FIG. 13). The metal substrate 33 is drawn on the upper side and the back electrode layer 82 is on the lower side. The back electrode layer 82 may be formed on the first single crystal layer 11 made of a single crystal of the first semiconductor material provided on the second single crystal layer 5, and further, the first single crystal layer 11 may be formed on a buffer layer made of a semiconductor material provided on the substrate 11. That is, the configuration of the multilayer substrate 6 forming the MOSFET element 76 may be any of the multilayer substrates 6a, 6b, 6c, 6d, and 6e shown in FIG.
FIG. 13 shows an example in which a SiC substrate 25 is used as the second substrate 2 and the second semiconductor material (and the first semiconductor material) is SiC. Each drawing in FIG. 13 represents a region corresponding to one semiconductor element, and the single crystal buffer layer 52, the first single crystal layer 11, the buffer layers (41, 412, 413), and the like are omitted.
FIG. 6A shows a P well 751, a source portion 752, a drain portion 753, an interlayer insulating film 754, and a gate oxide film formed on the second single crystal layer 5 by the same process as the case of the MOSFET element 75 shown in FIG. 756, an electrode film 758, a wiring layer 759, and the like are formed. The SiC substrate 25 does not need to be covered with the polycrystalline SiC layer 42 or the like. Note that a gate metal is formed in a region where the gate oxide film 756 between the source portion 752 and the drain portion 753 becomes the gate portion 755 (not shown).
FIG. 13B shows a state in which a through hole 851 penetrating the second single crystal layer 5 is formed. The through hole 851 can be formed by a trench structure. Then, as shown in FIG. 4C, the inner wall surface of the through hole 851 is covered with an insulating film 852, and a through electrode 85 is formed by evaporating metal or the like. In order to improve the connectivity of the metal layer, the through hole 851 can be tapered.
FIG. 4D shows a state in which the interconnection layer 36 and the metal bonding layer 38 are provided on the element, and the metal substrate 33 is bonded as a support substrate on the metal bonding layer 38. In the interconnect layer 36, the gate portion 755, which is a metal film portion on the gate oxide film, and the through electrode 85 are electrically connected. Further, the metal bonding layer 38 is electrically connected to the source portion 752 by the interconnection layer 36, and the metal substrate 33 becomes the source electrode S for external connection. The metal bonding layer 38 can be formed by forming a thick plating layer on a metal such as Ni by sputtering and planarizing the surface of the plating layer. The metal bonding layer 38 and the metal substrate 33 can be directly bonded by intermetal bonding.
Then, SiC substrate 25 bonded to the lower surface side of second single crystal layer 5 is removed. As described above, when the GaN film 413 is formed on the surface of the SiC substrate 25, the SiC substrate 25 can be removed by irradiating the laser beam. Further, as described above, the first single crystal layer 11, the single crystal buffer layer 52, and the like can be removed by polishing or the like.
In FIG. 5E, a back insulating layer 83 is selectively formed on the surface of the second single crystal layer 5 exposed by removing the SiC substrate 25 and the like, and further, a back electrode layer 82 is selectively formed. Shows the state. Thereby, the back electrode layer 82 part in contact with the lower surface side (back drain part) of the second single crystal layer 5 becomes the drain electrode D for external connection, and the back electrode layer 82 part in contact with the through electrode 85 is the gate for external connection. It becomes the electrode G. Through the steps described above, the semiconductor substrate 66 on which the MOSFET element 76 is formed can be obtained.
　上記構造において、素子の発熱が生じるチャンネル部であるソース部７５２とドレイン部７５３部の間の表面部は、熱伝導のために金属基板３３に近いことが好ましい。そのため相互配線層３６の厚さは薄いことが好ましい。相互配線層３６の厚さを薄くするために、相互配線層３６内のゲート配線部の下の第２単結晶層５の領域は、ゲート電位に近いソース又はＰウェルの電位となるように配置することが好ましい。また、チャンネル部から金属基板３３に至る熱伝導を良くするために、ソース部、Ｐウェル部が存在する第２単結晶層５の表面から金属基板３３へ至る長さが短く、配線面積を大きくすることが好ましい。そのため、ゲート配線部をできるだけ小さくすることが好ましい。
　なお、本例においては、金属基板３３を接合する前に貫通電極８５を形成しているが、金属基板３３の接合後に、裏面側からトレンチ加工を行うことにより貫通電極８５を形成することも可能である。また、本例のＭＯＳＦＥＴの製造工程は、素子形成工程を変形することによりトレンチ構造のＭＯＳＦＥＴに適用することができる。 In the above structure, it is preferable that the surface portion between the source portion 752 and the drain portion 753, which is a channel portion where heat generation of the element occurs, is close to the metal substrate 33 for heat conduction. Therefore, the thickness of the interconnect layer 36 is preferably thin. In order to reduce the thickness of the interconnection layer 36, the region of the second single crystal layer 5 under the gate wiring portion in the interconnection layer 36 is arranged to have a source or P well potential close to the gate potential. It is preferable to do. Further, in order to improve the heat conduction from the channel portion to the metal substrate 33, the length from the surface of the second single crystal layer 5 where the source portion and the P well portion exist to the metal substrate 33 is short, and the wiring area is increased. It is preferable to do. Therefore, it is preferable to make the gate wiring portion as small as possible.
In this example, the through electrode 85 is formed before the metal substrate 33 is bonded. However, after the metal substrate 33 is bonded, the through electrode 85 can be formed by performing trench processing from the back surface side. It is. The MOSFET manufacturing process of this example can be applied to a MOSFET having a trench structure by modifying the element forming process.
　以上の実施形態においては、第２の基板２がカーボン基板であり、第１の半導体材料及び第２の半導体材料がＳｉＣである場合を主として説明した。第２の基板２がカーボンである場合には、その密度や結晶粒の大きさなどにより熱膨張係数を調整することができる。それにより、第１の半導体材料及び第２の半導体材料の熱膨張係数に応じて、カーボン基板の熱膨張係数を合わせることができる。これにより、第１単結晶層１１上に成膜する第２単結晶層５の結晶欠陥の低減を図ることができる。第２の半導体材料がＧａＮ、酸化ガリウム、酸化ガリウム等であっても同様である。
　第２の基板２の材料がサファイア又はＳｉＣである場合には、表面薄膜層４として、Ｇａを含む化合物半導体膜を成膜することが好ましい。Ｇａを含む化合物半導体膜としては、ＧａＮ、酸化ガリウム、ＧａＡs等が挙げられる。ＧａＮ膜を成膜した場合には、第３の基板３を接合後に第２の基板２の面よりレーザ光を照射することによってＧａＮからＧａを析出させ、ＧａＮ膜で第２の基板２を分離すること（所謂レーザリフトオフ）も容易である。 In the above embodiment, the case where the second substrate 2 is a carbon substrate and the first semiconductor material and the second semiconductor material are SiC has been mainly described. When the second substrate 2 is carbon, the thermal expansion coefficient can be adjusted by the density, the size of crystal grains, and the like. Thereby, the thermal expansion coefficient of the carbon substrate can be matched according to the thermal expansion coefficients of the first semiconductor material and the second semiconductor material. Thereby, the crystal defects of the second single crystal layer 5 formed on the first single crystal layer 11 can be reduced. The same applies when the second semiconductor material is GaN, gallium oxide, gallium oxide, or the like.
When the material of the second substrate 2 is sapphire or SiC, it is preferable to form a compound semiconductor film containing Ga as the surface thin film layer 4. Examples of the compound semiconductor film containing Ga include GaN, gallium oxide, and GaAs. When a GaN film is formed, Ga is deposited from GaN by irradiating laser light from the surface of the second substrate 2 after the third substrate 3 is bonded, and the second substrate 2 is separated by the GaN film. It is easy to do (so-called laser lift-off).
　以上の実施形態において、第１の半導体材料及び第２の半導体材料がＧａＮ、酸化ガリウム等である場合も同様である。また、第１の半導体材料及び第２の半導体材料がＳｉＣであり、縦型構造の半導体素子を形成する場合を説明したが、ＧａＮ等を用いて横型構造の半導体素子を形成する場合においても、同様に製造することができる。具体的には、第２の基板２にシリコン酸化膜４１を形成し、その上に第１の基板１を接合し、第２単結晶層５としてＧａＮ層を成膜して横型の素子を形成し、第３の基板３を接合した後に第２の基板２を除去することができる。この場合、圧電性の材料であるＧａＮ層を成膜するために、下地となる第２の基板２であるカーボン基板の熱膨張係数をＧａＮに合わせることにより、ＧａＮ層の内部応力を極小化することが可能である。カーボン基板は、その密度や結晶粒の大きさなどにより熱膨張係数を調整することができるからである。 In the above embodiment, the same applies to the case where the first semiconductor material and the second semiconductor material are GaN, gallium oxide, or the like. In addition, although the case where the first semiconductor material and the second semiconductor material are SiC and a semiconductor element having a vertical structure is formed has been described, even when a semiconductor element having a horizontal structure is formed using GaN or the like, It can be manufactured similarly. Specifically, a silicon oxide film 41 is formed on the second substrate 2, the first substrate 1 is bonded thereon, and a GaN layer is formed as the second single crystal layer 5 to form a lateral element. The second substrate 2 can be removed after the third substrate 3 is bonded. In this case, in order to form a GaN layer, which is a piezoelectric material, the internal stress of the GaN layer is minimized by matching the thermal expansion coefficient of the carbon substrate, which is the second substrate 2 as a base, to GaN. It is possible. This is because the thermal expansion coefficient of the carbon substrate can be adjusted depending on the density and the size of the crystal grains.
　図２に示した複層基板６（６ａ、６ｂ、６ｃ、６d、６e）は、高電力用途の素子を形成するための半導体基板として好適である。以上のような半導体素子の製造方法を適用すれば、複層基板６を基にして、半導体素子が形成された半導体基板を構成することができる。図１４及び１５は、複層基板６を使用し、支持基板３（前記第３の基板３）として、絶縁材料、半導体材料及び金属のうちの１つからなる基板を使用した半導体基板６５を表している。半導体基板６５には、半導体素子７が形成されている。（図１４及び１５は、支持基板３を下側、裏面電極層８を上側にして描いてある。）
　図１４に示す半導体基板６５は、絶縁材料、半導体材料及び金属のうちの１つからなる支持基板３（３１、３２又は３３）と、支持基板３上に接合層３４（３５、３６）を挟んで積層された第２の半導体材料の単結晶からなる第２単結晶層５を備えている。そして、第２単結晶層５に半導体素子７が形成されており、第２単結晶層５の上に半導体素子７の裏面電極層８（８１、８２）を備えている。半導体素子７の種類は問わず、例えば、前述のショットキーダイオード７１、ＭＯＳＦＥＴ７５、７６等を挙げることができる。 The multilayer substrate 6 (6a, 6b, 6c, 6d, 6e) shown in FIG. 2 is suitable as a semiconductor substrate for forming an element for high power use. By applying the semiconductor element manufacturing method as described above, a semiconductor substrate on which a semiconductor element is formed can be formed based on the multilayer substrate 6. 14 and 15 show a semiconductor substrate 65 using a multilayer substrate 6 and using a substrate made of one of an insulating material, a semiconductor material, and a metal as the support substrate 3 (the third substrate 3). ing. A semiconductor element 7 is formed on the semiconductor substrate 65. (FIGS. 14 and 15 are drawn with the support substrate 3 on the bottom and the back electrode layer 8 on the top.)
A semiconductor substrate 65 shown in FIG. 14 has a support substrate 3 (31, 32 or 33) made of one of an insulating material, a semiconductor material, and a metal, and a bonding layer 34 (35, 36) sandwiched on the support substrate 3. And a second single crystal layer 5 made of a single crystal of the second semiconductor material laminated. The semiconductor element 7 is formed on the second single crystal layer 5, and the back electrode layer 8 (81, 82) of the semiconductor element 7 is provided on the second single crystal layer 5. Regardless of the type of the semiconductor element 7, for example, the Schottky diode 71 and the MOSFETs 75 and 76 described above can be used.
　図１５は、半導体基板６５の別の形態（６５ａ、６５ｂ、６５ｃ）を表している。半導体基板（６５ａ、６５ｂ、６５ｃ）においては、第２単結晶層５上に第１の半導体材料の単結晶からなる第１単結晶層１１を備え、裏面電極層８（８１、８２）は、第１単結晶層１１の上に、又は第１単結晶層１１上に設けられた半導体材料からなるバッファ層４１２の上に備えている。すなわち、支持基板３（３１、３２又は３３）上に接合層３４（３５、３６）を挟んで第２単結晶層５及び第１単結晶層１１が備えられており、第２単結晶層５に半導体素子７が形成されている。
　同図（ａ）は、第１単結晶層１１の上に半導体素子７の裏面電極層８を備える半導体基板６５ａの例を示している。裏面電極層８は、同図（ｂ）に示すように、第１単結晶層１１上に、半導体材料からなるバッファ層４１２を介して設けられていてもよい。支持基板３としては、無アルカリガラス、サファイア、Ｓｉ等からなる基板を用いることができる。また、支持基板３には半導体素子７の電極部となる貫通孔３（３６，３７）が形成されていてもよい。
　同図（ｃ）は、支持基板３として金属基板３３を、金属接合層３８を介して接合した半導体基板６５ｃを表している。金属基板３３を使用すれば、熱伝導性に優れたパワー半導体とすることができる。
　上記半導体基板に使用する第１の半導体材料はＳｉＣ、ＧａＮ及び酸化ガリウムのうちの１つとし、第２の半導体材料はＳｉＣ、ＧａＮ及び酸化ガリウムのうちの１つとすることが好ましい。
　半導体基板（６５ａ、６５ｂ、６５ｃ）は、第１単結晶層１１の厚さが薄くてよい（０．５～１μｍ程度）ため、第１の半導体材料の単結晶からなる第１の基板１の使用量はわずかで済む。また、第２の基板２がサファイア基板又はＳｉＣ基板２５であり、レーザリフトオフにより除去すれば、第２の基板２として繰り返し使用することができる。このように製造工程においても消耗する部材が極めて少ないため、本形態の半導体基板６５は極めて低コストとすることが可能である。 FIG. 15 shows another form (65a, 65b, 65c) of the semiconductor substrate 65. The semiconductor substrate (65a, 65b, 65c) includes a first single crystal layer 11 made of a single crystal of a first semiconductor material on the second single crystal layer 5, and the back electrode layer 8 (81, 82) is It is provided on the first single crystal layer 11 or on the buffer layer 412 made of a semiconductor material provided on the first single crystal layer 11. That is, the second single crystal layer 5 and the first single crystal layer 11 are provided on the support substrate 3 (31, 32, or 33) with the bonding layer 34 (35, 36) interposed therebetween. A semiconductor element 7 is formed on the substrate.
FIG. 5A shows an example of a semiconductor substrate 65 a provided with the back electrode layer 8 of the semiconductor element 7 on the first single crystal layer 11. The back electrode layer 8 may be provided on the first single crystal layer 11 via a buffer layer 412 made of a semiconductor material, as shown in FIG. As the support substrate 3, a substrate made of alkali-free glass, sapphire, Si, or the like can be used. Further, the support substrate 3 may be formed with through holes 3 (36, 37) serving as electrode portions of the semiconductor element 7.
FIG. 3C shows a semiconductor substrate 65 c in which a metal substrate 33 is bonded as a support substrate 3 via a metal bonding layer 38. If the metal substrate 33 is used, a power semiconductor having excellent thermal conductivity can be obtained.
The first semiconductor material used for the semiconductor substrate is preferably one of SiC, GaN, and gallium oxide, and the second semiconductor material is preferably one of SiC, GaN, and gallium oxide.
In the semiconductor substrate (65a, 65b, 65c), since the thickness of the first single crystal layer 11 may be thin (about 0.5 to 1 μm), the first substrate 1 made of a single crystal of the first semiconductor material is used. Only a small amount is used. The second substrate 2 is a sapphire substrate or a SiC substrate 25, and can be repeatedly used as the second substrate 2 if it is removed by laser lift-off. As described above, since the number of members consumed in the manufacturing process is extremely small, the semiconductor substrate 65 of this embodiment can be extremely low in cost.
　尚、本発明は以上で詳述した実施形態に限定されず、本発明の請求項に示した範囲で様々な変形または変更が可能である。 Note that the present invention is not limited to the embodiments described in detail above, and various modifications or changes can be made within the scope of the claims of the present invention.
　ＳｉＣ等を用いたパワー系化合物半導体素子は、車においてはハイブリッド車、電気自動車等の普及に伴ってますます重要度が増している。また、家庭においてはスマートグリッドの普及に伴って家電製品の制御やエネルギー管理のためにパワー系化合物半導体装置の役割が重要になってくる。本発明により、高価な材料であるＳｉＣ単結晶の使用量を大幅に減らすことができ、安価なパワー半導体素子を製造することが可能となる。 Power-based compound semiconductor elements using SiC and the like are becoming increasingly important with the spread of hybrid cars and electric cars in cars. In addition, the role of power-based compound semiconductor devices becomes important for home appliance control and energy management with the spread of smart grids at home. According to the present invention, the amount of SiC single crystal, which is an expensive material, can be greatly reduced, and an inexpensive power semiconductor element can be manufactured.
　１；第１の基板、１１；第１単結晶層、１５；水素注入層、１０１；第１の基板の下面、２；第２の基板（カーボン基板）、２０１；第２の基板の上面、２０２；第２の基板の下面、２０３；第２の基板の側面、２５；第２の基板（ＳｉＣ基板）、３；第３の基板、３１；無アルカリガラス基板、３２：Ｓｉ基板、３３；金属基板、３４、３５；接合層、３６；相互配線層、３７；貫通孔、３８；金属接合層、４；表面薄膜層、４１；シリコン酸化膜、４１２；バッファ層（多結晶ＳｉＣ層）、４１３；ＧａＮ膜、４２；多結晶ＳｉＣ膜、５；第２単結晶層、５１；第２多結晶層、５２；単結晶バッファ層、５３；高窒素濃度の多結晶ＳｉＣ層、６、６ａ、６ｂ、６ｃ、６ｄ、６ｅ；複層基板、６５、６５ａ、６５ｂ、６５ｃ、６５ｄ；半導体基板、７；半導体素子、７１；ショットキーダイオード、７０１、７０２；マスク、７１１、７１２；Ｐ型不純物領域、７１３；層間絶縁膜、７１４；電極膜、７５、７６；ＭＯＳＦＥＴ、７５１；Ｐウエル、７５２；ソース部、７５３；ドレイン部、７５４；層間絶縁膜、７５５；ゲート部、７５６；ゲート酸化膜、７５７；コンタクト、７５８；電極膜、７５９；配線層、８；裏面電極層、８１；シリサイド層、８２；金属層、８３；裏面絶縁層、８５；貫通電極、９１；ショットキーダイオード、９２；ＭＯＳＦＥＴ。 DESCRIPTION OF SYMBOLS 1; 1st board | substrate, 11; 1st single crystal layer, 15; Hydrogen injection layer, 101; The lower surface of 1st board | substrate, 2; 2nd board | substrate (carbon substrate), 201; 202; lower surface of the second substrate, 203; side surface of the second substrate, 25; second substrate (SiC substrate), 3; third substrate, 31; alkali-free glass substrate, 32: Si substrate, 33; Metal substrate, 34, 35; Bonding layer, 36; Interconnection layer, 37; Through hole, 38; Metal bonding layer, 4; Surface thin film layer, 41; Silicon oxide film, 412; Buffer layer (polycrystalline SiC layer), 413; GaN film, 42; polycrystalline SiC film, 5; second single crystal layer, 51; second polycrystalline layer, 52; single crystal buffer layer, 53; polycrystalline nitrogen layer with high nitrogen concentration, 6, 6a, 6b, 6c, 6d, 6e; multilayer substrate, 65, 65a, 65b, 65c, 65d; half Body substrate, 7; semiconductor element, 71; Schottky diode, 701, 702; mask, 711, 712; P-type impurity region, 713; interlayer insulating film, 714; electrode film, 75, 76; MOSFET, 751; 752; Source part 753; Drain part 754; Interlayer insulating film 755; Gate part 756; Gate oxide film 757; Contact 758; Electrode film 759; Wiring layer 8: Back electrode layer 81; Silicide layer, 82; metal layer, 83; back insulating layer, 85; through electrode, 91; Schottky diode, 92;

Claims (21)

  1. 　仮支持基板とするための第２の基板上に第２の半導体材料の単結晶からなる第２単結晶層を成膜する第２成膜工程と、
    　前記第２単結晶層に半導体素子を形成する素子形成工程と、
    　前記半導体素子が形成された前記第２単結晶層上に第３の基板を接合する第２接合工程と、
    　前記第３の基板を接合した後に前記第２の基板を除去する基板除去工程と、
    　を含むことを特徴とする半導体素子の製造方法。     A second film forming step of forming a second single crystal layer made of a single crystal of the second semiconductor material on the second substrate to be a temporary support substrate;
    An element forming step of forming a semiconductor element in the second single crystal layer;
    A second bonding step of bonding a third substrate on the second single crystal layer on which the semiconductor element is formed;
    A substrate removing step of removing the second substrate after bonding the third substrate;
    The manufacturing method of the semiconductor element characterized by the above-mentioned.
  2. 　第１の半導体材料の単結晶からなる第１の基板の一方の平面と前記第２の基板とを接合する接合工程と、
    　前記第２の基板との接合面から所定の深さにおいて前記第１の基板を分離することにより、前記第１の基板の前記一方の平面側を第１単結晶層として前記第２の基板上に残す分離工程と、
    　を含み、
    　前記第２成膜工程において、前記第２単結晶層は前記第２の基板上に形成された前記第１単結晶層上に成膜される請求項１記載の半導体素子の製造方法。     A bonding step of bonding one plane of the first substrate made of a single crystal of the first semiconductor material and the second substrate;
    By separating the first substrate at a predetermined depth from the bonding surface with the second substrate, the one plane side of the first substrate is used as a first single crystal layer on the second substrate. A separation process to leave in,
    Including
    2. The method of manufacturing a semiconductor element according to claim 1, wherein in the second film formation step, the second single crystal layer is formed on the first single crystal layer formed on the second substrate.
  3. 　前記基板除去工程において、前記第１単結晶層を更に除去する請求項２記載の半導体素子の製造方法。 3. The method of manufacturing a semiconductor element according to claim 2, wherein the first single crystal layer is further removed in the substrate removing step.
  4. 　前記第１の基板の前記一方の平面から所定の深さに水素注入層を形成する水素層形成工程と、
    　前記第２の基板の少なくとも１つの平面上に絶縁材料又は半導体材料の１層以上の薄膜からなる表面薄膜層を成膜する第１成膜工程と、
    　を含み、
    　前記接合工程において、前記第１の基板の前記一方の平面と前記第２の基板上に形成された前記表面薄膜層の表面とを接合し、
    　前記分離工程において、前記第１の基板を前記水素注入層で分離することにより、前記第１単結晶層を前記第２の基板に形成された前記表面薄膜層上に残し、
    　前記第２成膜工程により、前記第２の基板上に前記表面薄膜層と前記第１単結晶層と前記第２単結晶層とが順に積層された複層基板が形成され、
    　基板除去工程において、更に前記表面薄膜層を除去する請求項２又は３に記載の半導体素子の製造方法。     A hydrogen layer forming step of forming a hydrogen injection layer at a predetermined depth from the one plane of the first substrate;
    A first film forming step of forming a surface thin film layer made of one or more thin films of an insulating material or a semiconductor material on at least one plane of the second substrate;
    Including
    In the bonding step, the one plane of the first substrate and the surface of the surface thin film layer formed on the second substrate are bonded,
    In the separation step, the first substrate is separated by the hydrogen injection layer to leave the first single crystal layer on the surface thin film layer formed on the second substrate,
    The second film forming step forms a multilayer substrate in which the surface thin film layer, the first single crystal layer, and the second single crystal layer are sequentially stacked on the second substrate,
    4. The method of manufacturing a semiconductor element according to claim 2, wherein the surface thin film layer is further removed in the substrate removing step.
  5. 　前記第２成膜工程において、前記第２の半導体材料の単結晶からなる単結晶バッファ層を形成した後に前記第２単結晶層を成膜し、
    　前記基板除去工程において、前記単結晶バッファ層を更に除去する請求項１乃至４のいずれかに記載の半導体素子の製造方法。     In the second film forming step, after forming a single crystal buffer layer made of a single crystal of the second semiconductor material, forming the second single crystal layer,
    The method for manufacturing a semiconductor device according to claim 1, wherein the single crystal buffer layer is further removed in the substrate removing step.
  6. 　前記第１の基板の前記一方の平面上にシリサイド層を形成するシリサイド層形成工程を含む請求項２乃至５のいずれかに記載の半導体素子の製造方法。 6. The method of manufacturing a semiconductor element according to claim 2, further comprising a silicide layer forming step of forming a silicide layer on the one plane of the first substrate.
  7. 　前記第１成膜工程において、前記表面薄膜層として前記第２の基板の一方の平面にシリコン酸化膜又はＧａを含む化合物半導体膜を成膜する請求項４乃至６のいずれかに記載の半導体素子の製造方法。 7. The semiconductor element according to claim 4, wherein, in the first film formation step, a silicon oxide film or a compound semiconductor film containing Ga is formed on one plane of the second substrate as the surface thin film layer. Manufacturing method.
  8. 　前記第１成膜工程において、前記表面薄膜層として前記第２の基板の前記一方の平面側に更に半導体材料からなるバッファ層を成膜する請求項４乃至７のいずれかに記載の半導体素子の製造方法。 8. The semiconductor element according to claim 4, wherein in the first film formation step, a buffer layer made of a semiconductor material is further formed on the one plane side of the second substrate as the surface thin film layer. Production method.
  9. 　前記第１成膜工程において、前記表面薄膜層として前記第２の基板の他方の平面にＳｉＣの多結晶からなる多結晶ＳｉＣ膜を成膜する請求項４乃至８のいずれかに記載の半導体素子の製造方法。 9. The semiconductor element according to claim 4, wherein in the first film formation step, a polycrystalline SiC film made of SiC polycrystal is formed on the other plane of the second substrate as the surface thin film layer. Manufacturing method.
  10. 　前記第２の基板は光を透過する基板であり、前記表面薄膜層はＧａを含む半導体材料であり、
    　前記基板除去工程において、前記第２の基板側からレーザ光を照射してＧａを析出させることによって前記第２の基板を除去する請求項１乃至５のいずれかに記載の半導体素子の製造方法。     The second substrate is a light transmitting substrate, and the surface thin film layer is a semiconductor material containing Ga;
    6. The method of manufacturing a semiconductor element according to claim 1, wherein, in the substrate removing step, the second substrate is removed by irradiating a laser beam from the second substrate side to deposit Ga.
  11. 　前記第２の基板はサファイア又はＳｉＣからなる基板である請求項１乃至１０のいずれかに記載の半導体素子の製造方法。 11. The method for manufacturing a semiconductor element according to claim 1, wherein the second substrate is a substrate made of sapphire or SiC.
  12. 　前記第２の基板はカーボンからなる基板であり、
    　前記第１成膜工程において、前記表面薄膜層は前記第２の基板の側面側を覆うように成膜される請求項１乃至９のいずれかに記載の半導体素子の製造方法。     The second substrate is a substrate made of carbon;
    The method for manufacturing a semiconductor element according to claim 1, wherein in the first film formation step, the surface thin film layer is formed so as to cover a side surface side of the second substrate.
  13. 　前記第３の基板は金属基板である請求項１乃至１２のいずれかに記載の半導体素子の製造方法。 13. The method for manufacturing a semiconductor element according to claim 1, wherein the third substrate is a metal substrate.
  14. 　前記第３の基板は、無アルカリガラス、サファイア及びＳｉのうちの１つからなる基板である請求項１乃至１２のいずれかに記載の半導体素子の製造方法。 13. The method for manufacturing a semiconductor element according to claim 1, wherein the third substrate is a substrate made of one of alkali-free glass, sapphire, and Si.
  15. 　前記基板除去工程により露出された面上に、前記半導体素子の裏面電極層を形成する裏面電極形成工程を備える請求項１乃至１４のいずれかに記載の半導体素子の製造方法。 15. The method of manufacturing a semiconductor element according to claim 1, further comprising a back electrode forming step of forming a back electrode layer of the semiconductor element on the surface exposed by the substrate removing step.
  16. 　前記第２接合工程又は前記基板除去工程の後、前記第３の基板に前記半導体素子の電極部となる貫通孔を形成する開孔工程を備える請求項１４又は１５に記載の半導体素子の製造方法。 The method for manufacturing a semiconductor device according to claim 14, further comprising an opening step of forming a through hole serving as an electrode portion of the semiconductor element in the third substrate after the second bonding step or the substrate removing step. .
  17. 　前記開孔工程において、前記貫通孔は前記第３の基板の表面側に向けて拡がるテーパ状に形成される請求項１６記載の半導体素子の製造方法。 The method for manufacturing a semiconductor element according to claim 16, wherein, in the opening step, the through hole is formed in a tapered shape that expands toward the surface side of the third substrate.
  18. 　前記第１の半導体材料はＳｉＣ、ＧａＮ及び酸化ガリウムのうちの１つであり、
    　前記第２の半導体材料はＳｉＣ、ＧａＮ及び酸化ガリウムのうちの１つである請求項１乃至１７のいずれかに記載の半導体素子の製造方法。     The first semiconductor material is one of SiC, GaN and gallium oxide;
    The method of manufacturing a semiconductor element according to claim 1, wherein the second semiconductor material is one of SiC, GaN, and gallium oxide.
  19. 　絶縁材料、半導体材料及び金属のうちの１つからなる支持基板と、前記支持基板上に接合層を挟んで積層された第２の半導体材料の単結晶からなる第２単結晶層を備え、
    　前記第２単結晶層に半導体素子が形成されており、
    　前記第２単結晶層の上に前記半導体素子の裏面電極層を備えることを特徴とする半導体基板。     A support substrate made of one of an insulating material, a semiconductor material, and a metal, and a second single crystal layer made of a single crystal of a second semiconductor material laminated on the support substrate with a bonding layer interposed therebetween,
    A semiconductor element is formed in the second single crystal layer;
    A semiconductor substrate comprising a back electrode layer of the semiconductor element on the second single crystal layer.
  20. 　前記第２単結晶層上に第１の半導体材料の単結晶からなる第１単結晶層を備え、
    　前記裏面電極層は、前記第１単結晶層の上に、又は前記第１単結晶層上に設けられた半導体材料からなるバッファ層の上に備えられている請求項２０記載の半導体基板。     A first single crystal layer comprising a single crystal of a first semiconductor material on the second single crystal layer;
    21. The semiconductor substrate according to claim 20, wherein the back electrode layer is provided on the first single crystal layer or on a buffer layer made of a semiconductor material provided on the first single crystal layer.
  21. 　前記第１の半導体材料はＳｉＣ、ＧａＮ及び酸化ガリウムのうちの１つであり、
    　前記第２の半導体材料はＳｉＣ、ＧａＮ及び酸化ガリウムのうちの１つである請求項２０又は２１に記載の半導体基板。     The first semiconductor material is one of SiC, GaN and gallium oxide;
    The semiconductor substrate according to claim 20 or 21, wherein the second semiconductor material is one of SiC, GaN, and gallium oxide.
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