WO2018041258A1 - Procédé de traitement de commande de désattribution, et dispositif de mémoire - Google Patents

Procédé de traitement de commande de désattribution, et dispositif de mémoire Download PDF

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Publication number
WO2018041258A1
WO2018041258A1 PCT/CN2017/100317 CN2017100317W WO2018041258A1 WO 2018041258 A1 WO2018041258 A1 WO 2018041258A1 CN 2017100317 W CN2017100317 W CN 2017100317W WO 2018041258 A1 WO2018041258 A1 WO 2018041258A1
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Prior art keywords
command
allocation
physical
logical address
read
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PCT/CN2017/100317
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English (en)
Chinese (zh)
Inventor
于松海
蔡述楠
郭志红
高慧娟
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北京忆恒创源科技有限公司
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Priority claimed from CN201610804881.1A external-priority patent/CN107797934B/zh
Priority claimed from CN201610803054.0A external-priority patent/CN107797938B/zh
Application filed by 北京忆恒创源科技有限公司 filed Critical 北京忆恒创源科技有限公司
Publication of WO2018041258A1 publication Critical patent/WO2018041258A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

Definitions

  • the present application relates to storage technologies, and more particularly to a processing method for processing a de-allocation command and a storage device thereof.
  • the host and the storage device can be coupled in various ways, including but not limited to connecting to the host through, for example, SATA, IDE, USB, PCIE, NVMe (NVM Express), SAS, Ethernet, Fibre Channel, wireless communication network, and the like.
  • the host may be an information processing device capable of communicating with the storage device in the manner described above, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, and the like.
  • FIG. 1 is a block diagram of a storage device.
  • the solid state storage device 102 is coupled to the host for providing storage capabilities to the host.
  • the host and the solid-state storage device 102 can be coupled in various manners, including but not limited to, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface). , SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe, High Speed Peripheral Component Interconnect) NVMe (NVM Express, high speed nonvolatile storage), Ethernet, Fibre Channel, wireless communication network, etc. are connected to the host and solid state storage device 102.
  • SATA Serial Advanced Technology Attachment
  • SCSI Serial Attached SCSI
  • IDE Integrated Drive Electronics
  • USB Universal Serial Bus
  • PCIE Peripheral Component Interconnect Express
  • PCIe High Speed Peripheral Component Interconnect
  • NVMe High Speed
  • the host may be an information processing device capable of communicating with the storage device in the manner described above, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, and the like.
  • the storage device 102 includes an interface 103, a control unit 104, one or more NVM (Non-Volatile Memory) chips 105, and a DRAM (Dynamic Random Access Memory) 110.
  • NVM Non-Volatile Memory
  • DRAM Dynamic Random Access Memory
  • the interface 103 can be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, and the like.
  • Control component 104 is used to control data transfers between interface 103, NVM chip 105, and DRAM 110, as well as for storage management, host logical address to flash physical address mapping, erase equalization, bad block management, and the like.
  • Control component 104 can be implemented in a variety of ways, including software, hardware, firmware, or a combination thereof.
  • the control unit 104 may be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.
  • Control component 104 may also include a processor or controller that executes software in the processor or controller to manipulate the hardware of control component 104 to process IO commands.
  • Control component 104 is also coupled to DRAM 110 and can access data from DRAM 110.
  • the DRAM can store data for FTL tables and/or cached IO commands.
  • Control component 104 includes a flash interface controller (or referred to as a flash channel controller).
  • the flash interface controller is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner consistent with the interface protocol of the NVM chip 105 to operate the NVM chip 105 and receive command execution results output from the NVM chip 105.
  • the interface protocol of the NVM chip 105 includes well-known interface protocols or standards such as "Toggle” and "ONFI".
  • a memory target is one or more Logic Units of a shared chip enable (CE, Chip Enable) signal within a NAND flash package.
  • Each logical unit has a LUN (Logic Unit Number).
  • One or more dies (Die) may be included in the NAND flash package.
  • Die may be included in the NAND flash package.
  • the logic unit can include a plurality of planes. Multiple planes within a logical unit can be accessed in parallel, while multiple logical units within a NAND flash chip can execute command and report states independently of each other.
  • a page on a storage medium (referred to as a physical page) has a fixed size, such as 17,664 bytes. Of course, physical pages can also have other sizes.
  • a logical address constitutes a storage space of a solid-state storage device perceived by an upper layer software such as an operating system.
  • the physical address is the address of the physical storage unit used to access the solid state storage device.
  • the Trim command is defined in ATA8-ACS2. Commands with the same or similar meaning are called UNMAP (Unmap) in the SCSI (Small Computer System Interface) specification, and are in the NVMe specification. Called Deallocate.
  • de-allocation is used to indicate a data set management command having the same or similar function as "pruning" of ATA8-ACS2, “de-mapping” of SCSI, “de-allocation” of NVMe, and also indicating other or Commands with the same or similar functions that appear in future protocols, specifications, or technologies.
  • a logical address range is described. After performing the de-allocation command, there can be different effects. For example, (1) after executing the de-allocation command, and then reading the logical address range indicated by the de-allocation command, the obtained is determined (before performing other write operations on the logical address range); (2) execution After the command is allocated, and the logical address range indicated by the allocation command is read, the result is all 0 (before performing other write operations on the logical address range); (3) after executing the deal allocation command, When the logical address range indicated by the allocation command is read again, the result obtained can be any value (before performing other write operations on the logical address range). In the de-allocation command or other commands, you can set or select to assign the execution effect of the command.
  • the host can tell the SSD which logical address space no longer stores valid data, so that the SSD does not have to move the expired data when reclaiming storage space.
  • a large number of memory access operations are required in the process of performing the deallocation command, which seriously prolongs the processing time of the deallocation command and affects the performance of the solid state hard disk, thereby affecting the simultaneous IO commands. carried out.
  • a first aspect of the present application provides a de-allocation method, the method comprising: obtaining a logical address range indicated by a de-allocation command according to a de-allocation command; updating a de-allocation table, and de-allocating a table corresponding to a logical address range indicated by the de-allocation command The entry is set to a first specified value; wherein the de-allocation table is used to record information on whether the logical address in the FTL table is allocated; indicating that the execution of the allocation command is completed.
  • the de-allocation method further includes: updating the FTL table, The entry of the FTL table corresponding to the logical address range indicated by the allocation command is set to the first specified value.
  • the de-allocation method further includes: updating a valid data unit table, where the valid data unit table is used to record each physical of the storage device The state of the data of the data unit; the valid data unit count table is updated, wherein the valid data unit count table is used to record the number of physical data units in a physical block, a large block, or a physical block group that are in an active state.
  • the valid data unit table is a valid data unit bitmap, and each bit in the valid data unit bitmap is used to indicate storage. The state of the data for each physical data unit of the device.
  • the physical data unit is part of a physical page or physical page.
  • the de-allocation method further includes: updating the physical block according to the valid data unit count table, The first priority of the block or physical block group, the first priority being a priority for performing a garbage collection operation; performing a garbage collection operation according to the first priority.
  • a physical block, a large block, or a physical block group having fewer valid data units has a higher first priority.
  • the seventh possible implementation manner during the updating of the FTL table, other components are prevented from accessing the entry of the FTL table being updated. Or, to prevent other components from accessing the entries of the FTL table being updated.
  • updating the FTL table includes updating a plurality of entries of the FTL table each time.
  • updating the FTL table includes updating, by using a DMA operation, a memory that stores multiple entries of the FTL table. space.
  • the de-allocation method further includes: before the FTL table is updated, the logic of the command indication is to be allocated The entry of the FTL table corresponding to the address range is locked. After the FTL table is updated, the entry of the FTL table corresponding to the logical address range indicated by the command is unlocked.
  • the de-allocation method further includes: in response to receiving the read command, by de-allocating the table Determining whether a logical address read by the read command is allocated, wherein if the read logical address is not allocated, the second specified value is used as a response to the read command, if the read logical unit address is In the case of allocation, the FTL table is queried to obtain the physical address corresponding to the logical address to be read, and the data is read from the physical address as a response to the read command.
  • the de-allocation method further includes: by receiving a read command, by using a de-allocation table Determining whether the logical address read by the read command is allocated, wherein if the read logical address is not allocated, the status information is notified to the host that the read logical address is invalid, illegal, or in one or more Go to assign status.
  • the de-allocation method further includes: the driver of the host generates the read for the read based on the notified state information The read result or data of the application of the logical address.
  • the de-allocation method further includes: in response to receiving the write command, a write command The physical address is assigned, and the FTL table and the de-allocation table are updated according to the assigned physical address.
  • the de-allocation method further includes: in response to receiving the write command, after updating the FTL table, to the physical The address is written to the data, and the write command processing is completed to the host.
  • the de-allocation method is provided by using the de-allocation method provided by the first aspect of the present application
  • the logical address range indicated by the de-allocation command is first obtained according to the de-allocation command, and then the de-allocation table is updated, and the de-allocation corresponding to the logical address range indicated by the de-allocation command is allocated.
  • the table entry is set to a first specified value, wherein the de-allocation table is used to record whether the logical address in the FTL table is allocated, and then indicates that the allocation command execution is completed, so that the de-allocation command can be processed at a high speed, and
  • the process of assigning commands does not affect the execution of concurrent IO commands.
  • a second aspect of the present application provides a method of processing a read command, the method comprising: determining, by a de-allocation table, whether a logical address read by the read command is allocated, in response to receiving the read command, wherein If the logical address is not allocated, the second specified value is used as a response to the read command. If the read logical unit address is allocated, the FTL table is queried to obtain the physical address corresponding to the logical address to be read, from the physical The address reads the data as a response to the read command.
  • a third aspect of the present application provides a method of processing a read command, the method comprising: determining, by a de-allocation table, whether a logical address read by the read command is allocated, in response to receiving the read command, wherein The logical address fetched is not assigned, and the status information is notified to the host that the read logical address is invalid, illegal, or in one or more de-allocation states.
  • the method for processing a read command further includes: a driver of the host generates a read provided to an application that reads the logical address based on the notified state information Take results or data.
  • a fourth aspect of the present application provides a method of processing a write command, the method comprising: assigning a physical address to a write command, updating an FTL table, a valid data unit table, and valid data with the allocated physical address in response to receiving the write command Unit count table and de-allocation table.
  • the method for processing a write command further includes: in response to receiving the write command, after the FTL table is updated, writing data to the physical address, and The feedback write command processing is completed.
  • a fifth aspect of the present application provides a storage device, where the storage device includes an acquisition module, an update module, and an indication module, wherein the acquisition module is configured to obtain a logical address range indicated by the de-allocation command according to the de-allocation command; and the update module is used to update De-allocating the table, setting an entry of the de-allocation table corresponding to the logical address range indicated by the allocation command to a first specified value, wherein the de-allocation table is used to record information about whether the logical address in the FTL table is allocated; The instruction is executed to complete the execution of the command.
  • a sixth aspect of the present application provides a storage device including a control unit, an interface, a DRAM, and one or more NVMs, wherein the DRAM stores a de-allocation table and an FTL table for exchanging data with the control unit ,
  • the control unit acquires the logical address range indicated by the de-allocation command according to the de-allocation command, and updates the de-allocation table, and sets the entry of the de-allocation table corresponding to the logical address range indicated by the de-allocation command to the first specified value, where the de-allocation table A message for recording whether a logical address in the FTL table is allocated, and instructing to allocate the command execution completion.
  • a seventh aspect of the present application provides a computer program comprising computer program code for causing a control component to perform a first aspect or a first aspect of the first aspect when loaded onto a storage device and executed on a control component of the storage device A de-allocation method as described in one of the fifteenth possible implementations.
  • An eighth aspect of the present application provides a de-allocation method, the de-allocation method comprising: step S1, acquiring a logical address range indicated by a de-allocation command according to a de-allocation command; and step S2, updating an FTL table, and de-allocating the logic of the command indication
  • the entry of the FTL table corresponding to the address range is set to a preset value, where the entry of the FTL table is used to indicate the correspondence between the logical address and the physical address; and in step S3, the valid page table is updated in response to the update of the FTL table, and the valid
  • the page table is used to record the state of the data stored in the physical page of the storage device; in step S4, the valid page count table is updated in response to the update of the valid page table, wherein the valid page count table is used to record physical blocks, chunks or physics The number of physical pages in the block group that are in a valid state.
  • the de-allocation method further includes: in step S5, updating a priority of a physical block, a large block, or a physical block group in response to an update of the valid page count table,
  • the priority is a priority when performing a garbage collection operation on a physical block, a large block, or a physical block group; and in step S6, performing a garbage collection operation on the physical block, the large block, or the physical block group having the highest priority.
  • the step S2 includes: updating multiple entries of the FTL table each time.
  • the entries of the multiple FTL tables in the storage space are updated each time, and the storage space is continuously updated in one CPU. During the entry of multiple FTL tables, other CPUs are prevented from accessing the entries of the FTL table being updated, or other CPUs are not allowed to access the entries of the FTL table being updated.
  • step S2 the DMA operation is used to update and store the multiple FTL tables.
  • the memory space of the table entry is used to update and store the multiple FTL tables.
  • step S2 the preset value is 0.
  • the logical address is the address of the logical page, the physical address The address of the physical page.
  • the eighth possible implementation if the storage space corresponding to the logical page and the storage space of the physical page are the same, each bit in the valid page table Used to indicate the validity of a physical page.
  • each bit in the valid page table is used to indicate Physics corresponding to a logical address The validity of the storage area.
  • the effective page count table is an array, a linear table, or Linked list.
  • step S6 the physical block, the large block or the physical number of the valid page number is 0.
  • a block group is the highest priority physical block, large block, or physical block group.
  • the de-allocation method further includes: after step S2, The host feedback de-allocation command processing is completed; or, after step S4, the feedback processing to the host is completed.
  • the de-allocation method further includes: in step S1 and step S2 The entry of the FTL table corresponding to the logical address range indicated by the allocation command is locked; and between the step S2 and the step S3, the entry of the FTL table corresponding to the logical address range indicated by the allocation command is unlocked.
  • the de-allocation method further includes: at step S1 and step S2 Between the entries of the allocation table is cleared, wherein the table of the allocation table is used to store information about whether each logical address is allocated.
  • the de-allocation method further includes: after the de-allocation table is cleared, the command processing is sent to the host to be distributed. carry out.
  • the de-allocation method further includes: updating the de-allocation table by using a DMA operation.
  • Figure 1 is a block diagram of a storage device
  • FIG. 2 is a schematic diagram of an FTL table before processing a deallocation command in Embodiment 2 of the present application;
  • FIG. 3 is a schematic diagram of a valid page table before processing a deallocation command in Embodiment 2 of the present application;
  • FIG. 4 is a schematic diagram of a valid page count table before processing a deallocation command in Embodiment 2 of the present application;
  • FIG. 5 is a flowchart of a method for processing a deallocation command according to Embodiment 2 of the present application.
  • FIG. 6 is a schematic diagram of an FTL table after processing a deallocation command according to Embodiment 2 of the present application;
  • FIG. 7 is a schematic diagram of a valid page table after processing a deallocation command in Embodiment 2 of the present application.
  • FIG. 8 is a schematic diagram of a valid page count table after processing a deallocation command in Embodiment 2 of the present application;
  • Embodiment 9 is a flowchart of processing a read command in Embodiment 2 of the present application.
  • FIG. 10 is a schematic diagram of a de-allocation table before processing a deallocation command in Embodiment 3 of the present application;
  • FIG. 11 is a schematic diagram of a de-allocation table after processing a deallocation command in Embodiment 3 of the present application;
  • FIG. 12A is a flowchart of a method for processing a deallocation command in Embodiment 3 of the present application.
  • FIG. 12B is a flowchart of a method for responding to a read command in Embodiment 3 of the present application.
  • FIG. 12C is a flowchart of a method for responding to a write command in Embodiment 3 of the present application.
  • FIG. 13 is a schematic diagram of a large block in the fourth embodiment of the present application.
  • FIG. 14 is a schematic diagram of an FTL table before processing a deallocation command in Embodiment 4 of the present application;
  • FIG. 15 is a schematic diagram of a valid page table before processing a deallocation command in Embodiment 4 of the present application;
  • FIG. 16 is a schematic diagram of a valid page count table before processing a deallocation command in Embodiment 4 of the present application;
  • FIG. 17 is a flowchart of a method for processing a deallocation command in Embodiment 4 of the present application.
  • FIG. 18 is a schematic diagram of an FTL table after processing a deallocation command according to Embodiment 4 of the present application.
  • FIG. 19 is a schematic diagram of a valid page table after processing a deallocation command in Embodiment 4 of the present application.
  • FIG. 20 is a schematic diagram of a valid page count table after processing a deallocation command in Embodiment 4 of the present application;
  • FIG. 21 is a flowchart of a method for processing a deallocation command according to Embodiment 5 of the present application.
  • a table structure that stores mapping information from a logical address to a physical address is called an FTL table.
  • FTL tables are important metadata in solid state storage devices.
  • the FTL table records the address mapping relationship in the storage device in units of data pages.
  • the FTL table includes entries (or entries) of multiple FTL tables.
  • a correspondence between a logical page address and a physical page is recorded in an entry of each FTL table.
  • a correspondence between consecutive logical page addresses and consecutive multiple physical pages is recorded in an entry of each FTL table.
  • a correspondence between a logical block address and a physical block address is recorded in an entry of each FTL table.
  • the FTL table records the mapping relationship between logical block addresses and physical block addresses, and/or the mapping relationship between logical page addresses and physical page addresses.
  • a logical address range is described. After performing the de-allocation command, there can be different effects. For example, (1) after executing the de-allocation command, when reading the logical address range indicated by the de-allocation command, what is obtained is determined (before performing other write operations on the logical address range); (2) execution After the command is allocated, when the logical address range indicated by the allocation command is read, the result is all 0 (before performing other write operations on the logical address range); (3) after executing the deal allocation command, When reading the range of logical addresses indicated by the de-allocation command, the result obtained can be any value (before performing other write operations on the logical address range). In the de-allocation command or other commands, you can set or select to assign the execution effect of the command. By using the Disassign command, the host can tell the SSD which logical address space no longer stores valid data, so that the SSD does not have to move the expired data when reclaiming storage space.
  • the FTL entry indicated by the logical address range described by the de-allocation command in the FTL table is set to a special flag (for example, 0).
  • the logical address range indicated by the de-allocation command includes 0-7 and 100-103.
  • the contents of the entries in the FTL table in which logical addresses 0-7 and 100-103 are recorded are set to 0.
  • the physical address corresponding to the logical addresses in the FTL table is 0 (meaning a special mark), thereby conforming
  • the result of assigning the specified effect of the command (for example, all 0s) is used as a response to the read command.
  • the logical address range indicated by the de-allocation command may have a different unit size than the entry of the FTL table. For example, in the allocation command, one logical address corresponds to 512 bytes of storage space, and in the FTL table, one entry corresponds to 4 KB (kilobytes) of storage space.
  • the erasing or garbage collection operation is performed in units of physical blocks, chunks, or physical block groups, and the erasing or garbage collection operation is performed in units of physical blocks, and in units of large blocks.
  • the method of performing the erasing or garbage collection operation corresponding to the process of allocating the command is described in detail, and the method of performing the erasing or garbage collection operation corresponding to the physical block group to allocate the command can be obtained by referring to the contents of the two contents. No more details are given.
  • the erasing or garbage collection operation is performed in units of physical blocks in the storage device.
  • a correspondence between a logical page address and a physical page is recorded in an entry of each FTL table.
  • the FTL table, the valid page table, and the valid page count table are maintained.
  • 2 is a schematic diagram of an FTL table before processing a deallocation command in the embodiment, where the FTL table indicates a correspondence between a logical page address and a physical page address.
  • 3 is a schematic diagram of a valid page table before processing a deallocation command in the embodiment (only the valid page table of the physical block associated with the FTL table in FIG. 2 is shown in FIG. 3), and the valid page table records the corresponding physical block.
  • the state of the data stored in the corresponding logical page. 4 is a schematic diagram of a valid page count table before processing a deallocation command in the embodiment, in which the number of physical pages in a valid state in each physical block is recorded in the effective page count table.
  • the valid bits indicated by the horizontal lines in the valid page table shown in FIG. 3 indicate the physical pages corresponding to the logical addresses LBA0-LBA7 shown in FIG. 2, and other valid bits not marked with horizontal lines indicate The physical page corresponding to the other logical address, and the physical page corresponding to the invalid bit is not referenced by any logical address.
  • bitmaps are used as data structures to indicate the validity of individual physical pages of a physical block, it being understood that a variety of other data structures can be used as well.
  • a physical page whose physical address is "PBA 1-4" stores data having a logical address of "LBA 0", and thus a valid page of physical block 1 shown in FIG.
  • the state of the physical page whose physical address is "PBA 1-4" is valid (in FIG. 3, the position in the second row and the first column is indicated by "1").
  • the physical page of physical block 1 shown in FIG. 2 whose physical address is "PBA 1-0" is not referred to by any logical address, and thus the physical address of the physical page 1 shown in FIG. 3 is "
  • the state of the physical page of PBA 1-0" is invalid (in FIG. 3, the position of the first column and the first column is indicated by "0").
  • the valid page count table in FIG. 4 indicates that there are currently 5 physical pages in physical block 0, 9 physical pages in physical block 1 are currently valid, and 0 physical pages in physical block 2 are currently valid. There are currently 11 physical pages in physical block 3 that are valid.
  • each bit in the valid page table is used to indicate a valid physical storage area.
  • the storage space corresponding to the logical page is the same as the storage space of the physical page.
  • 1 bit is used to indicate the state of the corresponding physical page to reduce the occupation of the memory space.
  • a logical page in an FTL table corresponds to 4 KB of storage space
  • a physical page has a storage space of 4 KB (including additional out-of-band storage space).
  • each bit in the valid page table indicates a physical page. status.
  • the storage space corresponding to the logical page is different from the storage space of the physical page.
  • the storage space of the physical page can accommodate multiple logical pages
  • the logical page corresponds to 4 KB of storage space
  • the storage space of the physical page can accommodate Multiple logical pages (eg, four), in this case, in the valid page table, each bit indicates the validity of the physical storage area corresponding to the logical address.
  • the effective page table of physical block 1 includes 2048 bits.
  • the effective page count table records the number of 4 KB of memory space currently stored in the physical block that is referenced by the logical address in the FTL table. For example, if physical block 1 includes 512 16KB physical pages, and the physical address corresponding to 9 LBAs in the FTL table belongs to physical block 1, the effective page count of physical block 1 is 9.
  • FIG. 5 is a flowchart of a method for processing a deallocation command according to the embodiment.
  • the method for processing a deallocation command according to the embodiment includes: obtaining a deallocation command indication in response to receiving a deallocation command.
  • the logical address range(s) for example, LBA0-LBA3.
  • the entries of the locked FTL table are unlocked, allowing other tasks to access these entries of the FTL table.
  • FIG. 6 is a schematic diagram of an FTL table after processing a deallocation command in the embodiment.
  • Figure 2 shows the FTL table before processing the allocation command.
  • FIG. 7 is a schematic diagram of a valid page table after processing a deallocation command in the embodiment.
  • Figure 3 shows the valid page table before processing the assignment command. Accordingly, as shown in FIG.
  • FIG. 8 is a schematic diagram of a valid page count table after processing a deallocation command in the embodiment.
  • 4 is a schematic diagram of a valid page count table before the process of allocating a command in the embodiment.
  • the entry of the FTL table corresponding to LBA0-LBA3 is cleared, and the physical The effective page count of block 1 changes from 9 to 6, and the effective page count of physical block 3 changes from 11 to 10.
  • a valid page count can be used to indicate the priority of the garbage collection operation. For example, when performing a garbage collection operation, the physical block with a low effective page count is preferentially reclaimed.
  • the valid page count table can be a plurality of data structures such as an array, a linear table, and a linked list.
  • the feedback processing to the host is completed.
  • the FTL table is obtained.
  • the host can also be indicated to the host by other means that the read logical address is de-allocated, for example, the read data is not provided to the host, and the status information is used to inform the host that the read logical address is invalid, illegal or in a kind of Or multiple to assign status.
  • the driver of the host generates a read result or data provided to the application that reads the addresses based on the status information notified by the storage device.
  • the FTL table, the valid page table, and the valid page count table in this embodiment may be stored in the DRAM.
  • the command is allocated for efficient processing, and the allocation table is also maintained. Further, the de-allocation table is also written to the NVM, so that when the device is restarted after an abnormal power failure, the correct FTL table can be obtained by de-allocating the information recorded in the table.
  • FIG. 10 and FIG. 11 are schematic diagrams of a de-allocation table, where FIG. 10 is a schematic diagram of a de-allocation table before processing a de-allocation command in the embodiment of the present application; FIG. 11 is a de-allocation after processing a de-allocation command in the embodiment of the present application. Schematic diagram of the table. As shown in FIG. 10 and FIG. 11, in the deallocation table, information corresponding to whether or not each logical address in the FTL table is allocated is stored. By way of example, one bit of storage space is provided for each logical address of the FTL table in the de-allocation table.
  • the logical address when a logical address has been allocated (ie, the logical address has a valid physical address in the FTL table), in the de-allocation table, the logical address is marked as "assigned" (eg, corresponding) The 1-bit memory space is set to 0); when the logical address is not allocated or the de-allocation command has been applied, the logical address is marked as "de-allocated" in the de-allocation table (for example, the corresponding 1-bit memory space is set) Is 1).
  • LBA 0-LBA 7 in the FTL table are all assigned valid physical addresses, so in the de-allocation table shown in FIG. 10, LBA 0-LBA 7 is marked as "assigned" (corresponding 1 bit) The storage space is set to 0).
  • LBA 0 - LBA 3 In response to receiving the de-allocation command, during the execution of the de-allocation command for the logical address range of LBA 0 - LBA 3, as shown in FIG.
  • the LBA 0-LBA 3 in the de-allocation table is marked as "de-allocation” ( The corresponding 1-bit memory space is set to 1), and the LBA 4-LBA 7 in the de-allocation table is still marked as "assigned" (the corresponding 1-bit memory space is set to 0).
  • the physical address of the entry corresponding to the logical address LBA 0-LBA 3 is set to zero.
  • the valid page table and the valid page count table are modified accordingly. Referring to FIG. 3 and FIG. 7, the effective page table of physical block 0 and physical block 1 is also updated accordingly. Similarly, referring to FIG. 4 and FIG. 8, the effective page count table is also updated accordingly.
  • the de-allocation table in this embodiment is stored in the DRAM.
  • the de-allocation table in the DRAM is updated by a DMA operation.
  • FIG. 12A is a flowchart of a method for processing a deallocation command according to Embodiment 3 of the present application.
  • the logical address range indicated by the de-allocation command is acquired (see 1212 in FIG. 12A), for example, de-allocation is performed on the logical address range of LBA 0 - LBA 3. Updating the entries of the de-allocation table (see FIG. 10 and FIG. 11) according to the logical address range indicated by the de-allocation command (see FIG. 12A and FIG. 11), for example, the de-allocation table shown in FIG.
  • the FTL table entry is updated according to the logical address range indicated by the de-allocation command, for example, the FTL entry corresponding to the one or more logical addresses indicated by the de-allocation command is cleared, or set to a specified value ( See 1218 in Figure 12A.
  • the entry of the FTL table corresponding to the one or more logical addresses to be updated is also locked (refer to 1216 in FIG. 12A), so as to prevent other tasks from being read during the update of the FTL entry. Take these FTL entries. And after updating the FTL table, the entries of the FTL table corresponding to the updated one or more logical addresses are also unlocked (refer to 1220 in FIG. 12A).
  • the valid page table of the physical block corresponding to the physical address of the entry of the updated FTL table (see FIG. 7 and 1222 in FIG. 12A) and the valid page count table (see FIG. 8 and 1224 in FIG. 12A) are also updated. .
  • FIG. 12B is a flowchart of a method for responding to a read command in Embodiment 3 of the present application.
  • the host when the de-allocation table update is completed, the host is informed that the de-allocation command execution is completed. After the host reads the assigned logical address, it should receive a specified indication such as all 0s.
  • the de-allocation table in response to receiving the read command (see 1230 in Fig. 12B), the de-allocation table (see Fig. 11) is queried to determine whether the logical address read by the read command is de-allocated (see 1232 in Fig. 12B).
  • the de-allocation table indicates that the read logical address is in the de-allocation state, then all 0s or other specified indications are used as responses to the read command (see 1234 in Figure 12B). Only when the area allocation table indicates that the read logical address has been allocated, the FTL table is queried to obtain the physical address corresponding to the logical address to be read (see 1236 in FIG. 12B), and the data is read from the obtained physical address as Response to a read command (see 1238 in Figure 12B).
  • the tag storage device In response to receiving the de-allocation command (see 1210 in Figure 12A), the tag storage device is executing a de-allocation command. In this case, if a read command is received, the de-allocation table is first queried (see 1232 in Fig. 12B). When the execution of the de-allocation command is completed, for example, after the execution of step 1218 or step 1220 shown in FIG. 12A is completed, the tag storage device has completed execution of the de-allocation command. In this case, if a read command is received, step 1232 in Fig. 12B is not necessarily performed, and step 1236 in Fig. 12B is directly executed.
  • FIG. 12C is a flowchart of a method for responding to a write command in Embodiment 3 of the present application.
  • its de-allocation table indicates that all logical addresses are in a de-allocation state.
  • the table corresponding to the logical address of the de-allocation table and the data to be written is modified to the allocated state.
  • the de-allocated logical address in the de-allocation table is modified again to the de-allocation state.
  • step 12C a physical address is assigned to the write command, and the FTL table is updated with the logical address indicated by the write command and the assigned physical address (see 1242 in Fig. 12C).
  • the data is written to the assigned physical address and the write command processing is completed to the host (see 1244 in Fig. 12C).
  • step 1242 the write command processing is completed to the host before the data is written to the physical address.
  • the valid page table and valid page count table are also updated to be a response to the physical block being written to the data.
  • the de-allocation table is also updated, and the entry of the logical address to be written in the de-allocation table is set to be allocated (see 1248 in Fig. 12C).
  • the order of step 1244, step 1246, and step 1248 may be adjusted, or may be performed in parallel or simultaneously.
  • step 1244, step 1246, and step 1248 occur after step 1242.
  • FIG. 13 is a schematic diagram of a large block.
  • a large block is constructed on every 16 logical units (LUNs).
  • Each chunk consists of 16 physical blocks from each of the 16 logical units (LUNs).
  • chunk 0 includes physical block 0 from each of 16 logical units (LUNs)
  • chunk 1 includes physical block 1 from each logical unit (LUN).
  • each logical address corresponds to 4 KB of storage space
  • each physical page in the NVM includes 4 physical units, each of which holds data corresponding to 1 logical address (optionally, Also included is out-of-band data such as check data.
  • FIG. 14 is a schematic diagram of the FTL table before processing the deallocation command in the embodiment. Referring to FIG.
  • the PBA 0-4 recorded in the FTL table indicates the physical unit of the address 0 of the large block 0, and the PBA 1-6 indicates the large
  • the physical unit of block 1 has an address of 6
  • the PBA0-9 recorded in the FTL table indicates the physical unit whose address of the large block 0 is 9
  • the PBA0-15 indicates the physical unit whose address of the large block 0 is 15.
  • a page strip is constructed in chunks, and the physical pages of the same physical address within each logical unit (LUN) constitute a "page strip.”
  • LUN logical unit
  • physical page 0-0, physical page 0-1, ... and physical page 0-x constitute a page strip 0.
  • physical page 0-0, physical page 0-1... physical page 0-14 is used to store user data
  • physical pages 0-15 are used to store check data calculated from all user data in the strip.
  • the physical page used to store the verification data can be located anywhere in the page strip, which is by way of example and not limitation.
  • the physical page 2-0, the physical page 2-1, ... and the physical page 2-x constitute the page strip 2.
  • a valid page table is provided for each large block for recording the state of data (data unit) corresponding to the logical address stored in the corresponding large block.
  • 15 is a valid page table before processing the deallocation command in the embodiment. It should be noted that, in FIG. 15, the valid bits indicated by the horizontal lines in the valid page table indicate the logical addresses in the FTL table of FIG.
  • the physical unit corresponding to LBA0-LBA7, the other valid bits not marked with a horizontal line indicate the physical unit corresponding to other logical addresses, and the physical unit corresponding to the invalid bit is not referenced by any logical address.
  • the physical unit whose physical address is "PBA 0-4" stores the data whose logical address is "LBA 0", and thus in the valid page table of the large block 0, the address is The state of the physical unit of "PBA 0-4" is valid (in FIG. 15, indicated by "1" in the second row and first column of the valid page table (large block 0)).
  • the physical unit of the block 0 whose address is "PBA 0-0" shown in FIG. 15 is not referred to by any logical address, and thus the physical address of the address "PBA 0-0" in the valid page table of the large block 0
  • the state of the cell is invalid (in FIG.
  • 1 bit is used to indicate the state of the corresponding one physical unit to reduce the occupation of the memory space.
  • 16 is a valid page count table before processing the deallocation command in the embodiment, in which the number of physical units in the active state in each large block is recorded in the valid page count table.
  • the number of physical units in the active state in each large block is recorded in the valid page count table.
  • FIG. 16 there are currently 9 physical units in the large block 0, 11 physical units in the large block 1 are currently valid, and 0 physical units in the large block 2 are valid, and the large block 3 is in the middle. There are 11 physical units available.
  • FIG. 17 is a flowchart of a method for processing a deallocation command according to the embodiment.
  • the method for processing a deallocation command according to this embodiment includes: responding to receiving a deallocation command (refer to 1710 in FIG. 17). And obtaining the logical address range(s) to which the command command is assigned (for example, LBA0-LBA3) (refer to 1720 in FIG. 17).
  • the entry of the FTL table corresponding to the logical address(s) (for example, LBA0-LBA3) is cleared, or the entry of the FTL table is set to a specified value (refer to 1740 in FIG. 17).
  • a specified value (refer to 1740 in FIG. 17).
  • zero or other specified value is taken as the physical address, indicating that reading the physical address will acquire the value specified for executing the de-allocation command (for example, a value of all 0s or a value of all specified values).
  • the entries of the locked FTL table are unlocked (see 1750 in Figure 17), allowing other tasks to access these entries of the FTL table.
  • FIG. 18 is a schematic diagram of an FTL table after processing a deallocation command in the embodiment.
  • 14 is a schematic diagram of the FTL table before the process of assigning a command in the embodiment.
  • the physical addresses PBA 0-4, PBA 1-6, PBA 0-9, and PBA 0-10 no longer store valid data.
  • FIG. 19 is a process of assigning a life in the embodiment.
  • FIG. 15 is a schematic diagram of a valid page table before the process of allocating a command in the embodiment.
  • the physical unit of the chunk 0 is PBA 0-4, and the physical units of PBA 0-9 and PBA0-10 become invalid (for example, the corresponding bit is set to 0), and in the valid page table of the chunk 1, the physical unit of the chunk 1 whose address is PBA 1-6 becomes invalid.
  • FIG. 20 is a schematic diagram of the valid page count table after the process of allocating the command in the embodiment.
  • 16 is a schematic diagram of a valid page count table before the process of allocating a command in the embodiment.
  • the effective page count of chunk 0 changes from 9 to 6
  • the effective page count of chunk 1 changes from 11 to 10.
  • a valid page count can be used to indicate the priority of the garbage collection operation. For example, when performing a garbage collection operation, a large chunk with a low effective page count is preferentially reclaimed.
  • an erase operation can be performed immediately to reclaim the storage space.
  • the priority of the bulk of the valid page number being updated for garbage collection is also updated (refer to 1780 in FIG. 17), thereby performing the garbage collection operation according to Large chunks of garbage collection priority to select the chunks to be recycled.
  • the valid page count table can be a plurality of data structures such as an array, a linear table, and a linked list.
  • the feedback processing to the host is completed.
  • the FTL table is obtained in response to receiving the read command.
  • the host can also be indicated to the host by other means that the read logical address is de-allocated, for example, the read data is not provided to the host, and the status information is used to inform the host that the read logical address is invalid, illegal or in a kind of Or multiple to assign status.
  • the driver of the host generates a read result or data provided to the application that reads the addresses based on the status information notified by the storage device.
  • Embodiment 4 of the present application if the allocation command indicates a large number of logical address ranges (for example, LBA 10000-LBA 20000), the clearing of multiple FTL table entries is Time consuming.
  • There are several ways to speed up the update of FTL table entries For example, each time multiple FTL table entries are updated, and during the update of multiple FTL table entries by one CPU, other CPUs are prevented from accessing the updated FTL table entries, or other CPUs are not allowed to try to access the updated FTL table. Entry.
  • a DMA operation is used to update the memory space in which multiple FTL table entries are stored.
  • the entries of the FTL table in the storage space are updated each time, and the operations of accessing the FTL table entries are blocked during the update of the FTL table entries in the storage space to reduce random access to the memory. To speed up the update of FTL table entries.
  • the FTL table, the valid page table, and the valid page count table in this embodiment may be stored in the DRAM.
  • the command is allocated for efficient processing, and the allocation table is also maintained. Further, the de-allocation table is also written to the NVM, so that when the device is restarted after an abnormal power failure, the correct FTL table can be obtained by de-allocating the information recorded in the table.
  • the de-allocation table shown in Figs. 10 and 11 is used.
  • the storage corresponds to the FTL table. Whether each logical address is assigned information. By way of example, one bit of storage space is provided for each logical address of the FTL table in the de-allocation table.
  • FIG. 21 is a flowchart of a method for processing a deallocation command according to Embodiment 5 of the present application.
  • the logical address range(s) indicated by the de-allocation command is obtained (see 2112 in FIG. 21), for example, the logic to be used for LBA 0 - LBA 3.
  • the address range is executed to be assigned. Updating the entries of the de-allocation table (refer to FIG. 10 and FIG. 11) according to the logical address range indicated by the de-allocation command (refer to FIG. 21 and FIG. 11), for example, the de-allocation table shown in FIG.
  • the FTL table entry is updated according to the logical address range indicated by the de-allocation command, for example, the FTL entry corresponding to the one or more logical addresses indicated by the de-allocation command is cleared, or set to a specified value ( See 2118 in Figure 21).
  • the entry of the FTL table corresponding to the one or more logical addresses to be updated is also locked (refer to 2116 in FIG. 21), so as to prevent other tasks from being read during the update of the FTL entry. Take these FTL entries.
  • the entries of the FTL table corresponding to the updated one or more logical addresses are also unlocked (refer to 2120 in FIG. 21).
  • the valid page table of the large block corresponding to the physical address of the entry of the updated FTL table (see 2122 in FIG. 7 and FIG. 21) and the valid page count table are also updated (see FIG. 8 and FIG. 21, 2124). ).

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Abstract

L'invention concerne un procédé de traitement d'une commande de désattribution et un dispositif de mémoire. Le procédé de traitement d'une commande de désattribution consiste : à acquérir, en fonction de la commande de désattribution, une plage d'adresses logiques indiquée par la commande de désattribution ; à mettre à jour une table FTL et à définir une entrée de la table FTL correspondant à la plage d'adresses logiques indiquée par la commande de désattribution en tant que première valeur désignée ; et à indiquer que l'exécution de la commande de désattribution est achevée.
PCT/CN2017/100317 2016-09-05 2017-09-04 Procédé de traitement de commande de désattribution, et dispositif de mémoire WO2018041258A1 (fr)

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CN201610804881.1A CN107797934B (zh) 2016-09-05 2016-09-05 处理去分配命令的方法与存储设备
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CN201610804881.1 2016-09-05
CN201610803054.0A CN107797938B (zh) 2016-09-05 2016-09-05 加快去分配命令处理的方法与存储设备

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