WO2018004160A1 - Wafer and manufacturing method therefor - Google Patents

Wafer and manufacturing method therefor Download PDF

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Publication number
WO2018004160A1
WO2018004160A1 PCT/KR2017/006235 KR2017006235W WO2018004160A1 WO 2018004160 A1 WO2018004160 A1 WO 2018004160A1 KR 2017006235 W KR2017006235 W KR 2017006235W WO 2018004160 A1 WO2018004160 A1 WO 2018004160A1
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wafer
mode
tzdb
value
defect
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PCT/KR2017/006235
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French (fr)
Korean (ko)
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이우성
김자영
신정원
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에스케이실트론 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Definitions

  • the embodiment relates to a wafer and a method of manufacturing the same, and more particularly, to an improvement in TZDB characteristics of a wafer.
  • Silicon wafers include a single crystal growth process for making a single crystal ingot, a slicing process for slicing the single crystal ingot to obtain a thin disk-shaped wafer, a polishing process for mirror- mirroring the wafer, and polishing
  • the wafer is polished and manufactured through a cleaning process of removing abrasives or foreign matters attached to the wafer to be used as a substrate of a semiconductor device.
  • Growth conditions of the single crystal ingot during the single crystal growth process determine the crystal quality and crystal defect region of the single crystal silicon. That is, depending on the growth conditions of the single crystal ingot, the vacancy-type defects predominate, and the O-band (Oxidation-Induced Stacking Fault) (OSF: Oxidation Induced Stacking Fault), which has a defect in which supersaturated vacancy is aggregated, exists. Induced defect band), VDP area with vacancy-type defects but no cohesive defects, IDP area with interstitial defects but no coherent defects, and supersaturated interstitial silicon due to interstitial defects LDP regions having aggregated defects are present.
  • O-band Oxidation-Induced Stacking Fault
  • the crystal defect regions of the single crystal silicon can be distinguished by a Cu-haze method using a copper haze phenomenon by contaminating the surface of the single crystal silicon with a copper (Cu) contamination solution.
  • BMD Bit Micro Defect
  • DZ layer defected zone
  • BMDs are not generated inside the wafer manufacturing process, but subsequent heat treatment of a device process or the like allows deeper than the device active region while maintaining a DZ layer without BMD near the wafer surface, which is a device active region.
  • the silicon wafer may be subjected to a rapid thermal process (RTP).
  • FIG. 1A is a diagram illustrating crystal regions according to Cu haze characteristics of a wafer
  • FIG. 1B is a diagram illustrating TZDB (Time Zero Dielectric Breakdown) when rapid heat treatment is not performed
  • FIG. It is a figure which shows TZDB.
  • FIG. 1A an O band region, an interstitial dominant point defect zone (IDP), and a vacancy dominant point defect zone (VDP) region of the wafer are illustrated.
  • IDP interstitial dominant point defect zone
  • VDP vacancy dominant point defect zone
  • FIG. 1B shows good TZDB characteristics on the surface of the wafer without rapid heat treatment.
  • FIG. 1C defects of the C mode, the B mode, and the A mode are shown on the surface of the wafer after the rapid heat treatment.
  • a mode has a TZDB value of 0 to 4 Mega volt / cm
  • B mode has a TZDB value of 4 to 8 Mega volt / cm
  • C mode has a TZDB value of 8 to 10 ega volt / cm
  • C + mode The TZDB value may be a region of 10 to 12 Mega Volt / cm and a steady state (Pass) of 12 Mega Volt / cm or more.
  • the embodiment is intended to prevent degradation of the TZDB in the rapidly heat treated wafer.
  • An embodiment is a wafer, wherein in mode zero time breakdown (TZDB) evaluation, A mode defect and B mode defect C mode defect and C + mode defect are less than 1%, respectively, wherein the A mode defect has the TZDB value of 0 to 4 Mega volt / cm, the B mode defect has the TZDB value of 4 to 8 Mega volt / cm, the C mode defect has the TZDB value of 8 to 10 Mega volt / cm, and the C + mode defect has the TZDB value. It provides a wafer of 10 to 12 Mega volt / cm.
  • TZDB mode zero time breakdown
  • the wafer may be removed from the surface after a rapid thermal process, for example by a thickness of 5 micrometers to 7 micrometers.
  • Rapid heat treatment can rapidly cool the wafer, and after heating for about tens of seconds to a temperature around 1200 °C.
  • nano voids may be injected into the surface of the wafer.
  • Nanovoids may be larger in size or density at the surface than the bulk region of the wafer.
  • the wafer may have a planar diameter of an interstitial dominant point defect zone (IDP) of at least 40% of the total diameter.
  • IDP interstitial dominant point defect zone
  • the wafer may have a mixture of IDP regions and VDP (Vacancy Dominant Point defect zone) regions.
  • Another embodiment includes preparing a wafer of silicon single crystal; Rapid thermal process of the wafer; And removing 5 to 7 micrometers from the surface of the rapidly heat-treated wafer.
  • Rapid heat treatment may be carried out in a nitrogen atmosphere, argon atmosphere, ammonia atmosphere or a mixed atmosphere thereof.
  • the silicon single crystal ingot can be grown by the Czochralski method.
  • the wafer and the method of manufacturing the same according to the embodiment can remove the thickness of the microseed wafer from the surface by 5 micrometers to 7 micrometers, for example 5.5 micrometers, in the bulk direction after rapid heat treatment. And, a wafer manufactured by this method can exhibit improved TZDB characteristics as described above. In addition, it can be seen that the wafers have improved TZDB characteristics when the width of the IDP region on the surface is 40% or more of the total width.
  • 1A is a diagram illustrating crystal regions according to Cu haze characteristics of a wafer
  • 1B is a diagram illustrating TZDB when rapid heat treatment is not performed.
  • Figure 1c is a view showing the TZDB after the rapid heat treatment
  • 3A to 3E are diagrams illustrating crystal regions according to Cu haze characteristics of wafers of Comparative Examples 1 to 3 and Examples 1 to 2;
  • 4A to 4E show TZDB characteristics after removing 4 micrometers from the surfaces of the wafers of Comparative Examples 1 to 3 and Examples 1 and 2,
  • 5A to 5E show TZDB characteristics after removing 5.5 micrometers from the surfaces of the wafers of Comparative Examples 1-3 and Examples 1-2;
  • 6A to 6C show TZDB characteristics after the removal of the surfaces of the wafers of Comparative Examples 1-2 and Example 7 by 7 micrometers
  • 7A to 7E are graphs showing TZDB characteristics according to removal amounts of the surfaces of the wafers of Comparative Examples 1 to 3 and Examples 1 and 2;
  • the upper (up) or the lower (down) (on or under) when described as being formed on the “on” or “on” (under) of each element, the upper (up) or the lower (down) (on or under) includes both the two elements are in direct contact with each other (directly) or one or more other elements are formed indirectly formed (indirectly) between the two elements.
  • each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description.
  • the size of each component does not necessarily reflect the actual size.
  • the surface of the rapidly heat treated wafer may be removed from 5 to 7 micrometers.
  • Silicon single crystal wafers manufactured by the above-described process can measure A mode defects, B mode defects, C mode defects, and C + mode defects, respectively, when measuring time zero dielectric breakdown (TZDB). It may be due to.
  • TZDB time zero dielectric breakdown
  • V / is the ratio of the pulling speed V of the single crystal to the average value G of the temperature gradient in the single crystal in the direction of the pulling axis of the single crystal (° C./mm).
  • G the temperature gradient in the single crystal in the direction of the pulling axis of the single crystal (° C./mm).
  • vacancy may be determined at the wafer surface and in the bulk region.
  • the initial vacancy concentration due to V / G is constantly shown as a dotted line in the longitudinal axis direction.
  • Nano-voids are voids of several nanometers in diameter, may occur in the rapid heat treatment process of the wafer, and the frequency of occurrence may vary for each crystal region of the wafer. That is, vacancy varies for each crystal region of the wafer before the rapid heat treatment, and accordingly, nanovoids generated after the rapid heat treatment of the wafer may also vary for each crystal region.
  • the concentration of bacon sea gradually decreases from the surface of the wafer to a certain thickness in the bulk direction, and is almost constant inside a certain thickness.
  • the size of the nano voids gradually decreases from the surface of the wafer to a predetermined thickness in the bulk direction, and is almost constant inside the predetermined thickness.
  • Polished wafers may be prepared by slicing, grinding, lapping and mirror polishing a single crystal ingot grown by CZ.
  • a wafer can be heat-treated rapidly. Rapid heat treatment may be carried out in a nitrogen atmosphere, argon atmosphere, ammonia atmosphere or a mixed atmosphere thereof. The rapid heat treatment can rapidly cool the wafer again after the temperature is rapidly raised, held at a temperature of about 1200 ° C. for several tens of seconds.
  • the injection of nanovoids from the wafer surface may occur during the high temperature holding of 1200 ° C. in a nitrogen atmosphere, and the nanovoids may be larger in size or density at the surface than the bulk area of the wafer.
  • Table 1 shows the results of measuring the TZDB of the wafers of Comparative Examples 1 to 3 and Examples 1 to 2 by removing 4 micrometers of the surface after the rapid heat treatment step described above.
  • FIGS. 4A to 4E are Comparative Examples 1 to 3 and Example 1 It is a figure which shows the TZDB characteristic after removing 4 micrometers of the surface of the wafer of -2.
  • IDP area width (mm) object TZDB (Ratio by Mode,%) A mode B mode C mode C + mode yield 37.5 Comparative Example 1 0.56 2.25 23.41 18.91 54.87 45 Comparative Example 2 0 27.72 30.34 14.04 27.9 52.5 Comparative Example 3 1.12 30.15 45.88 14.42 8.43 132 Example 1 0.6 0.2 0.7 3.9 94.6 67.5 Example 2 0.56 0.56 3.56 5.43 89.89
  • the width of the IDP region means the width of the IDP region in the radial region.
  • the width of the IDP region is 132 millimeters in the radius region of 150 millimeters.
  • a VDP (Vacancy Dominant Point defect zone) region or an O-band (Oxidation-induced defect Band) region may exist.
  • mode A has a TZDB value of less than 0 to 4 Mega volt / cm
  • mode B has a TZDB value of less than 4 to 8 Mega volt / cm
  • mode C has a TZDB value of less than 8 to 10 ega volt / cm
  • the C + mode may be a region where the TZDB value is less than 10 to 12 Mega Volt / cm.
  • the width of the IDP region may be less than 40% of the width of the wafer, and the sum of the regions where the TZDB values of the A mode, the B mode, the C mode, and the C + mode are less than 12 Mega Volt / cm. 45.13%, 72.1%, and 91.57%, respectively.
  • the sum of the regions in which the TZDB values of the A mode, the B mode, the C mode, and the C + mode is less than 12 Mega Volt / cm is 5.4% and 10.11%, respectively.
  • the wafers of Comparative Examples 1 to 3 had a pass rate of 54.87%, 27.9% and 8.43%, respectively, and the wafers of Examples 1 to 2 had a yield of 94.6% and 89.89%, respectively.
  • a region having a TZDB value of less than 12 Mega Volt / cm among A mode, B mode, C mode, and C + mode may decrease.
  • the surface of the wafer was further removed 1.5 micrometers.
  • 5A to 5E show TZDB characteristics of the wafers of Comparative Examples 1 to 3 and Examples 1 and 2 according to Table 2, respectively, and are TZDB characteristics after removing 5.5 micrometers from the surface of the wafer.
  • Increasing the amount of removal of the surface of the wafer from Tables 1 and 2 further reduces the area where the TZDB values of A mode, B mode and C mode, and C + mode are less than 12 Mega Volt / cm.
  • the surface of the wafer was removed 1.5 micrometers.
  • 6A to 6C show the TZDB characteristics of the wafers of Comparative Examples 1 to 2 and Example 1, and the TZDB of the wafers having a removal amount of 7 micrometers in total is measured.
  • the TZDB characteristics when the surface removal amount of the wafer is 7 micrometers from FIGS. 6A to 6C are almost the same as the TZDB characteristics when the surface removal amount of the wafer is 5.5 micrometers in Table 2 and FIGS. 5A to 5E. It can be seen.
  • the TZDB measurement result showed a yield of 98% or more.
  • a mode of less than 1% was also measured on the wafers of Examples 1 and 2, but this may be due to noise generated during pretreatment for TZDB evaluation. The noise may be due to defects in the wafering process, particle addition, and contamination / measuring equipment failure.
  • the wafer manufacturing method after the rapid heat treatment of the polysid wafer, it is possible to remove from the surface by the thickness of 5 micrometers to 7 micrometers, for example 5.5 micrometers. And, a wafer manufactured by this method can exhibit improved TZDB characteristics as described above. In addition, it can be seen that the wafers have improved TZDB characteristics when the width of the IDP region on the surface is 40% or more of the total width.
  • FIGS. 7A to 7E are graphs showing TZDB characteristics according to removal amounts of the surfaces of the wafers of Comparative Examples 1 to 3 and Examples 1 and 2;
  • the wafers of Comparative Examples 1 and 2 and Example 1 of FIGS. 7A, 7B and 7D are shown with data removed from the surface of 4 micrometers, 5.5 micrometers and 7 micrometers, respectively, and Comparative Examples of FIGS. 7C and 7E
  • the wafers of 3 and Example 2 are shown with data removed by 4 micrometers and 5.5 micrometers, respectively.
  • the wafers of Comparative Examples 1 to 3 even if the amount of removal in the bulk direction from the surface is increased, the TZDB characteristics are not significantly improved.
  • the wafers of Examples 1 to 2 have a C + mode of less than 1%, which is a region where the TZDB value is less than 12 Mega Volt / cm when the amount of removal from the surface in the bulk direction is 5.5 micrometers or more, but in the measurement process as described above. May be due to noise.
  • the wafer according to the embodiment has improved TZDB characteristics.

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Abstract

An embodiment provides a wafer having an A mode defect, a B mode defect, a C mode defect, and a C+ mode defect, which are respectively less than 1% in a time zero dielectric breakdown (TZDB) evaluation, wherein the A mode defect has a TZDB value of 0 to 4 mega volt/cm, the B mode defect has a TZDB value of 4 to 8 mega volt/cm, the C mode defect has a TZDB value of 8 to 10 mega volt/cm, and the C+ mode has a TZDB value of 10 to 12 mega volt/cm.

Description

웨이퍼 및 그 제조방법Wafer and its manufacturing method
실시예는 웨이퍼 및 그 제조방법에 관한 것으로, 보다 상세하게는 웨이퍼의 TZDB 특성 향상에 관한 것이다.The embodiment relates to a wafer and a method of manufacturing the same, and more particularly, to an improvement in TZDB characteristics of a wafer.
실리콘 웨이퍼는, 단결정 잉곳(Ingot)을 만들기 위한 단결정 성장 공정과, 단결정 잉곳을 슬라이싱(Slicing)하여 얇은 원판 모양의 웨이퍼를 얻는 슬라이싱 공정과, 상기 웨이퍼를 경면화하는 연마(Polishing) 공정과, 연마된 웨이퍼를 연마하고 웨이퍼에 부착된 연마제나 이물질을 제거하는 세정 공정을 통하여 제조되어, 반도체 디바이스의 기판으로 사용하게 된다.Silicon wafers include a single crystal growth process for making a single crystal ingot, a slicing process for slicing the single crystal ingot to obtain a thin disk-shaped wafer, a polishing process for mirror- mirroring the wafer, and polishing The wafer is polished and manufactured through a cleaning process of removing abrasives or foreign matters attached to the wafer to be used as a substrate of a semiconductor device.
단결정 성장 공정 중 단결정 잉곳의 성장 조건은 단결정 실리콘의 결정 품질 및 결정 결함 영역을 결정한다. 즉, 단결정 잉곳의 성장 조건에 따라서 베이컨시형 점결함이 우세하여 과포화된 베이컨시가 응집된 결함을 갖는 v-rich 영역, 산화 유기 적층 결함(OSF:Oxidation Induced Stacking Fault)이 존재하는 O band(Oxidation-induced defect Band) 영역, 베이컨시형 점결함이 우세하나 응집된 결함이 없는 VDP 영역, 인터스티셜 점결함이 우세하나 응집된 결함이 없는 IDP 영역, 그리고 인터스티셜 점결함이 우세하여 과포화된 인터스티셜 실리콘이 응집된 결함을 갖는 LDP 영역 등이 존재한다. Growth conditions of the single crystal ingot during the single crystal growth process determine the crystal quality and crystal defect region of the single crystal silicon. That is, depending on the growth conditions of the single crystal ingot, the vacancy-type defects predominate, and the O-band (Oxidation-Induced Stacking Fault) (OSF: Oxidation Induced Stacking Fault), which has a defect in which supersaturated vacancy is aggregated, exists. Induced defect band), VDP area with vacancy-type defects but no cohesive defects, IDP area with interstitial defects but no coherent defects, and supersaturated interstitial silicon due to interstitial defects LDP regions having aggregated defects are present.
그리고, 구리(Cu) 오염 용액으로 단결정 실리콘 표면을 오염시켜 구리의 헤이즈(Haze) 현상을 이용하는 Cu-haze법 등으로 단결정 실리콘의 결정 결함 영역을 구별할 수 있다.The crystal defect regions of the single crystal silicon can be distinguished by a Cu-haze method using a copper haze phenomenon by contaminating the surface of the single crystal silicon with a copper (Cu) contamination solution.
그리고, 상술한 공정으로 성장된 웨이퍼에 열처리가 실시되면, 실리콘 웨이퍼 내의 과포화된 산소가 산소 석출물로서 석출된다. 이러한 산소 석출물은 BMD(Bulk Micro Defect)라 칭한다. BMD가 웨이퍼 내의 디바이스 활성 영역에서 발생하면, 접합 리크(leak) 등의 디바이스 특성에 악영향을 끼치지만, 디바이스 활성 영역 이외의 벌크(bulk) 중에 존재하면, 디바이스 프로세스 중에 혼입된 금속 불순물을 포획하는 게터링 사이트로서 작용할 수 있다.When heat treatment is performed on the wafer grown in the above-described process, supersaturated oxygen in the silicon wafer is precipitated as an oxygen precipitate. Such oxygen precipitates are called BMD (Bulk Micro Defect). When BMDs occur in the device active region within the wafer, they adversely affect device characteristics such as junction leaks, but when present in bulk other than the device active region, trapping metallic impurities incorporated during the device process It can act as a turing site.
따라서, 웨이퍼의 제조 공정에서 웨이퍼의 벌크 중에 BMD를 형성하고, 디바이스의 활성 영역인 표면 근방은 BMD 등이 존재하지 않는 무결함 영역(Denuted Zone; 이하 DZ층이라 함)을 유지할 필요가 있다.Therefore, it is necessary to form BMD in the bulk of the wafer in the manufacturing process of the wafer, and to maintain the defected zone (hereinafter referred to as DZ layer) where BMD and the like are not present in the vicinity of the surface, which is the active region of the device.
이를 위하여 웨이퍼의 제조 공정에서는 내부에 BMD는 발생하고 있지 않지만, 이후의 디바이스 프로세스 등의 열처리를 행함으로써, 디바이스 활성 영역인 웨이퍼 표면 근방에는 BMD가 없는 DZ층을 유지한 채, 디바이스 활성 영역보다 깊은 벌크 중에는 BMD가 형성되어 게터링 능력을 갖도록 설계된 실리콘 웨이퍼의 제조방법으로서, 실리콘 웨이퍼를 급속 열처리(Rapid Thermal Process, RTP)할 수 있다.To this end, BMDs are not generated inside the wafer manufacturing process, but subsequent heat treatment of a device process or the like allows deeper than the device active region while maintaining a DZ layer without BMD near the wafer surface, which is a device active region. As a method for manufacturing a silicon wafer designed to have a gettering capability by forming a BMD in bulk, the silicon wafer may be subjected to a rapid thermal process (RTP).
도 1a는 웨이퍼의 Cu haze 특성에 따른 결정 영역을 구분한 도면이고, 도 1b는 급속 열처리를 진행하지 않은 경우의 TZDB(Time Zero Dielectric Breakdown)를 나타낸 도면이고, 도 1c는 급속 열처리를 진행한 후의 TZDB를 나타낸 도면이다.FIG. 1A is a diagram illustrating crystal regions according to Cu haze characteristics of a wafer, and FIG. 1B is a diagram illustrating TZDB (Time Zero Dielectric Breakdown) when rapid heat treatment is not performed, and FIG. It is a figure which shows TZDB.
도 1a에서 웨이퍼의 O Band 영역과 IDP(Interstitial Dominant Point defect zone) 및 VDP(Vacancy Dominant Point defect zone) 영역이 도시되고 있다.In FIG. 1A, an O band region, an interstitial dominant point defect zone (IDP), and a vacancy dominant point defect zone (VDP) region of the wafer are illustrated.
도 1b에서 급속 열처리를 진행하지 않은 상태에서 웨이퍼의 표면에서는 양호한 TZDB 특성을 보이고 있다. 도 1c에서 급속 열처리를 진행 한 후의 웨이퍼의 표면에, C 모드와 B 모드 및 일부 영역에서 A 모드 결함까지 나타나고 있다.1B shows good TZDB characteristics on the surface of the wafer without rapid heat treatment. In FIG. 1C, defects of the C mode, the B mode, and the A mode are shown on the surface of the wafer after the rapid heat treatment.
여기서, A 모드는 TZDB 값이 0 내지 4 Mega volt/cm이고, B 모드는 TZDB 값이 4 내지 8 Mega volt/cm이고, C 모드는 TZDB 값이 8 내지 10 ega volt/cm이고, C+ 모드는 TZDB 값이 10 내지 12 Mega Volt/cm이고 정상 상태(Pass)는 12 Mega Volt/cm이상인 영역일 수 있다.Here, A mode has a TZDB value of 0 to 4 Mega volt / cm, B mode has a TZDB value of 4 to 8 Mega volt / cm, C mode has a TZDB value of 8 to 10 ega volt / cm, and C + mode The TZDB value may be a region of 10 to 12 Mega Volt / cm and a steady state (Pass) of 12 Mega Volt / cm or more.
실시예는 급속 열처리된 웨이퍼에서 TZDB의 열화를 방지하고자 한다.The embodiment is intended to prevent degradation of the TZDB in the rapidly heat treated wafer.
실시예는 웨이퍼에 있어서, TZDB(Time Zero Dielectric Breakdown) 평가시 A 모드 결함과 B 모드 결함 C 모드 결함 및 C+ 모드 결함이 각각 1% 미만이고, 여기서 상기 A 모드 결함은 상기 TZDB 값이 0 내지 4 Mega volt/cm이고, 상기 B 모드 결함은 상기 TZDB 값이 4 내지 8 Mega volt/cm이고, 상기 C 모드 결함은 상기 TZDB 값이 8 내지 10 Mega volt/cm이고, C+ 모드 결함은 상기 TZDB 값이 10 내지 12 Mega volt/cm인 웨이퍼를 제공한다.An embodiment is a wafer, wherein in mode zero time breakdown (TZDB) evaluation, A mode defect and B mode defect C mode defect and C + mode defect are less than 1%, respectively, wherein the A mode defect has the TZDB value of 0 to 4 Mega volt / cm, the B mode defect has the TZDB value of 4 to 8 Mega volt / cm, the C mode defect has the TZDB value of 8 to 10 Mega volt / cm, and the C + mode defect has the TZDB value. It provides a wafer of 10 to 12 Mega volt / cm.
웨이퍼는 급속 열처리(Rapid thermal process) 후 표면이 제거될 수 있으며, 예를 들면 5 마이크로 미터 내지 7 마이크로 미터의 두께만큼 제거될 수 있다.The wafer may be removed from the surface after a rapid thermal process, for example by a thickness of 5 micrometers to 7 micrometers.
급속 열처리는 상기 웨이퍼를 급속하게 승온하고, 1200℃ 전후의 온도로 수십 초 정도 가열 후, 급속하게 냉각시킬 수 있다.Rapid heat treatment can rapidly cool the wafer, and after heating for about tens of seconds to a temperature around 1200 ℃.
웨이퍼의 가열 중, 상기 웨이퍼의 표면으로 나노 보이드가 주입될 수 있다.During heating of the wafer, nano voids may be injected into the surface of the wafer.
나노 보이드는 상기 웨이퍼의 벌크 영역보다 표면에서 크기 또는 밀도가 더 클 수 있다.Nanovoids may be larger in size or density at the surface than the bulk region of the wafer.
웨이퍼는 IDP(Interstitial Dominant Point defect zone)의 면방향 직경이 전체 직경의 40% 이상일 수 있다.The wafer may have a planar diameter of an interstitial dominant point defect zone (IDP) of at least 40% of the total diameter.
웨이퍼는 IDP 영역과 VDP(Vacancy Dominant Point defect zone) 영역이 혼재될 수 있다.The wafer may have a mixture of IDP regions and VDP (Vacancy Dominant Point defect zone) regions.
다른 실시예는 실리콘 단결정의 웨이퍼를 준비하는 단계; 상기 웨이퍼를 급속 열처리(Rapid thermal process)하는 단계; 및 상기 급속 열처리된 웨이퍼의 표면을 5 마이크로 미터 내지 7 마이크로 미터 제거하는 단계를 포함하는 웨이퍼의 제조 방법을 제공한다.Another embodiment includes preparing a wafer of silicon single crystal; Rapid thermal process of the wafer; And removing 5 to 7 micrometers from the surface of the rapidly heat-treated wafer.
급속 열처리는 질소 분위기, 아르곤 분위기, 암모니아 분위기 또는 이들의 혼합 분위기에서 진행될 수 있다.Rapid heat treatment may be carried out in a nitrogen atmosphere, argon atmosphere, ammonia atmosphere or a mixed atmosphere thereof.
실리콘 단결정의 웨이퍼를 준비하는 단계는, 쵸크랄스키 법으로 실리콘 단결정 잉곳을 성장시킬 수 있다.In the preparing of the wafer of the silicon single crystal, the silicon single crystal ingot can be grown by the Czochralski method.
실시예에 따른 웨이퍼 및 그 제조방법은, 폴리시드 웨이퍼를 급속 열처리한 후에 표면으로부터 벌크 방향으로 5 마이크로 미터 내지 7 마이크로 미터, 예를 들면 5.5 마이크로 미터의 두께만큼 제거할 수 있다. 그리고, 이러한 방법으로 제조된 웨이퍼는 상술한 바와 같이 개선된 TZDB 특성을 보일 수 있다. 또한, 웨이퍼들은 표면에서 IDP 영역의 폭이 전체 폭의 40% 이상인 경우에, TZDB 특성이 개선될 것을 알 수 있다.The wafer and the method of manufacturing the same according to the embodiment can remove the thickness of the microseed wafer from the surface by 5 micrometers to 7 micrometers, for example 5.5 micrometers, in the bulk direction after rapid heat treatment. And, a wafer manufactured by this method can exhibit improved TZDB characteristics as described above. In addition, it can be seen that the wafers have improved TZDB characteristics when the width of the IDP region on the surface is 40% or more of the total width.
도 1a는 웨이퍼의 Cu haze 특성에 따른 결정 영역을 구분한 도면이고,1A is a diagram illustrating crystal regions according to Cu haze characteristics of a wafer;
도 1b는 급속 열처리를 진행하지 않은 경우의 TZDB를 나타낸 도면이고,1B is a diagram illustrating TZDB when rapid heat treatment is not performed.
도 1c는 급속 열처리를 진행한 후의 TZDB를 나타낸 도면이고,Figure 1c is a view showing the TZDB after the rapid heat treatment,
도 2는 웨이퍼의 표면으로부터 벌크 영역까지 나노 보이드의 밀도 또는 크기를 나타낸 도면이고,2 is a view showing the density or size of nano voids from the surface of the wafer to the bulk region,
도 3a 내지 도 3e는 비교예 1 내지 3과 실시예 1 내지 2의 웨이퍼의 Cu haze 특성에 따른 결정 영역을 구분한 도면이고,3A to 3E are diagrams illustrating crystal regions according to Cu haze characteristics of wafers of Comparative Examples 1 to 3 and Examples 1 to 2;
도 4a 내지 도 4e는 비교예 1 내지 3과 실시예 1 내지 2의 웨이퍼의 표면을 4 마이크로 미터 제거한 후의 TZDB 특성을 나타내고,4A to 4E show TZDB characteristics after removing 4 micrometers from the surfaces of the wafers of Comparative Examples 1 to 3 and Examples 1 and 2,
도 5a 내지 도 5e는 비교예 1 내지 3과 실시예 1 내지 2의 웨이퍼의 표면을 5.5 마이크로 미터 제거한 후의 TZDB 특성을 나타내고,5A to 5E show TZDB characteristics after removing 5.5 micrometers from the surfaces of the wafers of Comparative Examples 1-3 and Examples 1-2;
도 6a 내지 도 6c는 비교예 1 내지 2와 실시예 1의 웨이퍼의 표면을 7 마이크로 미터 제거한 후의 TZDB 특성을 나타내고, 6A to 6C show TZDB characteristics after the removal of the surfaces of the wafers of Comparative Examples 1-2 and Example 7 by 7 micrometers,
도 7a 내지 도 7e는 비교예 1 내지 3과 실시예 1 내지 2의 웨이퍼의 표면의 제거량에 따른 TZDB 특성을 나타낸 그래프이다.7A to 7E are graphs showing TZDB characteristics according to removal amounts of the surfaces of the wafers of Comparative Examples 1 to 3 and Examples 1 and 2;
이하, 본 발명을 구체적으로 설명하기 위해 실시 예를 들어 설명하고, 발명에 대한 이해를 돕기 위해 첨부도면을 참조하여 상세하게 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the following examples, and the present invention will be described in detail with reference to the accompanying drawings.
그러나, 본 발명에 따른 실시 예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시 예들에 한정되는 것으로 해석되지 않아야 한다. 본 발명의 실시 예들은 당 업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해서 제공되는 것이다.However, embodiments according to the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art.
본 발명에 따른 실시 예의 설명에 있어서, 각 element의 " 상(위)" 또는 "하(아래)(on or under)"에 형성되는 것으로 기재되는 경우에 있어, 상(위) 또는 하(아래)(on or under)는 두개의 element가 서로 직접(directly)접촉되거나 하나 이상의 다른 element가 상기 두 element사이에 배치되어(indirectly) 형성되는 것을 모두 포함한다.In the description of the embodiment according to the present invention, when described as being formed on the "on" or "on" (under) of each element, the upper (up) or the lower (down) (on or under) includes both the two elements are in direct contact with each other (directly) or one or more other elements are formed indirectly formed (indirectly) between the two elements.
또한 "상(위)" 또는 "하(아래)(on or under)"로 표현되는 경우 하나의 element를 기준으로 위쪽 방향뿐만 아니라 아래쪽 방향의 의미도 포함할 수 있다.In addition, when expressed as "up" or "on (under)", it may include the meaning of the downward direction as well as the upward direction based on one element.
또한, 이하에서 이용되는 "제1" 및 "제2," "상부" 및 "하부" 등과 같은 관계적 용어들은, 그런 실체 또는 요소들 간의 어떠한 물리적 또는 논리적 관계 또는 순서를 반드시 요구하거나 내포하지는 않으면서, 어느 한 실체 또는 요소를 다른 실체 또는 요소와 구별하기 위해서만 이용될 수도 있다.Also, the relational terms used below, such as "first" and "second," "upper" and "lower", etc., do not necessarily require or imply any physical or logical relationship or order between such entities or elements. It may be used only to distinguish one entity or element from another entity or element.
도면에서 각층의 두께나 크기는 설명의 편의 및 명확성을 위하여 과장되거나 생략되거나 또는 개략적으로 도시되었다. 또한 각 구성요소의 크기는 실제크기를 전적으로 반영하는 것은 아니다.In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.
실시예에 따른 웨이퍼의 제조 방법은, 실리콘 단결정의 폴리시드 웨이퍼를 준비하고 웨이퍼를 급속 열처리(Rapid thermal process)한 후, 급속 열처리된 웨이퍼의 표면을 5 마이크로 미터 내지 7 마이크로 미터 제거할 수 있다. 상술한 공정으로 제조된 실리콘 단결정 웨이퍼는 TZDB(Time Zero Dielectric Breakdown) 평가시 A 모드 결함과 B 모드 결함과 C 모드 결함 및 C+ 모드 결함이 각각 1% 미만으로 측정될 수 있으며, 이러한 결함들은 측정 노이즈에 기인한 것일 수 있다.According to the method of manufacturing a wafer according to the embodiment, after preparing a polysilicon wafer of silicon single crystal and performing a rapid thermal process, the surface of the rapidly heat treated wafer may be removed from 5 to 7 micrometers. Silicon single crystal wafers manufactured by the above-described process can measure A mode defects, B mode defects, C mode defects, and C + mode defects, respectively, when measuring time zero dielectric breakdown (TZDB). It may be due to.
도 2는 웨이퍼의 표면으로부터 벌크 영역까지 나노 보이드의 밀도 또는 크기를 나타낸 도면이다. 세로축이 웨이퍼의 표면으로부터 벌크까지의 깊이를 나타내고, 가로축이 나노 보이드(nano void)의 밀도 또는 크기를 나타낸다.FIG. 2 shows the density or size of nanovoids from the surface of the wafer to the bulk region. The vertical axis represents the depth from the surface of the wafer to the bulk, and the horizontal axis represents the density or size of the nano voids.
웨이퍼를 제조하기 위하여 실리콘 단결정 잉곳을 CZ 법으로 성장시키는 공정에서, 단결정의 인상 속도 V(mm/min)와 단결정의 인상축 방향의 단결정 내 온도 구배의 평균값 G(℃/mm)와의 비인 V/G에 따라 웨이퍼의 표면과 벌크 영역에서 베이컨시가 결정될 수 있다. 도 2에서 V/G에 의한 초기 베이컨시 농도가 세로 축 방향으로 점선으로 일정하게 도시되고 있다.In the process of growing a silicon single crystal ingot by the CZ method for manufacturing a wafer, V / is the ratio of the pulling speed V of the single crystal to the average value G of the temperature gradient in the single crystal in the direction of the pulling axis of the single crystal (° C./mm). Depending on G, vacancy may be determined at the wafer surface and in the bulk region. In FIG. 2, the initial vacancy concentration due to V / G is constantly shown as a dotted line in the longitudinal axis direction.
나노 보이드는 직경이 수 나노 미터 스케일인 보이드이고, 웨이퍼의 급속 열처리 공정에서 발생할 수 있으며, 웨이퍼의 결정 영역별로 발생 빈도가 다를 수 있다. 즉, 급속 열처리 전의 웨이퍼의 결정 영역별로 베이컨시(vacancy)이 상이하고, 이에 따라 웨이퍼의 급속 열처리 후에 발생하는 나노 보이드도 결정 영역별로 상이할 수 있다.Nano-voids are voids of several nanometers in diameter, may occur in the rapid heat treatment process of the wafer, and the frequency of occurrence may vary for each crystal region of the wafer. That is, vacancy varies for each crystal region of the wafer before the rapid heat treatment, and accordingly, nanovoids generated after the rapid heat treatment of the wafer may also vary for each crystal region.
도 2에서 베이컨시의 농도는 웨이퍼의 표면으로부터 벌크 방향으로 일정 두께까지는 점차 감소하다가, 일정 두께의 내부에서는 거의 일정하다. 그리고, 나노 보이드의 크기도 웨이퍼의 표면으로부터 벌크 방향으로 일정 두께까지는 점차 감소하다가, 일정 두께의 내부에서는 거의 일정하다.In FIG. 2, the concentration of bacon sea gradually decreases from the surface of the wafer to a certain thickness in the bulk direction, and is almost constant inside a certain thickness. In addition, the size of the nano voids gradually decreases from the surface of the wafer to a predetermined thickness in the bulk direction, and is almost constant inside the predetermined thickness.
상술한 도 2에 도시된 나노 보이드의 배치는 육안 내지 기타의 방법으로 확인하기 어렵고, 웨이퍼의 급속 열처리 후에 TZDB를 통하여 확인할 수 있다.The above-described arrangement of the nano voids shown in FIG. 2 is difficult to check by visual or other methods, and can be confirmed through TZDB after rapid heat treatment of the wafer.
먼저 폴리시드(polished) 웨이퍼를 준비한다. 폴리시드 웨이퍼는 CZ 법으로 성장된 단결정 잉곳을 슬라이싱과 그라인딩과 랩핑과 경면 연마 공정을 통하여 준비될 수 있다.First, a polished wafer is prepared. Polished wafers may be prepared by slicing, grinding, lapping and mirror polishing a single crystal ingot grown by CZ.
그리고, 웨이퍼를 급속 열처리할 수 있다. 급속 열처리는 질소 분위기, 아르곤 분위기, 암모니아 분위기 또는 이들의 혼합 분위기에서 진행될 수 있다. 급속 열처리는 웨이퍼를 급속하게 승온하고, 1200℃ 전후의 온도로 수십 초 정도 가열 유지한 후, 다시 급속하게 냉각시킬 수 있다.And a wafer can be heat-treated rapidly. Rapid heat treatment may be carried out in a nitrogen atmosphere, argon atmosphere, ammonia atmosphere or a mixed atmosphere thereof. The rapid heat treatment can rapidly cool the wafer again after the temperature is rapidly raised, held at a temperature of about 1200 ° C. for several tens of seconds.
급속 열처리에서 예를 들면 질소 분위기 중에서 1200℃의 고온 유지 중에 웨이퍼 표면으로부터 나노 보이드의 주입이 일어날 수 있으며, 나노 보이드는 웨이퍼의 벌크 영역보다 표면에서 크기 또는 밀도가 더 클 수 있다.In rapid heat treatment, for example, the injection of nanovoids from the wafer surface may occur during the high temperature holding of 1200 ° C. in a nitrogen atmosphere, and the nanovoids may be larger in size or density at the surface than the bulk area of the wafer.
그리고, 웨이퍼의 표면을 일정 깊이 제거하고 TZDB를 측정할 수 있다. 표 1은 비교예 1 내지 3과 실시예 1 내지 2의 웨이퍼를, 상술한 급속 열처리 공정 후에 표면을 4 마이크로 미터 제거하고 TZDB를 측정한 결과이다.Then, the surface of the wafer can be removed to a certain depth and the TZDB can be measured. Table 1 shows the results of measuring the TZDB of the wafers of Comparative Examples 1 to 3 and Examples 1 to 2 by removing 4 micrometers of the surface after the rapid heat treatment step described above.
그리고, 도 3a 내지 도 3e는 비교예 1 내지 3과 실시예 1 내지 2의 웨이퍼의 Cu haze 특성에 따른 결정 영역을 구분한 도면이고, 도 4a 내지 도 4e는 비교예 1 내지 3과 실시예 1 내지 2의 웨이퍼의 표면을 4 마이크로 미터 제거한 후의 TZDB 특성을 나타낸 도면이다.3A to 3E are diagrams illustrating crystal regions according to Cu haze characteristics of the wafers of Comparative Examples 1 to 3 and Examples 1 to 2, and FIGS. 4A to 4E are Comparative Examples 1 to 3 and Example 1 It is a figure which shows the TZDB characteristic after removing 4 micrometers of the surface of the wafer of -2.
IDP 영역의 폭(mm)IDP area width (mm) 대상object TZDB (모드별 비율, %)TZDB (Ratio by Mode,%)
A 모드A mode B 모드B mode C 모드C mode C+ 모드C + mode 수율yield
37.537.5 비교예 1Comparative Example 1 0.560.56 2.252.25 23.4123.41 18.9118.91 54.8754.87
4545 비교예 2Comparative Example 2 00 27.7227.72 30.3430.34 14.0414.04 27.927.9
52.552.5 비교예 3Comparative Example 3 1.121.12 30.1530.15 45.8845.88 14.4214.42 8.438.43
132132 실시예 1Example 1 0.60.6 0.20.2 0.70.7 3.93.9 94.694.6
67.567.5 실시예 2Example 2 0.560.56 0.560.56 3.563.56 5.435.43 89.8989.89
비교예들과 실시예들에서 직경 300 밀리미터의 웨이퍼를 사용하였으며, IDP 영역의 폭은 반경 영역에서의 IDP 영역의 폭을 의미한다. 예를 들어, 실시예 2의 웨이퍼의 경우 150 밀리미터의 반경 영역에서 IDP 영역의 폭이 132 밀리미터인 경우이다. IDP 영역 이외에는 VDP(Vacancy Dominant Point defect zone) 영역 또는 O Band(Oxidation-induced defect Band) 영역이 존재할 수 있다.In Comparative Examples and Examples, a wafer having a diameter of 300 millimeters was used, and the width of the IDP region means the width of the IDP region in the radial region. For example, in the case of the wafer of Example 2, the width of the IDP region is 132 millimeters in the radius region of 150 millimeters. In addition to the IDP region, a VDP (Vacancy Dominant Point defect zone) region or an O-band (Oxidation-induced defect Band) region may exist.
그리고, A 모드는 TZDB 값이 0 내지 4 Mega volt/cm 미만이고, B 모드는 TZDB 값이 4 내지 8 Mega volt/cm 미만이고, C 모드는 TZDB 값이 8 내지 10 ega volt/cm 미만이고, C+ 모드는 TZDB 값이 10 내지 12 Mega Volt/cm 미만인 영역일 수 있다. And mode A has a TZDB value of less than 0 to 4 Mega volt / cm, mode B has a TZDB value of less than 4 to 8 Mega volt / cm, mode C has a TZDB value of less than 8 to 10 ega volt / cm, The C + mode may be a region where the TZDB value is less than 10 to 12 Mega Volt / cm.
비교예 1 내지 비교예 3의 웨이퍼는 IDP 영역의 폭이 웨이퍼의 폭의 40% 미만일 수 있으며, A 모드와 B 모드와 C 모드, 그리고 C+ 모드인 TZDB 값이 12 Mega Volt/cm 미만인 영역의 합이 각각 45.13%와 72.1%와 91.57%이다. 그리고, 실시예 1 내지 실시예 2의 웨이퍼는 A 모드와 B 모드와 C 모드, 그리고 C+ 모드인 TZDB 값이 12 Mega Volt/cm 미만인 영역의 합이 각각 5.4%와 10.11%이다. 따라서, 비교예 1 내지 3의 웨이퍼는 수율(pass rate)이 각각 54.87%와 27.9%와 8.43%이고, 실시예 1 내지 2의 웨이퍼는 수율이 각각 94.6%와 89.89%이다.In the wafers of Comparative Examples 1 to 3, the width of the IDP region may be less than 40% of the width of the wafer, and the sum of the regions where the TZDB values of the A mode, the B mode, the C mode, and the C + mode are less than 12 Mega Volt / cm. 45.13%, 72.1%, and 91.57%, respectively. In the wafers of Examples 1 to 2, the sum of the regions in which the TZDB values of the A mode, the B mode, the C mode, and the C + mode is less than 12 Mega Volt / cm is 5.4% and 10.11%, respectively. Thus, the wafers of Comparative Examples 1 to 3 had a pass rate of 54.87%, 27.9% and 8.43%, respectively, and the wafers of Examples 1 to 2 had a yield of 94.6% and 89.89%, respectively.
상기의 도 2에서 검토한 바와 같이 웨이퍼의 표면의 제거(removal)량을 증가하면, A 모드와 B 모드와 C 모드, 그리고 C+ 모드 중 TZDB 값이 12 Mega Volt/cm미만인 영역이 감소할 수 있으므로, 추가로 웨이퍼의 표면을 1.5 마이크로 미터 제거하였다.As discussed above with reference to FIG. 2, if the removal amount of the surface of the wafer is increased, a region having a TZDB value of less than 12 Mega Volt / cm among A mode, B mode, C mode, and C + mode may decrease. In addition, the surface of the wafer was further removed 1.5 micrometers.
표 2는 비교예 1 내지 3과 실시예 1 내지 2의 웨이퍼의 표면을 추가로 1.5 마이크로 미터 제거하여, 총 5.5 마이크로 미터의 제거량(removal amount)을 가지는 웨이퍼의 TZDB를 측정한 결과이다.Table 2 shows the results of measuring the TZDB of the wafers having a removal amount of 5.5 micrometers in total by further removing the surfaces of the wafers of Comparative Examples 1 to 3 and Examples 1 to 2 by 1.5 micrometers.
그리고, 도 5a 내지 도 5e는 표 2에 따른 비교예 1 내지 3과 실시예 1 내지 2의 웨이퍼의 TZDB 특성을 나타내며, 웨이퍼의 표면을 5.5 마이크로 미터 제거한 후의 TZDB 특성이다.5A to 5E show TZDB characteristics of the wafers of Comparative Examples 1 to 3 and Examples 1 and 2 according to Table 2, respectively, and are TZDB characteristics after removing 5.5 micrometers from the surface of the wafer.
IDP 영역의 폭(mm)IDP area width (mm) 대상object TZDB (모드별 비율, %)TZDB (Ratio by Mode,%)
A 모드A mode B 모드B mode C 모드C mode C+ 모드C + mode 수율yield
37.537.5 비교예 1Comparative Example 1 0.370.37 1.691.69 19.119.1 16.6716.67 62.1762.17
4545 비교예 2Comparative Example 2 9494 2.062.06 24.7224.72 23.623.6 48.6948.69
52.552.5 비교예 3Comparative Example 3 0.40.4 0.60.6 11.211.2 24.724.7 63.163.1
132132 실시예 1Example 1 0.190.19 00 0.190.19 1.51.5 98.1398.13
67.567.5 실시예 2Example 2 0.40.4 0.20.2 0.00.0 1.51.5 99.399.3
비교예 1 내지 비교예 3의 웨이퍼는 상술한 바와 같이 IDP 영역의 폭이 웨이퍼의 폭의 40% 미만일 수 있으며, A 모드와 B 모드와 C 모드, 그리고 C+ 모드인 TZDB 값이 12 Mega Volt/cm 미만인 영역의 합이 각각 37.83%와 51.31%와 36.9%이다. 그리고, 실시예 1 내지 실시예 2의 웨이퍼는 A 모드와 B 모드와 C 모드, 그리고 C+ 모드인 TZDB 값이 12 Mega Volt/cm 미만인 영역의 합이 각각 1.87%와 0.7%이다. 따라서, 비교예 1 내지 3의 웨이퍼는 수율(pass rate)이 각각 62.17%와 48.69와 63.1%이고, 실시예 1 내지 2의 웨이퍼는 수율이 각각 98.13%와 99.3%이다.In the wafers of Comparative Examples 1 to 3, the width of the IDP region may be less than 40% of the width of the wafer as described above, and the TZDB values of A mode, B mode, C mode, and C + mode are 12 Mega Volt / cm. The sum of the areas below is 37.83%, 51.31% and 36.9%, respectively. In the wafers of Examples 1 to 2, the sum of the regions in which the TZDB values of the A mode, the B mode, the C mode, and the C + mode is less than 12 Mega Volt / cm is 1.87% and 0.7%, respectively. Accordingly, the wafers of Comparative Examples 1 to 3 had a pass rate of 62.17%, 48.69 and 63.1%, respectively, and the wafers of Examples 1 and 2 had 98.13% and 99.3%, respectively.
표 1과 표 2로부터 웨이퍼의 표면의 제거(removal)량을 증가하면, A 모드와 B 모드와 C 모드, 그리고 C+ 모드인 TZDB 값이 12 Mega Volt/cm 미만인 영역이 감소할 수 있으므로, 추가로 웨이퍼의 표면을 1.5 마이크로 미터 제거하였다.Increasing the amount of removal of the surface of the wafer from Tables 1 and 2 further reduces the area where the TZDB values of A mode, B mode and C mode, and C + mode are less than 12 Mega Volt / cm. The surface of the wafer was removed 1.5 micrometers.
도 6a 내지 도 6c는 비교예 1 내지 2와 실시예 1의 웨이퍼의 TZDB 특성을 나타내며, 총 7 마이크로 미터의 제거량(removal amount)을 가지는 웨이퍼의 TZDB를 측정한 결과이다.6A to 6C show the TZDB characteristics of the wafers of Comparative Examples 1 to 2 and Example 1, and the TZDB of the wafers having a removal amount of 7 micrometers in total is measured.
도 6a 내지 도 6c로부터 웨이퍼의 표면의 제거량이 7 마이크로 미터인 경우의 TZDB 특성은, 표 2 및 도 5a 내지 도 5e에서 웨이퍼의 표면의 제거량이 5.5 마이크로 미터인 경우와 TZDB 특성의 차이가 거의 없음을 알 수 있다.The TZDB characteristics when the surface removal amount of the wafer is 7 micrometers from FIGS. 6A to 6C are almost the same as the TZDB characteristics when the surface removal amount of the wafer is 5.5 micrometers in Table 2 and FIGS. 5A to 5E. It can be seen.
표 1과 표 2로부터 IDP 영역이 40% 이상인 웨이퍼를 표면으로부터 벌크 방향으로 5.5 마이크로 미터 제거하면, TZDB 측정 결과 98% 이상의 수율을 확인할 수 있다. 실시예 1과 실시예 2의 웨이퍼에서도 1% 미만의 A 모드가 측정되었으나, 이는 TZDB 평가를 위한 전처리 중에 발생하는 노이즈(noise)에 기인한 것일 수 있다. 상기의 노이즈는, 웨이퍼링(wafering) 공정기의 결함, 파티클(particle) 추가, 오염/측정 장비 불량에 기인한 것일 수 있다.From Table 1 and Table 2, when the wafer having a IDP area of 40% or more was removed 5.5 micrometers in the bulk direction from the surface, the TZDB measurement result showed a yield of 98% or more. A mode of less than 1% was also measured on the wafers of Examples 1 and 2, but this may be due to noise generated during pretreatment for TZDB evaluation. The noise may be due to defects in the wafering process, particle addition, and contamination / measuring equipment failure.
따라서, 실시예에 따른 웨이퍼의 제조 방법에서는, 폴리시드 웨이퍼를 급속 열처리한 후에 표면으로부터 벌크 방향으로 5 마이크로 미터 내지 7 마이크로 미터, 예를 들면 5.5 마이크로 미터의 두께만큼 제거할 수 있다. 그리고, 이러한 방법으로 제조된 웨이퍼는 상술한 바와 같이 개선된 TZDB 특성을 보일 수 있다. 또한, 웨이퍼들은 표면에서 IDP 영역의 폭이 전체 폭의 40% 이상인 경우에, TZDB 특성이 개선될 것을 알 수 있다.Therefore, in the wafer manufacturing method according to the embodiment, after the rapid heat treatment of the polysid wafer, it is possible to remove from the surface by the thickness of 5 micrometers to 7 micrometers, for example 5.5 micrometers. And, a wafer manufactured by this method can exhibit improved TZDB characteristics as described above. In addition, it can be seen that the wafers have improved TZDB characteristics when the width of the IDP region on the surface is 40% or more of the total width.
도 7a 내지 도 7e는 비교예 1 내지 3과 실시예 1 내지 2의 웨이퍼의 표면의 제거량에 따른 TZDB 특성을 나타낸 그래프이다. 도 7a와 7b와 도 7d의 비교예 1 내지 2와 실시예 1의 웨이퍼는 표면을 각각 4 마이크로 미터와 5.5 마이크로 미터와 7 마이크로 미터 제거한 데이타(data)가 도시되고, 도 7c와 7e의 비교예 3과 실시예 2의 웨이퍼는 표면을 각각 4 마이크로 미터와 5.5 마이크로 미터 제거한 데이타가 도시되고 있다.7A to 7E are graphs showing TZDB characteristics according to removal amounts of the surfaces of the wafers of Comparative Examples 1 to 3 and Examples 1 and 2; The wafers of Comparative Examples 1 and 2 and Example 1 of FIGS. 7A, 7B and 7D are shown with data removed from the surface of 4 micrometers, 5.5 micrometers and 7 micrometers, respectively, and Comparative Examples of FIGS. 7C and 7E The wafers of 3 and Example 2 are shown with data removed by 4 micrometers and 5.5 micrometers, respectively.
비교예 1 내지 3의 웨이퍼는 표면으로부터 벌크 방향으로 제거량이 증가하여도 TZDB 특성이 크게 개선되지 않는다. 그리고, 실시예 1 내지 2의 웨이퍼는 표면으로부터 벌크 방향으로 제거량이 5.5 마이크로 미터 이상일 때 TZDB 값이 12 Mega Volt/cm 미만인 영역인 C+ 모드가 1% 미만으로 측정되나, 상술한 바와 같이 측정 공정에서의 노이즈에 기인한 것일 수 있다.In the wafers of Comparative Examples 1 to 3, even if the amount of removal in the bulk direction from the surface is increased, the TZDB characteristics are not significantly improved. In addition, the wafers of Examples 1 to 2 have a C + mode of less than 1%, which is a region where the TZDB value is less than 12 Mega Volt / cm when the amount of removal from the surface in the bulk direction is 5.5 micrometers or more, but in the measurement process as described above. May be due to noise.
이상과 같이 실시예는 비록 한정된 실시예와 도면에 의해 설명되었으나, 본 발명은 상기의 실시예에 한정되는 것은 아니며, 본 발명이 속하는 분야에서 통상의 지식을 가진 자라면 이러한 기재로부터 다양한 수정 및 변형이 가능하다.As described above, although the embodiments have been described by the limited embodiments and the drawings, the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains various modifications and variations from such descriptions. This is possible.
그러므로, 본 발명의 범위는 설명된 실시예에 국한되어 정해져서는 아니되며, 후술하는 특허청구범위뿐 아니라 이 특허청구범위와 균등한 것들에 의해 정해져야 한다.Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims below but also by the equivalents of the claims.
실시예에 따른 웨이퍼는 TZDB 특성이 개선될 것을 알 수 있다.It can be seen that the wafer according to the embodiment has improved TZDB characteristics.

Claims (15)

  1. 웨이퍼에 있어서,In the wafer,
    TZDB(Time Zero Dielectric Breakdown) 평가시 A 모드와 B 모드와 C 모드와 C+ 모드가 각각 1% 미만이고, 여기서 상기 A 모드는 상기 TZDB 값이 0 내지 4 Mega volt/cm이고, 상기 B 모드는 상기 TZDB 값이 4 내지 8 Mega volt/cm이고, 상기 C 모드는 상기 TZDB 값이 8 내지 10Mega volt/cm이고, 상기 C+ 모드는 상기 TZDB 값이 10 내지 12 Mega volt/cm인 웨이퍼.Mode A, B, C and C + modes are each less than 1% when evaluating Time Zero Dielectric Breakdown (TZDB), wherein the A mode has the TZDB value of 0 to 4 Mega volt / cm, and the B mode is And a TZDB value of 4 to 8 Mega volt / cm, the C mode of the TZDB value of 8 to 10 Mega volt / cm, and the C + mode of the TZDB value of 10 to 12 Mega volt / cm.
  2. 제1 항에 있어서,According to claim 1,
    급속 열처리(Rapid thermal process) 후 표면이 제거된 웨이퍼.Wafers whose surface has been removed after a rapid thermal process.
  3. 제2 항에 있어서,The method of claim 2,
    표면이 5 마이크로 미터 내지 7 마이크로 미터의 두께만큼 제거된 웨이퍼.A wafer with a surface removed by a thickness of 5 micrometers to 7 micrometers.
  4. 제1 항에 있어서,According to claim 1,
    IDP(Interstitial Dominant Point defect zone)의 면방향 직경이 전체 직경의 40% 이상인 웨이퍼.Wafers with an interstitial dominant point defect zone (IDP) of at least 40% of the total diameter.
  5. 제4 항에 있어서,The method of claim 4, wherein
    상기 웨이퍼는 IDP 영역과 VDP(Vacancy Dominant Point defect zone) 영역이 혼재된 웨이퍼.The wafer is a wafer in which an IDP region and a VDP (Vacancy Dominant Point defect zone) region are mixed.
  6. 실리콘 단결정의 웨이퍼를 준비하는 단계;Preparing a wafer of silicon single crystal;
    상기 웨이퍼를 급속 열처리(Rapid thermal process)하는 단계; 및Rapid thermal process of the wafer; And
    상기 급속 열처리된 웨이퍼의 표면을 5 마이크로 미터 내지 7 마이크로 미터 제거하는 단계를 포함하는 웨이퍼의 제조 방법.Removing 5 to 7 micrometers from the surface of the rapidly heat-treated wafer.
  7. 제6 항에 있어서,The method of claim 6,
    상기 급속 열처리는 질소 분위기, 아르곤 분위기, 암모니아 분위기 또는 이들의 혼합 분위기에서 진행되는 웨이퍼의 제조 방법.The rapid heat treatment is a method for manufacturing a wafer which is carried out in a nitrogen atmosphere, argon atmosphere, ammonia atmosphere or a mixed atmosphere thereof.
  8. 제6 항에 있어서,The method of claim 6,
    상기 급속 열처리는 상기 웨이퍼를 급속하게 승온하고, 1200℃ 전후의 온도로 수십 초 정도 가열 후, 급속하게 냉각시키는 웨이퍼의 제조 방법.The rapid heat treatment is a method for producing a wafer in which the temperature of the wafer is rapidly raised, heated to a temperature of about 1200 ° C. for several tens of seconds, and then rapidly cooled.
  9. 제8 항에 있어서,The method of claim 8,
    상기 웨이퍼의 가열 중, 상기 웨이퍼의 표면으로 나노 보이드가 주입되는 웨이퍼의 제조 방법.During the heating of the wafer, a nanovoid is injected into the surface of the wafer.
  10. 제9 항에 있어서,The method of claim 9,
    상기 나노 보이드는 상기 웨이퍼의 벌크 영역보다 표면에서 크기 또는 밀도가 더 큰 웨이퍼의 제조 방법.And the nano voids are larger in size or density at the surface than the bulk region of the wafer.
  11. 제6 항에 있어서,The method of claim 6,
    상기 웨이퍼는 IDP(Interstitial Dominant Point defect zone)의 면방향 직경이 전체 직경의 40% 이상인 웨이퍼의 제조 방법.The wafer has a planar diameter of the interstitial dominant point defect zone (IDP) is at least 40% of the total diameter.
  12. 제6 항에 있어서,The method of claim 6,
    상기 웨이퍼는 IDP 영역과 VDP(Vacancy Dominant Point defect zone) 영역이 혼재된 웨이퍼의 제조 방법.The wafer is a method of manufacturing a wafer in which the IDP region and VDP (Vacancy Dominant Point defect zone) region is mixed.
  13. 제6 항에 있어서,The method of claim 6,
    상기 웨이퍼를 TZDB(Time Zero Dielectric Breakdown) 평가하는 단계를 더 포함하는 웨이퍼의 제조 방법.And evaluating the wafer for time zero dielectric breakdown (TZDB).
  14. 제13 항에 있어서,The method of claim 13,
    상기 평가 단계에서, 상기 웨이퍼의 A 모드 결함과 B 모드 결함 및 C 모드 결함과 C+ 모드 결함이 각각 1% 미만이고, 여기서 상기 A 모드 결함은 상기 TZDB 값이 0 내지 4 Mega volt/cm이고, 상기 B 모드 결함은 상기 TZDB 값이 4 내지 8 Mega volt/cm이고, 상기 C 모드 결함은 상기 TZDB 값이 8 내지 10 Mega volt/cm이고, 상기 C+ 모드는 상기 TZDB 값이 10 내지 12 Mega volt/cm인 웨이퍼의 제조 방법.In the evaluation step, the A mode defect and the B mode defect and the C mode defect and the C + mode defect of the wafer are less than 1%, respectively, wherein the A mode defect has the TZDB value of 0 to 4 Mega volt / cm, The B mode defect has the TZDB value of 4 to 8 Mega volt / cm, the C mode defect has the TZDB value of 8 to 10 Mega volt / cm, and the C + mode has the TZDB value of 10 to 12 Mega volt / cm The manufacturing method of a phosphorus wafer.
  15. 제6 항에 있어서,The method of claim 6,
    상기 실리콘 단결정의 웨이퍼를 준비하는 단계는, 쵸크랄스키 법으로 실리콘 단결정 잉곳을 성장시키는 웨이퍼의 제조 방법.The preparing of the wafer of silicon single crystal comprises growing a silicon single crystal ingot by a Czochralski method.
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Citations (5)

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JP4743010B2 (en) * 2005-08-26 2011-08-10 株式会社Ｓｕｍｃｏ Silicon wafer surface defect evaluation method
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