WO2017209251A1

WO2017209251A1 - Method for manufacturing substrate, method for manufacturing solar cell, substrate, and solar cell

Info

Publication number: WO2017209251A1
Application number: PCT/JP2017/020471
Authority: WO
Inventors: 達也高本
Original assignee: シャープ株式会社
Priority date: 2016-06-01
Filing date: 2017-06-01
Publication date: 2017-12-07

Abstract

A method for manufacturing a substrate (11), comprising: a step for implanting an atom species (2) into a semiconductor single crystal (1) including at least one atom selected from the group consisting of germanium, gallium, and indium; a step for forming a support substrate (3) on the surface (1a) of the semiconductor single crystal (1) after implantation of the atomic species (2), the support substrate (3) being formed by at least one method selected from the group consisting of deposition, CVD, plating, printing, sputtering, the sol-gel method, and thermal spraying; and a step for performing peeling with the support substrate (3) formed on a part (10) of the semiconductor crystal (1).

Description

Substrate manufacturing method, solar cell manufacturing method, substrate and solar cell

The present invention relates to a substrate manufacturing method, a solar cell manufacturing method, a substrate, and a solar cell. This application claims priority based on Japanese Patent Application No. 2016-110436, which is a Japanese patent application filed on June 1, 2016. All the descriptions described in the Japanese patent application are incorporated herein by reference.

For example, Patent Document 1 discloses a method for producing a semi-insulating InP (indium phosphide) layer compensated with Fe (iron) by using a smart cut technique. The method described in Patent Document 1 is performed as follows.

First, each of a support made of Si (silicon) and a donor wafer made of InP is treated with hydrofluoric acid (paragraph [0030] of Patent Document 1). This is to remove the native oxide layer from each of the support and the donor wafer (paragraph [0030] of Patent Document 1).

Next, the support is oxidized by thermal oxidation to form a bonding layer made of oxide, and a bonding layer made of oxide or the like is formed on the donor wafer by plasma deposition (paragraph [0030] of Patent Document 1).

Next, an embrittlement zone is formed by implanting atomic species on the surface of the donor wafer on which the bonding layer is formed (paragraph [0031] of Patent Document 1).

Next, each of the surface of the bonding layer on the surface of the support and the surface of the bonding layer on the surface of the donor wafer is subjected to mechanical chemical polishing (paragraph [0034] of Patent Document 1). This is because a flat and smooth surface is required for bonding between the bonding layer on the surface of the support and the bonding layer on the surface of the donor wafer (paragraph [0034] of Patent Document 1).

Next, the InP film is broken and removed from the donor wafer along the embrittled surface of the embrittlement zone of the donor wafer by annealing the support and the donor wafer (paragraph [0034] of Patent Document 1).

Next, the InP film on the support is thinned by etching or polishing (paragraph [0035] of Patent Document 1). Finally, a semi-insulating InP thin film is formed by heat-treating the InP film at 900 ° C. in an FeP ₂ gas atmosphere composed of Fe and P (phosphorus) and diffusing Fe into the InP film (see Patent Document 1). Paragraph [0036]).

JP 2004-179630 A

In the method described in Patent Document 1, the surface of the bonding layer on the support and the surface of the bonding layer on the donor wafer are mechanically polished for bonding between the bonding layer on the support and the bonding layer on the donor wafer. It is necessary to polish using technology.

However, the treatment using the mechanochemical polishing technique of the method described in Patent Document 1 is very expensive, and such a high-cost treatment is performed on the surface of the bonding layer on the support and the bonding layer on the donor wafer. Since it was necessary to carry out both of the surfaces, the improvement was desired.

Embodiments disclosed herein include a step of implanting atomic species into a semiconductor single crystal including at least one atom selected from the group consisting of germanium, gallium, and indium, and a surface after the implantation of the atomic species of the semiconductor single crystal And forming a support substrate by at least one method selected from the group consisting of a vapor deposition method, a CVD (chemical vapor deposition) method, a plating method, a printing method, a sputtering method, a sol-gel method, and a thermal spraying method; And a step of peeling the semiconductor single crystal in a state where a part of the semiconductor single crystal is formed on the supporting substrate.

The embodiment disclosed herein includes a step of manufacturing a substrate by the above-described substrate manufacturing method, a step of forming a solar cell structure on the substrate, a step of forming a first electrode on the substrate, Forming a second electrode on the battery structure.

Embodiment disclosed here removes a board | substrate after the process of manufacturing a board | substrate with the manufacturing method of said board | substrate, the process of forming a solar cell structure on a board | substrate, and the process of forming a solar cell structure. It is a manufacturing method of a solar cell including a process and the process of forming the 1st electrode and the 2nd electrode on a solar cell structure.

An embodiment disclosed herein includes a non-single crystal film and a single crystal film bonded to the non-single crystal film, and the single crystal film is at least selected from the group consisting of germanium, gallium, and indium. Including one atom, the non-single crystal film is thicker than the single crystal film, and the non-single crystal film includes at least one selected from the group consisting of metal, silicon, metal silicon compound, and metal oxide, The non-single crystal film is a substrate having a crystal grain boundary or pores at the interface with the single crystal film.

Embodiment disclosed here is a solar cell provided with said board | substrate and the solar cell structure on a board | substrate.

According to the embodiment disclosed herein, it is possible to manufacture a substrate and a solar cell at low cost.

(A)-(c) is typical sectional drawing illustrating the manufacturing process of the manufacturing method of the board | substrate of Embodiment 1. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 2. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 2. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 2. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 2. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the method for manufacturing a solar cell according to Embodiment 3. FIG.

Hereinafter, embodiments will be described. In the drawings used to describe the embodiments, the same reference numerals represent the same or corresponding parts.

[Embodiment 1]
FIG. 1A to FIG. 1C are schematic cross-sectional views illustrating manufacturing steps of a substrate manufacturing method according to Embodiment 1, which is an example of a substrate manufacturing method according to the present invention. Hereinafter, a substrate manufacturing method according to the first embodiment will be described with reference to FIGS. 1 (a) to 1 (c).

First, as shown in FIG. 1A, a step of injecting atomic species 2 into the surface 1a of the semiconductor single crystal 1 is performed.

The material of the semiconductor single crystal 1 can be a single crystal containing at least one atom selected from the group consisting of germanium (Ge), gallium (Ga), and indium (In).

The implantation of atomic species 2 means that atoms and / or molecules are accelerated and introduced by the surface, and the atoms and molecules may or may not be ionized. The implantation of atomic species can be performed using, for example, an ion beam implanter or a plasma immersion implanter. The same type of atoms and / or molecules may be injected, or different types of atoms and / or molecules may be injected.

The implantation depth of the atomic species 2 is not particularly limited, but can be, for example, 30 nm or more and 3000 nm or less from the surface 1a of the semiconductor single crystal 1. Further, the thickness of the semiconductor single crystal 1 is not particularly limited as long as it is thicker than the implantation depth of the atomic species 2, but it is 2000 nm or less from the viewpoint that a normal apparatus can be used and manufacturing of the substrate is facilitated. It is preferable.

The implantation amount of the atomic species 2 is not particularly limited, but can be, for example, 1 × 10 ¹⁶ cm ⁻¹ or more and 1 × 10 ¹⁸ cm ⁻¹ or less.

The temperature of the semiconductor single crystal 1 in the step of injecting the atomic species 2 is not particularly limited, but may be, for example, room temperature (25 ° C.) or more and 150 ° C. or less.

The atomic species 2 may contain, for example, hydrogen ions (H ⁺ ) or only H ⁺ . Examples of conditions for injecting H ⁺ as atomic species 2 into the surface 1a of the semiconductor single crystal 1 include the following conditions A and B, for example.

(1) Condition A
Semiconductor single crystal 1: Ge single crystal having a diameter of 4 inches and a thickness of 0.2 mm H ⁺ implantation energy: 100 keV
H ⁺ implantation depth: 700 nm
H ⁺ implantation amount: 3 × 10 ¹⁶ cm ⁻²
Semiconductor single crystal 1 temperature: room temperature (25 ° C.)
(2) Condition B
Semiconductor single crystal 1: GaAs single crystal having a diameter of 4 inches and a thickness of 0.4 mm H ⁺ implantation energy: 100 keV
H ⁺ implantation depth: 750 nm
H ⁺ implantation amount: 5 × 10 ¹⁶ cm ⁻²
Semiconductor single crystal 1 temperature: 150 ° C.
Next, as shown in FIG. 1B, the vapor deposition method, the CVD method, the plating method, the printing method, the sputtering method, the sol-gel method, and the thermal spraying are performed on the surface 1a of the semiconductor single crystal 1 after the implantation of the atomic species 2. The step of forming the support substrate 3 is performed by at least one method selected from the group consisting of methods.

As the material of the support substrate 3, it is not necessary to treat the surface 1 a of the semiconductor single crystal 1 after the implantation of the atomic species 2, and a material that is bonded to the surface 1 a of the semiconductor single crystal 1 after the implantation of the atomic species 2 is used. For example, from the viewpoint of reducing the distortion generated in the semiconductor single crystal 1 due to the formation of the support substrate 3, as the material of the support substrate 3, the linear thermal expansion coefficient of the support substrate 3 and the linear thermal expansion coefficient of the semiconductor single crystal 1 can be used. It is preferable to use a material in which the ratio R1 of the difference to the linear thermal expansion coefficient of the semiconductor single crystal 1 is within ± 30%.

The ratio R1 of the difference between the linear thermal expansion coefficient of the support substrate 3 and the linear thermal expansion coefficient of the semiconductor single crystal 1 to the linear thermal expansion coefficient of the semiconductor single crystal 1 can be calculated by the following equation (1). .

R1 = 100 × {(Linear thermal expansion coefficient of support substrate 3) − (Linear thermal expansion coefficient of semiconductor single crystal 1)} / (Linear thermal expansion coefficient of semiconductor single crystal 1) (1)
Further, “R1 is within ± 30%” means that R1 calculated by the above equation (1) satisfies the relationship of −30% ≦ R1 ≦ + 30%.

The material of the support substrate 3 may include at least one selected from the group consisting of metal, silicon, metal silicon compound, and metal oxide, for example. In this case, the cost of the support substrate 3 tends to be kept low. The metal silicon compound can include, for example, at least one of nickel silicon and aluminum silicon. The metal oxide can include, for example, at least one of aluminum oxide and silicon oxide.

The method of forming the support substrate 3 on the surface 1a of the semiconductor single crystal 1 after the implantation of the atomic species 2 by vapor deposition can be performed, for example, as follows. First, the semiconductor single crystal 1 after the implantation of the atomic species 2 is installed in a vapor deposition apparatus, and a material constituting the support substrate 3 is installed. Next, the inside of the vapor deposition apparatus is evacuated to a vacuum, and the material constituting the support substrate 3 is vaporized by heating, and then deposited on the surface 1a of the semiconductor single crystal 1, whereby the semiconductor after the implantation of the atomic species 2 is performed. A support substrate 3 can be formed on the surface 1 a of the single crystal 1.

The method of forming the support substrate 3 on the surface 1a of the semiconductor single crystal 1 after the implantation of the atomic species 2 by the CVD method can be performed, for example, as follows. First, the semiconductor single crystal 1 after the implantation of the atomic species 2 is placed in a CVD apparatus. Next, after the inside of the vapor deposition apparatus is evacuated to vacuum, a gas containing a material constituting the support substrate 3 is introduced into the CVD apparatus, and the support substrate 3 is placed on the surface 1a of the semiconductor single crystal 1 using a chemical reaction. By depositing, the support substrate 3 can be formed on the surface 1 a of the semiconductor single crystal 1 after the implantation of the atomic species 2.

The method of forming the support substrate 3 on the surface 1a of the semiconductor single crystal 1 after the implantation of the atomic species 2 by the plating method is, for example, using at least one of a conventionally known electrolytic plating method and electroless plating method. By depositing the support substrate 3 on the surface 1a of the semiconductor single crystal 1 after the implantation of the atomic species 2, the support substrate 3 can be formed on the surface 1a of the semiconductor single crystal 1 after the implantation of the atomic species 2. .

The method of forming the support substrate 3 on the surface 1a of the semiconductor single crystal 1 after the implantation of the atomic species 2 by the printing method can be performed as follows, for example. First, a paste containing a material constituting the support substrate 3 is printed on the surface 1 a of the semiconductor single crystal 1 after the implantation of the atomic species 2. Next, the support substrate 3 can be formed on the surface 1a of the semiconductor single crystal 1 after the implantation of the atomic species 2 by baking the paste.

The method of forming the support substrate 3 on the surface 1a of the semiconductor single crystal 1 after the implantation of the atomic species 2 by sputtering can be performed, for example, as follows. First, the semiconductor single crystal 1 after the implantation of the atomic species 2 is installed in a sputtering apparatus, and the material constituting the support substrate 3 is prepared as a target and installed in the sputtering apparatus. Next, the inside of the sputtering apparatus is evacuated and an inert gas is introduced. Thereafter, an inert gas ionized by applying a high voltage is made to collide with the target, and a material knocked out of the target is deposited on the surface 1a of the semiconductor single crystal 1, thereby allowing the semiconductor single body after the implantation of the atomic species 2 to be performed. A support substrate 3 can be formed on the surface 1 a of the crystal 1.

As an example of conditions for forming the support substrate 3 by the sputtering method, for example, the following condition C can be given.

(3) Condition C
Sputtering method: RF magnetron sputtering method Target: Aluminum silicon alloy Ultimate vacuum: 1 × 10 ⁻⁶ torr
Inert gas: Argon gas Inert gas pressure: 1.5 mtorr
Semiconductor single crystal 1 temperature: room temperature (25 ° C.)
Film forming speed: 1 nm / s (5.5 hours)
Film thickness: 20 μm
A method of forming the support substrate 3 on the surface 1a of the semiconductor single crystal 1 after the implantation of the atomic species 2 by the sol-gel method can be performed, for example, as follows. First, a powder of a material constituting the support substrate 3 is prepared and dispersed in a predetermined binder to prepare a sol having a predetermined viscosity. Next, the sol thus produced is applied onto the surface 1 a of the semiconductor single crystal 1 after the implantation of the atomic species 2. Then, the support substrate 3 can be formed on the surface 1a of the semiconductor single crystal 1 after the implantation of the atomic species 2 by gelling the sol by drying or the like.

As an example of conditions for forming the support substrate 3 by the sol-gel method, the following condition D can be given, for example.

(4) Condition D
Powder of material constituting support substrate 3: Mixed powder of aluminum oxide powder (average particle diameter 20 μm) and silicon oxide powder (average particle diameter 20 μm) (weight of aluminum oxide powder: weight of silicon oxide powder = 3: 2 )
Binder: Liquid silica (silicon oxide liquid)
Sol viscosity: 10 kcp
Sol coating method: Spin coating Sol coating thickness: 100 μm
Drying temperature: 200 ° C
Drying time: 2 hours Gel film thickness after drying of sol: 70 μm to 90 μm
The method of forming the support substrate 3 on the surface 1a of the semiconductor single crystal 1 after the implantation of the atomic species 2 by thermal spraying can be performed, for example, as follows. First, the material powder constituting the support substrate 3 is melted to form droplets. Next, the material constituting the supporting substrate 3 in the form of droplets is sprayed onto the surface 1a of the semiconductor single crystal 1 after the implantation of the atomic species 2 to thereby form the surface 1a of the semiconductor single crystal 1 after the implantation of the atomic species 2 The support substrate 3 can be formed.

As an example of conditions for forming the support substrate 3 by thermal spraying, the following condition E can be given, for example.

(5) Condition E
Material constituting support substrate 3: Mixed powder of aluminum oxide powder (average particle diameter 20 μm) and silicon oxide powder (average particle diameter 20 μm) (weight of aluminum oxide powder: weight of silicon oxide powder = 3: 2)
Melting method: plasma Sprayed film thickness: 100 μm
Thereafter, as shown in FIG. 1 (c), a step of peeling the semiconductor single crystal 1 in a state where a part 10 of the semiconductor single crystal 1 is formed on the support substrate 3 is performed. This peeling step can be performed, for example, by heating the semiconductor single crystal 1 after the support substrate 3 is formed.

As an example of the conditions for peeling in the state where the part 10 of the semiconductor single crystal 1 is formed on the support substrate 3 by heating, the following conditions F and G can be given, for example.

(6) Condition F
Heating atmosphere: Vacuum Heating temperature: 300 ° C
Heating time: 40 minutes (7) Condition G
Heating atmosphere: In inert gas Heating temperature: 500 ° C
Heating time: 5 minutes By the above, the board | substrate 11 provided with the support substrate 3 and the part 10 of the semiconductor single crystal 1 joined to the support substrate 3 can be manufactured. In the first embodiment, the support substrate 3 is formed on the surface 1a of the semiconductor single crystal 1 after the implantation of the atomic species 2 by at least one method selected from the group consisting of sputtering, sol-gel, and thermal spraying. ing. Therefore, unlike the patent document 1, it is not necessary to subject the surface 1a of the semiconductor single crystal 1 and the surface of the support substrate 3 to polishing using a mechanical chemical polishing technique before the formation of the support substrate 3. Therefore, in the method of the first embodiment, the substrate 11 can be manufactured at a lower cost than the method described in Patent Document 1.

Further, in the first embodiment, after the substrate 11 is manufactured, the step of injecting the atomic species 2 into the surface of the semiconductor single crystal 1 (FIG. 1A), the surface of the semiconductor single crystal 1 after the implantation of the atomic species 2 A step of forming a support substrate 3 on 1a by at least one method selected from the group consisting of vapor deposition, CVD, plating, printing, sputtering, sol-gel, and thermal spraying (FIG. 1B) ) And a step of peeling the semiconductor single crystal 1 in a state where the part 10 of the semiconductor single crystal 1 is formed on the support substrate 3 (FIG. 1C) is repeated in this order, whereby the part 10 of the semiconductor single crystal 1 is provided on the outermost surface. In addition, a plurality of substrates 11 can be manufactured at low cost.

The substrate 11 manufactured as described above includes, for example, a non-single crystal film forming the support substrate 3 and a single crystal film forming a part 10 of the semiconductor single crystal 1 bonded to the non-single crystal film. The single crystal film is thicker than the single crystal film, and the non-single crystal film includes at least one selected from the group consisting of metal, silicon, metal silicon compound, and metal oxide. Can do. Therefore, in this case, the substrate 11 can be used as a seed substrate for growing a semiconductor single crystal by forming the outermost surface of the substrate 11 from a portion 10 of a single crystal semiconductor single crystal. Here, the non-single crystal film is a film that is not a single crystal, and examples thereof include a polycrystalline film, an amorphous film, a particle composite film, a sintered film, and any porous film. As the non-single crystal film, a non-single crystal film having a crystal grain boundary or pores at the interface with the single crystal film can be used.

Note that also in the substrate 11, a part of the semiconductor single crystal 1 is different from the linear thermal expansion coefficient of the polycrystalline film forming the support substrate 3 and the linear thermal expansion coefficient of the single crystal film forming part 10 of the semiconductor single crystal 1. The ratio R2 to the linear thermal expansion coefficient of the single crystal film forming 10 is preferably within ± 30% from the viewpoint of reducing distortion generated in the single crystal film forming part 10 of the semiconductor single crystal 1. The coefficient of linear thermal expansion of the material of the non-single-crystal film forming the support substrate 3 is, for example, the mixing ratio or porosity of at least one material selected from the group consisting of metal, silicon, metal silicon compounds, and metal oxides. It can be controlled by adjusting.

The ratio R2 of the difference between the linear thermal expansion coefficient of the material of the polycrystalline film and the linear thermal expansion coefficient of the material of the single crystal film to the linear thermal expansion coefficient of the single crystal film is calculated by the following equation (2). Can do.

R2 = 100 × {(Linear thermal expansion coefficient of material of polycrystalline film) − (Linear thermal expansion coefficient of material of single crystal film)} / (Linear thermal expansion coefficient of material of single crystal film) (2)
Further, “R2 is within ± 30%” means that R2 calculated by the above formula (2) satisfies the relationship of −30% ≦ R2 ≦ + 30%.

Further, in the substrate 11, the single crystal film forming part 10 of the semiconductor single crystal 1 contains at least one atom selected from the group consisting of germanium, gallium and indium, and the material of the non-single crystal film forming the support substrate 3 The linear thermal expansion coefficient is preferably 4 ppm / K or more and 8 ppm / K or less at 300 K (Kelvin) from the viewpoint of reducing strain generated in the single crystal film forming part 10 of the semiconductor single crystal 1.

Further, in the substrate 11, the thickness of the non-single crystal film forming the support substrate 3 is preferably 5 μm or more and 200 μm or less as a thickness capable of maintaining the mechanical strength. Furthermore, from the viewpoint of handling and reducing the material cost, the thickness of the non-single crystal film forming the support substrate 3 is preferably 20 μm or more and 50 μm or less.

[Embodiment 2]
2 to 5 are schematic cross-sectional views illustrating manufacturing steps of the method for manufacturing a solar cell according to Embodiment 2, which is an example of the method for manufacturing a solar cell of the present invention. Hereinafter, a method for manufacturing the solar cell of Embodiment 2 will be described with reference to FIGS. The method for manufacturing a solar cell according to the second embodiment is characterized in that a compound semiconductor solar cell is manufactured by stacking using the substrate 11 manufactured by the substrate manufacturing method of the first embodiment as a seed substrate.

In Embodiment 2, a solar cell structure 20 shown in FIG. 2 is manufactured by sequentially epitaxially growing the following compound semiconductor single crystal layers on a p-type Ge substrate. Note that the solar cell structure 20 only needs to have a structure in which a potential difference is generated when light is incident. For example, the solar cell structure 20 includes a structure including a pn junction formed by a junction of a p-type semiconductor and an n-type semiconductor. And any conventionally known solar cell such as a structure including a pin junction formed by joining an i-type semiconductor to each of the p-type semiconductor and the n-type semiconductor between the p-type semiconductor and the n-type semiconductor. Including the structure.

In the second embodiment, first, a semiconductor single crystal made of a p-type Ge single crystal doped with Ga on a disk-like conductive support substrate 3 having a diameter of 50 mm, for example, by the substrate manufacturing method of the first embodiment. A substrate 11 to which a part 10 is bonded is manufactured. Next, an n-type GaAs layer 21 having a thickness of 0.5 μm, for example, is epitaxially grown as a buffer layer on a part 10 of the semiconductor single crystal. Next, As in the n-type GaAs layer 21 is diffused into the semiconductor single crystal 10 to form an n-type Ge layer (not shown) having a thickness of, for example, 0.1 μm on the surface of the semiconductor crystal 10.

Next, an n-type InGaP layer 22 having a thickness of, for example, 0.02 μm is epitaxially grown on the n-type GaAs layer 21, and a p-type AlGaAs layer 23 having a thickness of, for example, 0.02 μm is epitaxially grown on the n-type InGaP layer 22. Here, the n-type InGaP layer 22 and the p-type AlGaAs layer 23 form a tunnel junction.

Next, a p-type InGaP layer 24 having a thickness of, for example, 0.1 μm is epitaxially grown on the p-type AlGaAs layer 23 as a back surface field layer, and a p-type GaAs layer 25 having a thickness of, for example, 3 μm is formed on the p-type InGaP layer 24 as a base layer. Is epitaxially grown. An n-type GaAs layer 26 having a thickness of 0.1 μm, for example, is epitaxially grown on the p-type GaAs layer 25 as an emitter layer, and an n-type AlInP layer 27 having a thickness of 0.03 μm, for example, as a window layer on the n-type GaAs layer 26. Is epitaxially grown.

Next, an n-type InGaP layer 28 having a thickness of, for example, 0.02 μm is epitaxially grown on the n-type AlInP layer 27, and a p-type AlGaAs layer 29 having a thickness of, for example, 0.02 μm is epitaxially grown on the n-type InGaP layer 28. Here, the n-type InGaP layer 28 and the p-type AlGaAs layer 29 form a tunnel junction.

Next, a p-type AlInP layer 30 having a thickness of, for example, 0.03 μm is epitaxially grown on the p-type AlGaAs layer 29 as a back surface field layer, and a p-type InGaP having a thickness of, for example, 0.5 μm is formed on the p-type AlInP layer 30 as a base layer. Layer 31 is grown epitaxially. Then, an n-type InGaP layer 32 having a thickness of, for example, 0.05 μm is epitaxially grown on the p-type InGaP layer 31 as an emitter layer, and an n-type AlInP layer 33 having a thickness of, for example, 0.03 μm as a window layer on the n-type InGaP layer 32. Is epitaxially grown.

Next, an n-type GaAs layer 34 having a thickness of 0.5 μm, for example, is epitaxially grown on the n-type AlInP layer 33 as a cap layer. Thereby, the solar cell structure 20 shown in FIG. 2 can be produced.

As a condition for the above epitaxial growth, the temperature was about 700.degree. As a raw material for growing the GaAs layer, for example, TMG (trimethylgallium) and AsH ₃ (arsine) can be used. Moreover, as a raw material for growing the InGaP layer, for example, TMI (trimethylindium), TMG, and PH ₃ (phosphine) can be used. Further, as a raw material for growing the AlInP layer, for example, TMA (trimethylaluminum), TMI, and PH ₃ can be used. As an n-type impurity source for forming the n-type GaAs layer, the n-type InGaP layer, and the n-type AlInP layer, for example, SiH ₄ (monosilane) can be used. As a p-type impurity source for forming the p-type GaAs layer, the p-type InGaP layer, and the p-type AlInP layer, for example, DEZn (diethyl zinc) can be used. As a raw material for growing the AlGaAs layer, for example, TMI, TMG, and AsH ₃ can be used, and as a p-type impurity source for forming the p-type AlGaAs layer, for example, CBr ₄ (four odors) is used. Carbon) can be used.

Next, as shown in FIG. 3, a part of the n-type GaAs layer 34 is removed into a predetermined pattern using, for example, an ammonia-based etchant. Then, for example, a Ti film having a thickness of 50 nm, for example, a Pd film having a thickness of 20 nm, for example, an Ag film having a thickness of 3000 nm, is sequentially deposited on the surface of the remaining n-type GaAs layer 34 and then heat-treated. A surface electrode 35 is formed as shown.

Thereafter, as shown in FIG. 5, an Au film having a thickness of, for example, 100 nm and an Ag film having a thickness of, for example, 5000 nm are sequentially deposited on the surface of the support substrate 3 opposite to the side on which the part 10 of the semiconductor single crystal is formed. After that, the back electrode 36 is formed by heat treatment.

By the above, a compound semiconductor solar cell can be manufactured with the manufacturing method of the solar cell of Embodiment 2. The compound semiconductor solar cell manufactured by the method for manufacturing a solar cell according to the second embodiment does not need to be polished using a mechanical chemical polishing technique, and can be manufactured at a low cost, using the substrate 11 of the first embodiment as a seed substrate. Therefore, it can be manufactured at a low cost.

[Embodiment 3]
FIGS. 6 to 25 are schematic cross-sectional views illustrating manufacturing steps of the solar cell manufacturing method according to Embodiment 3, which is another example of the solar cell manufacturing method of the present invention. Hereinafter, a method for manufacturing the solar cell of Embodiment 3 will be described with reference to FIGS. The solar cell manufacturing method of Embodiment 3 is characterized in that a compound semiconductor solar cell element is manufactured by reverse stacking using the substrate 11 manufactured by the substrate manufacturing method of Embodiment 1 as a seed substrate.

First, as shown in FIG. 6, an etching stop layer 40 made of InGaP, a contact layer 41 made of n-type AlInP, and an emitter made of n-type InGaP are formed on a portion 10 of a semiconductor single crystal made of GaAs single crystal on the substrate 11. The layer 42, the base layer 43 made of p-type InGaP, and the buffer layer 44 made of p-type AlInP are epitaxially grown in this order. In the third embodiment, the solar cell structure 20 is configured by a stacked body of the contact layer 41, the emitter layer 42, the base layer 43, and the buffer layer 44.

Next, as shown in FIG. 7, a back electrode 45 is formed on the buffer layer 44. The back electrode 45 can be formed by, for example, applying a metal paste containing Ag (silver) or the like on the surface of the buffer layer 44 and then baking it.

Next, as shown in FIG. 8, a highly heat-resistant back film 46 is formed on the back electrode 45. As the back film 46, for example, polyimide can be used.

Next, as shown in FIG. 9, a reinforcing material 47 for reinforcing the compound semiconductor layer is pasted on the back film 46. As the reinforcing material 47, a polyester (PET) film or the like can be used.

Next, as shown in FIG. 10, the substrate 11 is removed from the etching stop layer 40. The substrate 11 can be removed, for example, by etching the substrate 11 using a first etching solution. As the first etching solution, for example, an etchant having an etching rate of the substrate 11 higher than that of the etching stop layer 40 can be used.

Next, as shown in FIG. 11, the etching stop layer 40 is removed. The etching stop layer 40 can be removed by etching using, for example, a second etching solution. As the second etching solution, for example, an etchant having an etching rate of the etching stop layer 40 higher than that of the contact layer 41 can be used.

Next, as shown in FIG. 12, a protective film 48 is formed on the surface of the contact layer 41. As the protective film 48, for example, a photoresist or the like having etching resistance against a third etching solution used for etching the contact layer 41 in a patterning step of the contact layer 41 described later can be used.

Next, as shown in FIG. 13, the protective film 48 is patterned into a predetermined shape. The protective film 48 is patterned into the shape of the contact layer 41 remaining on the emitter layer 42 in the patterning step of the contact layer 41 described later.

Next, as shown in FIG. 14, the contact layer 41 is patterned. The patterning of the contact layer 41 can be performed, for example, by removing a part of the contact layer 41 with a third etching solution used for etching the contact layer 41 as described above. At this time, the protective film 48 functions as an etching mask for the third etching solution. Thereafter, as shown in FIG. 15, the protective film 48 is removed from the contact layer 41.

Next, as shown in FIG. 16, a protective film 49 is formed so as to cover the emitter layer 42 and the contact layer 41 after patterning. As the protective film 49, for example, a photoresist having etching resistance against a fourth etching solution used for etching the emitter layer 42 and the base layer 43 in a patterning process of the emitter layer 42 and the base layer 43 described later is used. Can do.

Next, as shown in FIG. 17, the protective film 49 is patterned into a predetermined shape. The protective film 49 is patterned into the shape of the emitter layer 42 and the base layer 43 remaining on the buffer layer 44 in the patterning step of the emitter layer 42 and the base layer 43 described later.

Next, as shown in FIG. 18, the emitter layer 42 and the base layer 43 are patterned. The emitter layer 42 and the base layer 43 are patterned by, for example, removing a part of the emitter layer 42 and the base layer 43 with the fourth etching solution used for etching the emitter layer 42 and the base layer 43 as described above. Can be done. At this time, the protective film 49 functions as an etching mask for the fourth etching solution. Thereafter, as shown in FIG. 19, the protective film 49 is removed from the emitter layer 42 and the patterned contact layer 41.

Next, as shown in FIG. 20, a protective film 50 is formed so as to cover the buffer layer 44, the contact layer 41 after patterning, the emitter layer 42, and the base layer 43. As the protective film 50, for example, a photoresist that can be used in a surface electrode lift-off process described later can be used.

Next, as shown in FIG. 21, the protective film 50 is patterned into a predetermined shape. The protective film 50 is patterned so as to have an opening 52 at a surface electrode formation location to be described later.

Next, as shown in FIG. 22, the surface electrode 51 is formed so as to cover the protective film 50 having the opening 52. Next, as shown in FIG. 23, the protective film 50 on which the surface electrode 51 is formed is removed by lift-off. As a result, the surface electrode 51 remains only on the surface of the contact layer 41 exposed from the opening 52 of the protective film 50.

Next, as shown in FIG. 24, the back film 46 is peeled from the reinforcing material 47.
Next, as shown in FIG. 25, a compound semiconductor solar cell element can be manufactured by the solar cell manufacturing method of Embodiment 3 by separating into a plurality of compound semiconductor solar cell elements. The compound semiconductor solar cell element manufactured by the method for manufacturing a solar cell according to the third embodiment also does not need to be polished using a mechanical chemical polishing technique, and can be manufactured at a low cost. Therefore, it can be manufactured at low cost.

(1) Ion implantation As the semiconductor single crystal, a 6 ° off substrate of Ge single crystal having a (100) surface having a diameter of 4 inches and a thickness of 500 μm was used. Hydrogen ions (H +) were implanted into the (100) surface of this semiconductor single crystal at an implantation depth of 1.1 μm with an implantation amount of 1 × 10 ¹⁷ cm ² with an implantation energy of 150 keV.

(2) Formation of Support Substrate Next, an aluminum oxide film having a thickness of 100 nm was formed by sputtering at room temperature on the surface of the Ge single crystal after the above hydrogen ion implantation. Next, a mixture of aluminum oxide powder and water glass was applied onto the aluminum oxide film formed by sputtering. Thereafter, the aluminum oxide powder and water glass mixture were dried at room temperature for 10 hours, then dried at 90 ° C. for 3 hours, and then dried at 150 ° C. for 1 hour, whereby the aluminum oxide powder was formed on the surface of the Ge single crystal. A support substrate composed of a mixture of water and glass was formed. The support substrate was thicker than 0.2 mm, and the support substrate had pores.

(3) Peeling of the support substrate from the semiconductor single crystal The Ge single crystal on which the support substrate composed of the mixture of aluminum oxide powder and water glass was formed as described above was heated in a nitrogen atmosphere at 520 ° C. for 15 minutes. As a result, the support substrate could be peeled off while a part of the semiconductor single crystal, in this case, a Ge single crystal film having a thickness of about 1.1 μm was bonded to the support substrate.

(4) Characteristics of Support Substrate A substrate composed of the support substrate and the semiconductor single crystal bonded to the support substrate as described above can be manufactured at a lower cost than the method described in Patent Document 1. This leads to the ability to manufacture solar cells at low cost. The surface roughness Ra of the Ge single crystal film was larger than 10 nm. Further, the surface roughness Ra of the Ge single crystal film may be reduced by removing the oxide film by treating the surface of the support substrate with hydrogen fluoride and then heating the substrate at about 900 ° C. in a hydrogen atmosphere. It becomes possible.

Although the embodiments and examples have been described above, it is also planned from the beginning to appropriately combine the configurations of the above-described embodiments and examples.

The embodiments and examples disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 semiconductor single crystal, 1a surface, 2 atomic species, 3 support substrate, 10 part of semiconductor single crystal, 11 substrate, 20 solar cell structure, 21 n-type GaAs layer, 22 n-type InGaP layer, 23 p-type AlGaAs layer 24 p-type InGaP layer, 25 p-type GaAs layer, 26 n-type GaAs layer, 27 n-type AlInP layer, 28 n-type InGaP layer, 29 p-type AlGaAs layer, 30 p-type AlInP layer, 31 p-type InGaP layer, 32 n-type InGaP layer, 33 n-type AlInP layer, 34 n-type GaAs layer, 35 surface electrode, 36 back electrode, 40 etching stop layer, 41 contact layer, 42 emitter layer, 43 base layer, 44 buffer layer, 45 back electrode, 46 back film, 47 reinforcing material, 48, 49, 50 protective film, 51 table Electrode, 52 opening.

Claims

Implanting atomic species into a semiconductor single crystal containing at least one atom selected from the group consisting of germanium, gallium and indium;
Supported by at least one method selected from the group consisting of a vapor deposition method, a CVD method, a plating method, a printing method, a sputtering method, a sol-gel method, and a thermal spraying method on the surface of the semiconductor single crystal after the implantation of the atomic species. Forming a substrate;
Separating the semiconductor single crystal in a state of being formed on the support substrate.
The method for manufacturing a substrate according to claim 1, wherein the atomic species include hydrogen ions.
3. The method of manufacturing a substrate according to claim 1, wherein the support substrate includes at least one selected from the group consisting of metal, silicon, a metal silicon compound, and a metal oxide.
The ratio of the difference between the linear thermal expansion coefficient of the support substrate and the linear thermal expansion coefficient of the semiconductor single crystal to the linear thermal expansion coefficient of the semiconductor single crystal is within ± 30%. The manufacturing method of the board | substrate of any one of Claims 1.
A step of manufacturing a substrate by the method of manufacturing a substrate according to any one of claims 1 to 4,
Forming a solar cell structure on the substrate;
Forming a first electrode on the substrate;
Forming a second electrode on the solar cell structure.
A step of manufacturing a substrate by the method of manufacturing a substrate according to any one of claims 1 to 4,
Forming a solar cell structure on the substrate;
Removing the substrate after the step of forming the solar cell structure;
Forming a first electrode and a second electrode on the solar cell structure.
A non-single crystal film;
A single crystal film joined to the non-single crystal film,
The single crystal film includes at least one atom selected from the group consisting of germanium, gallium, and indium;
The non-single crystal film is thicker than the single crystal film,
The non-single crystal film includes at least one selected from the group consisting of metal, silicon, metal silicon compound, and metal oxide,
The non-single crystal film has a crystal grain boundary or pores at an interface with the single crystal film.
The ratio of the linear thermal expansion coefficient of the non-single crystal film and the linear thermal expansion coefficient of the single crystal film to the linear thermal expansion coefficient of the single crystal film is within ± 30%. substrate.
The substrate according to claim 7 or 8, wherein the non-single crystal film has a thickness of 5 µm to 200 µm.
A substrate according to any one of claims 7 to 9,
And a solar cell structure on the substrate.