WO2017195276A1

WO2017195276A1 - Information processing device and reboot control method

Info

Publication number: WO2017195276A1
Application number: PCT/JP2016/063898
Authority: WO
Inventors: 由梨香 ▲高▼橋; 章雄出原; 寛隆茂田井; 章代田口
Original assignee: 三菱電機株式会社
Priority date: 2016-05-10
Filing date: 2016-05-10
Publication date: 2017-11-16
Also published as: JP6073004B1; JPWO2017195276A1; TW201740274A; TWI632454B

Abstract

According to the present invention, if an abnormality has arisen in one of a plurality of operating systems, a hypervisor (101) causes the core (111) running the operating system in which the abnormality has arisen to reboot the operating system in which the abnormality has arisen. During the reboot, the hypervisor monitors the state of an information processing device (100). If the information processing device assumes, during the reboot, a state meeting a restriction condition for restricting the reboot, then the hypervisor performs restriction control to restrict the reboot.

Description

Information processing apparatus and restart control method

The present invention relates to control when an operating system is restarted in an information processing apparatus that operates a plurality of operating systems.

With the development of virtualization technology associated with high performance of CPUs (Central Processing Units), it is possible to install a plurality of OSs (Operating Systems) in one information processing system. Software that controls a plurality of OSs is called a hypervisor, and an OS controlled by the hypervisor is called a guest OS.
The virtualization technology is used in various fields including FA (Factory Automation).
Specifically, the virtualization technology is used in an environment in which a real-time OS for performing processing with high real-time characteristics and a general-purpose OS such as Windows (registered trademark) are simultaneously executed on a single hardware platform. .

Patent Document 1 discloses a technique for performing processing when an abnormality occurs in the guest OS.
In this technique, the master OS determines the operating status of each guest OS using a WDC (watchdog counter). If it is determined that the guest OS is in an abnormal state, the guest OS in the abnormal state is restarted.

However, when a guest OS in an abnormal state is restarted, a restart process is performed by the hypervisor, which causes an overhead for a real-time OS that is in operation. As a result, the performance of the operating real-time OS is degraded.
Therefore, when the restart process by the hypervisor is performed, it is required to reduce the overhead for the operating real-time OS in order to suppress the performance degradation of the operating real-time OS.

In the restart process, input / output initialization and the like are performed, so there is a possibility of frequent access to the bus. The frequent access to the bus causes an overhead for the operating real-time OS.
Specifically, when the operating real-time OS accesses the bus and the bus is frequently accessed in the restart process, the operating real-time OS must wait for the bus to be released. As a result, real-time properties are hindered.

JP 2009-116699 A

An object of the present invention is to suppress a decrease in performance of an operating system that is in operation during the restart of the operating system.

The information processing apparatus of the present invention includes a multi-core processor having a plurality of processor cores, and operates a plurality of operating systems by the plurality of processor cores.
The information processing apparatus includes:
A restart unit that causes a processor core included in the plurality of processor cores to restart the operating system in which an abnormality has occurred when an abnormality occurs in the operating system included in the plurality of operating systems;
A state monitoring unit that monitors the state of the information processing apparatus during execution of the restart;
A restart control unit configured to perform restriction control for restricting execution of the restart when a state of the information processing apparatus satisfies a restriction condition for restricting execution of the restart during execution of the restart;

According to the present invention, it is possible to suppress a decrease in performance of the operating system that is in operation while the operating system is restarted.

1 is a configuration diagram of an information processing apparatus 100 according to Embodiment 1. FIG. FIG. 3 is a configuration diagram of a processor 110 according to the first embodiment. 2 is a configuration diagram of a hypervisor unit 140 according to Embodiment 1. FIG. 5 is a flowchart of a restart control method according to the first embodiment. The block diagram of the restart control part 144 in Embodiment 2. FIG. 10 is a flowchart of a restart control method according to the second embodiment. 10 is another flowchart of the restart control method according to the second embodiment. FIG. 6 is a configuration diagram of an information processing apparatus 100 according to Embodiment 3. FIG. 10 is a configuration diagram of a restart control unit 144 according to the third embodiment. 10 is a flowchart of a restart control method according to Embodiment 3. 10 is another flowchart of the restart control method according to Embodiment 3. FIG. 6 is a configuration diagram of an information processing apparatus 100 according to a fourth embodiment. FIG. 10 is a configuration diagram of a restart control unit 144 according to the fourth embodiment. 10 is a flowchart of a restart control method according to the fourth embodiment.

In the embodiment and the drawings, the same reference numerals are given to the same elements or elements corresponding to each other. Description of elements having the same reference numerals will be omitted or simplified as appropriate.

Embodiment 1 FIG.
An information processing apparatus 100 that operates a plurality of operating systems will be described with reference to FIGS.

*** Explanation of configuration ***
Based on FIG. 1, the hardware configuration and software configuration of the information processing apparatus 100 will be described.
The information processing apparatus 100 includes hardware such as a processor 110, a memory 121, a WDT 122, an I / O device 123, and a cache 129.
The processor 110 is connected to the memory 121, the WDT 122, the I / O device 123, and the cache 129 via the bus 120.

The processor 110 is a multi-core processor including a plurality of processor cores. Specifically, the processor 110 is a multi-core CPU (Central Processing Unit).
The processor 110 includes a core 111A and a core 111B as a plurality of processor cores.
The core 111A is a processor core that executes the hypervisor 101, the real-time OS 102, and the real-time application 103. The hypervisor 101, the real-time OS 102, and the real-time application 103 will be described later.
The core 111 </ b> B is a processor core that executes the general-purpose OS 104 and the general-purpose application 105. The general-purpose OS 104 and the general-purpose application 105 will be described later.
The core 111A and the core 111B are collectively referred to as the core 111.

Furthermore, the processor 110 includes hardware such as a frequency changing mechanism 112, a clock generator 113, and an interrupt controller 114.
The frequency changing mechanism 112 changes the operating frequency of the core 111 by controlling the clock generator 113.
The clock generator 113 generates a clock signal corresponding to the operating frequency.
The interrupt controller 114 detects an interrupt from the I / O device 123 and generates an interrupt signal.

The memory 121 is a storage device. The memory 121 is also referred to as a main storage device or a main memory. Specifically, the memory 121 is a RAM (Random Access Memory).

WDT 122 is a watchdog timer used for detecting an abnormality in the operating system.

The I / O device 123 is an input / output device. I / O is an abbreviation for input / output.

The cache 129 is a storage device that can be accessed faster than accessing the memory 121.

Hardware such as the memory 121, the WDT 122, the I / O device 123, and the cache 129 is accessed from the plurality of cores 111.

The information processing apparatus 100 executes software such as a hypervisor 101, a real-time OS 102, a real-time application 103, a general-purpose OS 104, and a general-purpose application 105.

The hypervisor 101 is software for executing a plurality of operating systems simultaneously.
Specifically, the plurality of operating systems are a real-time OS 102 and a general-purpose OS 104. OS is an abbreviation for operating system.

The real time OS 102 is an operating system for executing the real time application 103.
The real-time application 103 is an application program for real-time processing. Real-time processing is processing with high real-time characteristics.

The general purpose OS 104 is an operating system for executing the general purpose application 105.
The general application 105 is an application program for general processing. General-purpose processing is processing other than real-time processing.

The functional configuration of the core 111 of the processor 110 will be described with reference to FIG.
The core 111A includes functional components such as an OS unit 131A, an application unit 132A, and a hypervisor unit 140.
The OS unit 131A operates the real-time OS 102 by executing the real-time OS 102.
The application unit 132A executes the real-time application 103.
The hypervisor unit 140 executes the hypervisor 101.

The core 111B includes functional components such as an OS unit 131B and an application unit 132B.
The OS unit 131B operates the general-purpose OS 104 by executing the general-purpose OS 104.
The application unit 132B executes the general-purpose application 105.

The functional configuration of the hypervisor unit 140 will be described based on FIG.
The hypervisor unit 140 includes an abnormality detection unit 141, a restart unit 142, a state monitoring unit 143, and a restart control unit 144. These functions will be described later.

*** Explanation of operation ***
A restart control method will be described.
The restart control method is a method for suppressing the influence of restart on the operation of an operating OS while any OS (operating system) is restarted.
The procedure of the restart control method corresponds to the procedure of the restart control program.

The restart control method will be described based on FIG.
Step S110 is an abnormality detection process.
In step S110, a plurality of OSs are operating. Specifically, the OS unit 131A of the core 111A operates the real-time OS 102, and the OS unit 131B of the core 111B operates the general-purpose OS 104.
The abnormality detection unit 141 monitors the operation of the operating OS using the WDT 122 (watchdog timer).
When an abnormality occurs in the operating OS, the abnormality detection unit 141 detects an abnormality that has occurred in the operating OS.
If an abnormality that has occurred in the operating OS is detected, that is, if an abnormality has occurred in the operating OS, the process proceeds to step S120.

In the description after step S120, the OS in which an abnormality has occurred in step S110 is referred to as a target OS.

Step S120 is a restart process.
In step S120, the restart unit 142 causes the core 111 to restart the target OS. The restart unit 142 is one of the functions of the hypervisor unit 140 provided in the core 111A.
When the target OS is the real-time OS 102, the core 111A starts restarting the real-time OS 102.
When the target OS is the general-purpose OS 104, the restart unit 142 instructs the core 111B to restart the general-purpose OS 104, and the core 111B starts restarting the general-purpose OS 104.

Step S130 is a state monitoring process.
In step S130, the state monitoring unit 143 performs state monitoring.
The state monitoring is an operation for monitoring the state of the information processing apparatus 100 during execution of restart.
Specific status monitoring will be described in the second and subsequent embodiments.

Steps S141 to S143 are restart control processing.
In step S141, the restart control unit 144 determines whether the state of the information processing apparatus 100 satisfies the restriction condition during the execution of the restart.
The restriction condition is a condition for restricting execution of restart.
Specific restriction conditions will be described in the second and subsequent embodiments.
If the state of the information processing apparatus 100 satisfies the restriction condition, the process proceeds to step S142.

In step S142, the restart control unit 144 performs restriction control.
The restriction control is control for restricting execution of restart.
Specific restriction control will be described in the second and subsequent embodiments.

In step S143, the restart control unit 144 determines whether the restart has been completed.
Specifically, the restart control unit 144 determines whether the restart has ended by referring to the state of the restart process.
When the restart is finished, the process is finished.
If the restart has not ended, the process returns to step S130.

*** Effects of Embodiment 1 ***
By limiting the execution of the restart during the restart of the OS, it is possible to suppress a decrease in the performance of the operating OS.

*** Other configurations ***
The number of OSs may be three or more.
Each OS may be either the real-time OS 102 or the general-purpose OS 104, or may be another type of OS.

The number of cores 111 may be three or more.
The core 111B may include the hypervisor unit 140. That is, the hypervisor 101 may be executed by the core 111B.
The information processing apparatus 100 may include a core that executes the hypervisor 101 in addition to the core 111 that executes the OS. That is, the hypervisor unit 140 may be provided in a core different from the core 111 that executes the OS.

Embodiment 2. FIG.
With respect to the form in which the number of accesses per unit time to the memory 121 at the time of restarting is the target of state monitoring, differences from the first embodiment will be mainly described with reference to FIGS.

*** Explanation of configuration ***
The hardware configuration and software configuration of the information processing apparatus 100 are the same as those in FIG. 1 of the first embodiment.
The functional configuration of the core 111 is the same as that in FIG. 2 of the first embodiment.
The functional configuration of the hypervisor unit 140 is the same as that in FIG. 3 of the first embodiment.

Based on FIG. 5, the functional configuration of the restart control unit 144 will be described.
The restart control unit 144 includes an access amount determination unit 151, a frequency determination unit 152, and a frequency change unit 153. These functions will be described later.

*** Explanation of operation ***
The state monitoring, the limiting conditions, and the limiting control in the second embodiment are as follows.
The state of the information processing apparatus 100 monitored by the state monitoring is the target access amount.
The target access amount is the number of accesses per unit time to the memory 121 upon restart. That is, the target access amount is the number of accesses that have occurred in the memory 121 per unit time due to restart.

The restriction condition is a condition that the target access amount exceeds the reference value. The reference value is a predetermined value.
The restriction control is control for making the operating frequency of the target core lower than the operating frequency of the target core before the target access amount exceeds the reference value. The target core is the core 111 that performs restart.

The restart control method will be described based on FIG.
Step S210 and step S220 are the same as step S110 and step S120 of FIG. 4 in the first embodiment.
That is, when an abnormality occurs in the operating OS in S210, restart of the OS in which the abnormality has occurred is started in step S220.

Step S230 corresponds to step S143 of FIG. 4 in the first embodiment.
In step S230, the restart control unit 144 determines whether the restart has been completed. The determination method is the same as step S143 in FIG. 4 in the first embodiment.
If the restart is completed, the process proceeds to step S260.
If the restart has not ended, the process proceeds to step S240.

Step S240 corresponds to step S130 of FIG. 4 in the first embodiment.
In step S240, the state monitoring unit 143 monitors the target access amount.
Specifically, the state monitoring unit 143 functions as a performance monitor for the target core, and acquires the number of accesses per unit time to the memory 121 by the restart process. The obtained number of accesses is the target access amount.

Step S251 corresponds to step S141 of FIG. 4 in the first embodiment.
In step S251, the access amount determination unit 151 compares the target access amount with a reference value.
If the target access amount exceeds the reference value, the process proceeds to step S252.
If the target access amount does not exceed the reference value, the process returns to step S230.

In step S252, the access amount determination unit 151 determines whether the target access amount is the first time that exceeds the reference value.
Specifically, the number flag is stored in the memory 121. The access amount determination unit 151 sets the number flag to 0 after step S220 and before step S230. Then, the access amount determination unit 151 determines whether or not the value of the count flag is 0 in step S252. A count flag value of 0 means the first time the target access amount exceeds the reference value.
If the target access amount exceeds the reference value, the process proceeds to step S253.
If it is not the first time that the target access amount exceeds the reference value, the process proceeds to step S254.

In step S253, the frequency changing unit 153 stores the operating frequency of the target core.
Specifically, the frequency changing unit 153 acquires the operating frequency of the target core from the target core, and stores the acquired operating frequency in the memory 121.

The operating frequency stored in step S253 is referred to as a normal frequency.
The normal frequency corresponds to the operating frequency of the target core before the target access amount exceeds the reference value.

Step S254 corresponds to step S142 of FIG. 4 in the first embodiment.
In step S254, the frequency changing unit 153 makes the operating frequency of the target core lower than the normal frequency.
Specifically, the low frequency is stored in the memory 121. The low frequency is a predetermined frequency and is a frequency lower than the normal frequency. The frequency determination unit 152 acquires a low frequency from the memory 121. Then, the frequency changing unit 153 uses the frequency changing mechanism 112 and the clock generator 113 to change the operating frequency of the target core to a low frequency.

Further, the frequency changing unit 153 sets 1 to the number flag described in step S252. The value 1 of the count flag means the second and subsequent times when the target access amount exceeds the reference value.
After step S254, the process returns to step S230.

In step S260, the frequency changing unit 153 returns the operating frequency of the target core to the normal frequency. However, when the operating frequency of the target core is not changed from the normal frequency, it is not necessary to return the operating frequency of the target core to the normal frequency.
Specifically, the frequency determination unit 152 refers to the number flag. When the value of the count flag is 0, it is not necessary to return the operating frequency of the target core to the normal frequency. When the value of the count flag is 1, the frequency determination unit 152 acquires the normal frequency stored in step S253 from the memory 121. Then, the frequency changing unit 153 uses the frequency changing mechanism 112 and the clock generator 113 to change the operating frequency of the target core to the normal frequency.

*** Effects of Embodiment 2 ***
By lowering the operating frequency of the core 111 that is to be restarted, it is possible to reduce the number of accesses per unit time to the memory 121 upon restart.
As a result, the occupancy rate of the bus 120 at the time of restart is reduced, and the waiting time of the operating OS when accessing the hardware via the bus 120 is reduced.
Therefore, it is possible to suppress a decrease in the performance of the operating OS.

*** Other configurations ***
In step S254 of FIG. 6, the frequency changing unit 153 may change the operating frequency of the target core to a low frequency corresponding to the operating frequency of the target core.
In that case, the frequency determination unit 152 determines a low frequency using the frequency table.
The frequency table is a table in which a frequency range and a low frequency are associated with each other. The frequency table is stored in the memory 121.
Specifically, the frequency determination unit 152 selects a frequency range including the operating frequency of the target core from the frequency table, and acquires a low frequency associated with the selected frequency range from the frequency table.

When the target access amount is large, the restart control unit 144 may pause the restart.
Based on FIG. 7, a re-control method for pausing the restart when the target access amount exceeds the reference value will be described.

Steps S210 to S240 and step S260 are as described in FIG.
In step S271, the access amount determination unit 151 compares the target access amount with the first reference value.
If the target access amount exceeds the first reference value, the process proceeds to step S272.
If the target access amount does not exceed the first reference value, the process returns to step S230.

Step S272 and step S273 are the same as step S252 and step S253 of FIG.

In step S274, the access amount determination unit 151 compares the target access amount with the second reference value. The second reference value is larger than the first reference value. That is, the number of accesses indicated by the second reference value is greater than the number of accesses indicated by the first reference value.
If the target access amount exceeds the second reference value, the process proceeds to step S276.
If the target access amount does not exceed the second reference value, the process proceeds to step S275.

Step S275 is the same as step S254 in FIG. After step S275, the process returns to step S230.

In step S276, the restart control unit 144 pauses the restart.
Specifically, the restart control unit 144 switches the restart process from the execution state or the executable state to the sleep state. Then, the restart control unit 144 sets the restart process to an execution state or an executable state when a pause time elapses after the restart process is set to the sleep state.
After step S276, the process returns to step S230.

Embodiment 3 FIG.
With respect to the form in which the amount of direct memory access that occurs in the memory 121 upon restart is the target of state monitoring, differences from the first embodiment will be mainly described with reference to FIGS.

*** Explanation of configuration ***
Based on FIG. 8, the hardware configuration of the information processing apparatus 100 will be described.
The information processing apparatus 100 includes hardware such as a bus controller 124 and a DMA controller 125 in addition to the hardware described in the first embodiment. DMA is an abbreviation for direct memory access.

The software configuration of the information processing apparatus 100 is the same as that in FIG. 1 of the first embodiment.
The functional configuration of the core 111 is the same as that in FIG. 2 of the first embodiment.
The functional configuration of the hypervisor unit 140 is the same as that in FIG. 3 of the first embodiment.

Based on FIG. 9, the functional configuration of the restart control unit 144 will be described.
The restart control unit 144 includes an access amount determination unit 161 and an instruction conversion unit 162. These functions will be described later.

*** Explanation of operation ***
The state monitoring, the limiting conditions, and the limiting control in the third embodiment are as follows.
The state of the information processing apparatus 100 monitored by the state monitoring is the target access amount.
The target access amount is an access amount of direct memory access that occurs with respect to the memory 121 upon restart. Specifically, the access amount is the number of DMA instructions or the size of data to be accessed. The DMA instruction is a direct memory access instruction and is executed by the DMA controller 125.

The restriction condition is a condition that the target access amount exceeds the reference value. The reference value is a predetermined value.
The restriction control is a control for converting a direct memory access instruction generated to the memory 121 upon restart into a program control instruction. The program control method is called PIO (Programmed I / O). A program control type instruction is called a PIO instruction. The PIO instruction is executed by the bus controller 124.

Based on FIG. 10, the restart control method will be described.
Step S310 and step S320 are the same as step S110 and step S120 of FIG. 4 in the first embodiment.
That is, when an abnormality occurs in the operating OS in step S310, restart of the OS in which the abnormality has occurred is started in step S320.

Step S330 corresponds to step S143 of FIG. 4 in the first embodiment.
In step S330, the restart control unit 144 determines whether the restart has been completed. The determination method is the same as step S143 in FIG. 4 in the first embodiment.
When the restart is finished, the process is finished.
If the restart has not ended, the process proceeds to step S340.

Step S340 corresponds to step S130 of FIG. 4 in the first embodiment.
In step S340, the state monitoring unit 143 monitors the target access amount.
Specifically, the state monitoring unit 143 detects the DMA instruction generated by the restart and obtains the number of detected DMA instructions. Alternatively, the state monitoring unit 143 detects a DMA instruction and obtains the size of data accessed by the detected DMA instruction. The required number of DMA instructions or the size of data is the target access amount.

Step S351 corresponds to step S141 in FIG. 4 in the first embodiment.
In step S351, the access amount determination unit 161 compares the target access amount with a reference value.
If the target access amount exceeds the reference value, the process proceeds to step S352.
If the target access amount does not exceed the reference value, the DMA instruction generated by the restart is executed by the DMA controller 125, and the process returns to step S330.

Step S352 corresponds to step S142 of FIG. 4 in the first embodiment.
In step S352, the instruction conversion unit 162 converts the DMA instruction generated by the restart into a PIO instruction. The converted PIO instruction is executed by the bus controller 124.
After step S352, the process returns to step S330.

*** Effects of Embodiment 3 ***
By converting the DMA instruction generated at the restart into the PIO instruction, the number of accesses per unit time to the memory 121 at the restart can be reduced.
As a result, the occupancy rate of the bus 120 at the time of restart is reduced, and the waiting time of the operating OS when accessing the hardware via the bus 120 is reduced.
Therefore, it is possible to suppress a decrease in the performance of the operating OS.

*** Other configurations ***
When the target access amount is large, the restart control unit 144 may convert some or all of the DMA instructions generated by the restart into PIO instructions.
Based on FIG. 11, a restart control method for converting a part or all of DMA instructions generated by restart into PIO instructions when the target access amount exceeds the reference value will be described.

Steps S310 to S340 are as described in FIG.
In step S361, the access amount determination unit 161 compares the target access amount with the first reference value.
If the target access amount exceeds the first reference value, the process proceeds to step S362.
If the target access amount does not exceed the first reference value, the process returns to step S330.

In step S362, the access amount determination unit 161 compares the target access amount with the second reference value. The second reference value is larger than the first reference value. That is, the access amount indicated by the second reference value is larger than the access amount indicated by the first reference value.
If the target access amount exceeds the second reference value, the process proceeds to step S364.
If the target access amount does not exceed the second reference value, the process proceeds to step S363.

In step S363, the instruction conversion unit 162 selects some DMA instructions from the DMA instructions generated by the restart, and converts the selected DMA instructions into PIO instructions. Specifically, the instruction conversion unit 162 converts half of the DMA instructions into PIO instructions. The DMA instruction that has not been converted is executed by the DMA controller 125, and the PIO instruction after conversion is executed by the bus controller 124.
After step S363, the process returns to step S330.

In step S364, the instruction conversion unit 162 converts the DMA instruction generated by the restart into a PIO instruction. Specifically, the instruction conversion unit 162 converts all DMA instructions generated by the restart into PIO instructions. The converted PIO instruction is executed by the bus controller 124.
After step S364, the process returns to step S330.

Embodiment 4 FIG.
Based on FIG. 12 to FIG. 14, the differences between the first embodiment and the first embodiment in which the miss rate of the cache miss that occurs when the cache 129 is accessed from the OS that is not the restart target are mainly monitored. explain.

*** Explanation of configuration ***
Based on FIG. 12, the hardware configuration of the information processing apparatus 100 will be described.
The information processing apparatus 100 includes hardware called a cache controller 126 in addition to the hardware described in the first embodiment.

Based on FIG. 13, a functional configuration of the restart control unit 144 will be described.
The restart control unit 144 includes a miss rate determination unit 171 and an access control unit 172. The function of the access control unit 172 will be described later.

*** Explanation of operation ***
The state monitoring, the limiting condition, and the limiting control in the fourth embodiment are as follows.
The state of the information processing apparatus 100 monitored by the state monitoring is a target error rate.
The target miss rate is a miss rate of a cache miss that occurs when the cache 129 is accessed from an operating system that is not the target of restart.

The limiting condition is a condition that the target error rate exceeds the reference value. The reference value is a predetermined value.
The restriction control is control for prohibiting access to the cache 129 from the operating system being restarted.

Based on FIG. 14, the restart control method will be described.
Step S410 and step S420 are the same as step S110 and step S120 of FIG. 4 in the first embodiment.
That is, when an abnormality occurs in the operating OS in step S410, restart of the OS in which the abnormality has occurred is started in step S420.

Step S430 corresponds to step S143 of FIG. 4 in the first embodiment.
In step S430, the restart control unit 144 determines whether the restart has been completed. The determination method is the same as step S143 in FIG. 4 in the first embodiment.
When the restart is finished, the process is finished.
If the restart has not ended, the process proceeds to step S440.

Step S440 corresponds to step S130 of FIG. 4 in the first embodiment.
In step S440, the state monitoring unit 143 monitors the target error rate.
Specifically, the state monitoring unit 143 counts the number of accesses to the cache 129 from the operating OS and the number of cache misses that occurred due to the access to the cache 129 from the operating OS. Then, the state monitoring unit 143 calculates the target miss rate using the number of accesses and the number of cache misses. Specifically, the target miss rate is a quotient obtained by dividing the number of cache misses by the number of accesses.

Step S451 corresponds to step S141 of FIG. 4 in the first embodiment.
In step S451, the miss rate determination unit 171 compares the target miss rate with a reference value.
If the target error rate exceeds the reference value, the process proceeds to step S452.
If the target error rate does not exceed the reference value, the process returns to step S430.

Step S452 corresponds to step S142 of FIG. 4 in the first embodiment.
In step S452, the access control unit 172 prohibits access to the cache 129 from the restarting OS.
Specifically, the access control unit 172 sets the cache controller 126 to prohibit access to the cache 129 from the OS being restarted.
After step S452, the process returns to step S430.

In step S460, the access control unit 172 permits access to the cache 129 from the restarted OS. However, if access to the cache 129 from the OS being restarted is not prohibited, it is not necessary to permit access to the cache 129 from the OS after restarting.
Specifically, the access control unit 172 acquires a setting value indicating a setting for access to the cache 129 from the OS after restart from the cache controller 126. When the acquired setting value is a value that means prohibition of access, the access control unit 172 performs setting for canceling the prohibition on the cache controller 126.
After step S460, the process ends.

*** Effects of Embodiment 4 ***
By prohibiting access to the cache 129 at restart, updating of the cache 129 by restart can be suppressed.
As a result, cache misses when the operating OS accesses the cache 129 are reduced. Therefore, it is possible to suppress a decrease in the performance of the operating OS.

*** Supplement to the embodiment ***
The information processing apparatus 100 includes “units” such as an abnormality detection unit 141, a restart unit 142, a state monitoring unit 143, and a restart control unit 144 as elements of the functional configuration. The function of “part” is realized by software. Specifically, the function of “unit” is realized as a function of the hypervisor 101.
A program that realizes the function of “unit” is loaded into the memory 121 and executed by the processor 110.
Data obtained by executing a program that implements the function of “unit” is stored in a storage device such as the memory 121 or the cache 129.
A program that realizes the function of “unit” can be stored in a computer-readable manner in a nonvolatile storage medium such as a magnetic disk, an optical disk, or a flash memory. A non-volatile storage medium is a tangible medium that is not temporary.
“Part” may be read as “processing”, “process”, or “circuit”. Hardware in which the processor 110, the memory 121, and the cache 129 are collected is referred to as a “processing circuit”.

The embodiment is an example of a preferred embodiment and is not intended to limit the technical scope of the present invention. The embodiment may be implemented partially or in combination with other embodiments. The procedure described using the flowchart and the like may be changed as appropriate.

100 information processing apparatus, 101 hypervisor, 102 real-time OS, 103 real-time application, 104 general-purpose OS, 105 general-purpose application, 110 processor, 111 core, 112 frequency change mechanism, 113 clock generator, 114 interrupt controller, 120 bus, 121 memory, 122 WDT, 123 I / O device, 124 bus controller, 125 DMA controller, 126 cache controller, 129 cache, 131 OS unit, 132 application unit, 140 hypervisor unit, 141 error detection unit, 142 restart unit, 143 status monitoring Unit, 144 restart control unit, 151 access amount determination unit, 152 frequency determination unit, 153 frequency Additional unit, 161 access amount determination unit, 162 command converter, 171 error rate judgment section 172 access controller.

Claims

An information processing apparatus comprising a multi-core processor having a plurality of processor cores and operating a plurality of operating systems with the plurality of processor cores,
A restart unit that causes a processor core included in the plurality of processor cores to restart the operating system in which an abnormality has occurred when an abnormality occurs in the operating system included in the plurality of operating systems;
A state monitoring unit that monitors the state of the information processing apparatus during execution of the restart;
An information processing comprising: a restart control unit configured to perform restriction control for restricting execution of the restart when a state of the information processing apparatus satisfies a restriction condition for restricting execution of the restart during execution of the restart apparatus.
The information processing apparatus includes a memory accessed from the plurality of processor cores,
The restriction condition is a condition that a target access amount that is the number of accesses per unit time to the memory at the restart exceeds a reference value,
The state monitoring unit monitors the target access amount as the state of the information processing apparatus,
When the target access amount exceeds the reference value, the restart control unit, as the restriction control, sets an operation frequency of a target core that is a processor core that executes the restart, and the target access amount is the reference value. The information processing apparatus according to claim 1, wherein the information processing apparatus is set to be lower than an operating frequency of the target core before exceeding.
The restart control unit, when the restart is completed after the operating frequency of the target core is lower than the normal frequency that is the operating frequency of the target core before the target access amount exceeds the reference value, The information processing apparatus according to claim 2, wherein the operating frequency of the target core is returned to the normal frequency.
The information processing apparatus according to claim 2, wherein the restart control unit pauses the restart when the target access amount exceeds a second reference value that is larger than a first reference value that is the reference value.
The information processing apparatus includes a memory accessed from the plurality of processor cores,
The restriction condition is a condition that a target access amount that is an access amount of direct memory access that occurs to the memory by the restart exceeds a reference value,
The state monitoring unit monitors the target access amount as the state of the information processing apparatus,
When the target access amount exceeds the reference value, the restart control unit converts, as the restriction control, a direct memory access instruction generated for the memory by the restart into a program control instruction. The information processing apparatus according to claim 1.
The restart control unit, when the target access amount exceeds the reference value, a part of direct memory access instructions among the direct memory access generated for the memory by the restart The information processing apparatus according to claim 5, wherein the information processing apparatus converts the instruction into an instruction.
When the target access amount exceeds a second reference value that is larger than the first reference value, which is the reference value, all the direct memory accesses that occur to the memory by the restart are performed. The information processing apparatus according to claim 6, wherein the instruction is converted into a program control instruction.
The information processing apparatus includes a cache accessed from the plurality of processor cores,
The restriction condition is a condition that a target miss rate that is a miss rate of a cache miss that occurs when accessing the cache from an operating system that is not the target of restart exceeds a reference value,
The state monitoring unit monitors the target error rate as the state of the information processing apparatus,
The information processing apparatus according to claim 1, wherein when the target miss rate exceeds the reference value, the restart control unit prohibits access to the cache from the operating system being restarted as the restriction control. .
The restart control unit permits access to the cache from the operating system after restarting when the restarting is terminated after prohibiting access to the cache from the operating system being restarted. The information processing apparatus according to 8.
A restart control method by an information processing apparatus including a multi-core processor having a plurality of processor cores and operating a plurality of operating systems by the plurality of processor cores,
When an abnormality occurs in the operating system included in the plurality of operating systems, the restart unit causes the processor core included in the plurality of processor cores to restart the operating system in which the abnormality has occurred,
A state monitoring unit monitors the state of the information processing apparatus during execution of the restart;
Reboot control for performing a restriction control for restricting the execution of the restart when the restart control unit satisfies a restriction condition for restricting the execution of the restart during the execution of the restart Method.