WO2017166737A1

WO2017166737A1 - Film thickness measuring device

Info

Publication number: WO2017166737A1
Application number: PCT/CN2016/099939
Authority: WO
Inventors: 林永辉; 戴朋飞; 韩晓伟
Original assignee: 威海华菱光电股份有限公司
Priority date: 2016-04-01
Filing date: 2016-09-23
Publication date: 2017-10-05
Also published as: CN105674871A

Abstract

A film thickness measuring device comprises at least one common electrode (100) and at least one measurement chip. Each measurement chip comprises: a measurement electrode array (1), which comprises a plurality of measurement electrodes (11) and is arranged opposite to and at intervals with the common electrode (100) in a first direction; a reset unit, electrically connected to the measurement electrodes (11) in the measurement electrode array (1) and used for resetting electrical signals of the measurement electrodes; an initial amplification unit (30), electrically connected to the detection electrodes (11) and used for amplifying the electrical signals; a displacement control unit (4), electrically connected to the initial amplification unit (30) and used for controlling an output sequence of the electrical signals; a scanning bit bus (01), comprising a plurality of scanning connection points, wherein one scanning connection point is electrically connected to the displacement control unit (4); and a logic control unit, used for receiving an external input signal, generating a control signal for controlling the measurement chip, and outputting a detection signal. The measuring device has high measurement precision.

Description

Film thickness detecting device

Technical field

The present application relates to the field of film thickness detection, and in particular to a film thickness detecting device.

Background technique

In the financial field, the money detector, the ATM machine and the sorting machine identify and screen the authenticity of the banknotes in various ways, many of which identify the authenticity of the banknotes by detecting the thickness of the banknotes. Most of the detection of the thickness of the banknote adopts the detection method of the pressure roller, that is, when the banknote passes through the pressure roller, the gap of the pressure roller is measured, and then the thickness of the banknote is determined by the gap. This detection method has many shortcomings, including a large detection structure, low resolution, easy to cause banknotes when fed into a banknote at a high speed, and low detection accuracy. For example, when a small foreign object is attached to a banknote, it is not easy to detect. come out.

Summary of the invention

The main object of the present application is to provide a film thickness detecting device that solves the problems of the prior art detecting device being bulky and having low detection accuracy.

In order to achieve the above object, according to an aspect of the present application, a film thickness detecting device is provided, the detecting device comprising at least one common electrode and at least one detecting chip, wherein each of the detecting chips comprises: a detecting electrode array, and the above The common electrodes are opposite and spaced apart in the first direction, and the interval between the common electrode and the detecting electrode array constitutes a transmission channel of the film to be tested, the detecting electrode array includes a plurality of detecting electrodes, a reset unit, and the detecting electrode array Each of the detecting electrodes is electrically connected to reset an electrical signal of each of the detecting electrodes; an initial amplifying unit is electrically connected to each of the detecting electrodes in the detecting electrode array, and the initial amplifying unit is configured to amplify each of the detecting signals An electrical signal of the electrode; a shift control unit electrically connected to the initial amplifying unit, wherein the shift control unit is configured to control an output sequence of the plurality of the amplified electrical signals; the scan bit bus includes a plurality of scan connection points, and The scan connection point is electrically connected to the shift control unit; Editing control means for receiving external input signals, generates a control signal and the output detection signal of the detection chip.

Further, the detecting chip further includes: a gain amplifying unit, comprising: a first input end and a second input end, wherein the first input end is electrically connected to one of the scanning connection points.

Further, the initial amplifying unit is an initial amplifier array, and the initial amplifier array includes a plurality of initial amplifiers. The initial amplifiers are in one-to-one correspondence with the detecting electrodes, and the input ends of the initial amplifiers are electrically connected to corresponding detecting electrodes.

Further, the reset unit is a reset switch array, and the reset switch array includes a plurality of reset switches, wherein the reset switch is in one-to-one correspondence with the detecting electrodes, and each of the reset switches includes a reset switch first end, a reset switch second end, and a reset The third end of the switch, the first end of each of the reset switches is connected to a fixed voltage, and the second end of each reset switch is connected to the reset The signal, the third end of each of the reset switches is electrically connected to the corresponding detecting electrode, and the reset signal controls the reset switch to be turned on, and resets the electrical signal of the corresponding detecting electrode.

Further, the shift control unit includes: a shift switch array including a plurality of shift switches, wherein the shift switch has a one-to-one correspondence with the initial amplifier, and each of the shift switches includes a shift switch first end and a shift switch The second end and the third end of the shift switch, the first end of each of the shift switches is electrically connected to the output end of the corresponding initial amplifier; the shift control circuit is electrically connected to the second end of each of the shift switches, and the shift control is The circuit is used to control the turning on and off of each of the above shift switches.

Further, the detecting chip further includes: a scan storage switch array, comprising a plurality of scan storage switches, wherein the scan storage switch has a one-to-one correspondence with the initial amplifier, and each of the scan storage switches comprises a first end of the scan storage switch and a scan storage switch. The first end of each of the scan storage switches is electrically connected to the output end of the corresponding initial amplifier, and the second end of each of the scan storage switches is connected to the scan switch signal; the storage capacitor array is scanned, including The scan storage capacitor includes a first end of the scan capacitor and a second end of the scan capacitor, wherein the scan storage capacitor is in one-to-one correspondence with the scan storage switch, and the first end of each scan capacitor is electrically connected to the corresponding scan storage switch The third end of each of the scan capacitors is grounded between the third end and the first end of the corresponding shift switch, and each of the scan storage capacitors is used to store an output electrical signal of the corresponding initial amplifier when scanning the corresponding detection electrode.

Further, the detecting chip further includes: a scan bit bus clamp switch, comprising: a first end of the scan clamp switch, a second end of the scan clamp switch and a third end of the scan clamp switch, wherein the first end of the scan clamp switch is electrically Connected between the scan bit bus and the first input end, the second end of the scan clamp switch is connected to the clamp switch signal, and the third end of the scan clamp switch is connected to the fixed voltage Vc, and each scan is read. Before storing the electrical signal of the capacitor, the clamp switch signal controls the scan bit bus clamp switch to be turned on, and clamps the voltage of the scan bit bus to the voltage Vc.

Further, the gain amplifying unit comprises: a gain amplifier comprising two input ends and one output end, wherein the two input ends respectively correspond to the first input end and the second input end, the first input end and the scan bit bus An electrical connection; a reference voltage sampling circuit electrically connected to the second input end, wherein the reference voltage sampling circuit is configured to adjust an output electrical signal of the gain amplifier; an output buffer circuit, an input end of the output buffer circuit and the gain amplifier The output is electrically connected to increase the driving capability of the output signal of the above gain amplifier.

Further, the shift switch array includes a plurality of pairs of shift switches, and the plurality of pairs of shift switches are in one-to-one correspondence with the plurality of initial amplifiers, and each pair of shift switches includes two shift switches, respectively, a first shift switch And the second shift switch, each of the first shift switches includes a first shift switch first end, a first shift switch second end and a first shift switch third end; each of the second shift switches comprises a first end of the second shift switch, a second end of the second shift switch, and a third end of the second shift switch, wherein the first end of each of the first shift switches is electrically connected to the first end of the corresponding scan capacitor, The third end of each of the first shift switches is electrically connected to the scan bit bus, and the second end of each of the first shift switches is electrically connected to the shift control circuit, and the detecting chip further comprises: a reset storage switch array, including a plurality of reset storage switches, wherein the reset storage switch has a one-to-one correspondence with the initial amplifier, and each of the reset storage switches includes a first end of the reset storage switch, a second end of the reset storage switch, and a third end of the reset storage switch. The first end of the reset storage switch is electrically connected to the output end of the corresponding initial amplifier, and the second end of each of the reset storage switches is connected to the reset switch signal; the reset storage capacitor array includes a plurality of reset storage capacitors, and the reset storage capacitor and the reset The storage switch has a one-to-one correspondence, and each of the reset storage capacitors includes a first end of the reset capacitor and a second end of the reset capacitor, and the first end of each of the reset capacitors is electrically connected to the third end of the corresponding reset storage switch and the corresponding end Between the first ends of the two shift switches, the second ends of the reset capacitors are grounded, and each of the reset storage capacitors is used to store an output electrical signal of the corresponding initial amplifier when the corresponding detection electrode is reset; the reset bit bus includes multiple Resetting the connection point, one of the reset connection points is electrically connected to the third end of each of the second shift switches and the second input end, or one of the reset connection points is electrically connected to the third end of each of the second shift switches, and A reset connection point is electrically connected to the second input terminal.

Further, the detecting chip further includes: a reset bit bus clamp switch, comprising: a first end of the reset clamp switch, a second end of the reset clamp switch and a third end of the reset clamp switch, wherein the first end of the reset clamp switch is electrically Connected between the reset bit bus and the second input end, the second end of the reset clamp switch is connected to the clamp switch signal, and the third end of the reset clamp switch is connected to a fixed voltage Vc, and each of the above is read Before resetting the electrical signal of the storage capacitor, the clamp switch signal controls the reset bit bus clamp switch to be turned on, and clamps the voltage of the reset bit bus to the voltage Vc.

Further, the gain amplifying unit comprises: a gain amplifier comprising two input ends and one output end, wherein the two input ends respectively correspond to the first input end and the second input end, the first input end and the scan bit bus Electrically connecting, the second input end is electrically connected to the reset bit bus; a reference voltage sampling circuit is configured to adjust an output electrical signal of the gain amplifier; an output buffer circuit, an input end of the output buffer circuit and the gain amplifier The output is electrically connected to increase the driving capability of the output signal of the above gain amplifier.

Further, the reference electric signal of the reference voltage sampling circuit is a reference voltage, and the Vc is the same as the reference voltage.

Further, the logic control unit includes an input pin and an output pin, wherein the output pin is a scan end signal pin, and is used to output a pulse signal when the scan ends, and the input pin includes: a clock signal pin. , for providing a stable frequency signal for the logic control unit; a scan enable signal pin for inputting a scan enable signal; and a first chip select pin for controlling start of the detection signal output of the above detection chip by the same The above-mentioned shift control unit control in one of the above detection chips is also controlled by the above-mentioned output pin of another detection chip connected to the above-mentioned detection chip; a resolution selection pin for controlling the thickness detection resolution of the above detection chip.

Further, the detecting chip is formed of a structural film layer, the structural film layer includes: a substrate; and an insulating film disposed on a surface of the substrate, wherein the insulating film includes a first insulating layer disposed in contact with the substrate, the first An insulating layer is an oxidized insulating layer, and the detecting electrode array is disposed on a surface of the insulating film remote from the substrate.

Further, the detecting electrode is a narrow strip electrode, the maximum width of the narrow strip electrode in the second direction is smaller than the maximum width in the third direction, and the second direction and the third direction are both perpendicular to the first direction And the third direction is the moving direction of the film to be tested.

Further, at least one of the detecting electrodes includes a plurality of top electrode and bottom electrode regions, wherein the bottom electrode region is disposed in the insulating film, the bottom electrode region is not disposed in contact with the substrate, and a surface of the insulating film away from the substrate is opened. There are a plurality of via holes, and the top electrodes are in one-to-one correspondence with the via holes, and each of the top electrodes and the bottom electrode region are electrically connected through corresponding via holes.

Further, the insulating film includes: a second insulating layer disposed on a surface of the first insulating layer away from the substrate; and a third insulating layer disposed on a surface of the second insulating layer away from the first insulating layer on.

Further, the bottom electrode region is disposed in the third insulating layer, and the plurality of via holes are formed on a surface of the third insulating layer remote from the second insulating layer.

Further, the structural film layer further includes a protective layer covering the exposed surface of each of the detecting electrodes and the exposed surface of the insulating film.

Applying the technical solution of the present application, the detecting device integrates the detecting electrode array, the reset unit, the initial amplifying unit, the shift control unit, the scan bit bus and the logic control unit on one detecting chip, so that the film thickness detecting device is small in volume. The problem of inconvenience in detection caused by the bulky detection device in the prior art is avoided, and the detection chip includes a reset unit, and the reset switch array detects each before the banknote detection, that is, before detecting the electrical signals of the detection electrodes. The electrical signal of the electrode is reset to avoid the detection of the electrical signal on the detection electrode before the detection, thereby avoiding the inaccuracy of the detection result and improving the detection accuracy of the detection device.

DRAWINGS

The accompanying drawings, which are incorporated in the claims of the claims In the drawing:

1 is a block diagram showing a partial structure of a detecting apparatus provided by an embodiment of the present application;

FIG. 2 is a schematic diagram showing a partial circuit structure of a detecting apparatus provided in Embodiment 1 of the present application;

FIG. 3 is a schematic diagram showing a partial circuit structure of a detecting apparatus provided in Embodiment 2 of the present application;

4 is a partial circuit structural diagram of a detecting apparatus provided in Embodiment 3 of the present application;

FIG. 5 is a partial cross-sectional structural diagram of a detecting chip according to an embodiment of the present application;

FIG. 6 is a partial cross-sectional structural diagram of a detecting chip according to another embodiment of the present application;

FIG. 7 is a partial plan view showing a detecting chip according to another embodiment of the present application;

FIG. 8 is a partial cross-sectional structural view showing the detecting chip shown in FIG. 7; FIG.

FIG. 9 is a partial plan view showing a detecting chip according to still another embodiment of the present application;

FIG. 10 is a partial cross-sectional structural view showing the detecting chip shown in FIG. 9; FIG.

FIG. 11 is a partial plan view showing a detecting chip according to still another embodiment of the present application;

Fig. 12 is a partial cross-sectional structural view showing the detecting chip shown in Fig. 11.

Wherein, the above figures include the following reference numerals:

01, scan bit bus; 011, scan bit bus clamp switch; 02, reset bit bus; 021, reset bit bus clamp switch; 1, detection electrode array; 2, first combination unit; 3, second combination unit; 4. Shift control unit; 11, detecting electrode; 12, insulating film; 20, reset switch; 30, initial amplifier; 40, shift switch; 41, shift control circuit; 42, first shift switch; a second shift switch; 50, scan memory switch; 60, scan storage capacitor; 70, reset memory switch; 80, reset storage capacitor; 91, gain amplifier; 92, reference voltage sampling circuit; 93, output buffer circuit; a common electrode; 101, a substrate; 102, a first insulating layer; 103, a second insulating layer; 104, a third insulating layer; 105, a bottom electrode region; 106, a via hole; 107, a top electrode; 108, a protective layer.

detailed description

It should be noted that the following detailed description is illustrative and is intended to provide a further description of the application. All technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise indicated.

It is to be noted that the terminology used herein is for the purpose of describing particular embodiments, and is not intended to limit the exemplary embodiments. As used herein, the singular " " " " " " There are features, steps, operations, devices, components, and/or combinations thereof.

As described in the background art, the film thickness detecting device of the prior art is bulky and has low detection accuracy. To solve the above technical problems, the present application proposes a film thickness detecting device.

In an exemplary embodiment of the present application, a film thickness detecting device is provided, the detecting device comprising at least one common electrode 100 and at least one detecting chip, the detecting chip comprising a detecting electrode array 1, a reset unit, and an initial amplification Unit, shift control unit 4, scan bit bus 01 and logic control unit, FIG. 1 is a block diagram of a partial detection chip, in which only detection electrode array 1, first combination unit 2, second combination unit 3 and The shift control unit 4, wherein the first combining unit 2 comprises a reset unit and an initial amplifying unit, and the second combining unit 3 comprises a logic control unit.

The common electrode 100 in the detecting device is used to provide a constant electric field during scanning, the number may be one or more, and the detecting chip may also be one or more. When the common electrode 100 is one, the detecting chip may be one. It may be a plurality of cascades; when the common electrode 100 is plural, the detection chip may be a plurality of cascades or may be one. Whether one or more, all of the common electrodes 100 need to cover all of the detecting electrode arrays 1. A person skilled in the art can determine the number of the detecting chip and the common electrode 100 according to actual conditions.

The detecting electrode array 1 and the common electrode 100 are opposite to each other in a first direction, and the interval between the common electrode 100 and the detecting electrode array 1 constitutes a transmission channel of a film to be tested, and the detecting electrode array 1 includes a plurality of The detecting electrodes 11 are sequentially arranged; the resetting unit is electrically connected to each of the detecting electrodes 11 in the detecting electrode array 1 for resetting the electrical signals of the detecting electrodes 11; the initial amplifying unit and the detecting electrode array Each of the detecting electrodes is electrically connected, the initial amplifying unit is configured to amplify an electrical signal of each of the detecting electrodes, the shift control unit 4 is electrically connected to the initial amplifying unit, and the shift control unit 4 is configured to control the amplified plurality of the above Output sequence of electrical signals; The scan bit bus 01 includes a plurality of scan connection points, and one of the scan connection points is electrically connected to the shift control unit. The logic control unit is configured to receive an input signal from the outside, generate a control signal for controlling the detection chip, and output a detection signal.

The control signal of the common electrode 100 is an electrode pulse signal. When the scan enable signal arrives (ie, a high level pulse signal), the detection chip starts to work, the electrode pulse signal is at a low level, and the reset unit initializes the corresponding connected detection electrode 11 The voltage (ie, reset), after the reset continues for several clock signals, the electrode pulse signal is at a high level, and the detecting electrode array 1 starts to detect the external electric field change in real time. When the banknote passes through the surface of the chip, the difference in the thickness of the banknote affects the opposite direction. The electric field between the pulse electrode and the chip detecting electrode array 1 causes a change in the electrical signal on the detecting electrode 11 of the detecting electrode array 1. The electric signals on the detecting electrodes 11 are amplified in real time after being amplified by the corresponding primary amplifying unit, and the shift control unit 4 sequentially supplies the output values of the respective primary amplifiers to the scanning bit bus 01, and outputs a row representing the thickness of the banknotes by the scanning bit bus 01. electric signal. The detecting chip scans the electric signals on the detecting electrode array 1 at a high speed under the control of the logic control unit, and continuously scans a plurality of lines to complete the detection of the thickness of the whole banknote.

The detecting device described above integrates the detecting electrode array 1, the reset unit, the initial amplifying unit, the shift control unit 4, the scan bit bus 01 and the logic control unit on one detecting chip, so that the film thickness detecting device is small in size and avoids The detection device in the prior art has a problem of inconvenience in detection caused by a bulky volume, and the detection chip includes a reset unit, and before the banknote detection, that is, before detecting the electrical signal of each detection electrode 11, the reset switch array sets each detection electrode The electrical signal of 11 is reset to avoid the detection of the electrical signal on the detecting electrode 11 before the detection, thereby avoiding the inaccuracy of the detection result and improving the detection accuracy of the detecting device.

In order to further amplify the electrical signal output by the scan bit bus, and improve the anti-interference capability of the electrical signal, the preferred detection chip further includes a gain amplifying unit, the gain amplifying unit includes a first input end and a second input end, the first input The terminal is electrically connected to one of the scan connection points of the scan bit bus 01, and the second combination unit 3 in FIG. 1 further includes a gain amplifying unit.

In an embodiment of the present application, the initial amplifying unit is an initial amplifier array, and the initial amplifier array includes a plurality of initial amplifiers 30. The initial amplifier 30 is in one-to-one correspondence with the detecting electrodes 11, and the input ends of the initial amplifiers 30 are respectively It is electrically connected to the corresponding detecting electrode 11. The electrical signals on the respective detecting electrodes 11 are amplified by the corresponding primary amplifiers and output in real time.

Fig. 2 shows a partial structural view of the detecting device, in which a rectangular dotted line indicates a circuit unit connected to one detecting electrode 11, and in the actual detecting chip, a plurality of identical circuit units are included. An initial amplifier 30 electrically connected to the detecting electrode 11 is shown in the circuit unit.

In another embodiment of the present application, the reset unit is a reset switch array, the reset switch array includes a plurality of reset switches 20, the reset switch 20 is in one-to-one correspondence with the detecting electrodes 11, and each of the reset switches 20 includes a reset switch. The first end, the second end of the reset switch and the third end of the reset switch, the first end of each of the reset switches is connected to a fixed voltage (ie corresponding to Vreset in FIG. 2), and the second end of each of the reset switches is connected to the reset signal (also The third end of each of the reset switches is electrically connected to the detection electrode 11 corresponding to the above, and the reset signal controls the reset switch 20 to be turned on to reset the electrical signal of the corresponding detection electrode 11.

The control signal of the common electrode 100 is an electrode pulse signal. When the scan start signal arrives, that is, a high-level pulse signal, the detection chip starts to work, the electrode pulse signal is low level, and the reset signal is high level, each reset switch 20 is turned on, the electrical signal (ie, reset) on the corresponding detecting electrode 11 is initialized, and after resetting for several clock signals, the electrode pulse signal is at a high level, and when the reset signal is at a low level, each reset switch 20 is turned off. The detecting electrode array 1 starts to detect the change of the external electric field in real time. When the banknote passes through the surface of the chip, the difference in the thickness of the banknote affects the electric field between the opposite pulse electrode and the chip detecting electrode array 1, thereby causing the detecting electrode 11 of the detecting electrode array 1. The power-on signal changes. The shift control unit 4 sequentially supplies the output values of the respective primary amplifiers to the scan bit bus line 01, and then amplifies them by the gain amplifying unit, and outputs a line of electric signals representing the thickness of the banknotes. The detecting chip scans the electric signals on the detecting electrode array 1 at a high speed under the control of the logic control unit, and continuously scans a plurality of lines to complete the detection of the thickness of the whole banknote.

In still another embodiment of the present application, the shift control unit 4 includes: a shift switch array and a shift control circuit, wherein the shift switch array includes a plurality of shift switches 40, as shown in FIG. The position switch 40 has a one-to-one correspondence with the initial amplifier 30. Each of the shift switches 40 includes a first end of the shift switch, a second end of the shift switch and a third end of the shift switch, and the first end of each of the shift switches corresponds to The output of the initial amplifier 30 is electrically connected; the shift control circuit 41 is electrically connected to the second end of the shift switch of each of the shift switches 40, and the shift control circuit 41 is configured to control the connection of each of the shift switches 40. Turning on and off, the third end of the shift switch is electrically connected to the scan bit bus 01.

When the detecting electrode array 1 starts to detect the change of the external electric field in real time, the banknote passes through the surface of the chip, and the difference in the thickness of the banknote affects the electric field between the opposite pulse electrode and the chip detecting electrode array 1, thereby causing the detecting electrode 11 of the detecting electrode array 1. The power-on signal changes. The shift control circuit 41 controls the shift switches 40 to be sequentially turned on, sequentially supplies the output values of the respective primary amplifiers to the scan bit bus line 01, and performs amplification and subsequent operations through the gain amplifying unit.

The above-mentioned "reset switch 20 in one-to-one correspondence with the detecting electrodes 11" means that the number of reset switches 20 in the reset switch array is the same as the number of detecting electrodes 11, and the reset switch 20 and the detecting electrode 11 are one. A corresponding connection. All the similar expressions of the present application indicate that the number of the two is the same and one-to-one correspondence.

Moreover, the above-mentioned shift switch 40 and reset switch 20 are both MOSFETs, and other switches mentioned in the present application are MOSFETs unless otherwise specified. However, all of the above switches are not limited to MOSFETs, and those skilled in the art can select suitable switches according to actual conditions.

In an embodiment of the present application, the detecting chip further includes a scan storage switch array and a scan storage capacitor array, wherein the scan storage switch array includes a plurality of scan storage switches 50, and the scan storage switch 50 and the initial amplifier 30 are one by one. Correspondingly, each of the scan storage switches 50 includes a first end of the scan storage switch, a second end of the scan storage switch and a third end of the scan storage switch, and the first end of each of the scan storage switches is electrically connected to the output end of the corresponding initial amplifier 30. The scanning storage capacitor array includes a plurality of scanning storage capacitors 60, and each of the scanning storage capacitors 60 includes a first end of the scanning capacitor and a second end of the scanning capacitor. The scan storage capacitor 60 is in one-to-one correspondence with the scan storage switch 50. The first end of each scan capacitor is electrically connected to the third end of the corresponding scan storage switch and the first end of the shift switch of the corresponding shift switch 40. The second end of each of the scanning capacitors is grounded, and each of the scan storage capacitors 60 is used to store a corresponding initial amplification. 30 11 outputs an electric signal corresponding to the detection of the scanning electrode. Fig. 3 shows a partial structural view of the detecting device, in which a rectangular dotted line frame indicates a circuit unit connected to a detecting electrode 11, and in the actual detecting device, a plurality of identical circuit units are included.

After the voltage on the detecting electrode 11 is reset, the electrode pulse signal is at a high level, the reset signal is at a low level, and when the scan switch signal is at a high level, the reset switches 20 are turned off, and the detecting electrode array 1 starts to detect an external electric field change in real time. When the banknote passes through the surface of the chip, the difference in the thickness of the banknote affects the electric field between the opposite pulse electrode and the chip detecting electrode array 1, thereby causing a change in the electrical signal on the detecting electrode 11 of the detecting electrode array 1. The electrical signal on each detecting electrode 11 is amplified by the corresponding primary amplifier and outputted in real time. After the output voltage is stored in the corresponding scanning storage capacitor 60, the scanning switch signal is at a low level, that is, the scanning storage switch array is disconnected and moved. The bit control circuit 41 controls the shift switches 40 to be sequentially turned on, and sequentially stores the stored values in the respective scan storage capacitors 60 to the scan bit bus line 01, and then amplifies them by the gain amplifying unit. The scanning storage capacitor array and the scanning storage switch array are arranged in the detecting chip, and the electrical signals detected on the detecting electrodes 11 can be simultaneously stored and then read out in order, thereby avoiding the deviation caused by the scanning mode while scanning, and further improving the deviation. The detection accuracy of the detection device.

In order to clamp the potential of the scan bit bus 01 to a fixed value before reading the storage voltage of the scan storage capacitor 60, the influence of the parasitic capacitance of the scan bit bus 01 on the detection accuracy is avoided, thereby further improving the detection accuracy of the detection device. The preferred detection chip of the present application further includes a scan bit bus clamp switch 011, which includes a first end of the scan clamp switch, a second end of the scan clamp switch and a third end of the scan clamp switch, and each of the scan clamp switches is first The third end of each of the scan clamp switches is connected to the fixed voltage Vc, and the second end of each of the scan clamp switches is connected to the clamp. The first end of the scan clamp bus is connected to the first input end of the gain amplifying unit. a bit switch signal (also referred to as a Sc signal), the clamp switch signal controls the scan bit bus clamp switch 011 to be turned on, and the voltage of the scan bit bus 01 is clamped before reading the electrical signal of each of the scan storage capacitors 60 Bit to voltage Vc. Further, the clamp switch signal is opposite to the signal of the shift control circuit 41, that is, when the clamp switch signal controls the scan bit bus clamp switch 011 to be turned on, the shift control circuit 41 controls the shift switches 40 to be turned off.

In still another embodiment of the present application, as shown in FIGS. 2 and 3, the gain amplifying unit includes a gain amplifier 91, a reference voltage sampling circuit 92, and an output buffer circuit 93. The gain amplifier 91 includes two input ends and one output end. The two input ends respectively correspond to the first input end and the second input end, and the first input end is electrically connected to the scan bit bus line 01; the reference voltage sampling The circuit 92 is electrically connected to the second input end, and the reference voltage sampling circuit 92 is configured to adjust an output electrical signal of the gain amplifier 91. The input end of the output buffer circuit 93 is electrically connected to the output end of the gain amplifier 91. In order to increase the driving capability of the output signal of the gain amplifier 91, the output terminal outputs a detection signal (ie, a SIG signal) of the detection chip. The gain amplifying unit can amplify the output value on the scan bit bus 01, and adjust the reference of the output value to make the range of the output signal of the gain amplifier 91 more adjustable, which facilitates subsequent reading by a plurality of read modules. For example, when testing an object, the reference voltage applied to the gain amplifier 91 is 1V, the output range of the gain amplifier 91 is 1 to 1.5V, and the same object is tested. When the reference voltage applied to the gain amplifier 91 is 2V, the amplifier output range is 2 to 2.5V.

In still another embodiment of the present application, the shift switch array includes a plurality of pairs of shift switches, and the plurality of pairs of shift switches are in one-to-one correspondence with the plurality of initial amplifiers 30, and each pair of shift switches includes two shift switches. The first shift switch 42 and the second shift switch 43, respectively, each of the first shift switches 42 includes a first shift switch first end, a first shift switch second end, and a first shift switch Each of the second shift switches 43 includes a second shift switch first end, a second shift switch second end, and a second shift switch third end, wherein each of the first shift switches is first The first end of the first shift switch is electrically connected to the scan bit bus 01, and the second end of each of the first shift switches is electrically connected to the first end of the first scan switch. It is electrically connected to the shift control circuit 41 described above. Fig. 4 shows a partial structural view of the detecting device, in which a rectangular dotted line indicates a circuit unit connected to a detecting electrode 11, and in the actual detecting device, a plurality of identical circuit units are included.

The above detection chip further includes a reset memory switch array, a reset storage capacitor array and a reset bit bus 02. The reset storage switch array includes a plurality of reset storage switches 70. The reset storage switch 70 has a one-to-one correspondence with the initial amplifiers 30. Each of the reset storage switches 70 includes a reset storage switch first end, a reset storage switch second end, and a reset. The first end of the storage switch is electrically connected to the output end of the initial amplifier 30, and the second end of each of the reset storage switches is connected to a reset switch signal (also referred to as an Sd signal); the reset storage capacitor array includes The reset storage capacitor 80 has a one-to-one correspondence with the reset storage switch 70. Each of the reset storage capacitors 80 includes a first end of the reset capacitor and a second end of the reset capacitor, and the first end of the reset capacitor is electrically connected to Between the third end of the corresponding reset storage switch and the first end of the corresponding second shift switch, the second end of the reset capacitor is grounded, and each of the reset storage capacitors 80 is configured to store a corresponding initial amplifier 30 at the corresponding detection electrode of the reset 11 o'clock output electrical signal; reset bit bus 02 includes a plurality of reset connection points, one of the above reset connection points And the second input end of each of the second shift switches and the second input end of the gain amplifying unit, or one of the reset connection points is electrically connected to the third end of each of the second shift switches, and the other reset connection point And electrically connected to the second input end of the gain amplifying unit.

The electrode pulse signal is at a low level, and when the reset signal is at a high level, each reset switch 20 is turned on for several clock cycles to reset the electrical signal on the detecting electrode 11, and when the reset switch signal is at a high level, the reset storage switch 70 is connected. After several clock cycles, the output signal of each initial amplifier 30 is stored in the corresponding reset storage capacitor 80. The reset signal is low level, the electrode pulse signal is high level, and the scan switch signal is high level. The reset switch 20 is turned off, and the detecting electrode array 1 starts detecting the change of the external electric field. After several clock cycles, the scan switch signal is at a high level, and the scan voltage output from the initial amplifier 30 is stored in the scan storage capacitor 60; the shift control circuit 41 sequentially controls A pair of shift switches are turned on, electrically connecting the voltage in the scan storage capacitor 60 to the first input end of the gain amplifying unit, and electrically connecting the electrical signal in the reset storage capacitor 80 to the second input end of the gain amplifying unit. Therefore, the voltages of the respective scan storage capacitors 60 are subtracted from the corresponding electrical signals of the respective reset storage capacitors 80, and then amplified, thereby eliminating the unit circuits. Between discrete, to further improve the detection accuracy of the thickness.

In order to clamp the potential of the reset bit bus 02 to a fixed value before reading the storage voltage of the reset storage capacitor 80, the influence of the parasitic capacitance of the reset bit bus 02 on the detection accuracy is avoided, thereby further improving the detection accuracy of the detecting device. Preferably, the detection chip further includes a reset bit bus clamp switch 021, and the reset bit bus clamp switch 021 includes a first end of the reset clamp switch, a second end of the reset clamp switch, and a third end of the reset clamp switch. The first end of the reset clamp switch is electrically connected between the reset bit bus 02 and the second input end of the gain amplifying unit, and the third end of the reset clamp switch is connected to a fixed voltage Vc, and the reset clamp switch The two ends are connected to the clamp switch signal, and before the electrical signals of the reset storage capacitors 80 are read, the clamp switch signal controls the reset bit bus clamp switch 021 to be turned on, and the voltage of the reset bit bus 02 is clamped. Bit to voltage Vc.

In still another embodiment of the present application, as shown in FIGS. 2 to 4, the gain amplifying unit includes a gain amplifier 91, a reference voltage sampling circuit 92, and an output buffer circuit 93. The gain amplifier 91 includes two input ends and one output end. The two input ends respectively correspond to the first input end and the second input end, and the first input end is electrically connected to the scan bit bus line 01, and the second The input terminal is electrically connected to the reset bit bus 02; the reference voltage sampling circuit 92 is used for tuning The output electrical signal of the gain amplifier 91 is electrically connected to the output terminal of the gain amplifier 91 for increasing the driving capability of the output signal of the gain amplifier 91.

The reference electric signal of the reference voltage sampling circuit is a reference voltage, and the Vc may be the same as or different from the reference voltage. In order to initialize the gain amplifier 91 and balance the output voltage of the gain amplifier 91, it is preferable that the above Vc is generally the same as the reference voltage in the above-described reference voltage sampling circuit 92.

In another embodiment of the present application, the logic control unit includes an input pin and an output pin, wherein the output pin is a scan end signal pin, and is used to output a pulse signal when the scan ends. The above input pins include: a clock signal pin, a scan enable signal pin, a first chip select pin and a resolution select pin.

The clock signal pin is used to provide a stable frequency signal for the logic control unit, that is, a timing clock reference for providing operation of the detection chip, and a half clock signal period is a minimum unit of each signal action in the logic control unit.

The scan enable signal pin is used to input a scan enable signal, and a high-level pulse signal of one clock cycle is input on the scan enable signal pin to start scanning of the detection chip for one line; the first chip select pin is used to control the above Whether the activation of the detection signal output of the detection chip is controlled by the above-described shift control unit in the same detection chip or by the output pin of another detection chip connected to the detection chip, when the detection device includes only one In the above detecting chip, the detection signal is immediately output under the control of the shift control unit, and when the detecting device includes a plurality of the detecting chips, the second detecting chip and the first chip detecting pin of the subsequent detecting chip and the previous one The scan end signal pin of the detection chip is connected, and the output start of the detection signal of the second detection chip and the subsequent detection chip is controlled by the scan end signal of the previous detection chip, that is, after the detection signal output of the first detection chip is finished. , a high-level pulse appears on the scan end signal pin to the second Detecting a first chip select pin chip, the second chip starts detecting the detection signal, and so on until all the chips of the detection signal is completed. The resolution selection pin is used to control the thickness detection resolution of the above detection chip.

The electrical signals of the present application are not specifically described as referring to voltage signals. However, it is not limited to a voltage signal. In different cases, the voltage signal may be a current signal or the like. A person skilled in the art can set the above electrical signal as a specific voltage or current signal according to a specific situation.

In still another embodiment of the present application, as shown in FIG. 5 and FIG. 6, the detecting chip is formed by a structural film layer, and the structural film layer includes a substrate 101 and an insulating film 12, wherein the insulating film 12 is disposed on the substrate 101. On the surface of the insulating film 12, the first insulating layer 102 is disposed in contact with the substrate 101. The first insulating layer 102 is an oxidized insulating layer, and the detecting electrode array 1 is disposed on the insulating film 12 away from the substrate 101. on the surface.

The detecting electrode is also a layer in the structural film layer, and the detecting circuit in the integrated detecting chip is also formed by the structural film layer. The structural film layer forming the detecting circuit includes not only the substrate and the insulating film, but also other technologies in the field. The structural film that is known to the person is not explained here.

In order to further reduce the area of the detecting electrode 11, thereby reducing the parasitic capacity thereof, the voltage resetting speed on the detecting electrode 11 during scanning is increased, thereby improving the response speed of the entire detecting device. As shown in FIG. 7 and FIG. 8, the present application preferably The detecting electrode 11 is a narrow strip electrode. And the maximum width of the narrow strip electrode in the second direction is smaller than that in the third direction The maximum width, the second direction and the third direction are both perpendicular to the first direction, and the third direction is a moving direction of the film to be tested.

In another embodiment of the present application, as shown in FIG. 9 to FIG. 12, at least one of the detecting electrodes 11 includes a plurality of top electrodes 107 and a bottom electrode region 105, and the bottom electrode region 105 is disposed in the insulating film 12. The bottom electrode region 105 is not disposed in contact with the substrate 101, and a plurality of via holes 106 are formed in a surface of the insulating film 12 away from the substrate 101. The top electrode 107 is in one-to-one correspondence with the via hole 106, and each of the top electrodes 107 is provided. The bottom electrode region 105 is electrically connected to the via hole 106 corresponding thereto. The top electrode 107 of such a structure corresponds to a large top electrode 107 which is divided into a strip-like (cuboid) or square (square) array, which increases the contact area of the detecting electrode with the external electric field, and further improves the sensitivity of the detecting electrode 11.

As shown in FIG. 7, FIG. 9, or FIG. 11, the detecting electrode 11 or the bottom electrode region 105 is not a strict cuboid or a square, but has a small protrusion on one side, and the small protrusion facilitates charge concentration and is electrically connected to other structures. of. This small protrusion may also be absent, and those skilled in the art may set the shape of the detecting electrode or the bottom electrode area according to actual conditions.

In order to further ensure the susceptibility of the detecting electrode 11 in the production preparation, as shown in FIG. 6 , FIG. 8 , FIG. 10 and FIG. 12 , the present invention preferably includes the second insulating layer 103 and the third insulating layer 104 . The second insulating layer 103 is disposed on a surface of the first insulating layer 102 away from the substrate 101. The third insulating layer 104 is disposed on a surface of the second insulating layer 103 away from the first insulating layer 102.

In still another embodiment of the present application, as shown in FIG. 10 or FIG. 12 (the structures of the detecting chips of FIGS. 10 and 12 are different themselves, but the cross-sectional structural views are the same), the bottom electrode region 105 is disposed at In the third insulating layer 104, a plurality of the via holes 106 are formed on a surface of the third insulating layer 104 that is away from the second insulating layer 103.

In order to protect the detecting electrode 11 from external factors, as shown in FIG. 6, FIG. 8, FIG. 10 and FIG. 12, the detecting chip preferably further includes a protective layer 108 covering the bareness of each of the top electrodes 107. The surface is exposed to the exposed surface of the insulating film 12 described above.

The structure of each of the above-described detecting electrodes 11 can be applied to the above different detecting chips. A person skilled in the art can set the detecting electrode 11 in the detecting chip to a suitable structure according to a specific case.

The detecting chip in the detecting device is an integrated circuit chip, and the preparation thereof can be realized by an integrated circuit process, which will not be described herein.

In order to make the technical solutions of the present application more clear to those skilled in the art, the technical solutions of the present application will be described below in conjunction with specific embodiments.

Example 1

The detecting device includes a common electrode 100 and a detecting chip. The detection chip includes a detection electrode array 1, a reset switch array, an initial amplifier array, a shift switch array, a shift control circuit 41, a scan bit bus 01, Gain amplification unit and logic control unit. The rectangular dotted frame of Fig. 2 shows only the unit circuit corresponding to one detecting electrode 11, and a plurality of such unit circuits are shared in the detecting chip.

The detecting electrode array 1 is opposite to the common electrode 100 and spaced apart from each other. The interval between the common electrode 100 and each of the detecting electrode arrays 1 constitutes a transmission channel of the film to be tested, and the detecting electrode array 1 includes an equidistant row of rows. A plurality of identical detecting electrodes 11; each detecting electrode 11 shown in FIG. 2 corresponds to a reset switch 20, an initial amplifier 30, a shift switch 40, a shift control circuit 41, a gain amplifying unit, and a logic control unit. The shift control circuit 41 controls the shift switches 40 to be sequentially turned on and off. The gain amplifying unit is composed of a gain amplifier 91, a reference voltage sampling circuit 92, and an output buffer circuit 93.

The input pins of the logic control circuit have a clock signal CLK pin (also called CLK pin), a scan enable signal FS pin (also called FS pin), and a first chip select SI pin (also called SI pin) and The resolution selects the MODE pin (also known as the MODE pin). The SI pin is used to control the activation of the detection signal output of the detection chip. When the detection device includes only one of the detection chips, the SI pin is connected to a high level, and the detection signal is under the control of the shift control circuit 41. Immediately outputting, when the detecting device includes a plurality of the detecting chips, the SI pin is connected to the SO pin of the detecting chip, and the output of the detecting signal of the second detecting chip and the subsequent detecting chip is started by the previous detecting chip. Scanning end signal control, that is, after the detection signal output of the first detecting chip is finished, a high level pulse appears on the scan end signal pin to the first chip select pin of the second detecting chip, and the second detecting chip starts. The detection signal is output, and so on, until the detection signal output of all the chips is completed. The MODE pin is a resolution selection pin. The high-low level or pulse input of this pin can select the operation mode of the detection electrode array 1. At the highest resolution, all the detection electrodes 11 work independently, and the adjacent detection electrodes 11 are pressed at the low resolution. Regularly combined work, the thickness resolution of the test chip can reach 200 DPI. The CLK signal is a clock input pin that is externally supplied with a clock signal to the detection chip. A pulse signal at the output SO pin of the logic control circuit indicates that one line of the scan output process is complete.

The sampling reference of the reference voltage sampling circuit 92 is provided by the VREF pin, which is also the second input of the gain amplifier 91. As a reference for comparison amplification, the gain amplifying unit is finally outputted from the output signal SIG pin via the output buffer circuit 93.

The scanning operation timing of the detecting device is as follows: the scanning start signal FS pin inputs a high-level pulse (scanning start signal) of one clock cycle, and can start the detecting chip operation, the electrode pulse signal is low level, and the reset signal (Sr When the signal is high, the reset switch array is turned on for several clock cycles, and the voltage on the detection electrode array 1 is initialized and then turned off; the electrode pulse signal is at a high level, and when the Sr signal is at a low level, the detection electrode array 1 starts to be in real time. The change of the external electric field is detected. When the banknote passes through the surface of the chip at this time, the difference in the thickness of the banknote affects the electric field between the counter electrode 10 and the detecting electrodes 11 in the detecting electrode array 1, thereby causing a change in voltage on each detecting electrode 11. The voltage on each detecting electrode 11 is amplified in real time after being amplified by the corresponding primary amplifier, and the shift control circuit 41 controls the shift switch array to be sequentially turned on, and sequentially outputs the output of the primary amplifier array to the scan bit bus 01, and then passes through the gain. The amplifier 91 is differentially amplified with the reference voltage in sequence, and finally, outputted by the output buffer circuit 93. The voltage value of the bill thickness. The detecting chip scans the voltage on the detecting electrode array 1 at a high speed under the driving of the clock signal, and continuously scans a plurality of lines to complete the detection of the thickness of the whole banknote. The high-resolution detection of the thickness of the banknote can be realized by the present example, and the volume is small and the cost is low.

Example 2

The detecting device is based on the detecting device of the first embodiment. A scan memory switch array, a scan storage capacitor array, and a scan bit bus clamp switch 011 are added to the test chip. The rectangular dotted line frame of FIG. 3 only shows the unit circuit connected to one of the detecting electrodes 11, compared with FIG. The circuit only adds a scan memory switch 50, a scan storage capacitor 60 and a scan bit bus clamp switch 011. There are a plurality of such unit circuits in the test chip; scanning before reading each scan storage capacitor 60 The bit bus clamp switch 011 is turned on, and the voltage of the scan bit bus 01 is clamped to Vc, and the reference voltage leads to the equal potential of the VREF pin.

The timing of the scanning operation of one line of the detecting device is as follows: the high-level pulse of one clock cycle (ie, the scanning start signal) is input to the scanning start signal FS pin to start the detecting chip operation, and the reset signal (Sr signal) when the electrode pulse signal is low level. When the level is high, each reset switch 20 is turned on for several clock signal periods, and is initially turned off after the voltage on each detecting electrode 11 is turned off; the electrode pulse signal is at a high level, the Sr signal is at a low level, and the scan switch signal is When the level is high, each detecting electrode 11 starts to detect the external electric field change in real time, and the detection voltage on each detecting electrode 11 is amplified by the corresponding initial amplifier 30 array in real time; after several clock signal periods, the scanning switch signal (St signal) controls the scanning storage switch. The array is turned on, the voltage amplified by the array of initial amplifiers 30 is stored in the corresponding scan storage capacitor 60, and then the St signal controls the scan memory switch 50 to turn off. The shift control circuit 41 controls the shift switches 40 to be sequentially turned on, sequentially supplies the voltage on the scan storage capacitor 60 to the scan bit bus 01, and the voltage on the scan bit bus 01 is sequentially differentially amplified by the gain amplifier 91 and the reference voltage. Finally, a line of voltage signals is output through the output buffer circuit 93. In this embodiment, the scanning capacitor array is used, and the detection voltage of one line of the detecting chip is simultaneously stored and then read out in order, thereby avoiding the deviation caused by the scanning mode while scanning, and clamping the switch signal before reading the scanning capacitor voltage each time. (Sc signal) controls the scanning bit bus clamp switch 011 to be turned on, so that the scanning bit bus 01 is clamped to Vc, which reduces the influence of the bit bus parasitic capacitance and improves the scanning precision.

Example 3

Different from the detecting device of Embodiment 2, the detecting chip adds a reset memory switch array, a reset storage capacitor array, a reset bit bus 02 and a reset bit bus clamp switch 021, and the rectangular dotted line frame of FIG. 4 only shows A unit circuit connected to the detecting electrode 11 has a plurality of such unit circuits in the detecting chip; compared with FIG. 3, a second shift switch 43, a reset memory switch 70, and a reset storage capacitor are added to the figure. 80. The reset bit bus 02 and the reset bit bus clamp switch 021, and the reset bit bus 02 are connected to the second input terminal of the gain amplifier 91. The reset bit bus clamp switch 021 is used to clamp the reset bit bus 02 to Vc before reading each reset storage capacitor 80, and the clamp switch signal (Sc signal) controls the reset bit bus clamp switch 021 and the scan bit bus. The clamp switch 011 is turned on and off at the same time. The first shift switch 42 and the second shift switch 43 in this embodiment are simultaneously turned on and off by the shift control circuit 41 for simultaneously transmitting the voltage of the scan storage capacitor 60 and the voltage of the reset storage capacitor 80 to The bit bus 01 and the reset bit bus 02 are scanned.

The scan timing of one row is as follows. The scan enable signal FS pin inputs a high-level pulse of one clock cycle (ie, the scan enable signal), and the chip operation can be started, the electrode pulse signal is low level, and the Sr signal is high level. The reset switch array is turned on for several clock signal periods, the voltage corresponding to each detection electrode 11 is initialized, the Sd signal controls the reset storage switch array to be turned on, and the reset storage capacitor array stores the amplified voltage of each initial amplifier 30 at this time, and then resets the storage. The switch 70 is turned off and each reset switch 20 is turned off. The electrode pulse signal is at a high level, the Sr signal is at a low level, and the St signal is at a high level. The detecting electrode array 1 starts to detect an external electric field change in real time, and the detection voltage on each detecting electrode 11 is real-time by the initial amplifier 30. The array is amplified; after a plurality of clock signals, the scan memory switch array is turned on, and the voltage amplified by each of the initial amplifiers 30 is stored together in the corresponding scan storage capacitors 60, and the scan memory switch array is turned off.

At this time, when the storage capacitor array storage electrode pulse signal is at a high level, the scan voltage output from the array of the initial amplifier 30 is reset, and the reset voltage of the array of the initial amplifier 30 is output when the storage capacitor array storage electrode pulse signal is at a low level. The shift control circuit 41 controls the shift switch array to be sequentially turned on, and sequentially supplies the voltage on the scan storage capacitor 60 and the voltage on the reset storage capacitor 80 to the scan bit bus 01 and the reset bit bus 02 at the same time; Before the switch 40 is turned on, the logic signal can be used to control the Sc signal, thereby controlling the clamp switch to be turned on, and simultaneously clamping the scan bit bus 01 and the reset bit bus 02 voltage to Vc. The voltage on the scan bit bus 01 and the voltage on the reset bit bus 02 are sequentially differentially amplified by the gain amplifier 91, and finally, a line of voltage signals is output via the output buffer circuit 93.

In this embodiment, a reset storage capacitor array is used, and each unit circuit stores the initial amplifier 30 voltage in a reset state. When the subsequent gain is amplified, the voltage of the scan storage capacitor 60 of each unit circuit is subtracted from the voltage of the reset storage capacitor 80, and then amplified. The dispersion between the unit circuits further improves the thickness detection.

From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effects:

The detecting device of the present application integrates the detecting electrode array, the reset unit, the initial amplifying unit, the shift control unit, the scan bit bus and the logic control unit on one detecting chip, so that the film thickness detecting device is small in size, avoiding the existing The detection device in the technology has a problem of inconvenient detection caused by a bulky volume, and the detection chip includes a reset unit, and the reset switch array sets an electrical signal of each detection electrode before detecting the banknotes, that is, before detecting the electrical signals of the respective detection electrodes. Reset, to avoid detection, the electrical signal on the detection electrode will affect the detection value, thereby avoiding inaccurate detection results and improving the detection accuracy of the detection device.

The above description is only the preferred embodiment of the present application, and is not intended to limit the present application, and various changes and modifications may be made to the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application are intended to be included within the scope of the present application.

Claims

A film thickness detecting device, wherein the detecting device comprises at least one common electrode and at least one detecting chip, wherein each of the detecting chips comprises:

Detecting an electrode array, which is opposite to and spaced apart from the common electrode in a first direction, an interval between the common electrode and the detection electrode array constituting a transmission channel of a film to be tested, and the detection electrode array includes a plurality of detections electrode;

a reset unit electrically connected to each of the detecting electrodes in the detecting electrode array for resetting an electrical signal of each of the detecting electrodes;

An initial amplifying unit is electrically connected to each of the detecting electrodes in the detecting electrode array, and the initial amplifying unit is configured to amplify an electrical signal of each of the detecting electrodes;

a shift control unit electrically connected to the initial amplifying unit, wherein the shift control unit is configured to control an output sequence of the plurality of the electrical signals after the amplification;

Scanning a bit bus comprising a plurality of scan connection points, one of said scan connection points being electrically coupled to said shift control unit;

The logic control unit is configured to receive an input signal from the outside, generate a control signal for controlling the detection chip, and output a detection signal.
The detecting device according to claim 1, wherein each of the detecting chips further comprises:

The gain amplifying unit includes a first input end and a second input end, and the first input end is electrically connected to one of the scan connection points.
The detecting apparatus according to claim 2, wherein said initial amplifying unit is an initial amplifier array, said initial amplifier array comprises a plurality of initial amplifiers, said initial amplifiers are in one-to-one correspondence with said detecting electrodes, each of said The input of the initial amplifier is electrically connected to the corresponding detection electrode.
The detecting device according to claim 3, wherein the reset unit is a reset switch array, the reset switch array includes a plurality of reset switches, and the reset switch is in one-to-one correspondence with the detecting electrodes, each of the The reset switch includes a first end of the reset switch, a second end of the reset switch and a third end of the reset switch, the first end of each of the reset switches is connected to a fixed voltage, and the second end of each of the reset switches is connected to a reset signal, and each of the The third end of the reset switch is electrically connected to the corresponding detecting electrode, and the reset signal controls the reset switch to be turned on to reset the corresponding electrical signal of the detecting electrode.
The detecting device according to claim 4, wherein the shift control unit comprises:

The shift switch array includes a plurality of shift switches, the shift switch is in one-to-one correspondence with the initial amplifier, and each of the shift switches includes a first end of the shift switch, a second end of the shift switch, and a shift switch a third end, the first end of each of the shift switches being electrically connected to an output of a corresponding initial amplifier;

a shift control circuit electrically connected to the second end of each of the shift switches, wherein the shift control circuit is used to control each The shift switch is turned on and off.
The detecting device according to claim 5, wherein the detecting chip further comprises:

Scanning the memory switch array, comprising a plurality of scan memory switches, the scan memory switches are in one-to-one correspondence with the initial amplifiers, each of the scan memory switches comprising a first end of the scan memory switch, a second end of the scan memory switch, and a scan memory switch The third end, the first end of each of the scan storage switches is electrically connected to the output end of the corresponding initial amplifier, and the second end of each of the scan storage switches is connected to the scan switch signal;

Scanning the storage capacitor array, including a plurality of scan storage capacitors, the scan storage capacitor includes a first end of the scan capacitor and a second end of the scan capacitor, the scan storage capacitors are in one-to-one correspondence with the scan storage switch, each of the scan capacitors The first end is electrically connected between the third end of the corresponding scan storage switch and the first end of the corresponding shift switch, and the second end of each of the scan capacitors is grounded, and each of the scan storage capacitors is used to store a corresponding initial amplifier. The output electrical signal when scanning the corresponding detection electrode.
The detecting device according to claim 6, wherein the detecting chip further comprises:

Scanning a bit bus clamp switch, comprising: a first end of the scan clamp switch, a second end of the scan clamp switch and a third end of the scan clamp switch, the first end of the scan clamp switch being electrically connected to the scan bit bus Between the first input end, the second end of the scan clamp switch is connected to the clamp switch signal, and the third end of the scan clamp switch is connected to the fixed voltage Vc, and the read storage capacitors are read. Prior to the electrical signal, the clamp switch signal controls the scan bit bus clamp switch to turn on, clamping the voltage of the scan bit bus to voltage Vc.
The detecting device according to any one of claims 2 to 7, wherein the gain amplifying unit comprises:

The gain amplifier includes two input ends and one output end, and the two input ends respectively correspond to the first input end and the second input end, and the first input end is electrically connected to the scan bit bus;

a reference voltage sampling circuit electrically coupled to the second input, the reference voltage sampling circuit for adjusting an output electrical signal of the gain amplifier;

And an output buffer circuit, wherein an input end of the output buffer circuit is electrically connected to the output end of the gain amplifier for increasing a driving capability of an output signal of the gain amplifier.
The detecting device according to claim 7, wherein the shift switch array comprises a plurality of pairs of shift switches, and the plurality of pairs of shift switches are in one-to-one correspondence with the plurality of initial amplifiers, each pair of shift switches The second shift switch includes a first shift switch and a second shift switch, and each of the first shift switches includes a first shift switch first end, a first shift switch second end, and a first a third end of the shift switch; each of the second shift switches includes a first end of the second shift switch, a second end of the second shift switch, and a third end of the second shift switch, wherein each of the first ends The first end of the shift switch is electrically connected to the first end of the corresponding scan capacitor, and the third end of each of the first shift switches is electrically connected to the scan bit bus, and the second end of each of the first shift switches is The shift control circuit is electrically connected, and the detecting chip further includes:

Resetting the memory switch array, comprising a plurality of reset storage switches, the reset storage switches are in one-to-one correspondence with the initial amplifiers, each of the reset storage switches including a reset storage switch first end, a reset storage switch second end, and a reset a third end of the storage switch, a first end of each of the reset storage switches is electrically connected to an output end of the corresponding initial amplifier, and a second end of each of the reset storage switches is connected to the reset switch signal;

The reset storage capacitor array includes a plurality of reset storage capacitors, wherein the reset storage capacitors are in one-to-one correspondence with the reset storage switches, and each of the reset storage capacitors includes a first end of the reset capacitor and a second end of the reset capacitor, and each of the resets The first end of the capacitor is electrically connected between the third end of the corresponding reset storage switch and the first end of the corresponding second shift switch, and the second end of each of the reset capacitors is grounded, and each of the reset storage capacitors is used to store a corresponding An output electrical signal of the initial amplifier when resetting the corresponding detection electrode;

a reset bit bus comprising a plurality of reset connection points, one of the reset connection points being electrically connected to the third end of the second shift switch and the second input end, or

One of the reset connection points is electrically connected to the third end of each of the second shift switches, and the other of the reset connection points is electrically connected to the second input end.
The detecting device according to claim 9, wherein the detecting chip further comprises:

a reset bit bus clamp switch includes a first end of the reset clamp switch, a second end of the reset clamp switch and a third end of the reset clamp switch, and the first end of the reset clamp switch is electrically connected to the reset bit bus Between the second input end, the second end of the reset clamp switch is connected to the clamp switch signal, and the third end of the reset clamp switch is connected to a fixed voltage Vc, and each of the reset memories is read. Before the electrical signal of the capacitor, the clamp switch signal controls the reset bit bus clamp switch to be turned on, and the voltage of the reset bit bus is clamped to the voltage Vc.
The detecting device according to claim 10, wherein the gain amplifying unit comprises:

a gain amplifier comprising two input ends and one output end, the two input ends respectively corresponding to the first input end and the second input end, the first input end being electrically connected to the scan bit bus, The second input terminal is electrically connected to the reset bit bus;

a reference voltage sampling circuit for adjusting an output electrical signal of the gain amplifier;

And an output buffer circuit, wherein an input end of the output buffer circuit is electrically connected to the output end of the gain amplifier for increasing a driving capability of an output signal of the gain amplifier.
The detecting device according to claim 11, wherein the reference electric signal of said reference voltage sampling circuit is a reference voltage, and said Vc is the same as said reference voltage.
The detecting device according to claim 1, wherein the logic control unit comprises an input pin and an output pin, wherein the output pin is a scan end signal pin, and is used for output when scanning ends Pulse signal, the input pin includes:

a clock signal pin for providing a stable frequency signal to the logic control unit;

A scan enable signal pin for inputting a scan enable signal;

a first chip selection pin for controlling activation of the detection signal output of the detection chip by the same The shift control unit control in the detection chip is also controlled by the output pin of another of the detection chips connected to the detection chip;

A resolution selection pin for controlling the thickness detection resolution of the detection chip.
The detecting device according to claim 1, wherein the detecting chip is formed of a structural film layer, and the structural film layer comprises:

Substrate;

An insulating film disposed on a surface of the substrate, the insulating film includes a first insulating layer disposed in contact with the substrate, the first insulating layer is an oxidized insulating layer, and the detecting electrode array is disposed on the The surface of the insulating film is away from the substrate.
The detecting device according to claim 14, wherein the detecting electrode is a narrow strip electrode, and a maximum width of the narrow strip electrode in the second direction is smaller than a maximum width in a third direction, The two directions and the third direction are both perpendicular to the first direction, and the third direction is a moving direction of the film to be tested.
The detecting device according to claim 14, wherein at least one of said detecting electrodes comprises a plurality of top electrode and bottom electrode regions, said bottom electrode region being disposed in said insulating film, said bottom electrode region and said The substrate is not in contact with the substrate, and a plurality of via holes are formed in a surface of the insulating film away from the substrate, the top electrode is in one-to-one correspondence with the via holes, and each of the top electrodes corresponds to the bottom electrode region The vias are electrically connected.
The detecting device according to claim 16, wherein said insulating film comprises:

a second insulating layer disposed on a surface of the first insulating layer away from the substrate;

And a third insulating layer disposed on a surface of the second insulating layer away from the first insulating layer.
The detecting device according to claim 17, wherein the bottom electrode region is disposed in the third insulating layer, and the plurality of via holes are opened away from the second insulating layer of the third insulating layer The surface of the layer.
The detecting device according to any one of claims 14 to 18, wherein the structural film layer further comprises:

And a protective layer covering the exposed surface of each of the detecting electrodes and the exposed surface of the insulating film.