WO2017121077A1

WO2017121077A1 - Method and device for switching between two boot files

Info

Publication number: WO2017121077A1
Application number: PCT/CN2016/087679
Authority: WO
Inventors: 熊信民
Original assignee: 中兴通讯股份有限公司
Priority date: 2016-01-15
Filing date: 2016-06-29
Publication date: 2017-07-20
Also published as: CN106980513A

Abstract

Disclosed in an embodiment of the present disclosure is a method of switching between two boot files. The method comprises: performing detection to acquire a flag bit written into a register by a processor, and determining, according to the flag bit, whether a target boot file successfully starts the boot; and if it is determined that the target boot file fails to start the boot, switching a dual boot sector flag in the register from a target boot sector flag to a backup boot sector flag, and sending a reset signal to the processor. Also disclosed in an embodiment of the present disclosure is a device for switching between two boot files.

Description

Method and device for switching double boot file

Technical field

The present disclosure relates to computer technology, for example, to a method and apparatus for switching a dual boot file (BOOT).

Background technique

Currently, when a personal computer (PC) is started, it is usually booted by a BOOT stored in a flash memory to boot an operating system in the PC. If the flash memory of the storage BOOT fails, or an unexpected situation such as power failure occurs during remote upgrade of the BOOT, the BOOT fails to be booted, causing the BOOT to fail to start, and the operating system in the PC cannot be started normally. In order to solve this problem, two BOOTs are usually set in the related art, so that when a BOOT fails to boot, it is possible to switch to use another BOOT to boot the operating system in the PC. There are two main methods for performing dual BOOT switching in the related art:

One method is to store the two BOOTs in two storage devices respectively, and the central processing unit (CPU) controls the BOOT of one of the storage devices to boot the operating system in the PC. When the BOOT fails to boot, the peripheral circuit reset control CPU switches to start the BOOT in another storage device. However, the method requires two storage devices, which increases the hardware cost.

Another method is to divide two areas in Parallel NOR Flash to store the two BOOTs separately. Because Parallel NOR Flash is accessed by parallel bus interface and has multiple address lines, it can be erased and editable logic device (Erasable Programmable Logic). Device, EPLD) controls the high and low address lines for address mapping to implement switching between two BOOTs. But the hardware cost of Parallel NOR Flash is higher.

Summary of the invention

In view of this, the embodiment of the present invention provides a method and an apparatus for switching a dual boot file, which can reduce hardware costs.

In one aspect, the present disclosure provides a method for switching a dual boot file, the method comprising:

Detecting a flag bit in the processor write register, and determining, according to the flag bit, whether the target boot file BOOT is successfully started;

When it is determined that the target BOOT fails to start, the dual BOOT boot area flag in the register is switched from the target BOOT boot area flag to the standby BOOT boot area flag, and a reset signal is sent to the processor.

Optionally, before the detecting and acquiring the flag bit written in the register by the processor, the method further includes:

When detecting that the processor writes a timer trigger flag in the register, starting a first flip timer and a second flip timer in the register to start timing, wherein a timing of the first flip timer The duration of the second preset timer is a second preset time, and the first preset time is less than the second preset time;

The detection acquires a flag bit written in the processor, and determines whether the target BOOT is successfully started according to the flag bit, including:

When the first flip timer reaches the first preset time, detecting that the processor writes a first flag bit in the register; when the first flag bit is not the first predetermined value, Determine that the target BOOT failed to start;

When the first flag bit is a first predetermined value, and the second rollover timer reaches the second preset time, detecting that the processor writes the second flag bit in the register; When the second flag is not the second predetermined value, it is determined that the target BOOT fails to start.

The dual BOOT boot area flag is read from the serial peripheral interface flash SPI Flash and stored in the register.

The present disclosure provides a method for switching a dual boot file, the method further comprising:

Read the BOOT boot area flag of the dual boot file;

Reading the target BOOT corresponding to the dual BOOT boot zone flag, and running the target BOOT;

When an abnormality does not occur in the process of running the target BOOT, writing a flag value in the register of the EPLD to the target BOOT to start a normal identification value;

After receiving the reset signal, a reset operation is performed.

Optionally, before the dual boot file BOOT boot area flag is read, the method further includes:

Reading the secondary loader SPL from the SPI Flash, and writing a timer trigger flag to the register of the EPLD when the SPL is started to run;

And when the abnormality does not occur in the process of running the target BOOT, writing, to the flag bit in the register of the EPLD, the flag value of the target BOOT to start normal, including:

Writing the first predetermined value to the first flag bit in the register of the EPLD according to the first handshake information provided in the target BOOT when the target BOOT is run;

After writing the first predetermined value to the first flag bit in the register of the EPLD, before running to load the running version of the target BOOT, according to the second handshake information provided in the target BOOT, The second flag bit in the register of the EPLD is written to a second predetermined value.

Optionally, the dual boot file BOOT boot area flag is read, including:

At the end of the run of the SPL, the dual BOOT boot sector flag is read from the register of the EPLD.

Optionally, after the writing the second predetermined value in the register of the EPLD, the method further includes:

Loading the running version of the target BOOT and starting the watchdog operation when starting to run the running version of the target BOOT.

The present disclosure also provides an erasable editable logic device EPLD, comprising:

a detection determining unit, configured to detect a flag bit in the write processor write register, and determine, according to the flag bit, whether the target boot file BOOT is successfully started;

a switching unit, configured to: when the detection determining unit determines that the target BOOT fails to start, switch the dual BOOT boot area flag in the register from the target BOOT boot area flag to the standby BOOT boot area flag;

And a sending unit, configured to send a reset signal to the processor when the detection determining unit determines that the target BOOT fails to start.

Optionally, the EPLD further includes a timing starting unit;

The timing starting unit is configured to start a first inversion timer and a second inversion timer in the register to start timing when detecting that the processor writes a timer trigger flag in the register, where The timing of the first inversion timer is a first preset time, the timing of the second inversion timer is a second preset time, and the first preset time is less than the second preset time;

The detecting and determining unit is configured to detect, when the first inversion timer initiated by the timing starting unit reaches the first preset time, detecting that the processor writes the first in the register a flag bit; when the first flag bit is not the first predetermined value, determining that the target BOOT fails to start; When the first flag is a first predetermined value, and the second inversion timer initiated by the timing initiation unit reaches the second preset time, detecting that the processor is written into the register a second flag bit; when the second flag bit is not the second predetermined value, determining that the target BOOT fails to start.

Optionally, the EPLD further includes a first reading unit;

The first reading unit is configured to read the dual BOOT boot area flag from the serial peripheral interface flash SPI Flash and store the same in the register.

The present disclosure also provides a processor, the processor comprising:

a second reading unit configured to read the dual boot file BOOT boot region flag from a register of the erasable editable logic device EPLD; and read the dual BOOT boot region flag identifier from the serial peripheral interface flash SPI Flash Target BOOT;

a running unit, configured to run the target BOOT read by the second reading unit;

a writing unit, configured to write to the flag bit in the register of the EPLD to generate a normal identification value of the target BOOT when an abnormality does not occur in the process of running the target BOOT by the running unit;

a receiving unit, configured to receive a reset signal sent by a register of the EPLD;

The reset unit is configured to perform a reset operation after the receiving unit receives the reset signal.

Optionally, the second reading unit is further configured to read the secondary loader SPL from the SPI Flash;

The operating unit is further configured to run the SPL read by the second reading unit;

The writing unit is further configured to write a timer trigger flag to a register of the EPLD when the operating unit starts to run the SPL;

The writing unit is configured to, when the running unit runs the target BOOT, write to the first flag bit in the register of the EPLD according to the first handshake information provided in the target BOOT Entering a first predetermined value; after writing the first predetermined value to the first flag bit in the register of the EPLD, before the running unit runs to load the running version of the target BOOT, according to the target BOOT The second handshake information is provided, and a second predetermined value is written to the second flag bit in the register of the EPLD.

Optionally, the second reading unit is configured to read the dual BOOT boot area flag from the register of the EPLD when the running unit runs to the end of the SPL.

Optionally, the processor further includes a startup unit;

The running unit is configured to load an running version of the target BOOT, and run an running version of the target BOOT;

The startup unit is configured to initiate a watchdog operation when the operation unit starts running the running version of the target BOOT.

The embodiment of the invention provides a method and a device for switching a dual boot file. First, the processor reads a BOOT boot area flag of the dual boot file from the register of the EPLD, that is, a target BOOT boot area flag; according to the dual BOOT boot area flag The processor reads the target BOOT from the SPI Flash and runs the target BOOT; the processor writes to the flag bit in the register of the EPLD when no abnormality occurs during the running of the target BOOT The target BOOT starts a normal identification value; the EPLD detection acquires a flag bit in the processor write register, and determines whether the target BOOT is successfully started according to the flag bit; the EPLD determines that the target BOOT is started. In case of failure, the dual BOOT boot area flag in the register is switched from the target BOOT boot area flag to the standby BOOT boot area flag, and a reset signal is sent to the processor; the processor receives the register of the EPLD After the reset signal is sent, a reset operation is performed; after the processor is reset, the switched dual boot file BOOT boot area is read again from the register of the EPLD. Chi, i.e. spare flag BOOT promoter region; and then read from the SPI Flash promoter in the spare area flag marked BOOT The standby BOOT is recognized and the standby BOOT is operated. Thus, the processor utilizes the dual BOOT boot area flag in the EPLD register to implement switching to use the dual BOOT stored in the single-chip SPI Flash, thereby reducing hardware costs.

The embodiment of the invention further provides a computer readable storage medium storing computer executable instructions for performing the above method.

Embodiments of the present invention also provide an apparatus including one or more processors, a memory, and one or more programs, the one or more programs being stored in a memory when executed by one or more processors , perform the above method.

DRAWINGS

1 is a schematic flowchart of a method for switching a dual boot file applied to an EPLD side according to Embodiment 1 of the present disclosure;

2 is a schematic flowchart of a method for switching a dual boot file applied to a processor side according to Embodiment 1 of the present disclosure;

3 is a schematic flowchart of a method for switching a dual boot file according to Embodiment 2 of the present disclosure;

4 is a system architecture diagram of a method for implementing a dual boot file according to Embodiment 2 of the present disclosure;

FIG. 5 is a structural block diagram of an EPLD according to Embodiment 3 of the present disclosure;

FIG. 6 is a structural block diagram of a processor according to Embodiment 3 of the present disclosure.

Implementation

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure.

Example 1

The embodiment of the present disclosure provides a method for switching a dual boot file, which is applied to the EPLD side. As shown in FIG. 1 , the method in this embodiment includes step 101 and step 102.

In step 101, the flag bit in the acquisition processor write register is detected, and it is determined according to the flag bit whether the target BOOT is successfully started.

In order to reduce the hardware cost, in this embodiment, Serial Peripheral Interface Nor Flash (SPI Flash) can be used to store dual boot files (ie, dual BOOT): LOW BOOT and HIGH BOOT; EPLD registers (Register) , REG) stores a boot area flag, which is used to control whether the processor uses the LOW BOOT in the SPI Flash or the HIGH BOOT to boot the operating system. The boot area flag may be obtained from an external storage device, such as SPI Flash, or may be initially set in a register of the EPLD.

After the processor and the EPLD are powered on or reset, the processor reads the current boot area flag from the register of the EPLD; then reads the corresponding BOOT from the SPI Flash according to the boot area flag, and runs the BOOT. The processor writes a normal identification value to a flag bit in a register of the EPLD when an abnormality does not occur in the process of running the BOOT. For example, the initial value of the flag bit in the register of the EPLD is 0; the processor may write the identification value 1 to the flag bit in the register of the EPLD when no abnormality occurs during the running of the target BOOT.

The EPLD detection acquires a flag bit written by the processor into the register, and determines whether the target BOOT is successfully started according to the flag bit. When the EPLD detects that the flag bit in the register is the identification value 1, it indicates that the processor does not generate an abnormality during the running of the target BOOT, and the flag bit in the register is written to the target BOOT to start. The normal identification value is 1, the EPLD determines that the target BOOT is successfully started; when the flag bit in the register is the identification value 0, it indicates that the processor has an abnormality in the process of running the target BOOT, not in the register. Flag bit write The target BOOT starts a normal identification value of 1, and the EPLD determines that the target BOOT fails to start.

In step 102, when it is determined that the target BOOT fails to start, the dual BOOT boot area flag in the register is switched from the target BOOT boot area flag to the standby BOOT boot area flag, and a reset signal is sent to the processor. When the EPLD determines that the target BOOT fails to be started, for example, when the identifier value of the flag bit is not 1, the dual BOOT boot area flag in the register of the EPLD is switched by the boot area flag corresponding to the target BOOT. It is a boot area flag corresponding to the standby BOOT, and sends a reset signal to the processor.

For example, the dual BOOT boot zone flag is 0, indicating that the LOW BOOT is started; the dual BOOT boot zone flag is 1, indicating that the HIGH BOOT is started. If the processor reads the current boot area flag from the register of the EPLD to be 0, the target BOOT corresponding to the boot area flag read by the processor from the SPI Flash is 0, that is, LOW BOOT According to the above example, the boot area flag corresponding to the target BOOT is 0, and the boot target BOOT: LOW BOOT is identified; the standby BOOT boot area flag is 1, and the identifier starts the standby BOOT: HIGH BOOT.

When the EPLD determines that the LOW BOOT fails to start, the EPLD switches the boot area flag in the register from the boot area flag 0 corresponding to the target BOOT to the boot area flag 1 corresponding to the standby BOOT, and A reset signal is sent to the processor.

The processor performs a reset operation after receiving the reset signal sent by the register of the EPLD. After performing the reset operation, the processor reads, from the register of the EPLD, a boot area identifier that is a switch, that is, a boot area flag 1 corresponding to the standby BOOT, and the processor is configured according to the boot area corresponding to the standby BOOT. Marking, reading the standby BOOT from the SPI Flash, and running the standby BOOT, so that the processor can boot from the target BOOT to the standby BOOT to boot the operating system when the startup target BOOT fails. , to achieve the switching of dual BOOT.

The embodiment of the present disclosure further provides a method for switching a dual boot file, which is applied to a processor side. As shown in FIG. 2, the method of this embodiment includes step 201, step 202, step 203 and step 204.

In step 201, the dual boot file BOOT boot region flag is read from the register of the erasable editable logic device EPLD.

In order to reduce the hardware cost, the SPI Flash is used in this embodiment to store dual BOOTs: LOW BOOT and HIGH BOOT; the EPLD register stores a dual BOOT boot area flag, and the dual BOOT boot area flag is used to control the processor usage. The LOW BOOT in SPI Flash still uses HIGH BOOT to boot the operating system. The dual BOOT boot area flag may be obtained from an external storage device, such as SPI Flash, or may be initially set in a register of the EPLD.

After the processor and the EPLD are powered on or reset, the processor reads the current dual BOOT boot area flag, that is, the target BOOT boot area flag, from the register of the EPLD to determine to enable the LOW BOOT or HIGH BOOT in the dual BOOT. .

In step 202, the target BOOT of the dual BOOT boot area flag is read from the serial peripheral interface non-volatile flash SPI Flash, and the target BOOT is run.

The processor reads the target BOOT of the dual BOOT boot zone flag from the SPI Flash according to the dual BOOT boot zone flag, and runs the target BOOT. The target BOOT is LOW BOOT or HIGH BOOT.

For example, the dual BOOT boot zone flag is 0, indicating that the LOW BOOT is started; the dual BOOT boot zone flag is 1, indicating that the HIGH BOOT is started. If the processor reads the current dual BOOT boot area flag from the register of the EPLD to be 0, the dual BOOT boot area flag read by the processor from the SPI Flash is the target corresponding to 0. BOOT is LOW BOOT. According to the above example, the target BOOT boot zone flag is 0, and the boot target BOOT: LOW BOOT is identified; the standby BOOT boot zone flag is 1, and the logo initiates the standby BOOT: HIGH BOOT.

In step 203, when an abnormality does not occur in the process of running the target BOOT, the flag bit in the register of the EPLD is written to the target BOOT to start a normal identification value.

And when the processor does not generate an abnormality in the process of running the target BOOT, writing, to the flag bit in the register of the EPLD, the target BOOT starts a normal identification value. For example, the flag bit in the register of the EPLD is initially 0; the processor may write the identifier value to the flag bit in the register of the EPLD when no abnormality occurs during the running of the target BOOT. 1.

In step 204, after receiving the reset signal transmitted by the register of the EPLD, a reset operation is performed.

The EPLD detection acquires a flag bit written by the processor in the register, and when detecting that the flag bit is written by the target BOOT to start a normal identification value, determining that the target BOOT is successfully started; When it is detected that the flag bit is not written by the target BOOT, the target BOOT is determined to fail to start. When determining that the target BOOT fails to start, the EPLD switches the dual BOOT boot area flag in the register from the target BOOT boot area flag 0 to the standby BOOT boot area flag 1, and sends a reset signal to the processor.

The processor performs a reset operation after receiving the reset signal sent by the register of the EPLD. After performing the reset operation, the processor performs step 201 to read the switched dual BOOT boot area flag, that is, the standby BOOT boot area flag 1 from the register of the EPLD, according to the standby BOOT. a boot area flag, reading the standby BOOT:HIGH BOOT from the SPI Flash, and running the standby BOOT, so that the processor can switch from the target BOOT to the standby BOOT when the startup target BOOT fails To boot the operating system and achieve dual BOOT switching.

Example 2

The embodiment of the present disclosure provides a method for switching a dual boot file, as shown in FIG. 3, this embodiment The method includes steps 301-312.

In step 301, the EPLD reads the dual BOOT boot area flag from the SPI Flash and stores it in the register.

In order to reduce the hardware cost, the SPI Flash is used in this embodiment to store dual BOOTs: LOW BOOT and HIGH BOOT; the address space inside the SPI Flash can be divided into: 0 to a address space, a to b address space, b~ c address space, c ~ d address space; wherein the 0 ~ a address space is used to store a secondary loader (SPL); the a ~ b address space for storing LOW BOOT; the b The ~c address space is used to store the HIGH BOOT; the c~d address space is used to store the dual BOOT boot area flag. The dual BOOT boot area flag is used to identify whether to activate HIGH BOOT or start LOW BOOT.

The SPL is used to boot the LOW BOOT or the HIGH BOOT; the contents of the LOW BOOT and the HIGH BOOT are the same; the dual BOOT boot area flag can be represented by one byte, if the byte The highest bit is 0, indicating that the LOW BOOT is enabled; if the highest bit in the byte is 1, it indicates that the HIGH BOOT is started.

Here, the user may set some basic configurations of the processor in the SPL according to the needs of the user, and set the basic configuration in the SPL according to the user requirements in the SPL. Better flexibility, smaller storage space and more.

In this embodiment, after the EPLD is powered on, the dual BOOT boot area flag can be read from the c-d address space of the SPI Flash and stored in the register of the EPLD.

Optionally, as shown in FIG. 4, the EPLD can read the dual BOOT boot zone flag in the SPI Flash through the serial peripheral interface (SPI) read timing of the dual BOOT controller and the dual The BOOT boot area flag is stored in the EPLD register.

In step 302, the processor reads the SPL from the SPI Flash and starts running the SPL. At this time, a timer trigger flag is written to the register of the EPLD.

After the processor is powered on or reset, the processor reads the SPL from the 0-a address space of the SPI Flash, and stores the read SPL in the memory of the processor, the processor is reading After the SPL is completed, the SPL is started to run. The processor writes a timer trigger flag to a register of the EPLD when the SPL is started to run.

As shown in FIG. 4, the processor has a general purpose input/output (GPIO) interface, and the GPIO interface can serve as a chip select terminal, and a chip select signal in the chip select terminal can control the EPLD. The multiplexer (MUX) in the multiplex chooses to access the register REG of the EPLD or to access the SPI Flash.

Here, the chip selection signal may be set by software, and may be set by other methods, which is not specifically limited in this embodiment.

In addition, the processor further has a synchronous queue serial peripheral interface (Queued SPI, QSPI), and when the processor selects to access the register of the EPLD, the register of the EPLD can be performed by the QSPI. Read and write operations.

For example, when the processor needs to access a register of the EPLD, the processor may set a chip select signal in the GPIO interface to 1, and control a MUX in the EPLD to select a register to access the EPLD. And reading and writing the register of the EPLD by using the QSPI; when the processor needs to access the SPI Flash, the processor may set the chip select signal in the GPIO interface to 0, and control The MUX in the EPLD selects to access the SPI Flash, and then reads the content in the SPI Flash through the QSPI.

In the method of this embodiment, the processor may perform a read/write operation on the register of the EPLD and read the content in the SPI Flash by using the foregoing method.

Optionally, in the embodiment, the processor may be an ARM (Advanced RISC Machines). processor.

In step 303, when the EPLD detects that the processor writes a timer trigger flag in the register, the fast flip timer and the slow flip timer in the register are started to start timing.

When the EPLD detects that the processor writes a timer trigger flag in the register, the fast flip timer and the slow flip timer in the register of the EPLD are started to start timing. The fast rollover timer and the slow rollover timer need to be preset with a preset duration. The timing of the fast rollover timer is less than ten seconds, and the timing of the slow rollover timer is longer. The timing of the fast rollover timer is a first preset time, the time duration of the slow rollover timer is a second preset time, and the first preset time is less than the second preset time. For example, the first preset time may be 5 seconds, and the second preset time may be 60 seconds.

In step 304, the processor reads the dual BOOT boot area flag from a register of the EPLD at the end of running the SPL.

The processor controls the MUX to select to access the EPLD through a chip select signal in the GPIO interface, and reads the current dual BOOT boot area from the register of the EPLD via the QSPI at the end stage of running the SPL. The flag, that is, the target BOOT boot area flag; and the target BOOT boot area flag is stored in the memory of the processor, and the LOW BOOT or the HIGH BOOT is used to boot the operating system according to the target BOOT boot area flag.

In step 305, the processor reads the target BOOT of the dual BOOT boot area flag identifier from the SPI Flash, and runs the target BOOT.

After reading the dual BOOT boot area flag, the processor controls the MUX to select to access the SPI Flash through a chip select signal in the GPIO interface; and then according to the dual BOOT boot area flag, that is, the target BOOT boot area. The flag reads the target BOOT from the SPI Flash via the QSPI, stores the target BOOT in the memory of the processor, and runs the target BOOT.

For example, when the dual BOOT boot area flag is 0, the processor reads a LOW BOOT whose dual BOOT boot area flag is 0 from the a to b address space of the SPI Flash, and the LOW BOOT is The target BOOT, and the HIGH BOOT of the b~c address space is the standby BOOT; when the dual BOOT boot area flag is 1, the processor reads the dual BOOT boot area flag from the b~c address space of the SPI Flash. For the HIGH BOOT identified by 1, the HIGH BOOT is the target BOOT, and the LOW BOOT of the a~b address space is the standby BOOT.

In step 306, when the processor runs the target BOOT, the processor writes a useful value to the first flag bit in the register of the EPLD according to the first handshake information provided in the target BOOT.

The target BOOT is stored in the memory of the processor, and the target BOOT is provided with first handshake information that interacts with the EPLD. Here, the first handshake information that interacts with the EPLD may be provided by the code board_init_r (Board.c file) that the target BOOT initially runs.

When the processor runs the target BOOT, according to the first handshake information provided in the target BOOT, the MUX selects to access the EPLD through a chip select signal in the GPIO interface, and the QSPI is used to The first flag bit in the register of the EPLD is written with a useful value. For example, the first flag bit in the register of the EPLD is BDBCR_REG[REV_F]; when the processor runs the target BOOT, according to the target The first handshake information provided in the BOOT writes the useful value 1 to the first flag bit BDBCR_REG[REV_F] in the register of the EPLD; the EPLD acquires the flag bit BDBCR_REG[REV_F], and detects the flag Whether the identifier value of the bit BDBCR_REG[REV_F] is 1; when the identifier value of the flag bit BDBCR_REG[REV_F] is 1, it indicates that the processor can correctly load the target BOOT.

It should be noted that, when the processor starts running the SPL to run the target BOOT, the fast flip timer in the register of the EPLD has not reached the first preset time of 5 seconds. Similarly, the fast flip timer continues to count and does not reach the first The preset time is 60 seconds; the fast flip timer does not allow the EPLD to switch the dual BOOT boot zone flag in the register from the target BOOT boot zone flag to the standby BOOT before the first preset time is reached. The boot area flag, that is, the EPLD is not allowed to reverse the highest bit of the dual BOOT boot area flag.

After the processor writes a useful value to the first flag bit in the register of the EPLD, the chip select signal of the GPIO interface is automatically set to zero.

In step 307, when the fast flip timer reaches the first preset time, the EPLD detects that the processor writes the first flag bit in the register.

When the fast flip timer in the register of the EPLD reaches the first preset time of 5 seconds, the EPLD detects whether the first flag bit written by the processor in the register is acquired. A useful value of 1 was successfully written.

In step 3081, the EPLD switches the dual BOOT boot zone flag in the register from the target BOOT boot zone flag to the standby BOOT boot zone flag when the first flag bit is not a useful value, and The processor sends a reset signal.

When the first flag is not a useful value, indicating that the processor does not obtain the first handshake information provided in the target BOOT, and does not write a useful value of 1 to the first flag in the register of the EPLD, The EPLD may determine that the target BOOT is not properly loaded by the processor, and the target BOOT is unavailable. At this time, the EPLD determines that the processor fails to start the target BOOT.

The EPLD, when determining that the target BOOT fails to start, switches the dual BOOT boot area flag in the register of the EPLD from the target BOOT boot area flag to the standby BOOT boot area flag, and sends the flag to the processor. The reset signal, the processor performs step 312.

Here, the EPLD switches the dual BOOT boot area flag in the register from the target BOOT boot area flag to the standby BOOT boot area flag, including: the EPLD will be in the register The highest bit of the dual BOOT boot area flag is inverted. That is, the standby BOOT boot area flag is a dual BOOT boot area flag after the highest bit of the target BOOT boot area flag is inverted.

For example, if the highest bit of the dual BOOT boot area flag is 0, the LOW BOOT is the target BOOT, and when the LOW BOOT fails to start, the EPLD sets the highest bit of the dual BOOT boot area flag in its register. The bit is inverted from 0 to 1, and a reset signal is sent to the processor, and after the processor resets, the highest bit of the dual BOOT boot area flag is read from the EPLD and read from its register. 1, the HIGH BOOT, that is, the standby BOOT, is started according to the dual BOOT boot area flag, and the switching from the LOW BOOT to the HIGH BOOT is realized.

In step 3082, after the processor writes a useful value to the first flag bit in the register of the EPLD, before running to load the running version of the target BOOT, according to the number provided in the target BOOT The second handshake information writes a valid value to the second flag bit in the register of the EPLD.

When the first flag bit in the register of the EPLD is set to a useful value of 1, indicating that the processor obtains the first handshake information provided in the target BOOT, to the first of the registers of the EPLD The flag bit is written to a useful value of 1, and the EPLD can determine that the target BOOT has been properly loaded by the processor. At this time, the EPLD does not perform the switching of the dual BOOT boot area flag, nor does it send a reset signal to the processor, and the processor continues to run the target BOOT.

Before the target BOOT runs to load the running version, the processor controls the MUX selection access by using a chip select signal in the GPIO interface according to the second handshake information provided in the target BOOT to interact with the EPLD. The register of the EPLD writes a valid value to the second flag of the register of the EPLD. For example, the valid value may be 1, and the valid value is used to indicate that the processor has completed the initial execution of the target BOOT. Boot, ready to load the running version of the target BOOT.

It should be noted here that the processor starts from running the SPL to load the target. Before the running version of the BOOT, the slow rollover timer in the register of the EPLD has not reached the second preset time of 60 seconds; the slow rollover timer before reaching the second preset time The EPLD is not allowed to switch the dual BOOT boot area flag in the register from the target BOOT boot area flag to the standby BOOT boot area flag, that is, the EPLD is not allowed to invert the highest bit of the dual BOOT boot area flag. operating.

After the processor writes a valid value to the second flag of the EPLD register, the chip select signal of the GPIO interface is automatically set to zero.

In step 309, the EPLD is a useful value when the first flag bit, and when the slow rollover timer reaches the second preset time, detecting that the processor is written into the register The second flag.

The first flag bit in the register of the EPLD is a useful value, and when the slow rollover timer reaches the second preset time of 60 seconds, the EPLD detection acquires the processor write location Whether the second flag bit in the register is successfully written to a valid value.

In step 3101, when the second flag bit is not a valid value, the EPLD switches the dual BOOT boot area flag in the register from the target BOOT boot area flag to the standby BOOT boot area flag, and sends the flag to the processor. Reset signal.

When the second flag is not a valid value, indicating that the processor does not obtain the second handshake information provided in the target BOOT, and does not write a useful value of 1 to the second flag in the register of the EPLD, The EPLD may determine that the processor does not initialize the target BOOT incorrectly, and the processor does not complete initial booting of the target BOOT. At this time, the EPLD determines that the processor starts the target. BOOT failed.

When it is determined that the target BOOT fails to be started, the EPLD switches the dual BOOT boot zone flag in the register of the EPLD from the target BOOT boot zone flag to the standby BOOT boot zone. The flag is sent to the processor and the processor executes step 312.

Here, the EPLD switches the dual BOOT boot area flag in the register from the target BOOT boot area flag to the standby BOOT boot area flag, including: the EPLD will mark the dual BOOT boot area in the register. The highest bit is inverted. That is, the standby BOOT boot area flag is a dual BOOT boot area flag after the highest bit of the target BOOT boot area flag is inverted.

For example, if the highest bit of the dual BOOT boot area flag is 0, the LOW BOOT is the target BOOT, and when the LOW BOOT fails to start, the EPLD sets the highest bit of the dual BOOT boot area flag in its register. The bit is inverted from 0 to 1, and a reset signal is sent to the processor.

In step 3102, the processor loads the running version of the target BOOT after writing a valid value to the second flag bit in the register of the EPLD.

When the second flag bit in the register of the EPLD is set to a valid value of 1, indicating that the processor obtains the second handshake information provided in the target BOOT, and the second in the register of the EPLD The flag bit is written to a valid value of 1, and the EPLD can determine that the processor has completed the initial boot of the target BOOT and prepare to load the running version of the target BOOT. The processor loads an running version of the target BOOT from a storage device that stores an running version of the target BOOT. Here, the storage device storing the running version of the target BOOT is a flash memory or other storage.

In step 311, the processor starts a watchdog operation when it starts running the running version of the target BOOT.

The processor starts a watchdog operation when the target BOOT starts running the running version, and a timer in the watchdog timer starts timing.

The processor periodically releases the dog to the watchdog during the running of the running version of the target BOOT; after the watchdog receives the dog feeding signal, Clearing the timer, the timer does not overflow the preset timing, and the reset signal cannot be generated. Indicates that the processor can normally run the running version of the target BOOT; if the processor is abnormal during the running of the running version of the target BOOT, the watchdog cannot be at the preset timing Receiving the dog feed signal, the timer cannot be cleared, and the timer overflows. At this time, the watchdog sends a reset signal to the EPLD and the processor, and the EPLD receives After the reset signal sent by the watchdog, the method of this embodiment starts from step 301 again.

In step 312, the processor performs a reset operation after receiving the reset signal sent by the register of the EPLD.

After receiving the reset signal sent by the register of the EPLD, the processor indicates that the processor fails to start the target BOOT, and the processor performs a reset operation, and the method in this embodiment starts from step 302 again.

After the processor performs a reset operation and returns to step 302, the processor reads the switched dual BOOT boot area flag, that is, the standby BOOT boot area flag, from the register of the EPLD, the processor according to the The standby BOOT boot area flag reads the standby BOOT from the SPI Flash, and runs the standby BOOT, so that the processor is switched from the target BOOT to the standby BOOT to boot the operating system, thereby realizing the use of the single piece. SPI Flash performs dual BOOT switching.

In this embodiment, the dual BOOT online upgrade can be performed in two ways, one is to connect a PC through an LPC (Low Pin Count) cable to download a new BOOT, the upgrade method is used to download the BOOT for the first time; the other is The running version is upgraded by the processor, and the upgrade of the running version can only be the running version of the non-target BOOT running.

In order to reduce the hardware cost, a single SPI Flash is used as the storage device. However, the SPI Flash is accessed by a serial peripheral interface. There is only one address line. The EPLD cannot implement address mapping by controlling the high and low address lines to implement two BOOTs. Switch. In the method of the embodiment, the single-chip SPI Flash is divided into different areas according to different address spaces to store SPL, LOW BOOT, HIGH BOOT and double. a BOOT boot area flag, when the processor does not generate an abnormality in the process of running the target BOOT, writing a flag value of the target BOOT to the flag in the register of the EPLD to start a normal identification value; the EPLD passes the detection Obtaining a flag bit in the processor write register to determine whether to switch a dual BOOT boot area flag in the register; and the processor selects to activate a BOOT according to the dual BOOT boot area flag in the EPLD; thus, The processor utilizes the dual BOOT boot area flag in the EPLD register to implement switching between dual BOOTs stored in a single SPI Flash, thereby reducing hardware costs.

Example 3

The embodiment of the present disclosure further provides an EPLD. As shown in FIG. 5, the EPLD includes: a detection determining unit 501, a switching unit 502, and a sending unit 503.

The detection determining unit 501 is configured to detect a flag bit in the write register of the acquisition processor, and determine, according to the flag bit, whether the target BOOT is successfully started;

The switching unit 502 is configured to, when the detection determining unit 501 determines that the target BOOT fails to start, switch the dual BOOT boot area flag in the register from the target BOOT boot area flag to the standby BOOT boot area flag.

The transmitting unit 503 is configured to transmit a reset signal to the processor when the detection determining unit 501 determines that the target BOOT fails to start.

Optionally, as shown in FIG. 5, the EPLD further includes a timing starting unit 504.

The timing initiation unit 504 is configured to initiate a fast rollover timer and a slow rollover timer in the register to start timing when detecting that the processor writes a timer trigger flag in the register, wherein the fast The timing of the rollover timer is a first preset time, and the time duration of the slow rollover timer is a second preset time, and the first preset time is less than the second preset time.

The detection determining unit 501 is specifically configured to start the fast when the timing starting unit 504 starts When the rollover timer reaches the first preset time, detecting that the processor writes the first flag bit in the register; when the first flag bit is not a useful value, determining that the target BOOT fails to start; The first flag is a useful value, and when the timing initiation unit 504 starts the slow rollover timer to reach the second preset time, detecting that the processor writes the second in the register Flag bit; when the second flag bit is not a valid value, it is determined that the target BOOT fails to start.

Optionally, the EPLD further includes a first reading unit 505.

The first reading unit 505 is configured to read a dual boot file BOOT boot area flag from the serial peripheral interface non-volatile flash SPI Flash and store the same in the register.

The embodiment of the present disclosure further provides a processor. As shown in FIG. 6, the processor includes: a second reading unit 601, an operating unit 602, a writing unit 603, a receiving unit 604, and a reset unit 605.

The second reading unit 601 is configured to read the dual boot file BOOT boot area flag from the register of the erasable editable logic device EPLD; read from the serial peripheral interface flash SPI Flash according to the dual BOOT boot area flag Take the target BOOT.

The running unit 602 is configured to run the target BOOT read by the second reading unit 601.

The writing unit 603 is configured to write to the flag bit in the register of the EPLD to write the flag value of the target BOOT to start normal when an abnormality does not occur in the process of the operation unit 602 running the target BOOT.

The receiving unit 604 is configured to receive a reset signal sent by a register of the EPLD.

The reset unit 605 is configured to perform a reset operation after the receiving unit 604 receives the reset signal.

Optionally, the second reading unit 601 is further configured to read the secondary loader SPL from the SPI Flash.

The running unit 602 is further configured to run the SPL read by the second reading unit 601.

The writing unit 603 is further configured to write a timer trigger flag to the register of the EPLD when the operating unit 602 starts to run the SPL.

The writing unit 603 is specifically configured to, when the running unit 602 runs the target BOOT, write to the first flag bit in the register of the EPLD according to the first handshake information provided in the target BOOT. a useful value; after writing the useful value to the first flag bit in the register of the EPLD, before the running unit 602 runs to load the running version of the target BOOT, according to the second provided in the target BOOT The handshake information writes a valid value to the second flag bit in the register of the EPLD.

Optionally, the second reading unit 601 is specifically configured to read the dual BOOT boot area flag from the register of the EPLD when the running unit 602 runs to the end of the SPL.

Optionally, the processor further includes a starting unit 606.

The running unit 602 is further configured to load an running version of the target BOOT and run a running version of the target BOOT.

The startup unit 606 is configured to initiate a watchdog operation when the execution unit 602 starts running the running version of the target BOOT.

In a practical application, the detection determining unit 501, the switching unit 502, the sending unit 503, the timing starting unit 504, and the first reading unit 505 described in this embodiment may be implemented by a central processing unit (CPU) on the adjusting device. Implemented by a Microcontroller Unit (MCU), a Digital Signal Processing (DSP), or a Field Programmable Gate Array (FPGA), a modem, or the like. The second reading unit 601, the running unit 602, the writing unit 603, the receiving unit 604, the reset unit 605, and the starting unit 606 described in this embodiment may be processed by a central processing unit (CPU) on the metadata node. Device (MPU), digital signal processor (DSP) or field programmable gate array (FPGA), modem and other device implementation.

Those skilled in the art will appreciate that embodiments of the present disclosure can be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware aspects. Moreover, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to an ARM processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing device to produce a machine such that instructions are executed by an ARM processor of a computer or other programmable data processing device Means are provided for implementing the functions specified in one or more of the flow or in one or more blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

The above description is only for the embodiments of the present disclosure, and is not intended to limit the scope of the disclosure.

Through the description of the above embodiments, those skilled in the art can clearly understand that the foregoing embodiment method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be hard. Pieces. Based on such understanding, the technical solution of the embodiments of the present disclosure may be embodied in the form of a software product stored in a storage medium (such as a ROM/RAM, a magnetic disk, an optical disk), including instructions for making one The terminal device (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) performs the method described in the embodiments of the present disclosure.

It should be noted that the terms "first", "second" and the like in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or order. .

Industrial applicability

The embodiment of the present disclosure realizes switching between dual BOOTs stored in a single SPI Flash by setting a dual BOOT boot area flag in a register of the EPLD, which does not require too many address lines, has simple control, and reduces hardware cost.

Claims

A method for switching a dual boot file, the dual boot file being stored in a serial peripheral interface flash memory (SPI Flash), comprising:

Detecting a flag bit in the processor write register, and determining, according to the flag bit, whether the first boot file fails to be started;

When the first boot file fails to be started, the boot area flag in the register is switched from the first boot area flag to the second boot area flag corresponding to the second boot file, and a reset signal is sent to the processor.
The method of claim 1, before the detecting the processor writes the flag bit in the register, the method further comprising:

When detecting that the processor writes a timer trigger flag in the register, starting a first flip timer and a second flip timer in the register to start timing, wherein a timing of the first flip timer The duration of the second preset timer is a second preset time, and the first preset time is less than the second preset time;

The detecting acquires a flag bit written in the register by the processor, and determines, according to the flag bit, whether the first boot file fails to be started, including:

When the first flip timer reaches the first preset time, detecting that the processor writes a first flag bit in the register; when the first flag bit is not the first predetermined value, Determining that the first boot file failed to start;

When the first flag bit is a first predetermined value, and the second rollover timer reaches the second preset time, detecting that the processor writes the second flag bit in the register; When the second flag is not the second predetermined value, it is determined that the first boot file fails to be started.
The method of claim 1, before the detecting the processor writes the flag bit in the register, the method further comprising:

The boot area flag is read from the serial peripheral interface flash (SPI Flash) and stored in the register.
A method for switching a dual boot file includes:

Read the boot area flag;

Reading a boot file corresponding to the boot area flag from the serial peripheral interface flash memory (SPI Flash), and running a boot file corresponding to the boot area flag;

Writing a first identification value to a flag bit in a register of an erasable editable logic device (EPLD) when the boot file corresponding to the boot area flag is successfully run;

After receiving the reset signal sent by the EPLD, a reset operation is performed.
The switching method according to claim 4, before the reading of the startup area flag, further comprising:

Reading a secondary loader SPL from the SPI Flash, and writing a timer trigger flag to a register of the EPLD when starting to run the SPL;

The first identification value is written to the flag bit in the register of the EPLD when the boot file corresponding to the boot area flag is successfully run, including:

When the boot file corresponding to the boot area flag is run, the first predetermined value in the register of the EPLD is written according to the first handshake information provided in the boot file corresponding to the boot area flag;

After writing the first predetermined value to the first flag bit in the register of the EPLD, before running to the running version of the boot file corresponding to the loading boot area flag, according to the boot file corresponding to the boot area flag The second handshake information writes a second predetermined value to the second flag bit in the register of the EPLD.
The method of claim 5 wherein said reading a boot zone flag comprises:

At the end of the run of the SPL, the dual BOOT boot sector flag is read from the register of the EPLD.
The method of claim 5 wherein said number in said register of said EPLD After the second flag is written to the second predetermined value, the method further includes:

Loading a running version of the boot file corresponding to the boot area flag, and starting a watchdog operation when starting to run a running version of the boot file corresponding to the boot area flag.
An erasable editable logic device EPLD, comprising:

register;

The detection determining unit is configured to detect a flag bit in the write register of the acquisition processor, and determine, according to the flag bit, whether the first boot file is successfully started;

a switching unit configured to switch the boot area flag in the register from the first boot area flag to the second boot area flag when the detection determining unit determines that the first boot file fails to start;

The transmitting unit is configured to send a reset signal to the processor when the detection determining unit determines that the first boot file fails to start.
The EPLD of claim 8 further comprising a timing activation unit;

The timing starting unit is configured to start a first inversion timer and a second inversion timer in the register to start timing when detecting that the processor writes a timer trigger flag in the register, where The timing of the first inversion timer is a first preset time, the timing of the second inversion timer is a second preset time, and the first preset time is less than the second preset time;

The detecting and determining unit is further configured to: when the first inversion timer started by the timing starting unit reaches the first preset time, detect that the processor writes into the register a flag bit; determining that the first boot file fails to start when the first flag bit is not the first predetermined value; wherein the first flag bit is a first predetermined value, and the timing start unit is activated When the second flip timer reaches the second preset time, detecting that the processor writes the second flag bit in the register; when the second flag bit is not the second predetermined value, determining the first boot The file failed.
The EPLD of claim 8 further comprising a first reading unit;

The first read unit is configured to read a boot area flag from the serial peripheral interface non-volatile flash SPI Flash and store the register.
A processor comprising:

a second reading unit configured to read a boot area flag from a register of the erasable editable logic device EPLD; and read a boot corresponding to the boot area flag from the serial peripheral interface non-volatile flash SPI Flash file;

a running unit, configured to run a boot file corresponding to the boot area flag;

a writing unit configured to write a first identification value to a flag bit in a register of the EPLD when an abnormality does not occur in a process in which the running unit runs a boot file corresponding to the boot area flag;

a receiving unit configured to receive a reset signal sent by a register of the EPLD;

The reset unit is configured to perform a reset operation after the receiving unit receives the reset signal.
The processor of claim 11 wherein

The second reading unit is further configured to read the secondary loader SPL from the SPI Flash;

The operating unit is further configured to run the SPL read by the second reading unit;

The writing unit is further configured to write a timer trigger flag to a register of the EPLD when the operating unit starts to run the SPL;

Wherein, when the running unit runs the boot file corresponding to the boot area flag, the writing unit is first to the EPLD register according to the first handshake information provided in the boot file corresponding to the boot area flag Writing a flag to the first predetermined value; after writing the first predetermined value to the first flag in the register of the EPLD, running the running unit to the running version of the boot file corresponding to the boot area flag Previously, the writing unit writes a second predetermined value to the second flag bit in the register of the EPLD according to the second handshake information provided in the target BOOT.
The processor of claim 12, wherein

The second read unit is configured to read a boot area flag from a register of the EPLD at a stage in which the run unit runs to the SPL.
The processor of claim 12 further comprising a boot unit;

The running unit is further configured to load and run an running version of the boot file corresponding to the boot area flag;

The startup unit is configured to initiate a watchdog operation when the running unit starts running an running version of the boot file corresponding to the boot area flag.
A computer readable storage medium storing computer executable instructions for performing the method of any of claims 1-7.