WO2017105447A1

WO2017105447A1 - Methods and apparatuses to provide ordered porosity

Info

Publication number: WO2017105447A1
Application number: PCT/US2015/066196
Authority: WO
Inventors: David J. Michalak; Eungnak Han; Robert L. Bristol; Kanwal Jit Singh
Original assignee: Intel Corporation
Priority date: 2015-12-16
Filing date: 2015-12-16
Publication date: 2017-06-22
Also published as: TWI720058B; TW201731059A

Abstract

A directed self-assembly (DSA) layer is deposited on one or more conductive features on an insulating layer on a substrate. The DSA layer comprises one or more first structures that are deposited on the insulating layer. One or more openings in the insulating layer are formed using the DSA layer as a mask to provide porosity for the insulating material. The one or more openings are self-aligned to the one or more conductive features.

Description

METHODS AND APPARATUSES TO PROVIDE ORDERED POROSITY

FIELD

Embodiments as described herein relate to a field of electronic device manufacturing, and in particular, to an integrated circuit manufacturing.

BACKGROUND

Generally, an integrated circuit (IC) refers to a set of electronic devices, e.g., transistors formed on a small chip of semiconductor material, typically, silicon. Typically, an interconnect structure incorporated into the IC includes one or more levels of metal lines to connect the electronic devices of the IC to one another and to external connections. An interlayer dielectric is placed between the metal levels of the IC for insulation. Generally, the efficiency of the interconnect structure depends on the resistance of each metal line and the coupling capacitance generated between the metal lines.

As the size of the IC decreases, the spacing between the metal lines decreases. Integration of small structures is made easier with strong dielectrics which tend to have higher dielectric constants that increase coupling capacitance between metal lines. Increase in the coupling capacitance between the metal lines has a negative impact on signal transmission along metal lines. Furthermore, increase in the coupling capacitance increases energy consumption of the integrated circuit.

One conventional technique to reduce the capacitive coupling between adjacent metal lines involves replacing a higher k dielectric material that separates the metal lines with a lower k dielectric material.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention may be best understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings:

Figure 1 shows a side view of a portion of an electronic device according to one embodiment.

Figure 2 is a view similar to Figure 1, after modifying a top surface of the one or more features on the insulating layer using a brush layer according to one embodiment.

Figure 3 is a view similar to Figure 2, after a DSA layer is deposited on the features on the insulating layer according to one embodiment.

Figure 4 A is a view similar to Figure 3, after the structures of the second component of the DSA layer are selectively removed to form openings to expose some of the top portions of the insulating layer according to one embodiment.

Figure 4B is a view similar to Figure 4B, after portions of the first component of the DSA layer are removed to increase a width of the openings in the DSA layer according to one embodiment.

Figure 5 is a view similar to one of Figures 4 A or 4B, after openings are formed in insulating layer using the DSA layer as a mask according to one embodiment.

Figure 6 is a view similar to Figure 5, after a patterned hard mask layer on an insulating layer on a capping layer are deposited on the conductive features in the insulating layer according to one embodiment.

Figure 7 is a view similar to Figure 6, after the exposed portions of the insulating layer are removed to form an opening according to one embodiment.

Figure 8 is a view similar to Figure 7, after a conductive layer is deposited into the opening according to one embodiment.

Figure 9 is a three-dimensional view of the portion of the electronic device shown in Figure 1 according to one embodiment.

Figure 10 is a three-dimensional view of the portion of the electronic device shown in Figure 2 according to one embodiment.

Figure 11 is a three-dimensional view of the portion of the electronic device shown in Figure 3 according to one embodiment.

Figure 12 is a three-dimensional view of the portion of the electronic device shown in Figure 4A according to one embodiment. Figure 13 is a three-dimensional view of the portion of the electronic device shown in Figure 5, according to one embodiment.

Figure 14 is a top view of a portion of the electronic device shown in Figure 13, according to one embodiment.

Figure 15 is a cross-sectional view along a line A- A' of the portion, according to one embodiment.

Figure 16 is a view of a top-down scanning electron microscope (SEM) image showing a self-aligned DSA mask on an insulating layer, according to one embodiment.

Figure 17 is a view showing a graph of Young's modulus values versus porosity for various ILD films, according to one embodiment.

Figure 18 is a view showing the porosity versus a ratio of the pore radius to the inter-pore distance, according to one embodiment.

Figure 19 illustrates an interposer that includes one or more embodiments of the invention.

Figure 20 illustrates a computing device in accordance with one embodiment of the invention.

DETAILED DESCRIPTION

Methods and apparatuses to provide ordered porosity for an integrated circuit manufacturing are described. In one embodiment, a directed self-assembly (DSA) layer is deposited on one or more conductive features on an insulating layer on a substrate. The DSA layer comprises one or more first structures that are deposited on the insulating layer. One or more openings in the insulating layer are formed using the DSA layer as an etch mask to provide porosity for the insulating material. The one or more openings are self-aligned to the one or more conductive features.

Typically, to enable scaling of the dielectric material to the low k- value below 2.0, the dielectric material needs to have porosity greater than 40%. Conventional techniques to fabricate a porous dielectric material involve randomly mixing a back bone precursor with a porogen material that is selectively burned or etched out of the matrix.

At high loading volumes of the porogen material, however, there is no longer a continuous interconnected network of the back bone precursor molecules, so that upon burn or etch out of the porogen material, the dielectric material collapses.

Typically, the increased loading of porogen results in a maximum achievable porosity of 50 percent (%)-60%. At or near the maximum porosity, the mechanical strength of the dielectric material becomes too low to withstand typical processing conditions for a backend of line processing and assembly.

In one embodiment, increasing the porosity of an interlayer dielectric (ILD) material involves etching the ILD material using a DSA material as an etch mask to form pores in the ILD material between metal lines compatible with current metallization schemes. Each of the pores formed between the metal lines has a shape that extends along a vertical axis. In one

embodiment, the vertical pores formed in the ILD using the DSA material as a mask are self- aligned to metal lines extending along a horizontal axis. The vertical pores are formed in the ILD after a layer metallization is completed. Forming the vertical pores in the ILD layer that are self aligned along the horizontal axis to the metal lines, increases the porosity of the ILD material while maximizing the mechanical strength of the ILD material along the vertical axis.

In one embodiment, the DSA mask protects the post-chemical mechanical polishing (CMP) top surfaces of the metal layer, barrier layer, and nearby ILD material layer.

Embodiments of the DSA mask may provide a triple point protection, as the DSA mask may prevent degradation of the metal features, barrier layer and the ILD during the ILD etch. In one embodiment, etching of the pores in the ILD layer using the DSA material as a mask is controlled so that a small volume of ILD material remains on the barrier layer sidewalls after the etching.

As the pores in the ILD layer are etched after the metallization of the layer is complete, a metal patterning can be performed with a nonporous ILD that is substantially stronger than the porous ILD. As some portions of the ILD between the metal lines are removed, the capacitance between the metal lines is decreased. After forming the vertical pores, some portions of the ILD remain between the metal lines. The remaining portions of the ILD between the metal lines provide an additional mechanical strength that increases a shear modulus and protection against a via fatigue comparing with conventional air-gap or porous ILD techniques.

Some embodiments of methods and apparatuses to form ordered vertical pores using a DSA layer as described herein may avoid the need to mask the plug regions, which could reduce the manufacturing cost compared with techniques where plug regions are masked, such as some air gap techniques. The conventional air gap techniques would require removal of all ILD material between the metal lines. In contrast to the conventional techniques, the size of the removed portion of the ILD is constrained to the size determined by the DSA material and does not need to correspond to the size of the portion of the ILD, so that only a portion of the ILD material between the metal lines is removed. The introduction of a structural order to the highly porous films not only allows an extension of porosity beyond 50%-60%, but the resulting mechanical properties are significantly higher comparing with conventional materials with unstructured pore shapes. In one embodiment, ordered pore structures are formed in the ILD layer between metal lines. In one embodiment, each of the pore structures formed in the ILD layer has a cylindrical shape and extends along a vertical axis towards a substrate, as described in further detail below.

Vertical cylindrical porosity arrangements may deliver mechanical stiffness along the vertical axis (layer-to-layer) with a benefit along the transverse (metal line-to-metal line) axis as well. Because current manufacturing methods result in the largest mechanical stresses along the vertical axis (e.g., stresses induced during subsequent chemical mechanical polish (CMP), die/package assembly, and thermal changes) forming ordered vertically oriented pores in the ILD layer between the metal lines may deliver the benefit to mechanical stiffness in the vertical direction for a given porosity in some embodiments. In one embodiment, vertically oriented cylindrical pores self aligned in the middle of the ILD between the metal lines allow for even greater porosity values comparing with conventional techniques. In one embodiment, vertically oriented cylindrical pores self aligned in the middle of the ILD between the metal lines provide an option to leave the ILD wall right beside the metal line untouched, as described in further detail below.

In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations .

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention; however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

While certain exemplary embodiments are described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive, and that the embodiments are not restricted to the specific constructions and arrangements shown and described because modifications may occur to those ordinarily skilled in the art. Reference throughout the specification to "one embodiment", "another embodiment", or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearance of the phrases, such as "one embodiment" and "an embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Moreover, inventive aspects lie in less than all the features of a single disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment. While the exemplary embodiments have been described herein, those skilled in the art will recognize that these exemplary embodiments can be practiced with modification and alteration as described herein. The description is thus to be regarded as illustrative rather than limiting.

Figure 1 shows a side view 100 of a portion of an electronic device according to one embodiment. Figure 9 is a three-dimensional view 900 of the portion of the electronic device shown in Figure 1 according to one embodiment. A plurality of features, e.g., a feature 103 and a feature 104 are formed on an insulating layer 102 on a substrate 101.

In an embodiment, the substrate 101 comprises a semiconductor material, e.g., silicon (Si). In one embodiment, substrate 101 is a monocrystalline Si substrate. In another embodiment, substrate 101 is a poly crystalline silicon substrate. In another embodiment, substrate 101 represents a previous interconnect layer. In yet another embodiment, substrate 101 is an amorphous silicon substrate. In alternative embodiments, substrate 101 includes silicon, germanium ("Ge"), silicon germanium ("SiGe"), a III-V materials based material e.g., gallium arsenide ("GaAs"), or any combination thereof. In one embodiment, the substrate 101 includes metallization interconnect layers for integrated circuits. In at least some embodiments, the substrate 101 includes electronic devices, e.g., transistors, memories, capacitors, resistors, optoelectronic devices, switches, and any other active and passive electronic devices that are separated by an electrically insulating layer, for example, an interlayer dielectric, a trench insulation layer, or any other insulating layer known to one of ordinary skill in the art of the electronic device manufacturing. In at least some embodiments, the substrate 101 includes interconnects, for example, vias, configured to connect the metallization layers. In an embodiment, substrate 101 is a semiconductor-on-isolator (SOI) substrate including a bulk lower substrate, a middle insulation layer, and a top monocrystalline layer. The top monocrystalline layer may comprise any material listed above, e.g., silicon.

In various implementations, the substrate can be, e.g., an organic, a ceramic, a glass, or a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials.

Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) may be built falls within the spirit and scope of the present invention.

In one embodiment, insulating layer 102 is an interlay er dielectric (ILD) layer. In one embodiment, insulating layer 102 is a non porous insulating layer. In another embodiment, insulating layer 102 has porosity less than 10%. In one embodiment, insulating layer 102 is a solid high-k dielectric having a k value greater than 3.9. In one embodiment, insulating layer 102 is a solid low k dielectric layer that has a k value less or equal to 3.9. In one embodiment, insulating layer 102 is an oxide layer, e.g., a silicon oxide layer, a silicon dioxide, a carbon doped oxide ("CDO"), or any combination thereof. In another embodiment, insulating layer 102 is a nitride layer, e.g., silicon nitride layer. In alternative embodiments, insulating layer 102 includes a nitride, oxide, a polymer, phosphosilicate glass, fluorosilicate ("SiOF") glass, organosilicate glass ("SiOCH"), other metal oxide, or any combination thereof. In alternative embodiments, insulating layer 102 is an aluminum oxide, silicon oxide nitride, other metal oxide/nitride layer, any combination thereof, or other electrically insulating layer determined by an electronic device design.

In one embodiment, the thickness of the insulating layer 102 is determined by design. In one embodiment, the insulating layer 102 is deposited to the thickness from about 20 nanometers (nm) to about 2 microns (μιη). In an embodiment, insulating layer 102 is deposited on substrate 101 using one of deposition techniques, such as but not limited to a chemical vapour deposition ("CVD"), e.g., a plasma enhanced chemical vapour deposition ("PECVD"), a physical vapour deposition ("PVD"), molecular beam epitaxy ("MBE"), metalorganic chemical vapor deposition ("MOCVD"), atomic layer deposition ("ALD"), spin-on, or other deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

As shown in Figures 1 and 9, features 103 and 104 are formed in insulating layer 102. In one embodiment, the features 103 and 104 are conductive features. In alternative embodiments, the conductive features are conductive lines, conductive vias that connect to components in the 101 layer, trenches, or any combination thereof. In one embodiment, at least one of the conductive features, e.g., conductive feature 103 comprises a via 131 to connect to substrate 101. In one embodiment, the center-to-center distance between the conductive features (pitch) is less than about 100 nm. In one embodiment, a pitch 110 between the conductive features is from about 10 nanometers (nm) to about 80 nm. In more specific embodiment, pitch 110 is from about 20 nm to about 50 nm. In one embodiment, the conductive features are a part of an interconnect layer.

In one embodiment, the conductive features are formed using one of conductive feature forming techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the insulating layer 102 is patterned and etched to form openings (e.g., trenches, or other openings) using patterning and etching techniques known to one of ordinary skill in the art of microelectronic device manufacturing. One or more conductive layers, e.g., a conductive layer on a base layer are deposited to fill the openings in the insulating layer 102. One of chemical-mechanical polishing (CMP) techniques is used to remove the portions of the one or more conductive layers that extend above the top of the insulating layer 102. The portions of the one or more conductive layers deposited within the openings in the insulating layer 102 are not removed and become the patterned conductive features, such as conductive features 103 and 104. In one embodiment, the width of the conductive feature is less than about 40 nm. In one embodiment, the width of the conductive feature is in an approximate range of 5 nm to about 40 nm. In one embodiment, the height of the conductive features is less than about 65 nm. In one embodiment, the thickness of the conductive feature is in the approximate range of 8 nm to 65 nm.

In one embodiment, the base layer includes a conductive seed layer deposited on a conductive barrier, one or more liner layers, or both. In one embodiment, the seed layer includes copper (Cu). In another embodiment, the seed layer includes tungsten (W). In alternative embodiments, the seed layer is copper, titanium nitride, ruthenium, nickel, cobalt, tungsten, or any combination thereof. In more specific embodiment, the seed layer is copper. In one embodiment, the conductive barrier layer includes aluminum, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, cobalt, ruthenium, other metals, or any combination thereof. Generally, the conductive barrier layer is used to prevent diffusion of the conductive material from the seed layer into insulating layer 102, to provide adhesion for the seed layer, or both. In one embodiment, the base layer comprises the seed layer on the barrier layer that is deposited on the sidewalls and bottom of the openings in the insulating layer 102. In another embodiment, the base layer includes the seed layer that is directly deposited on the sidewalls and bottom of the openings in the insulating layer 102. Each of the conductive barrier layer and seed layer may be deposited using any thin film deposition technique known to one of ordinary skill in the art of semiconductor manufacturing, e.g., by sputtering, blanket deposition, and the like. In one embodiment, each of the conductive barrier layer and the seed layer has the thickness in the approximate range of 0.5 nanometers (nm) to 100 nm. In one embodiment, the barrier layer may be a thin dielectric that has been etched to establish conductivity to the metal layer below. In one embodiment, the barrier layer may be omitted altogether and appropriate doping of the copper line may be used to make a "self-forming barrier".

In one embodiment, the conductive layer of copper is deposited onto the seed layer of copper by an electroplating process. In another embodiment, the conductive layer is deposited onto the seed layer using one of selective deposition techniques known to one of ordinary skill in the art of semiconductor manufacturing, e.g., electroplating, electroless plating, or the like techniques. In one embodiment, the choice of a material for the conductive layer determines the choice of a material for the seed layer. For example, if the material for conductive layer includes copper, the material for the seed layer also includes copper. In one embodiment, conductive layer includes e.g., copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), aluminum (Al), hafnium (Hf), tantalum (Ta), tungsten (W), Vanadium (V), Molybdenum (Mo), palladium (Pd), gold (Au), silver (Au), platinum (Pt), silicon (Si) or any combination thereof.

In alternative embodiments, examples of the conductive materials that may be used for the conductive layer to form the conductive features include, but are not limited to, metals, e.g., copper, tantalum, tungsten, ruthenium, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof.

In one embodiment, the conductive features are formed by removing the portions of the conductive layer and the base layer outside the openings in the insulating layer 102. The portions of the conductive layer may be removed chemically, e.g., using etching, mechanically, e.g., using polishing, or by a combination of thereof techniques, e.g., using a chemical-mechanical polishing ("CMP") technique known to one of ordinary skill in the art of microelectronic device manufacturing.

In another embodiment, the features 103 and 104 comprise a sacrificial material (e.g., a fillable carbon hardmask, oxide, nitride, or sacrificial metal like titanium nitride or tungsten that has been deposited in the trenches in the insulating layer 102 in place of the conductive material to avoid damaging the conductive material later on in a process. In alternative embodiments, the sacrificial layer is deposited to fill the openings in the insulating layer 102 using one of the sacrificial layer deposition techniques e.g., , sputtering, blanket deposition, spin-on, or other deposition technique known to one of ordinary skill in the art of electronic device manufacturing. In one embodiment, one of chemical-mechanical polishing (CMP) techniques is used to remove the portions of the sacrificial layer that extend above the top of the insulating layer 102.

Figure 2 is a view 200 similar to Figure 1 after modifying a top surface of the one or more features on the insulating layer 102 using a brush layer 105 according to one embodiment. Figure 10 is a three-dimensional view 1000 of the portion of the electronic device shown in Figure 2 according to one embodiment. In some embodiments, the brush layer comprises a material that at some process conditions bonds to conductors and does not bond to the insulating layer. In some embodiments, the brush layer comprises a material that chemically bonds to conductors and does not bond to the insulating layer when annealed at a temperature greater than a room temperature. As shown in Figures 2 and 10, portions of the brush layer 105, e.g., a portion 201 and a portion 202 are deposited on the top surface of the features, e.g., features 103 and 104. The brush layer 105 is not deposited on the top surface of the insulating layer 102. In one embodiment, the material of the brush layer 105 is a DSA material. In one embodiment, brush layer 105 comprises a termination component coupled to a tail component. In one non- limiting exemplary embodiment, the termination component of the brush layer 105 is a thiol, phosphonate, acid, or any combination thereof. In one non-limiting exemplary embodiment, the termination component of the brush layer 105 is a thiol (-SH), phosphonic acid (-PO₃R₂, where R = H, CH₃, C₂H₅, etc), Hydroxyl (-OH), Carboxyl (-COOH) group, aldehyde (-COH) any derivatives thereof, or a any combination thereof. In one embodiment, the tail component of the brush layer 105 corresponds to the component of the DSA material that is deposited on the conductive features later on in a process. In one embodiment the tail component of the brush layer 105 is a polymethyl methacrylate (PMMA) material. In one embodiment, the tail component of the brush layer 105 is a polystyrene (PS) material. In other embodiments, other materials are used as the termination and tail components of the brush layer. In one embodiment, the thickness the brush layer 105 is from about 0.5 nm to about 5nm. In one embodiment, a liquid solution of the brush layer 105 including the terminal component and tail component is deposited on the top surface of the conductive features and insulating layer 102 using one of the spin-on coating techniques. After being deposited, the brush layer 105 is baked at a temperature greater than a room temperature to chemically bond to the conductive features. In one embodiment, the brush layer 105 is baked at a temperature in an approximate range from about 60 degrees C to about 200 degrees C. In one embodiment, the brush layer 105 is bound to the features 103 and 104 by the termination component. Brush layer

105 is not chemically bound to the insulating layer 102. The portions of the brush layer 105 that are outside of the features are removed using one or more rinsing techniques. In alternative embodiments, brush layer 105 is deposited using one of many deposition techniques, such as but not limited to a chemical vapour deposition ("CVD"), e.g., a plasma enhanced chemical vapour deposition ("PECVD"), a physical vapour deposition ("PVD"), molecular beam epitaxy

("MBE"), metalorganic chemical vapor deposition ("MOCVD"), atomic layer deposition ("ALD"), or other deposition techniques known to one of ordinary skill in the art of electronic device manufacturing.

Figure 3 is a view similar 300 similar to Figure 2 after a DSA layer 106 is deposited on the features on the insulating layer 102 according to one embodiment. Figure 11 is a three- dimensional view 1100 of the portion of the electronic device shown in Figure 3 according to one embodiment. In one embodiment, DSA layer 106 comprises a polymer chain. In one embodiment, DSA layer 106 is a diblock copolymer. As shown in Figures 3 and 10, DSA layer

106 comprises a first component (e.g., a component block 107) and a second component (e.g., a component block 111). In one embodiment, the first component is PMMA and the second component is PS. In another embodiment, the first component is PS and the second component is PMMA. In other embodiments, other materials are used as the first and second components of the DSA layer.

As shown in Figures 3 and 11, some portions of the first component, such as a portion 108, are deposited on the portions, such as portion 201 of brush layer 105 on the features 103 and 104. Some portions of the first component, e.g., a portion 109, are deposited on some portions of insulating layer 102 outside the features 103 and 104. The portions of the second component 111 are deposited on some other portions of the insulating layer 102 outside the features 103 and 104. The portions of the second component 111 comprise structures, e.g., a structure 112 and a structure 113. In one embodiment, the structures are vertical cylinders that extend along a vertical axis 301 from the top surface of the DSA layer 106 towards the substrate 101. In one embodiment, each of the structures 112 and 113 extending along vertical axis 301 has a predetermined shape (e.g., a circular, an ellipsoidal, an ovoidal, a triangular, a rectangular, a hexagonal, or other shape) in a plane parallel to the top surface of the DSA layer 106. As shown in Figure 3, each of the structures 112 and 113 has substantially parallel opposing sidewalls. As shown in Figure 3, a width 302 at the top portion of the structure 113 is substantially similar to a width 303 at the bottom portion of the structure 113. In one non-limiting example, the width of the structure 113 is less than about 100 nm. In one non- limiting example, the width of the structure 113 is in an approximate range from about 5 nm to about 50 nm. In more specific non- limiting example, the width of the structure 113 is from about 10 nm to about 30 nm.

In one embodiment, DSA layer 106 is baked at a temperature greater than a room temperature to self-organize the second component 111 into the structures, such as structures 112 and 113, so that the structures of the second component 111 are only on the portions of the insulating layer 102 outside the conductive features. In one embodiment, DSA layer 106 is baked at a temperature in an approximate range from about 100 degrees C to about 250 degrees C.

In one embodiment, the tail component of the brush layer 105 is of the same material as the first component of the DSA layer 106. That is, modifying the top surface of the conductive features by the DSA brush layer 105 forces the structures of the second component of the DSA layer 106 to self align between the features 103 and 104.

In one embodiment, a volume fraction of the first component, second component, or any combination thereof is adjusted to provide a predetermined structure to form the self- aligned ordered pores in the insulating layer 102 between the conductive features. In one embodiment, the DSA layer 106 comprises from 20% to about 40% of the volume of the second component and from about 60% to about 80% of the volume of the first component. In more specific embodiment, the DSA layer 106 comprises about 30% of the volume of the second component and about 70% of the volume of the first component.

In one embodiment, a pitch 1101 between the neighboring structures of the second component 111 of the DSA layer 106 is adjusted to correspond to the pitch 110 of the underlying features 103 and 104. In one embodiment, the pitch of the DSA layer structures pattern is greater than the pitch of the underlying features 103 and 104 by about 2 divided by the square root of 3 (e.g., 2x(3)^~°^'5 ~ 1.15). In one embodiment, the pitch 1101 is a function of a total length of the first component molecule and the second component molecule of the DSA material. In one embodiment, the total length of the first component and the second component molecules of the DSA material is adjusted based on the pitch of the underlying conductive pattern. In one embodiment, the molecular weight of at least one of the second component and the first component of the DSA material is adjusted to ensure that the structures of the second component of the DSA layer are generated on the portions of the insulating layer 102 between the conductive features.

In one embodiment, the thickness of the DSA layer 106 is such that the pitch between the structures of the second component of the DSA layer corresponds to the pitch between the conductive features on the insulating layer 102. In one embodiment, the DSA layer is thin enough so that substantially all structures of the second component of the DSA layer extend along vertical axis 301. In one embodiment, the thickness of the DSA layer 106 is from about 10 nm to about 80 nm. In more specific embodiment, the thickness of the DSA layer 106 is from about 30 nm to about 50 nm.

In one embodiment, a liquid solution comprising a DSA material is spin coated onto the top portions of the insulating layer 102 and on the brush layer 105. In alternative embodiments, the DSA layer 106 is deposited using other deposition techniques, such as but not limited to a chemical vapor deposition ("CVD"), e.g., a plasma enhanced chemical vapor deposition

("PECVD"), a physical vapor deposition ("PVD"), molecular beam epitaxy ("MBE"), metalorganic chemical vapor deposition ("MOCVD"), atomic layer deposition ("ALD"), or other deposition techniques known to one of ordinary skill in the art of electronic device

manufacturing.

Figure 4A is a view 400 similar to Figure 3 after the structures of the second component of the DSA layer 106 are selectively removed to form openings 114 and 115 to expose some of the top portions of the insulating layer 102 according to one embodiment. Figure 12 is a three- dimensional view 1200 of the portion of the electronic device shown in Figure 4 A according to one embodiment.

In one embodiment, the second component 111 of the DSA layer 106 has a substantially high etch selectivity to the first component 107 of the DSA layer 106. In one embodiment, the ratio between the etching rate of the second component 111 to the etching rate of the first component 07 is at least 8:1. As shown in Figures 4 A and 12, the portions of the first component of the DSA layer 106 remain on the features 103 and 104 and on some other top portions of the insulating layer 102. As shown in Figures 4A and 13 openings 114 and 115 extend through the thickness of the DSA layer 106 along vertical axis 301. In one embodiment, the shape of the openings 114 and 115 is similar to the shape of the structures 112 and 113. In one embodiment, each of the openings 114 and 115 extending along vertical axis 301 has a cylindrical shape. In one embodiment, each of the openings 114 and 115 extending along vertical axis 301 has a predetermined shape (e.g., a circular, an ellipsoidal, an ovoidal, a triangular, a rectangular, a hexagonal, or any other shape) in a plane parallel to the top surface of the DSA layer 106. As shown in Figure 4A, each of the openings 114 and 115 has substantially parallel opposing sidewalls. As shown in Figures 4A and 12, a width 401 at a top portion of the opening 115 is substantially similar to a width 402 at a bottom portion of the opening 115. In one embodiment, the width of each of the openings 114 and 115 is from about 5 nm to about 50 nm.

In one embodiment, the structures of the second component of the DSA layer 106 are selectively removed using one or more of wet etching, dry etching, or a combination thereof techniques known to one of ordinary skill in the art of electronic device manufacturing. In one embodiment, after the structures of the second component of the DSA layer 106 are selectively removed, the DSA layer 106 is cured at a temperature greater than a room temperature.

In one embodiment, the second component of the DSA layer 106 is a PMMA material and the first component of the DSA layer 106 is a PS material. In one embodiment, the PMMA structures of the DSA layer 106 are selectively removed using a deep ultraviolet (DUV) flood exposure (to scission the PMMA) followed by a selective wet etch (e.g., using an acetic acid, isopropyl alcohol, or other wet solution). The remaining PS component of the DSA layer is used as an etch mask to etch into the ILD layer 102.

Figure 4B is a view 410 similar to Figure 4B after portions of the first component of the DSA layer 106 are removed to increase a width of the openings in the DSA layer 106 according to one embodiment. As shown in Figure 4B, an opening 411 is wider than opening 115. An opening 415 is wider than opening 114. The first component of the DSA layer 106 is isotropically etched using, for example, an ashing technique, or a wet etch technique, to widen the openings in the DSA layer 106. In one embodiment, the first component of the DSA layer 106 is etched using a hydrogen based ashing technique. In another embodiment, the first component of the DSA layer 106 is etched using an oxygen based ashing technique.

As shown in Figure 4B, each of the openings 411 and 415 has substantially parallel opposing sidewalls. As shown in Figure 4B, the width at the top portion of the opening 411 is substantially similar to the width at the bottom portion of the opening 411. In one embodiment, the width of each of the openings 411 and 415is from about 5 nm to about 50. In some embodiments, the openings 411 and 415 have a tapering towards the bottom, as described in further detail below.

Figure 5 is a view 500 similar to one of Figures 4A or 4B after openings are formed in insulating layer 102 using the DSA layer as a mask and then removal of the DSA mask using an ash, dry etch, or wet chemical etch according to one embodiment. Figure 13 is a three- dimensional view 1300 of the portion of the electronic device shown in Figure 5 according to one embodiment. Figure 14 is a top view 1400 of a portion 1303 of the electronic device shown in Figure 13 according to one embodiment. Figure 15 is a cross-sectional view along a line A-A' of the portion 1303, according to one embodiment.

As shown in Figures 5, 13, 14 and 15 a plurality of openings (pores), e.g., pores 116 and 117, 1301 and 1302 are formed in insulating layer 102 outside the conductive features. As shown in Figures 5, 13 and 15, the pores are formed in the insulating layer 102 between the conductive features 103 and 104. The pores are not formed in the insulating layer 102 underneath the features 103 and 104. The pores are separated from the conductive features by small portions of remaining insulating material 102, e.g., portions 503 and 504. In one embodiment, the sizes of the portions of remaining insulating material 102 range from about 0.1 nm to about 20 nm. In more specific embodiment, the sizes of the portions remaining insulating material 102 range from about lnm to about 5 nm. In one embodiment, in the direction parallel to the conductive features, the pores 116, 117, 1301, and 1302 are separated from each other by portions of remaining insulating material 102 e.g., portions 1307 and 1308, as shown in Figures 13, 14, and 15. The first component of the DSA layer 106 along with the brush layer 201 and 202 are removed to expose the features (e.g., features 103 and 104) and portions of the insulating layer 102 outside the conductive features.

As shown in Figures 5, 13 and 15 each of the pores in the insulating layer 102 has a predetermined shape (e.g., a circular, an elliptical, and ovoidal, a triangular, a rectangular, a hexagonal, or other shape) in a plane parallel to the top surface of the insulating layer 102 and extends to a predetermined depth through the thickness of the insulating layer 102 along vertical axis 301. Figures 14 and 15 illustrate an example of an ordered porosity for the insulating layer 102 in the shape of vertical cylinders that are self-aligned to the metal lines. In one embodiment, the shape of the pores in the insulating layer 102 is similar to the shape of the openings 114 and 115 in the DSA layer. In another embodiment, the shape of the pores 116 and 117 is similar to the shape of the openings 415 and 411. In one embodiment, the pores in the insulating layer 102 have an elongated shape along the thickness of the insulating layer (e.g., along vertical axis 301). In one embodiment, the etch process generates some taper at the bottom of the pores. In one embodiment, the pores in the insulating layer 102 have a slightly conical bottom shape. In at least some embodiments, the width of the elongated pores vary with the depth, so that the width at the top portion of the pore is different from the width at the bottom portion of the pore. In one embodiment, the width at the top portion of the pore is greater than at the bottom portion of the pore. In another embodiment, the width at the top portion of the pore is smaller than at the bottom portion of the pore. In one embodiment, each of the pores in the insulating layer 102 has a shape that is similar to the shape of a vertically oriented cylinder. In one embodiment, each of the openings in the insulating layer 102 has substantially parallel opposing sidewalls. As shown in Figure 5, a width 501 at the top portion of the opening 117 is substantially similar to a width 502 at a bottom portion of the opening 117. In one embodiment, the width of each of the openings in the insulating layer 102 is from about 5 nm to about 50 nm.

As shown in Figure 13, the openings in the insulating layer 102, e.g., an opening 117 and an opening 1302 are self aligned to the conductive features 103 and 105 that extend along a horizontal axis 1306 in a plane that is parallel to the top surface of the insulating layer 102.

In one embodiment, a pitch 1304 between the openings 1301 and 1302 in the insulating layer is adjusted based on the pitch 110 between the features 103 and 104. In one embodiment, pitch 1304 of the openings layer is greater than the pitch 110 of the features by about 2 divided by the square root of 3 (e.g., 2x(3)^~°^'5 ~ 1.15). As shown in Figures 15 and 13, the depth of the openings in the insulating layer 102, e.g., a depth 1501 is similar to the thickness of the conductive features. In another embodiment, the depth of the openings in the insulating layer 102 is greater than the thickness of the conductive features. In yet another embodiment, the depth of the openings in the insulating layer 102 is smaller than the thickness of the conductive features.

In one embodiment, the openings in the insulating layer 102 are etched through the openings in the DSA layer 106 between the features 103 and 104 using one of dry etching techniques, e.g., a plasma etching technique, or other dry etching technique. In one embodiment, the openings in the insulating layer 102 between the features 103 and 104 are etched using a fluoride based plasma etch. In one embodiment, the openings in the insulating layer 102 between the features 103 and 104 are etched using a carbon fluoride (e.g., CF₄, CH₂F₂, CH₃F, C₄Fg, etc.) based plasma etch.

In one embodiment, after the openings in the insulating layer 106 are formed, the portions of the first component of the DSA layer 106 are removed. In one embodiment, the portions of the first component of the DSA layer 106 are removed using one of dry etching techniques, e.g., a plasma etching technique, a wet etching technique, or any combination thereof techniques.

While the location of the pores in the insulating layer 102 is determined by the pattern of the DSA layer 106, the width of the pores and hence the porosity can be adjusted with an additional etch of the portions of the first component of the DSA layer 106, as illustrated in Figure 4B. This etch can also determine the width of the pores into the insulating layer 102. Both the width and the depth of the pores contribute to porosity and hence capacitance between metal lines. Generally, as the width, the depth or both of the pores increase, the porosity of the insulating layer increases. In one embodiment, an upper portion of the insulating layer 102 comprises the pores that extend through a fraction of the thickness of the insulating layer 102, so that the underlying bottom portion of the insulating layer 102 is stronger and denser than the upper portion of the ILD layer.

In another embodiment, when the features 103 and 104 comprise the sacrificial material, the vertical pores 116 and 117 in the insulating layer 102 are filled with a fill material (e.g., a fillable carbon hardmask, oxide, nitride, or sacrificial metal like titanium nitride or tungsten) using one or more of the fill material deposition techniques, e.g., spin-on deposition, flowable chemical vapor deposition, or atomic layer deposition. The sacrificial material can be removed from the trenches in the insulating layer 102 using one or more of the sacrificial material removal techniques known to one of ordinary skill in the art of electronic device manufacturing, e.g., a dry etching, a wet etching, or both. In one embodiment, after the sacrificial material is removed, the trenches in the insulating layer 102 are filled with the conductive material to form the conductive features, as described above with respect to Figure 1.

As shown in Figures 5, 13, 14, and 15, the periodic vertical pores 116, 117, 1301 and 1302 are separated by portions (walls) of ILD between the metal lines 503 and 504 and from each other by portions (walls) of ILD material 1307 and 1308. These portions of remaining ILD material provide some benefits. First, this remaining ILD portions shunt some of the vertical stress away from the vias (to minimize a via fatigue). Secondly, these portions of the ILD provide an additional transverse mechanical strength and reduce the failure risk upon shear stresses. Third, in some embodiments, the remaining ILD 503 and 504 can provide additional dielectric stability to the edges of the metal lines. Third, the DSA mask provides protection of the metal and barrier during the ILD etch in at least some embodiments. In at least some embodiments, the addition of the sacrificial material, the possibility of etch while protecting the metal, or both means is used to produce the openings in the DSA mask that are larger than the spaces between the metal lines.. In one embodiment, the ordered holes in the ILD are not significantly wider than the half pitch between the conductive features. In this case, the DSA mask provides protection of the metal and barrier during the ILD etch. In other embodiments, for example when a sacrificial metal is used or when a barrier/metal system that are stable toward the ILD etch are used, the ordered holes of the DSA mask can be larger than the half pitch between the conductive features. In this embodiment, the overall porosity of the ILD between the metals lines can be increased beyond 34% porosity.

Figure 6 is a view 600 similar to Figure 5 after a patterned hard mask layer 121 on an insulating layer 119 on a capping layer 118 are deposited on the conductive features 103 and 104 in the insulating layer 102 according to one embodiment. As shown in Figure 6, capping layer 118 bridges over the openings 116 and 117. In one embodiment, capping layer 118 extends down into the openings 116 and 117 to a depth 601. In alternative embodiments, the depth 601 is from about 0 nm to about 20 nm. In more specific embodiment, the depth 601 is from about 3 nm to about 10 nm.

In one embodiment, the thickness of the capping layer 118 is from about 2 nm to about 20 nm. In one embodiment, the capping layer 118 is an etch stop layer. In one embodiment, the capping layer 118 is a silicon nitride, silicon carbide, or any combination thereof. In alternate embodiments, the capping layer 118 is an oxide layer, e.g., a silicon oxide layer, a carbon doped oxide layer, e.g., a carbon doped silicon oxide layer, a silicon oxy carbide (SiOC) layer, a fluorine-doped silicon oxide, a metal oxide, e.g., a titanium oxide, an aluminum oxide, a hafnium oxide, or any other metal oxide; a hydrogensilesquioxane (HSQ), a fluorinated amorphous carbon, a methylsesquioxane (MSQ), a nitride layer, e.g., a silicon nitride, a silicon oxide nitride, silicon carbide, or other capping layer.

As discussed above, to continue integration of subsequent upper layers in the integration scheme, the vertical ordered holes in the underlying ILD layer are capped with capping layer 118. In one embodiment, the vertical pores (holes) in the ILD layer 102 are filled with a sacrificial material (not shown) (e.g., a fillable carbon hardmask, oxide, nitride, or sacrificial metal like titanium nitride or tungsten). In one embodiment, the sacrificial material that fills the holes is recessed slightly below the metal features 103 and 104 using a CMP, an etching, or both. In one embodiment, a semi -porous screen layer (e.g., silicon nitride, silicon carbide, silicon oxycarbide, carbon-doped oxide, or combinations of the above having porosity values between 5-30% volume) is deposited on the recessed sacrificial material. In one embodiment, the sacrificial material is removed through the semi-porous screen layer using one of the sacrificial material removal techniques known to one of ordinary skill in the art. In one embodiment, after the removal of the sacrificial material, the semi-porous screen is converted to a nonporous capping layer, such as capping layer 118 using any pore-filling strategy such as PECVD deposition, ALD deposition, or spin coating.

In one embodiment, capping layer 118 is deposited using one of deposition techniques, such as but not limited to a spin-on, a chemical vapour deposition ("CVD"), e.g., a plasma enhanced chemical vapour deposition ("PECVD"), a physical vapour deposition ("PVD"), molecular beam epitaxy ("MBE"), metalorganic chemical vapor deposition ("MOCVD"), atomic layer deposition ("ALD"), or other deposition techniques known to one of ordinary skill in the art of electronic device manufacturing. An insulating layer 119 is deposited on capping layer 118, as shown in Figure 6. In one embodiment, insulating layer 119 is one of the insulating layers, as described above with respect insulating layer 102 depicted in Figure 1. In one embodiment, insulating layer 119 is deposited using one or more of the insulating layer deposition techniques, as described above with respect insulating layer 102 depicted in Figure 1. In one embodiment, insulating layer 119 is a part of a next interconnect layer. A patterned hard mask layer 121 is deposited on insulating layer 119 to form a next interconnect layer. Patterned hard mask layer 121 exposes portions of the insulating layer 119. In one embodiment, hard mask layer 121 is a nitride layer, e.g., a silicon nitride, a silicon oxide nitride, a carbon layer, other hard mask layer, or any combination thereof. The patterned mask layer 121 can be formed using one of the hard mask layer deposition and patterning techniques known to one of ordinary skill in the art of electronic device manufacturing.

Figure 7 is a view 700 similar to Figure 6 after the exposed portions of the insulating layer 102 are removed to form an opening 122 according to one embodiment. As shown in Figure 7, opening 122 is formed down to conductive feature 104. In one embodiment, opening 122 comprises a trench region 701 and a via region 702. In one embodiment, the exposed portions of the insulating layer 102 are removed using one or more etching techniques e.g., a dry etching, a wet etching, or both techniques known to one of ordinary skill in the art of electronic device manufacturing. In one embodiment, hard mask layer 121 is removed using one or more of the hard mask layer removal techniques known to one of ordinary skill in the art of electronic device manufacturing. In one embodiment, hard mask layer 121 is removed using an ashing technique.

Figure 8 is a view 800 similar to Figure 7 after conductive layer 123 is deposited into opening 122 according to one embodiment. As shown in Figure 8, conductive layer 122 fills opening 122 to form a conductive via to conductive feature 104. In one embodiment, the conductive layer 122 is deposited using one of conductive layer deposition techniques known to one of ordinary skill in the art of semiconductor manufacturing, e.g., electroplating, electroless plating, or other conductive layer deposition techniques. In one embodiment, conductive layer 122 is one of the conductive layers, as described above with respect to Figure 1.

Figure 16 is a view of a top-down scanning electron microscope (SEM) image 1600 showing a self-aligned DSA mask on an insulating layer according to one embodiment. As shown in image 1600, metal lines, e.g., metal lines 1601, 1602 and 1603 are deposited on an ILD layer 1605. The DSA mask comprises a plurality of openings, such as an opening 1604 and an opening 1606 that are centered over portions of an ILD layer 1605. The DSA mask does not have openings over the metal lines, as shown in Figure 16. The openings 1604 and 1606 are centered over the portions of the ILD layer 1605 between the metal lines 1601 and 1602, as shown in Figure 16. The openings 1604 and 1606 are arranged substantially parallel to the metal lines 1601 and 1602, as shown in Figure 16. ILD layer 1605 has plug regions, such as a plug region 1606 . The plug regionsare the ILD regions that do not have metal lines. In these regions, the DSA mask still produces periodic openings, such as an opening 1607. The dielectric materials below the DSA mask is etched to include a similar plurality of ordered pores as those in the ILD layer between conductive features as described above. Due to the absence of the metal lines in these plug regions, the overall porosity is about a fraction of 2 lower than the overall porosity between the metal lines. The DSA mask provides an additional benefit relative to conventional airgap processing, wherein all ILD of the plug regions are completely etched and provide challenges for the processing of the hardmask layer 118 described above. Typically, the plug regions are masked from air-gap etch and this requires another expensive lithography step. In at least some embodiments, the DSA mask only allows for the creation of etched ILD holes in the plug region similar to the between the conductive features. The challenges of integrating hard mask layer 118 are similar in both the plug and non-plug region and therefore do not require the additional lithography step.

Figure 17 is a view 1700 showing a graph 1701 of a Young's modulus versus a porosity for various ILD films according to one embodiment. Generally, the Young's modulus is a parameter associated with a mechanical strength (or stiffness) of the material. The Young's modulus defines a relationship between a stress (force per unit area) and strain (proportional deformation) in the material. As shown in the graph 1701, for conventional films 1 (a curve 1702) and 2 (a curve 1703) the modulus decreases rapidly as the porosity increases and when the pores do not have a controlled shape or network of interconnection.

Data 1704 are generated for conventional film 2 using a Finite Element Modeling (FEM) technique when porosity and pore-size distributions are used as experimental inputs. The data 1704 accurately fit the curve 1703 for conventional film 2. Data 1705 and data 1706 are generated using FEM modeling for a non-porous ILD film that is processed to provide the controlled vertical cylindrical porosity, as described above. The FEM data 1705 show that the modulus of the film having the ordered vertical porosity substantially increases, e.g., from about three times (3X) to about seven times (7X) depending on porosity, along the longitudinal (vertical) axis of the cylinder pores. The FEM data 1706 show that the modulus of the film having the ordered vertical porosity increases by about two times (~2X) along the transverse axis of the cylinder pores. That is, the mechanical stiffness in both longitudinal and transverse directions of the ILD film having vertically ordered porosity is substantially larger than that of the conventional films. The Young modulus of the ILD films having vertically ordered pores as described herein increases up to about 7 times in the vertical direction that determines the ILD mechanical integrity during integration, assembly, and thermal stresses.Figure 18 is a view 1800 showing the porosity versus a relative radius of the pores according to one embodiment. A curve 1801 shows the porosity calculated for all ranges of pore sizes. In the graph, R is the radius of the vertical hole in the DSA (e.g., half of the distance 401,402) that corresponds to the size and shape of the hold cut into the ILD. Pm is the pitch of the metal interconnect (e.g., pitch 110). In the graph, the ILD porosity refers to the porous volume of the space between the metal lines. Insert "a" illustrates the metal lines deposited on the insulating layer (the radius of pores is zero). For regions of the curve 1801 between a and c, the pores are sufficiently small and are constrained entirely within the ILD between the metal lines (as illustrated in insert b). When the pores have substantially the same width as the space between the metal lines (as illustrated by insert "c"), the porosity is about 34%. As shown in Figure 4B, the radius of the DSA mask can be increased by an etch or an ash. If the metal can tolerate the ILD etch, a replacement

(sacrificial) metal is used, or both, then the structures shown in inserts d, e, and f are possible. These structures are generated using the DSA masks to produce the holes in the insulating layer that are wider than the spacing between metal lines. The metal lines block the etch when the ILD material is etched so that resulting the structures shown in inserts d, e, and f are produced.

A curve 1801 shows that the porosity can be controlled by tuning the radius of the vertical pores, as described above with respect to Figures 4A and 4B. The curve 1801 is calculated based on the DSA mask on a blanket ILD film. As the metal lines under the DSA masked regions typically take up about 50% of the ILD space, the porosity will increase in the areas of the ILD between the metal lines.

Curve 1801 shows the calculated porosity that can be achieved by varying the radius of the cylinder r relative to the cylinder pitch P (r/P) for a flat ILD surface without metal lines present according to one embodiment. In one embodiment, a DSA mask provides the ordered porosity in a porosity range given by a box 1802. In one embodiment, when the DSA mask aligns to an underlying metal trench pattern, the resulting porosity of the ILD between the metal lines etched by the DSA mask is geometrically increased in an approximate range from about 20 % to about 45% of total porosity. In one embodiment, the porosity between the metal lines is further increased to a range corresponding to a box 1803 by radially increasing the holes in the ILD through a longer etch or an ash process, as described above with respect to Figure 4B. In one embodiment, the maximum porosity of the ILD between the metal lines is about 34% when the diameter of the cylindrical hole matches the space between the metal lines. In one embodiment, the radius of the holes in the DSA mask is further increased such that some of the metals lines are exposed at the bottom of the DSA mask to increase the porosity between the metal lines.

Figure 19 illustrates an interposer 1900 that includes one or more embodiments of the invention. The interposer 1900 is an intervening substrate used to bridge a first substrate 1902 to a second substrate 1904. The first substrate 1902 may be, for instance, an integrated circuit die. The second substrate 1904 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 1900 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 1900 may couple an integrated circuit die to a ball grid array (BGA) 1906 that can subsequently be coupled to the second substrate 1904. In some embodiments, the first and second substrates 1902/1904 are attached to opposing sides of the interposer 1900. In other embodiments, the first and second substrates 1902/1904 are attached to the same side of the interposer 1900. And in further embodiments, three or more substrates are interconnected by way of the interposer 1900.

The interposer 1900 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include vias 1910, including but not limited to through-silicon vias

(TSVs) 1912, metal interconnects 1908 having an ordered porosity in an insulating layer, as described above. The interposer 1900 may further include embedded devices 1914, including passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1900. In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer 1900.

In one embodiment, an electronic device comprises a plurality of metal layers on a substrate. At least one of the metal layers of the electronic device has conductive features and pores in the insulating layer that are in a regular arrangement relative to at least one of the conductive features, as described with respect to Figures 5, 13, 14 and 15. At least one of the metal layers of the electronic device comprises conductive features and an air gap in the nonporous insulating layer. In another embodiment, each of the metal layers of the electronic device has conductive features and pores in the insulating layer that are in a regular arrangement relative to at least one of the conductive features, as described with respect to Figures 5, 13, 14 and 15.

Figure 20 illustrates a computing device 2000 in accordance with one embodiment of the invention. The computing device 2000 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a motherboard. The components in the computing device 2000 include, but are not limited to, an integrated circuit die 2002 and at least one communication chip 2008. In some implementations the communication chip 2008 is fabricated as part of the integrated circuit die 2002. The integrated circuit die 2002 may include a processor 2004 such as a central processing unit (CPU), an on-die memory 2006, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STTM-RAM).

Computing device 2000 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, a volatile memory 2010 (e.g., DRAM), a nonvolatile memory 2012 (e.g., ROM or flash memory), a graphics processing unit 2014 (GPU), a digital signal processor 2016 (DSP), a crypto processor 2042 (a specialized processor that executes cryptographic algorithms within hardware), a chipset 2020, an antenna 2022, a display or a touchscreen display 2024, a touchscreen display controller 2026, a battery 2028 or other power source, a global positioning system (GPS) device 2044, a power amplifier (PA), a compass, a motion coprocessor or sensors 2032 (that may include an accelerometer, a gyroscope, and a compass), a speaker 2034, a camera 2036, user input devices 2038 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 2040 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 2008 enables wireless communications for the transfer of data to and from the computing device 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 2008 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 2000 may include a plurality of communication chips 2008. For instance, a first communication chip 2008 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 2008 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. One or more components e.g., integrated circuit die 2002, communication chip 2008, GPU 2014, cryptoprocessor 2042, DSP 2016, chipset 2020, and other components may include the ordered porosity formed in accordance with embodiments of the invention. In further embodiments, another component housed within the computing device 2000 may contain the ordered porosity formed in accordance with embodiments of the invention.

In various embodiments, the computing device 2000 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 2000 may be any other electronic device that processes data.

The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

The following examples pertain to further embodiments:

In one embodiment, a method to manufacture an electronic device comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising one or more first structures deposited on the insulating layer, and forming one or more openings in the insulating layer using the DSA layer as a mask, wherein the one or more openings are self-aligned to the one or more conductive features.

In one embodiment, a method to manufacture an electronic device comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising one or more first structures deposited on the insulating layer, removing the one or more first structures, and forming one or more openings in the insulating layer using the DSA layer as a mask, wherein the one or more openings are self- aligned to the one or more conductive features.

In one embodiment, a method to manufacture an electronic device comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising one or more first structures deposited on the insulating layer, and forming one or more openings in the insulating layer using the DSA layer as a mask, wherein the one or more openings are self-aligned to the one or more conductive features, and wherein at least one of the one or more openings extends along a first axis towards the substrate.

In one embodiment, a method to manufacture an electronic device comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising one or more first structures deposited on the insulating layer, and forming one or more openings in the insulating layer using the DSA layer as a mask, wherein the one or more openings are self-aligned to the one or more conductive features, and wherein the width at a top portion of at least one of the openings is substantially similar to the width at a bottom portion of the at least one of the openings.

In one embodiment, a method to manufacture an electronic device comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising one or more first structures deposited on the insulating layer, and forming one or more openings in the insulating layer using the DSA layer as a mask, wherein the one or more openings are self-aligned to the one or more conductive features, and wherein at least one of the one or more first structures has a cylindrical shape.

In one embodiment, a method to manufacture an electronic device comprises depositing an insulating layer on a substrate; depositing one more conductive features on the insulating layer; depositing a directed self-assembly (DSA) layer on the one or more conductive features on the insulating layer on a substrate, the DSA layer comprising one or more first structures deposited on the insulating layer, and forming one or more openings in the insulating layer using the DSA layer as a mask, wherein the one or more openings are self-aligned to the one or more conductive features.

In one embodiment, a method to manufacture an electronic device comprises depositing a brush layer on one or more conductive features on an insulating layer on a substrate; depositing a directed self-assembly (DSA) layer on the one or more conductive features, the DSA layer comprising one or more first structures deposited on the insulating layer,; and forming one or more openings in the insulating layer using the DSA layer as a mask, wherein the one or more openings are self-aligned to the one or more conductive features.

In one embodiment, a method to provide an ordered porosity comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on the one or more conductive features, a second portion of the first component is deposited on one or more first portions the insulating layer and wherein the second component is deposited on one or more second portions of the insulating layer; removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more second openings in the insulating layer through the one or more first openings.

In one embodiment, a method to provide an ordered porosity comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on the one or more conductive features, a second portion of the first component is deposited on one or more first portions the insulating layer and wherein the second component is deposited on one or more second portions of the insulating layer; removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more second openings in the insulating layer through the one or more first openings, wherein the one or more second openings are self-aligned to the one or more conductive features

In one embodiment, a method to provide an ordered porosity comprises depositing a brush layer on one or more conductive features on an insulating layer on a substrate; depositing a directed self-assembly (DSA) layer over the one or more conductive features, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on the brush layer on the one or more conductive features, a second portion of the first component is deposited on one or more first portions the insulating layer and wherein the second component is deposited on one or more second portions of the insulating layer; removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more second openings in the insulating layer through the one or more first openings.

In one embodiment, a method to provide an ordered porosity comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on the one or more conductive features, a second portion of the first component is deposited on one or more first portions the insulating layer and wherein the second component is deposited on one or more second portions of the insulating layer; removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more second openings in the insulating layer through the one or more first openings, wherein at least one of the second openings extends along a first axis towards the substrate.

In one embodiment, a method to provide an ordered porosity comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on the one or more conductive features, a second portion of the first component is deposited on one or more first portions the insulating layer and wherein the second component is deposited on one or more second portions of the insulating layer; removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more second openings in the insulating layer through the one or more first openings, wherein the width at a top portion of at least one of the second openings is substantially similar to the width at a bottom portion of the at least one of the second openings.

In one embodiment, a method to provide an ordered porosity comprises depositing an insulating layer on a substrate; depositing one or more conductive features on the insulating layer; depositing a directed self-assembly (DSA) layer on the one or more conductive features on the insulating layer, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on the one or more conductive features, a second portion of the first component is deposited on one or more first portions the insulating layer and wherein the second component is deposited on one or more second portions of the insulating layer; removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more second openings in the insulating layer through the one or more first openings. In one embodiment, a method to provide an ordered porosity comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on the one or more conductive features, a second portion of the first component is deposited on one or more first portions the insulating layer and wherein the second component is deposited on one or more second portions of the insulating layer; removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more second openings in the insulating layer through the one or more first openings, wherein the second component comprises one or more structures having a predetermined shape.

In one embodiment, a method to provide an ordered porosity comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on the one or more conductive features, a second portion of the first component is deposited on one or more first portions the insulating layer and wherein the second component is deposited on one or more second portions of the insulating layer; annealing the DSA layer; removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more second openings in the insulating layer through the one or more first openings.

In one embodiment, a method to provide an ordered porosity comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on the one or more conductive features, a second portion of the first component is deposited on one or more first portions the insulating layer and wherein the second component is deposited on one or more second portions of the insulating layer; removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more second openings in the insulating layer through the one or more first openings, wherein the depth of at least one of the second openings is similar or greater than the thickness of the one or more conductive features.

In one embodiment, a method to provide an ordered porosity comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on the one or more conductive features, a second portion of the first component is deposited on one or more first portions the insulating layer and wherein the second component is deposited on one or more second portions of the insulating layer; removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more second openings in the insulating layer through the one or more first openings, wherein removing the second component comprises selectively etching the second component.

In one embodiment, a method to provide an ordered porosity comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on the one or more conductive features, a second portion of the first component is deposited on one or more first portions the insulating layer and wherein the second component is deposited on one or more second portions of the insulating layer; removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more second openings in the insulating layer through the one or more first openings, wherein the one or more second openings are etched using a dry etching.

In one embodiment, a method to provide an ordered porosity comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on the one or more conductive features, a second portion of the first component is deposited on one or more first portions the insulating layer and wherein the second component is deposited on one or more second portions of the insulating layer; removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more second openings in the insulating layer through the one or more first openings; and etching the second portion of the first component; and etching the second portion of the first component.

In one embodiment, a method to provide an ordered porosity comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on the one or more conductive features, a second portion of the first component is deposited on one or more first portions the insulating layer and wherein the second component is deposited on one or more second portions of the insulating layer; removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more second openings in the insulating layer through the one or more first openings, wherein a distance between the portions of the second component is adjusted based on a distance between the conductive features.

In one embodiment, a method to provide an ordered porosity comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on the one or more conductive features, a second portion of the first component is deposited on one or more first portions the insulating layer and wherein the second component is deposited on one or more second portions of the insulating layer; removing one or more portions of the second component to form one or more first openings in the DSA layer; forming one or more second openings in the insulating layer through the one or more first openings; depositing a capping layer over the one or more second openings; and forming an interconnect layer over the capping layer.

In one embodiment, a method to provide an ordered porosity comprises depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on the one or more conductive features, a second portion of the first component is deposited on one or more first portions the insulating layer and wherein the second component is deposited on one or more second portions of the insulating layer; removing one or more portions of the second component to form one or more first openings in the DSA layer; and forming one or more second openings in the insulating layer through the one or more first openings, wherein the one or more conductive features are conductive lines.

In one embodiment, an electronic device comprises one or more conductive features on an insulating layer on a substrate, and a plurality of openings in the insulating layer self-aligned to the one or more conductive features.

In one embodiment, an electronic device comprises one or more conductive features on an insulating layer on a substrate, and a plurality of openings in the insulating layer self-aligned to the one or more conductive features, wherein at least one of the one or more openings extends along a first axis towards the substrate.

In one embodiment, an electronic device comprises one or more conductive features on an insulating layer on a substrate, and a plurality of openings in the insulating layer self-aligned to the one or more conductive features, wherein the width at a top portion of at least one of the openings is substantially similar to the width at a bottom portion of the at least one of the openings. In one embodiment, an electronic device comprises one or more conductive features on an insulating layer on a substrate, and a plurality of openings in the insulating layer self-aligned to the one or more conductive features, wherein at least one of the one or more openings has a cylindrical shape.

In one embodiment, an electronic device comprises one or more conductive features on an insulating layer on a substrate, and a plurality of openings in the insulating layer self-aligned to the one or more conductive features, wherein a distance between the openings is adjusted based on a distance between the conductive features.

In one embodiment, an electronic device comprises one or more conductive features on an insulating layer on a substrate, a plurality of openings in the insulating layer self-aligned to the one or more conductive features, a capping layer over the one or more openings, and an interconnect layer over the capping layer.

In one embodiment, an electronic device comprises one or more conductive features on an insulating layer on a substrate, and a plurality of openings in the insulating layer self-aligned to the one or more conductive features, wherein the one or more conductive features are conductive lines.

In one embodiment, an electronic device comprises one or more conductive features on an insulating layer on a substrate, and a plurality of openings in the insulating layer self-aligned to the one or more conductive features, wherein the width of at least one of the openings is from 5 nanometers to 50 nanometers.

In one embodiment, an electronic device comprises one or more conductive features on an insulating layer on a substrate, and a plurality of openings in the insulating layer self-aligned to the one or more conductive features, wherein the depth of at least one of the openings is similar or greater than the thickness of the one or more conductive features.

In the foregoing specification, methods and apparatuses have been described with reference to specific exemplary embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of embodiments as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

CLAIMS What is claimed is:

1. A method to manufacture an electronic device, comprising:

depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising one or more first structures deposited on the insulating layer;

forming one or more openings in the insulating layer using the DSA layer as a mask, wherein the one or more openings are self-aligned to the one or more conductive features.

2. The method of claim 1, further comprising

removing the one or more first structures.

3. The method of claim 1, wherein at least one of the one or more openings extends along a first axis towards the substrate.

4. The method of claim 1, wherein the width of at least one of the openings is larger than the space between the conductive features.

5. The method of claim 1, wherein at least one of the one or more openings has an elongated shape.

6. The method of claim 1, further comprising

depositing the insulating layer on the substrate;

depositing the one more conductive features within the insulating layer;

7. The method of claim 1, further comprising

depositing a brush layer on the one or more conductive features.

8. A method to provide an ordered porosity, comprising:

depositing a directed self-assembly (DSA) layer on one or more conductive features on an insulating layer on a substrate, the DSA layer comprising a first component and a second component, wherein a first portion of the first component is deposited on the one or more conductive features, a second portion of the first component is deposited on one or more first portions the insulating layer and wherein the second component is deposited on one or more second portions of the insulating layer;

removing one or more portions of the second component to form one or more first openings in the DSA layer; and

forming one or more second openings in the insulating layer through the one or more first openings.

9. The method of claim 8, wherein the one or more second openings are self-aligned to the one or more conductive features

10. The method of claim 8, further comprising

depositing a brush layer on the one or more conductive features, wherein the first portion is deposited on the brush layer.

11. The method of claim 8, wherein at least one of the second openings extends along a first axis towards the substrate.

12. The method of claim 8, wherein the second component comprises one or more structures having a predetermined shape.

13. The method of claim 8, further comprising

depositing the insulating layer on the substrate; and

depositing one or more conductive features on the insulating layer.

14. The method of claim 8, further comprising

annealing the DSA layer.

15. The method of claim 8, further comprising

etching the second portion of the first component.

16. The method of claim 8, wherein a distance between the portions of the second component is adjusted based on a distance between the conductive features.

17. The method of claim 8, further comprising

depositing a capping layer over the one or more second openings; and

forming an interconnect layer over the capping layer.

18. An electronic device comprising:

one or more first conductive features on a first insulating layer on a substrate; and a plurality of openings in the first insulating layer that are in a regular arrangement relative to the one or more conductive features.

19. The electronic device of claim 18, wherein the regular arrangement includes at least two of the plurality of openings that are aligned to at least one of the first conductive features that extends along a top surface of the first insulating layer.

20. The electronic device of claim 18, wherein the regular arrangement includes at least two of the plurality of openings that are between at least two of the first conductive features.

21. The electronic device of claim 18, further comprising

one or more second conductive features on a second insulating layer coupled to the first conductive features; and

an air gap in the second insulating layer.

22. The electronic device of claim 18, wherein at least one of the one or more openings extends along a first axis towards the substrate.

23. The electronic device of claim 18, wherein the width of at least one of the openings is larger than the space between the conductive features.

24. The electronic device of claim 18, wherein at least one of the one or more openings has a cylindrical shape.

25. The electronic device of claim 18, wherein a distance between the openings is adjusted based on a distance between the first conductive features.

26. The electronic device of claim 18, further comprising

a capping layer over the one or more openings; and

an interconnect layer over the capping layer.

27. The electronic device of claim 18, wherein the one or more first conductive features are conductive lines.

28. The electronic device of claim 18, wherein the depth of at least one of the openings is similar or greater than the thickness of the one or more first conductive features.