WO2017036041A1

WO2017036041A1 - Data synchronous access method and synchronous access device

Info

Publication number: WO2017036041A1
Application number: PCT/CN2015/099893
Authority: WO
Inventors: 易鸿斌
Original assignee: 安一恒通（北京）科技有限公司
Priority date: 2015-08-31
Filing date: 2015-12-30
Publication date: 2017-03-09
Also published as: CN105159766A; CN105159766B

Abstract

A data synchronous access method (100) and a synchronous access device. The data synchronous access method (100) comprises the following steps: allocating a continuous memory unit to data to be synchronously accessed (110), the data digit of the continuous memory unit being a sum of the data digits of all pieces of data to be synchronously accessed; dividing an atomic operation instruction into data segments corresponding to the amount of the data to be synchronously accessed according to the amount of the data to be synchronously accessed and the data digit of each piece of data to be synchronously accessed, (120), the digit of each data segment being greater than or equal to the digit of the corresponding data to be synchronously accessed; and accessing the data to be synchronously accessed within an instruction period (130), the instruction period being a duration for executing the atomic operation instruction. By means of the method and the apparatus, multiple pieces of data having an association relationship can be synchronously accessed in the same atomic operation instruction period, thereby improving the data access efficiency and accordingly quickening the data processing speed of a computer.

Description

Synchronous access method of data and synchronous access device

Cross-reference to related applications

The present application claims priority to Chinese Patent Application No. 201510548924.X filed on Aug. 31, 2015, the entire content of which is incorporated herein in its entirety.

Technical field

The present disclosure relates generally to computer technology, and more particularly to data access technologies, and more particularly to a method for synchronous access of data and a synchronous access device.

Background technique

In the prior art, data is located somewhere in the storage area, and each data corresponds to a synchronization object for synchronization.

In the synchronous access of the shared and variable data, the synchronization object corresponding to the setting data is in a no-signal state, and the data is accessed through the atomic operation instruction, and if the value of the data satisfies the pre-specified correspondence, the corresponding synchronization object is set as There is a signal state.

When the synchronous access to the associated data exists, the synchronization object corresponding to all other data is waited for the signal state, and the data is accessed through the atomic operation instruction.

However, the existing synchronous access method needs to wait for a synchronization object for synchronous access of data having an association relationship, which affects efficiency. In addition, this method is not available when the processor's interrupt request level is above the thread scheduling level.

Summary of the invention

In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a synchronous access method and a synchronous access device for data, which can synchronously access data of multiple associated relationships in the same atomic operation instruction cycle, thereby improving data access. Efficiency, which speeds up the processing of computer data.

In a first aspect, an embodiment of the present application provides a method for synchronously accessing data, including: allocating a contiguous memory unit to data to be accessed synchronously, wherein a data bit of the contiguous memory unit is a data bit of data to be synchronously accessed. The sum of the numbers; based on the number of data to be accessed synchronously and the number of data bits of each data to be synchronously accessed, the atomic operation instruction is divided into data segments corresponding to the number of data to be synchronously accessed, wherein the bits of each data segment The number is greater than or equal to the number of bits of data to be accessed synchronously corresponding thereto; and accessing data to be accessed synchronously in one instruction cycle, wherein the instruction cycle is the duration of execution of the atomic operation instruction.

In a second aspect, the embodiment of the present application further provides a data synchronization access device, including: an allocation module, configured to allocate a contiguous memory unit to data to be accessed synchronously, wherein the data bits of the contiguous memory unit are data The sum of the data bits; the dividing module configured to divide the atomic operation instruction into data corresponding to the number of data to be synchronously accessed based on the number of data to be accessed synchronously and the number of data bits of each data to be synchronously accessed a segment, wherein the number of bits of each data segment is greater than or equal to a corresponding number of bits of data to be accessed synchronously; and an access module configured to access data to be accessed synchronously within one instruction cycle, wherein the instruction cycle The length of time to execute an atomic operation instruction.

The solution provided by the embodiment of the present application can simultaneously access multiple data in one atomic operation instruction cycle, thereby improving the efficiency of data reading and writing.

In addition, synchronous access of data under the premise that the total number of bits of data is less than or equal to the number of atomic operation instructions can avoid modification of data by other threads, and ensure the correctness of the relationship between the data.

In some implementations of the embodiments of the present application, the association relationship between the data may also be determined by an atomic operation instruction.

DRAWINGS

Other features, objects, and advantages of the present application will become more apparent from the detailed description of the accompanying drawings.

FIG. 1 is a schematic flowchart of a method for synchronous access of data according to an embodiment of the present application;

2 shows, in FIG. 1, the atomic operation instruction is divided into data to be accessed synchronously based on the number of data to be synchronously accessed and the number of data bits of data to be synchronously accessed. Schematic flow chart of the data segment corresponding to the quantity;

FIG. 3 is a schematic diagram of an application scenario of a method for synchronous access of data according to an embodiment of the present application;

FIG. 4 shows a schematic structural diagram of a synchronous access device for data according to an embodiment of the present application.

detailed description

The present application will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention, rather than the invention. It should also be noted that, for the convenience of description, only parts related to the invention are shown in the drawings.

It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 1, a schematic flowchart 100 of a method for synchronous access of data according to an embodiment of the present application is shown.

Specifically, in step 110, contiguous memory locations are allocated to the data to be accessed synchronously. The data bit number of the contiguous memory unit is the sum of the data bits of the data to be accessed synchronously.

Memory allocation refers to the operation of allocating or reclaiming storage space during program execution. The continuous allocation of memory refers to allocating a contiguous memory space for a user program. The continuous allocation of memory includes a single continuous allocation, fixed partition allocation, and dynamic partition allocation.

In this embodiment, by allocating a contiguous memory unit to the data, it is possible to facilitate quick and efficient access to each data in subsequent steps, thereby improving processing efficiency.

In some optional implementations, for example, there are four data to be accessed synchronously, and each data to be accessed synchronously includes 16 bits. Then, when allocating contiguous memory cells to these data, a 64-bit contiguous memory cell (16×4) can be allocated for storing the data to be accessed synchronously.

Next, in step 120, based on the number of data to be synchronously accessed and the number of data bits of each data to be synchronously accessed, the atomic operation instruction is divided into data segments corresponding to the number of data to be synchronously accessed, wherein each data The number of bits in the segment is greater than or equal to the number of bits of data to be accessed synchronously.

An atomic operation is an operation that cannot be interrupted, or an operation that is not interrupted by the thread scheduling mechanism. There is no context switch during the operation.

In this way, when the data to be synchronously accessed is accessed by the atomic operation instruction, the access is not interrupted by other threads, that is, the data stored in the memory unit before the execution of the atomic operation instruction instruction is completed. The value will not be changed by other threads.

Similarly, with a total of four data to be accessed synchronously, each data to be accessed synchronously includes 16 bits for explanation. In order to perform parallel access to the four data to be accessed synchronously, the atomic operation instruction may be divided into four data segments to respectively access the four data to be synchronously accessed. Moreover, the data processing digits of each data segment are not less than 16 bits.

Here, it should be noted that, in order to explain the relationship between the number of data processing bits of the atomic operation instruction and the data bit number of the data to be synchronously accessed, here, each of the data to be synchronously accessed includes 16 bits. However, in actual situations, the data to be accessed synchronously may have the same number of data bits, or may have different numbers of data bits. Correspondingly, in order to adapt to the number of data bits of the data to be accessed synchronously, the data processing bits of the data segment of the atomic operation instruction corresponding to the data to be synchronously accessed may also be the same or different.

For example, the data bit number of the data A to be synchronously accessed is 16 bits, and the data bit number of the data B to be synchronously accessed is 8 bits, then at least when the data segment is divided, the data segment for accessing the data A to be synchronously accessed is at least There are 16 bits of data processing bits, and the data segment for accessing data B to be accessed synchronously has at least 8 bits of data processing bits.

Next, in step 130, the data to be accessed synchronously is accessed during an instruction cycle, wherein the instruction cycle is the length of time during which the atomic operation instruction is executed.

That is to say, in this step, each data segment to be accessed synchronously is accessed through each data segment of the atomic operation instruction.

Here, access to each data to be accessed synchronously may include, for example, read, write or other operational categories.

With the synchronous access method of the data of this embodiment, parallel accesses to multiple data to be synchronously accessed can be simultaneously performed in one instruction cycle. In addition, since these data to be accessed synchronously are accessed through atomic operation instructions, the access is not interrupted by other thread scheduling mechanisms.

Referring to FIG. 2, in the synchronous access method for data of the embodiment, the schematic flow of the step of calling the atomic operation instruction of the processor (ie, step 120 shown in FIG. 1) based on the number of data bits of each data is shown. Figure 200.

Specifically, in step 210, the number of data bits of each data to be synchronously accessed is obtained.

In some optional implementations, for example, the number of data bits of each data to be accessed synchronously may be determined by the number of data bits of consecutive memory cells allocated to the data to be accessed synchronously.

As shown in FIG. 1, contiguous memory locations have been allocated to the data based on the number of data bits of the data in step 110. In this way, the number of data bits of each data to be synchronously accessed can be determined based on the number of data bits of the contiguous memory unit and the size of the memory space occupied when the memory unit is allocated to each data.

Return to continue with Figure 2. In step 220, the sum of the data bits of each data to be synchronously accessed and the number of data processed bits of the atomic operation instruction are compared.

Next, in step 230, the atomic operation instruction is divided into data segments corresponding to the number of data based on the sum of the data processing bits of the atomic operation instruction being greater than or equal to the data bit number of each data to be synchronously accessed.

For example, the data is also shared by four data to be accessed synchronously (A to D), and each data includes 16 bits for explanation. If the number of data processing bits of the atomic operation instruction is 64 bits, that is, the number of data processing bits of the atomic operation instruction is equal to the sum of the data bits of the data to be synchronously accessed (16×4), then the atomic operation can be performed. The instruction is divided into four data segments. Each data segment can respectively access one of the data to be accessed synchronously.

On the other hand, if the number of data processing bits of the atomic operation instruction is 32 bits, that is, the data processing digit of the atomic operation instruction is smaller than the sum of the data bits of the data to be synchronously accessed (16×4), The atomic operation instruction performs the corresponding data segment division. The reason is because the sum of the number of data bits to be accessed synchronously exceeds the index of an atomic operation instruction. The upper limit of the number of data bits that can be processed by the cycle. These data to be synchronized cannot be accessed synchronously within the instruction cycle of the same atomic operation instruction.

Return to continue with Figure 1. In some optional implementations, the step of performing the atomic operation instructions of step 130 to access the data corresponding thereto may include, for example, reading and/or modifying data in one instruction cycle. Here, the instruction cycle is the length of time during which the atomic operation instruction is executed.

For example, in some alternative implementations, the execution of the atomic operation instructions is "read." Then, after the atomic operation instruction is executed, the value of each data can be returned as a return value.

Alternatively, in other implementations, the execution of the atomic operation instructions is "modified." Then, after the atomic operation instruction is executed, the value of each data will be changed accordingly.

In some optional implementation manners, the method for synchronously accessing data of the embodiment may further include the step 140, determining, according to the return value of the data to be accessed synchronously, the association relationship of the data to be synchronously accessed in the instruction cycle. .

The association relationship of each data to be accessed synchronously may include, for example, a numerical operation relationship or a logical operation relationship.

For example, the data is also shared by four data to be accessed synchronously (A to D), and each data includes 16 bits for explanation. In some optional implementations, the values of other data to be accessed synchronously may be determined according to one of the four data to be accessed synchronously, for example, when the data to be accessed synchronously is B, C, and D. If the value is 0, the value of the data A to be accessed synchronously is set to 1. Alternatively, the value of the remaining data may be calculated according to the values of the data of the four to be accessed synchronously. For example, the value of A may be updated according to the value of the data to be synchronously accessed by A to D. That is to say, calculate A=A+B+C+D.

In the following, the execution process of the synchronous access method of the data in the embodiment of the present application will be further described in conjunction with the application scenario shown in FIG. 3, so that the features can be more fully explained.

As shown in FIG. 3, it is assumed that there are four data A, B, C, and D to be accessed synchronously. Referring to the flow shown in FIG. 1, first, a continuous memory unit 310 is allocated for the four to-be-synchronized access data A to D (as shown in step 110 in FIG. 1).

Then, in order to synchronously access the four data A to D to be synchronously accessed during the instruction cycle of an atomic operation instruction, if the sum of the data bits of the data A to D does not exceed the number of data processing bits of the atomic operation instruction, Divide the atomic operation instruction into four data segments 320, that is, data segment 1, data segment 2, data segment 3, and data segment 4 corresponding to the data A to D to be accessed synchronously, respectively (as shown in step 120 in FIG. 1), and within one instruction cycle. The data A to D corresponding to each data segment corresponding to each data segment are accessed in parallel through the data segments (as shown in step 130 in FIG. 1).

Then, as shown by reference numeral 330, according to the access result of each data segment to each of the data to be synchronized accesses A to D, in the same atomic operation instruction cycle, the data between the to-be-synchronized access data A to D is determined. The association relationship (shown as step 140 in Figure 1). After the association is determined, it may be necessary to update other data based on one or more of the data to be accessed synchronously.

By adopting the synchronous access method of the above data, multiple data to be accessed synchronously can be accessed simultaneously in one atomic operation instruction cycle, thereby improving the efficiency of reading and writing data.

In addition, synchronous access of data to be synchronously accessed is performed under the premise that the total number of bits of the data is less than or equal to the number of data processing bits of the atomic operation instruction, so that other threads can be prevented from modifying the data to be simultaneously accessed. The correctness of the association relationship between the data to be accessed synchronously.

Referring to FIG. 4, there is shown a schematic structural diagram 400 of a synchronous access device for data according to an embodiment of the present application.

The synchronous access device of the data of this embodiment may include an allocation module 410, a dividing module 420, and an access module 430.

The distribution module 410 can be configured to allocate contiguous memory units to data to be accessed synchronously.

Here, the number of data bits of the contiguous memory unit is the sum of the data bits of the data to be accessed synchronously.

The partitioning module 420 is configurable to divide the atomic operation instruction into data segments corresponding to the number of data to be accessed synchronously based on the number of data to be accessed synchronously and the number of data bits of data to be accessed synchronously.

Here, the number of bits of each data segment is greater than or equal to the number of bits of data to be accessed synchronously corresponding thereto.

The access module 430 can be configured to access data to be accessed synchronously within one instruction cycle.

Here, the instruction cycle is the length of time during which the atomic operation instruction is executed.

In some optional implementation manners, the dividing module 420 may be further configured to obtain data bits for each data to be accessed synchronously; compare the sum of the data bits of each data to be synchronously accessed and the data processing of the atomic operation instruction The number of bits; and the number of data processing bits based on the atomic operation instruction is greater than or equal to the sum of the data bits of the data to be synchronously accessed, and the atomic operation instruction is divided into data segments corresponding to the number of data.

In some alternative implementations, the access module 430 can be further configured to read and/or modify data to be accessed synchronously within one instruction cycle.

In some optional implementation manners, the synchronous access device of the data in this embodiment may further include an association determining module 440.

The association determining module 440 can be configured to determine an association relationship of each data to be synchronously accessed based on a return value of the data accessed for accessing the synchronization during the instruction cycle.

Here, the association relationship may include, for example, a numerical operation relationship or a logical operation relationship.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality and operation of possible implementations of systems, methods and computer program products in accordance with various embodiments of the invention. In this regard, each block of the flowchart or block diagrams can represent a module, a program segment, or a portion of code that includes one or more logic for implementing the specified. Functional executable instructions. It should also be noted that in some alternative implementations, the functions noted in the blocks may also occur in a different order than that illustrated in the drawings. For example, two successively represented blocks may in fact be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending upon the functionality involved. It is also noted that each block of the block diagrams and/or flowcharts, and combinations of blocks in the block diagrams and/or flowcharts, can be implemented in a dedicated hardware-based system that performs the specified function or operation. Or it can be implemented by a combination of dedicated hardware and computer instructions.

The units or modules described in the embodiments of the present application may be implemented by software or by hardware. The described unit or module may also be provided in the processor, for example, as a processor including an allocation module, a partitioning module, and an access module. The names of these units or modules do not constitute a limitation on the unit or the module itself in some cases. For example, the allocation module may also be described as "a module for allocating contiguous memory units to data".

In another aspect, the present application further provides a computer readable storage medium, which may be a computer readable storage medium included in the apparatus described in the foregoing embodiment, or may exist separately, not A computer readable storage medium that is assembled into the device. The computer readable storage medium stores one or more programs that are used by one or more processors to perform the formula input methods described in this application.

The above description is only a preferred embodiment of the present application and a description of the principles of the applied technology. It should be understood by those skilled in the art that the scope of the invention referred to in the present application is not limited to the specific combination of the above technical features, and should also be covered by the above technical features without departing from the inventive concept. Other technical solutions formed by any combination of their equivalent features. For example, the above features are combined with the technical features disclosed in the present application, but are not limited to the technical features having similar functions.

Claims

A method for synchronous access of data, comprising:

Allocating a contiguous memory unit to the data to be accessed synchronously, wherein the data bit number of the contiguous memory unit is a sum of data bits of each of the data to be synchronously accessed;

Determining, according to the number of data to be synchronously accessed and the number of data bits of each of the data to be synchronously accessed, a data operation instruction into a data segment corresponding to the number of data to be accessed synchronously, wherein each of the data segments The number of bits is greater than or equal to the number of bits of the data to be accessed synchronously corresponding thereto;

The data to be accessed synchronously is accessed during an instruction cycle, wherein the instruction cycle is a duration of execution of the atomic operation instruction.
The method according to claim 1, wherein the atomic operation instruction is divided into accesses to be synchronized according to the number of data to be synchronously accessed and the number of data bits of each of the data to be synchronously accessed. The data segment corresponding to the number of data includes:

Obtaining data digits of each of the data to be accessed synchronously;

Comparing a sum of data bits of each of the data to be accessed synchronously with a data processing digit of the atomic operation instruction;

The atomic operation instruction is divided into data segments corresponding to the number of data based on the sum of the data processing bits of the atomic operation instruction being greater than or equal to the data bit number of each of the data to be synchronously accessed.
The method according to claim 1, wherein the accessing the data to be accessed synchronously in one instruction cycle comprises:

The data to be accessed synchronously is read and/or modified in one instruction cycle.
The method of claim 3, wherein the method further comprises:

And determining, according to the return value of the data to be synchronously accessed, the association relationship of each of the data to be synchronously accessed.
The method of claim 4 wherein:

The association relationship includes a numerical operation relationship or a logical operation relationship.
A synchronous access device for data, comprising:

An allocation module, configured to allocate a contiguous memory unit to data to be accessed synchronously, wherein a data bit of the contiguous memory unit is a sum of data bits of each of the data;

a dividing module, configured to divide an atomic operation instruction into a data segment corresponding to the number of data to be synchronously accessed, based on the number of data to be synchronously accessed and the number of data bits of each of the data to be synchronously accessed, wherein The number of bits of each of the data segments is greater than or equal to the number of bits of the data to be accessed synchronously corresponding thereto;

And an access module configured to access the data to be accessed synchronously in one instruction cycle, wherein the instruction cycle is a duration of executing the atomic operation instruction.
The apparatus according to claim 6, wherein the dividing module is further configured to:

Obtaining data digits of each of the data to be accessed synchronously;

Comparing a sum of data bits of each of the data to be accessed synchronously with a data processing digit of the atomic operation instruction;

The atomic operation instruction is divided into data segments corresponding to the number of data based on the sum of the data processing bits of the atomic operation instruction being greater than or equal to the data bit number of each of the data to be synchronously accessed.
The apparatus according to claim 6, wherein the access module is further configured to:

The data to be accessed synchronously is read and/or modified in one instruction cycle.
The device according to any one of claims 6-8, wherein the device further comprises:

The association determining module is configured to determine an association relationship of each of the data to be synchronously accessed based on a return value of the data to be accessed synchronously during the instruction cycle.
The device of claim 9 wherein:

The association relationship includes a numerical operation relationship or a logical operation relationship.
A device that includes:

Processor; and

Memory,

The memory stores computer readable instructions executable by the processor, the processor executing the method of any one of claims 1 to 5 when the computer readable instructions are executed.
A non-volatile computer storage medium storing computer readable instructions executable by a processor, the processor executing claim 1 to when the computer readable instructions are executed by a processor The method of any of 5.