WO2017006346A1

WO2017006346A1 - System of disseminated parallel control computing in real time

Info

Publication number: WO2017006346A1
Application number: PCT/IN2016/050205
Authority: WO
Inventors: Venkatesh SAI
Original assignee: Sai Venkatesh
Priority date: 2015-07-09
Filing date: 2016-06-28
Publication date: 2017-01-12

Abstract

The present invention relates to an enhanced computing system based on parallel processing and concurrent execution in microprocessors on a distributed processing environment in real time. Further, the present invention relates to a system of disseminated parallel control computing, which eliminates the need to share logic, control and / or execution elements without risks of anomalous processing or the system freeze due to disruption of clock signal. The system includes plurality of processing units which are interconnected through data transfer unit to perform parallel processing said data transfer unit is programmable.

Description

SYSTEM OF DISSEMINATED PARALLEL CONTROL COMPUTING IN REAL TIME

FIELD OF THE INVENTION

The present invention relates to a system for control computing. More particularly, the present invention relates to an enhanced computing system based on parallel processing and concurrent execution in microprocessors on a distributed processing environment in real time. Further, the present invention relates to a system of disseminated parallel control computing, which eliminates the need to share logic, control and / or execution elements without risks of anomalous processing or the system freeze due to disruption of clock signal.

BACKGROUND OF THE INVENTION

The world has long since progressed from sequential processing to concurrent processing models to favor fast computation. Parallelism has today found able integration not only in high- performance computing systems but also personal computers, mobile phones and so on. However the potential of concurrent processing remains from being truly mass-utilized due to constraints including limited scalability, high power consumption, need for extensive heat management and persistent issues relating to data acquisition, routing of information to / between / from processing elements, synchronization / communication between sub-tasks and overall control of the process thus enabled. Besides these, it is pertinent to note that state-of-art parallel processing systems require software to be specially written as per processing framework made available and hence, suffer from frequent compatibility, redundancy as well as obsolescence concerns.

Conventionally, advent of processor grids and distributed computing systems have increased the potential of parallel processing performance where the processing elements can either be cores constituting the same processor, multiple processors on the same computer and also cores / processors of networked computers and any combinations thereof. However, failure of any among the processing elements generally results in system failures. Another issue is that while over-clocking the processors to enable high speed processing, pulse width of the clock pulse tends to be diminutive, leading to the obvious risk of system hanging due to disruption of clock signal by instruction overload or any noise / interference that may occur. Complex and expensive schedulers / PCB / EMF-proof enclosures are proposed for overcoming these concerns, however this additive approach enjoins high resource costs.

Conventionally, standalone VLIW (Very Long Instruction Word) processors have been put to use for processing efficiency and computational accuracy. However, the processor is not compatible to varying platforms due to the inflexibility arising with the compiler design. Most often the current parallel processing systems require software to be specially written as per processing framework and hence suffer from frequent incompatibility issues. Some of the prior arts are:

EP 1022658 discloses a method for load distribution in a multiprocessor system of a communication system, wherein a host of multi processors are programmed to balance the incoming load. Each processor notifies its load balancing indicator to the other processors, and determines its probable load distribution in response to the load balancing indicators of the other processors. The stability of the system is hence being sustained by parallel processing.

CN101894093 discloses a mixed-mode multi-CPU parallel computing system and a control method. The system comprises of four microprocessor modules consisting of individual control units and is connected by a parallel interface. By adopting the multi-microprocessor structure, each module can accomplish one or more specific functions so that the mixed-mode multi-CPU parallel computing system can accomplish operation with high quality and efficiency.

US20060168090 discloses a remotely accessible communication system integrated within a structure. The communication system includes a master microserver having a master microserver card and at least one subsystem microserver having a subsystem microserver card. The communication network connects the master microserver and the at least one subsystem microserver together and is operable for forming a massively parallel supercomputer.

Although the prior art describes parallel computing mechanisms, there exists a risks of anomalous processing or the system hanging due to disruption of clock signal. Also, the issue of shared logic and the time taken for routing of information between the processing units make the parallel processing systems inadequate to suit enhanced computing.

Accordingly, there exists a need for an enhanced computing system based on parallel processing and concurrent execution in microprocessors on a distributed processing environment in real time.

OBJECTS OF THE INVENTION

One or more of the problems of the conventional prior art may be overcome by various embodiments of the system and method of the present invention.

It is the primary object of the present invention to provide an enhanced computing system based on parallel processing and concurrent execution in microprocessors on a distributed processing environment in real time. It is another object of the present invention to provide a system for disseminated control computing in real time, which eliminates the need to share logic, control and/ or execution units without risks of anomalous processing or the system freezing due to disruption of clock signal.

It is another object of the present invention to provide a system that includes plurality of processing units which are interconnected through data transfer unit to perform parallel processing said data transfer unit is programmable.

It is another object of the present invention, wherein the programmable data transfer unit is configured resulting in instruction load being disseminated among the processing units, thereby avoiding instances of anomalous execution or system freeze.

It is another object of the present invention, wherein each of the processing units independently enables the system to simultaneously handle different processing speeds in real time as per function of input / output modules involved. SUMMARY OF THE INVENTION

Thus according to the basic aspect of the present invention there is provided a system of disseminated parallel control computing in real time comprising of:

plurality of processing units;

one or more input / output modules; and

data transfer unit;

wherein the processing units are interconnected through the data transfer unit to perform parallel processing, said data transfer unit is programmable,

wherein the programmable data transfer unit is configured resulting in instruction load being disseminated among the processing units, thereby avoiding instances of anomalous execution or system freeze,

wherein output from the processing units is fed to respective input / output modules, and wherein each of the processing units independently enables the system to simultaneously handle different processing speeds in real time as per function of the input / output modules involved.

It is another aspect of the present invention, wherein the system eliminates system hang attributable to instruction overload and / or instruction mix-up as each of the processing units process independently. It is another aspect of the present invention, wherein the system eliminates failure of the processing units due to system freeze as the resource allocation and process flow are inherently independent of any interaction between said processing units.

It is another aspect of the present invention, wherein the data transfer unit operates synchronously at pre-determined clock speed having a hardware data speed of maximum of 25kb/s between each of the processing units. BRIEF DESCRIPTION OF THE DRAWING

Figure 1 : illustrates the block diagram of the system for disseminated control computing in real time according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION WITH REFERENCE TO THE ACCOMPANYING FIGURE

The present invention is thus directed to a system for disseminated control computing in real time. Further, the present invention relates to a system of disseminated parallel control computing, which eliminates the need to share logic, control and / or execution elements without risks of anomalous processing or the system freezing due to disruption of clock signal.

Referring to Figure 1, the system of disseminated parallel control computing in real time comprises of plurality of processing units [1]; one or more input / output modules [2]; and data transfer unit [3]. Each of the processing unit [1] further comprises of an Arithmetic Logic Unit (ALU), control unit, scheduler, instruction register and one or more execution units. The processing units [1] are interconnected through the data transfer unit [3] to perform parallel processing, said data transfer unit [3] is programmable. The programmable data transfer unit [3] is configured resulting in instruction load being disseminated among the processing units [1], thereby avoiding instances of anomalous execution or system freeze. Output from the processing units [1] is fed to respective input / output modules [2]. Each of the processing units [1] independently enables the system to simultaneously handle different processing speeds in real time as per function of the input / output modules [2] involved.

In one embodiment, each of the processing units [1] is a 3 -pin module having port for common clock [4] line, common two-way data port and control transfer line and prompt and signaling bus in use line port.

In another embodiment, each of the processing units [1] is a 4-pin module has an address line port for connecting with remaining processing units [1] along with port for common clock [4] line, common two-way data port and control transfer line and prompt and signaling bus in use line port.

The system eliminates system freeze attributable to instruction overload and/ or instruction mix- up as each of the processing units [1] process independently. Also, the system eliminates failure of the processing units [2] due to system freeze as the resource allocation and process flow are inherently independent of any interaction between said processing units [2]. As the resource allocation and process flow are inherently independent of any interaction between said processing units [1], failure of any processing unit [1] does not lead to a system arrest. The data transfer unit [3] operates synchronously at pre-determined clock speed having a hardware data speed of maximum of 25kb/s between each of the processing units [1].

For example, consider a system consisting of both hardware and software that allows for automated high precision control of moving vehicles such as drone by humans through inbuilt parallel pre-programmed commands in real time, said system includes at least four processing units namely Kinematic Control Unit (KCU), Proportional-Integral-Derivative (PID) and pilot control unit, math and processing unit, and aux app development core unit as processing units. Each of the processing units operates at 30MHz and linked for processing a set of instructions. It is to be noted that the number of processing units may vary as per the requirement for applications to achieve multiplicative processing speeds. The processing units have a clock pulse width of 33ns per unit, which imply a clock signal to noise ratio (SNR_cik) being higher by as much as five times that of a single processor such as ARM having a clock pulse width of 6.25ns. It would be clear that total computing speed of the system achieved, that is, 4X30 = 120MHz is achieved at minimal cost resources than otherwise employing a single microprocessor and depending on the same for system performance.

Each of the processing units further comprises of an ALU, control unit, scheduler, instruction register and one or more execution units. The processing units are interconnected through a data transfer unit; said data transfer unit is programmable. The programmable data transfer unit is configured resulting in instruction load being disseminated among the processing units, thereby avoiding instances of anomalous execution or system freeze. Output from the processing units is fed to respective input / output modules. Each of the processing units independently enables the system to simultaneously handle different processing speeds in real time as per function of the input / output modules involved, said input modules include accelerometer sensor, gyroscope sensor, current sensor, one or more auxiliary sensors, ultra sonic sensor and Global Positioning System (GPS) and output modules include one or more actuators, barometer and magnetometer. Output from input modules that include accelerometer sensor and gyroscope sensor is fed to the KCU and controlled output from the KCU is fed to the output module that includes actuators to move the vehicle. Output from input modules that include accelerometer sensor, gyroscope sensor, current sensor, one or more auxiliary sensors, and ultrasonic sensor is fed to the respective processing units through the filter module to filter distorted signals.

Further, it is noted that the system is capable of concurrently sampling the sensors data like imu, barometer, magnetometer, GPS data and process it as a clock cycle based function execution. The cumulative processing speed of the four processing units is nearly that of a microprocessor. The separate / isolated nature of processing units enables the system to simultaneously handle different processing speeds as per function involved. Communications between individual processing units is provided by a system of data transfer unit which operates synchronously at a clock speed of 400 KHz having a hardware data speed of maximum of 25 kb/s between each of the processing units.

Output from the current sensor is fed to the PID and pilot control unit and controlled output from the PID and pilot control unit is fed to the barometer for measuring atmospheric pressure. Output from the input modules such as ultra sonic sensor and Global Positioning System (GPS) is fed to the math processing unit and controlled output from the math processing unit is fed to a display for navigating the vehicle. Output from the auxiliary sensors is fed to the aux app development core unit. Thus the system allows for automated control of the moving vehicles through inbuilt parallel pre-programmed commands. In one aspect, the system has two processing units namely reflex reaction unit and a higher operation unit to process two different types of dynamic controls. The system replicates control processes of humans such as reflex nerve pathways for lower level functions requiring spontaneous response and higher level cognitive activities for planned thought out activities for automated control of the moving vehicles.

The example in the specification is purely for illustrative purposes and the present invention can be embodied in many other forms or carried out in other ways, without departing from the spirit or essential characteristics thereof. Therefore, the above should not be construed as limiting the invention, which is defined by the appended objects.

The present invention finds applicability in any field requiring computing systems and especially in devices, gadgets, equipments or machines associated with high speed real-time computation of data/ feedback from multiple sensors/ sources with variable control loop speeds. Further applications, modifications and localizations for the same shall be obvious from the disclosures hereof and are intended to be integral to the present invention.

Claims

I CLAIM:

1. A system of disseminated parallel control computing in real time comprising of:

plurality of processing units [1];

one or more input / output modules [2] ; and

data transfer unit [3];

wherein the processing units [1] are interconnected through the data transfer unit [3] to perform parallel processing, said data transfer unit [3] is programmable,

wherein the programmable data transfer unit [3] is configured resulting in instruction load being disseminated among the processing units [1], thereby avoiding instances of anomalous execution or system freeze,

wherein output from the processing units [1] is fed to respective input / output modules

[2], and

wherein each of the processing units [1] independently enables the system to simultaneously handle different processing speeds in real time as per function of the input / output modules [2] involved.

2. The system as claimed in claim 1 eliminates system freeze attributable to instruction overload and / or instruction mix-up as each of the processing units [1] process independently.

3. The system as claimed in claim 2 eliminates failure of the processing units [1] due to system freeze as the resource allocation and process flow are inherently independent of any interaction between said processing units [1].

4. The system as claimed in claim 1, wherein the data transfer unit [3] operates synchronously at pre-determined clock speed having a hardware data speed of maximum of 25 kb/s between each of the processing units [1].