WO2016203565A1

WO2016203565A1 - Computer system and control method

Info

Publication number: WO2016203565A1
Application number: PCT/JP2015/067434
Authority: WO
Inventors: 勝美大内; 功大原
Original assignee: 株式会社日立製作所
Priority date: 2015-06-17
Filing date: 2015-06-17
Publication date: 2016-12-22

Abstract

Even when a failure occurs on a boundary between a PCIe device for notifying a server of a failure and a PCIe device for notifying a storage of a failure, the failure is notified to both of the server and the storage. In the case where an interface device detects a first failure of a second PCI Express wiring, the interface device executes a first changing process for changing a state of the second PCI Express wiring, and transmits a first server side message that indicates the first failure to a server processor via a third PCI Express wiring. On the basis of the change in the state of the second PCI Express wiring, a storage controller detects the first failure, and on the basis of the first server side message, a server processor detects the first failure.

Description

Computer system and control method

The present invention relates to a computer system.

In a computer system called an integrated platform, a technology using Fiber Channel (FC) for connection between a server and storage is known. When a failure occurs in the FC path, the server and storage cannot identify the failed part. Therefore, the administrator identifies the faulty part according to the FC-Switch (SW) log and the LED lighting state, and specifies the replacement target part.

According to Non-patent Document 1, in the PCI Express (PCIe) standard, a Root Complex (RC) and an Endpoint (EP) connected to the RC form a PCIe tree. When the EP detects an error by the Advanced Error Reporting (AER) function defined by PCIe, the EP transmits an error message to the RC upstream of the PCIe tree. Upon receipt of the error message, the RC issues an interrupt to the CPU, and the CPU confirms the register value indicating the failure, thereby identifying the failure site and the failure type.

When the server and the storage are connected via the PCIe device, the computer system is managed by dividing it into a server side management range and a storage side management range. A failure detected in the server-side management range is notified to the server, and a failure detected in the storage-side management range is notified to the storage.

For example, when a failure of a PCIe device is detected within the storage-side management range, the PCIe device may not be a failure occurrence site, but the PCIe device within the server-side management range may be a failure occurrence site. In this case, the storage recognizes the failure, but the server does not recognize the failure because no failure is detected within the server-side management range. As described above, in the computer system including the server-side management range and the storage-side management range, when a PCIe path failure occurs, the administrator may not be able to identify the failed part.

In order to solve the above problems, a computer system according to an aspect of the present invention includes a storage device, a storage controller connected to the storage device, and a switch connected to the storage controller via a first PCI-Express wiring. A module, an interface device connected to the switch module via a second PCI Express wiring, and a server processor connected to the interface device via a third PCI Express wiring. The storage controller includes a Root Complex of a first PCI Express tree, the server processor includes a Root Complex of a second PCI Express tree, the switch module belongs to the first PCI Express tree, and the interface device is A first endpoint connected to the second PCI Express wiring and belonging to the first PCI Express tree, and a second Endpoint connected to the third PCI Express wiring and belonging to the second PCI Express tree. When the interface device detects the first failure of the second PCI Express wiring, the interface device executes a first change process for changing the state of the second PCI Express wiring and indicates the first failure A first server side message is sent to the server processor via the third PCI Express wiring, and the storage controller detects the first failure based on a change in the state of the second PCI Express wiring, The server processor detects the first failure based on the first server side message.

Even if a failure occurs at the boundary between the PCIe device that notifies the server of the failure and the PCIe device that notifies the storage of the failure, and the failure is detected by one of the PCIe devices, the failure is detected between the server and the storage. Both can be notified.

The configuration of the computer system is shown. The path configuration inside and between the server chassis 100 and the storage chassis 200 is shown. The structure of the server side PCIe tree and the storage side PCIe tree is shown. The configuration of the connection between the I / F-LSI 105 and the PCIe-SW 112 is shown. The program of each part in a computer system is shown. The first failure process is shown. The second failure processing is shown. The third failure processing is shown. The structure for control of the power supply of PCIe-SW112 is shown. The 1st part of a 1st power activation process is shown. The 2nd part following the 1st part of a 1st power activation process is shown. The 1st part of a 2nd power-on process is shown.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

In the following description, information may be described using the expression “xxx table”, but the information may be expressed in any data structure. That is, “xxx table” can be referred to as “xxx information” to indicate that the information does not depend on the data structure. In the following description, the configuration of each table is an example, and one table may be divided into two or more tables, or all or part of the two or more tables may be a single table. Good.

In the following description, an ID is used as element identification information, but other types of identification information may be used instead of or in addition thereto.

In the following description, when a description is made without distinguishing the same type of element, a reference number or a common number in the reference number is used, and when a description is made by distinguishing the same type of element, the reference number of the element is used. Alternatively, an ID assigned to the element may be used instead of the reference code.

In the following description, an I / O (Input / Output) request is a write request or a read request, and may be referred to as an access request.

In the following description, the process may be described using “program” as a subject. However, the program is executed by a processor (for example, a CPU (Central Processing Unit)), so that a predetermined processing is appropriately performed. Since processing is performed using a storage resource (for example, a memory) and / or an interface device (for example, a communication port), the subject of processing may be a processor. The process described with the program as the subject may be a process or system performed by a processor or an apparatus having the processor. The processor may include a hardware circuit that performs a part or all of the processing. The program may be installed in a computer-like device from a program source. The program source may be, for example, a storage medium that can be read by a program distribution server or a computer. When the program source is a program distribution server, the program distribution server may include a processor (for example, a CPU) and a storage resource, and the storage resource may further store a distribution program and a program to be distributed. Then, the processor of the program distribution server executes the distribution program, so that the processor of the program distribution server may distribute the distribution target program to other computers. In the following description, two or more programs may be realized as one program, or one program may be realized as two or more programs.

In the following description, the management system may be composed of one or more computers. Specifically, for example, when the management computer displays information (specifically, for example, the management computer displays information on its own display device, or the management computer displays display information in a remote display computer) Management computer is the management system. For example, when a function equivalent to that of the management computer is realized by a plurality of computers, the plurality of computers (may include a display computer when the display computer performs display) is the management system. . The management computer (eg, management system) may include an interface device connected to the I / O system including the display system, a storage resource (eg, memory), and a processor connected to the interface device and the storage resource. The display system may be a display device included in the management computer or a display computer connected to the management computer. The I / O system may be an I / O device (for example, a keyboard and a pointing device or a touch panel) included in the management computer, a display computer connected to the management computer, or another computer. “Displaying display information” by the management computer means displaying the display information on the display system, which may be displaying the display information on a display device included in the management computer. The management computer may transmit display information to the display computer (in the latter case, the display information is displayed by the display computer). The management computer inputting / outputting information may be inputting / outputting information to / from an I / O device of the management computer, or a remote computer connected to the management computer (for example, a display) Information may be input / output to / from the computer. The information output may be a display of information.

Hereinafter, the configuration of the computer system of this embodiment will be described.

Fig. 1 shows the configuration of the computer system.

The computer system includes one or more server enclosures 100, one or more storage enclosures 200, one or more drive enclosures 250, and a management client 50 (management computer). The server chassis 100 is connected to the storage chassis 200 via a PCIe wiring. The PCIe wiring may be a cable or a substrate. The storage chassis 200 is connected to the drive chassis 250 via an interface such as PCIe, SAS, or SATA. The management client 50 is connected to the server casing 100 and the storage casing 200 via a communication network such as Local Area Network (LAN).

The server housing 100 includes one or more server units 101, a plurality of switch modules (SWM) 111, a plurality of Service Processors (SVP) 121, and a plurality of Power Supply Units (PSU) 122. The server unit 101 is connected to the SWM 111 via the PCIe wiring, and is connected to the SVP 121 via the LAN wiring. The SWM 111 is connected to the storage chassis 200.

The server unit 101 includes a central processing unit (CPU) 102, a memory (MEM) 103, an interface (I / F) board 104, and a baseboard management controller (BMC) 106. The server unit 101 is, for example, a server blade.

Hereinafter, for distinction, the CPU 102 may be referred to as a server CPU 102 (server processor), the SVP 121 may be referred to as a server SVP 121 (server management processor), and the PSU 122 may be referred to as a server PSU 122 (server power supply circuit).

The server CPU 102 is connected to the memory 103 and the BMC 106. The memory 103 stores programs and data such as Operating System (OS) and applications. The server CPU 102 executes processing such as I / O for the storage chassis 200 in accordance with a program stored in the memory 103. The server CPU 102 manages configuration information in the server unit 101 and a model name for each component in the server unit 101. When there is a discrepancy between the configuration information detected in the server unit 101 and the configuration information set from the server SVP 121, the server CPU 102 notifies the server SVP 121 via the BMC 106 of an error.

The BMC 106 is connected to the server SVP 121. The BMC 106 monitors the operating status of the server unit 101, such as the state of the server CPU 102, the temperature, voltage, and FAN rotation speed in the server unit 101, detects a fault in the server unit 101, and information on the detected fault Is transmitted to the server SVP 121.

The server CPU 102 is connected to the I / F board 104 via the PCIe wiring. Here, the server CPU 102, the memory 103, and the BMC 106 are mounted on the motherboard (server blade) of the server unit 101. The I / F board 104 is, for example, a mezzanine board connected to a motherboard and can be replaced.

The I / F board 104 includes an I / F-Large-Scale integrated circuit (LSI) 105. The I / F-LSI 105 is connected to the SWM 111 via a PCIe wiring. The I / F-LSI 105 includes a memory that stores a program and data, and a processor that executes processing according to the program.

The I / F-LSI 105 includes a DMA transfer control circuit, and executes DMA transfer between the memory 103 in the server unit 101 and the memory 203 in the storage controller 201 based on an instruction from the storage CPU 202. Further, when the upper layer protocol between the CPU 102 and the I / F-LSI 105 in the server unit 101 and the upper layer protocol between the CPU 202 and the I / F-LSI 105 in the storage controller 201 are different, the I / F-LSI 105 Performs protocol conversion.

The SWM 111 includes at least one PCIe switch (PCIe-SW) 112. The PCIe-SW 112 is connected to the I / F-LSI 105 of the server housing 100 via a PCIe wiring. The PCIe-SW 112 is further connected to the storage chassis 200. Instead of the PCIe-SW 112, another PCIe device such as a PCIe bridge may be used.

The server SVP 121 sets configuration information of modules in the server housing 100 such as the server unit 101 based on information from the management client 50. Further, the server SVP 121 executes power-on and shutdown of each server unit 101 based on information from the management client 50. The server SVP 121 also monitors the operating status of the server chassis 100 such as the state of the server unit 101, the temperature, voltage, and FAN rotation speed in the server chassis 100, and detects a failure in the server chassis 100. Information of the detected failure is transmitted to the management client 50.

The server PSU 122 supplies power to each part of the server chassis 100 from an external power source.

The storage chassis 200 includes a plurality of storage controllers (CTL) 201, a plurality of back-end (BE) interfaces 211, a plurality of SVPs 221 and a plurality of PSUs 222. The storage controller (CTL) 201 is connected to the PCIe-SW 112 via the PCIe wiring, and is connected to the BE interface 211 via the PCIe wiring. One or more drive housings 250 are connected to the BE interface 211. The PSU 222 is connected to an external power source and supplies power to each part of the storage chassis 200.

The storage controller 201 includes a CPU 202 and a memory (MEM) 203.

Hereinafter, for distinction, the CPU 202 may be referred to as a storage CPU 202 (storage processor), the SVP 221 may be referred to as a storage SVP 221 (storage management processor), and the PSU 222 may be referred to as a storage PSU 222 (storage power supply circuit).

The memory 203, SWM 111, and BE 211 are connected to the storage CPU 202. The memory 203 stores the program and data of the storage controller 201. The storage CPU 202 executes the processing of the storage controller 201 according to the program stored in the memory 203. The storage CPU 202 manages the configuration information in the storage chassis 200 and the drive chassis 250 and the model name for each component in the storage chassis 200 and the drive chassis 250. The storage CPU 202 notifies the storage SVP 221 of an error when there is a contradiction between the configuration information detected in the storage chassis 200 and the drive chassis 250 and the configuration information set from the storage SVP 221.

The drive housing 250 includes one or more drives 251. The drive 251 is connected to the BE interface 211 directly or via a device such as a switch.

The storage SVP 221 sets configuration information of modules in the storage chassis 200 and the drive chassis 250 such as the storage controller 201 and the drive 251 based on information from the management client 50. The storage SVP 221 also operates the storage chassis 200 and the drive chassis 250 based on information from the management client 50, such as the status of the storage controller 201, the temperature, voltage, and FAN rotation speed in the storage chassis 200. The status is monitored, a fault in the storage chassis 200 and the drive chassis 250 is detected, and information on the detected fault is transmitted to the management client 50.

The storage PSU 222 supplies power to each part of the storage chassis 200 from an external power source.

The management client 50 includes a memory that stores programs and data, a processor that executes processing according to the programs, an input device that receives input from the administrator, and a display device that displays information from the server SVP 121 and the storage SVP 221. Including. The management client 50 performs a remote access to the server SVP 121 to call a server management screen for managing the server chassis 100 and display the server management screen on a display device. The management client 50 further performs remote access to the storage SVP 221 to call a storage management screen for managing the storage chassis 200 and display the storage management screen on the display device. Further, the management client 50 receives failure information from the server SVP 121 and the storage SVP 221 and displays the received information on the display device.

FIG. 2 shows a path configuration inside and between the server chassis 100 and the storage chassis 200 in a computer system including one server chassis 100 and one storage chassis 200.

In this embodiment, the server chassis 100 includes eight server units 101 and two SWMs 111. Each SWM 111 includes one PCIe-SW 112. The PCIe-SW 112 includes four virtual switches VS0 to VS3. The storage chassis 200 includes two storage controllers 201 and eight BEs 211. Each storage controller 201 includes two storage CPUs 202. Each storage CPU 202 is connected to two BEs 211. The two storage CPUs 202 in each storage controller 201 are connected to each other. Two storage CPUs 202 in one storage controller 201 are connected to two storage CPUs 202 in the other storage controller 201, respectively.

Each I / F-LSI 105 is connected to two virtual switches in different SWMs 111 via PCIe wiring. These two virtual switches are respectively connected to the CPUs 202 in the two storage controllers 201 via PCIe wiring. The two storage CPUs 202 in each storage controller 201 include a total of four PCIe root ports, and each root port is connected to four virtual switches in one SWM 111. Each virtual switch is connected to two I / F-LSIs 105.

Thereby, the computer system of this embodiment includes eight server-side PCIe trees and eight storage-side PCIe trees. Further, the path between the I / F-LSI 105 and the storage controller 201 is made redundant. The server CPU 102 can select one of a plurality of paths. Further, when the server CPU 102 receives a failure notification from the PCIe device on the path being used, the server CPU 102 may continue the access to the storage controller 201 by switching the path including the failure to another path. it can.

In addition, the number of each part, the number of each wiring, and the connection destination of each wiring in the computer system are not limited to the configuration of this embodiment.

In this embodiment, the number of PCIe wirings between the plurality of server units 101 and the plurality of SWMs 111 is larger than the number of PCIe wirings between the plurality of SWMs 111 and the plurality of storage controllers 201. In this case, since the server chassis 100 includes a plurality of SWMs 111, the PCIe wiring between the server chassis 100 and the storage chassis 200 can be compared with a configuration in which a plurality of SWMs are provided in the storage chassis 200. The number can be reduced, the connection and management between those cases can be facilitated, and failures can be reduced.

According to this configuration, modules such as the I / F board 104 and the SWM 111 can be recognized as a faulty part, and can be replaced in units of modules.

According to this configuration, since the computer system is divided into the server casing 100 and the storage casing 200, the number of casings can be changed in scale-out or the like.

Further, the server CPU 102 and the I / F-LSI 105 are connected by PCIe, and the I / F-LSI 105 and the storage CPU 202 are connected by PCIe, so that the I / O performance can be improved. The BE 211 and the drive 251 may be connected by PCIe.

FIG. 3 shows the configuration of the server-side PCIe tree and the storage-side PCIe tree.

In the server-side PCIe tree, the server CPU 102 includes a Root Complex (RC) 610, and the PCIe port of the RC 610 is a Root port 611. In the I / F-LSI 105, the PCIe port connected to the root port 611 is an endpoint port 612.

In the PCIe tree on the storage side, the storage CPU 202 includes the RC 620, and the PCIe port of the RC 620 is the root port 621. In the PCIe-SW 112, the PCIe port connected to the root port 621 is the upstream port 622. In the PCIe-SW 112, the PCIe port on the I / F-LSI 105 side is the downstream port 311, and in the I / F-LSI 105, the PCIe port connected to the downstream port 311 of the PCIe-SW 112 is the endpoint port 301. That is, the Root port 611 and the Endpoint port 612 belong to the server side PCIe tree, and the Root port 621, the Upstream port 622, the Downstream port 311, and the Endpoint port 301 belong to the storage side PCIe tree.

The I / F-LSI 105 converts the server PCIe tree packet received at the endpoint port 612 into a storage-side PCIe tree packet, and transmits the packet from the endpoint port 301 to the PCIe-SW 112. Further, the I / F-LSI 105 converts the storage-side PCIe tree packet received at the Endpoint port 301 into a server PCIe tree packet, and transmits the packet from the Endpoint port 612 to the server CPU 102.

PCIe devices such as the I / F-LSI 105 and the PCIe-SW 112 include a register indicating the presence / absence of a failure for each port and each failure type. When the PCIe device detects a hardware failure (PCIe failure) of the PCIe path due to occurrence of an uncorrectable error such as Unsupported Request, the PCIe device writes failure information indicating the PCIe failure to a corresponding register. The server CPU 102 and the storage CPU 202 can identify the parts and types of all the faults that have occurred at the same time by reading these registers after receiving the PCIe fault notification.

When the PCIe device in the server side PCIe tree detects a PCIe failure, the PCIe device notifies the RC 610 of the server side PCIe tree of the PCIe failure. The server CPU 102 detects a PCIe failure by an interrupt from the RC 610.

When the PCIe device in the storage-side PCIe tree detects a PCIe failure, the PCIe failure is notified to the RC 620 of the storage-side PCIe tree. The storage CPU 202 detects a PCIe failure by an interrupt from the RC 620.

In this embodiment, apart from the range of each chassis and each PCIe tree, the range of the part managed together with the server unit 101 in the computer system is set as the server-side management range and managed together with the storage controller 201. The part range is set as the storage-side management range. The server side management range includes the server unit 101. The storage side management range includes the storage chassis 200, the drive chassis 250, and the SWM 111.

The server CPU 102 transmits a maintenance report indicating PCIe fault information, maintenance action, and maintenance component model name within the server-side management range to the management client 50 via the server SVP 121. The storage CPU 202 transmits a maintenance report indicating PCIe fault information, maintenance action, and maintenance component model name within the storage management range to the management client 50 via the storage SVP 221.

The part from the endpoint port 301 of the I / F-LSI 105 to the downstream port 311 of the PCIe-SW 112 is a boundary between the server side management range and the storage side management range. This part is called a boundary range. When the PCIe device on the packet receiving side detects a PCIe failure, there is a possibility of a hardware failure of the PCIe device on the packet receiving side and a hardware failure of the PCIe device on the packet transmitting side. Therefore, when a PCIe failure is detected in the boundary range, both the I / F-LSI 105 and the PCIe-SW 112 become replacement candidates. If only one of the I / F-LSI 105 and the PCIe-SW 112 detects a PCIe failure and notifies the RC of the PCIe tree to which the detected PCIe device belongs, only one of the I / F-LSI 105 and the PCIe-SW 112 is exchanged. The administrator will be notified. For example, when only the PCIe failure of the SWM 111 is detected in the boundary range and notified to the administrator by the storage CPU 202, the administrator can replace the SWM 111 but cannot replace the I / F board 104 that may have a PCIe failure. . Thus, in this embodiment, when one PCIe device in the boundary range detects a PCIe failure, the other PCIe device is also notified of the PCIe failure.

When the server chassis 100 and the storage chassis 200 notify the detected failure to one management client 50, the administrator can accurately recognize the location of the failure in the computer system, and the entire computer system Can be integrated and managed.

In addition, when the server-side management range and the storage-side management range are managed by different managers, management clients corresponding to the server-side management range and the storage-side management range may be provided. In this case, the maintenance notification for the server-side management range may be transmitted to the management client corresponding to the server-side management range, and the maintenance notification for the storage-side management range may be transmitted to the management client corresponding to the storage-side management range. The server side management range and the storage side management range may be managed by different management software. In this case, the management client 50 may display the maintenance report using management software corresponding to the maintenance report. Even if the boundary between the server-side management range and the storage-side management range in the computer system is different from the boundary between the server-side PCIe tree and the storage-side PCIe tree, the computer system can manage the server-side management range and the storage-side management range. It is possible to notify the administrator of the faulty part in each of the above.

FIG. 4 shows a connection configuration between the I / F-LSI 105 and the PCIe-SW 112.

The I / F-LSI 105 includes the above-described Endpoint port 301, a block request notification register 304, and a block request reception register 305. The Endpoint port 301 includes a PCIe link control register 302 and a PCIe link status register 303.

The PCIe-SW 112 includes the above-described downstream port 311, a block request reception register 314, and a block request notification register 315. The downstream port 311 includes a PCIe link control register 312 and a PCIe link status register 313.

The PCIe link control register 302 indicates PCIe link control information written by the I / F-LSI 105. The PCIe link status register 303 indicates the PCIe link status received by the I / F-LSI 105. The PCIe link control register 312 indicates PCIe link control information written by the storage CPU 202. The PCIe link status register 313 indicates the PCIe link status received by the storage CPU 202. The block request notification register 304 indicates a block request written by the I / F-LSI 105. The block request reception register 305 indicates a block request received by the I / F-LSI 105. The block request notification register 315 indicates a block request written by the storage CPU 202. The block request reception register 314 indicates a block request received by the storage CPU 202.

The PCIe wiring 320 between the I / F-LSI 105 and the PCIe-SW 112 includes a PCIe lane 321 and

sideband signals

322 and 323. Lane 321 is a pair of a differential signal for transmission and a differential signal for reception. The sideband signal 322 transmits the block request written in the block request notification register 304 of the I / F-LSI 105 to the block request reception register 314 of the PCIe-SW 112. The sideband signal 323 transmits the block request written in the block request notification register 315 of the PCIe-SW 112 to the block request reception register 305 of the I / F-LSI 105. The PCIe wiring 320 may be a cable or a substrate such as a backplane.

FIG. 5 shows programs of each part in the computer system.

The memory 103 in the server unit 101 stores an I / F-LSI driver 501 for controlling the I / F-LSI 105. The server CPU 102 executes processing for the I / F-LSI 105 according to the I / F-LSI driver 501. The I / F-LSI driver 501 includes a path switching program 502 and a maintenance notification program 503. The path switching program 502 switches the PCIe path to another path when the PCIe path including the PCIe failure is blocked. The maintenance notification program 503 transmits, to the management client 50 via the server SVP 121, a maintenance notification indicating PCIe failure information, maintenance action, and maintenance component model name notified from the I / F-LSI 105.

The memory 107 in the I / F-LSI 105 stores an I / F-LSI control program 504 for controlling the I / F-LSI 105. The processor in the I / F-LSI 105 executes processing according to the I / F-LSI control program 504. The I / F-LSI control program 504 includes a regular monitoring program 505 and a failure processing program 506. The periodic monitoring program 505 executes periodic monitoring that periodically reads the register in the I / F-LSI 105. When a PCIe failure is detected, the failure processing program 506 executes detection of another PCIe failure, blockage of the failed part, notification of the PCIe failure, and the like.

The memory 203 in the storage controller 201 stores a storage control program 507 for controlling the storage chassis 200. The storage CPU 202 executes processing according to the storage control program 507. The storage control program 507 includes an initial setting program 508, a periodic monitoring program 509, a failure processing program 510, and a maintenance notification program 511. The initial setting program 508 executes initial setting of the storage chassis 200. The periodic monitoring program 509 performs periodic monitoring that periodically reads the registers in the storage controller 201. When a PCIe failure is detected, the failure processing program 510 executes blockage of the failed part, notification of the PCIe failure, or the like. The maintenance notification program 511 transmits, to the management client 50 via the storage SVP 221, a maintenance notification indicating PCIe failure information, maintenance action, and maintenance component model name notified from the PCIe device in the storage-side PCIe tree.

The operation of the computer system is described below.

Here, the first failure process when the I / F-LSI 105 in the server-side management range detects a PCIe failure in the boundary range will be described.

FIG. 6 shows the first failure processing.

This sequence is an I / F-LSI control executed by an I / F-LSI driver 501 executed by the server CPU 102 and a processor in the I / F-LSI 105 as server-side processing that is processing in the server-side management range. The operations of the program 504 and the Endpoint port 301 in the I / F-LSI 105 are shown. This sequence further shows the operations of the downstream port 311 of the PCIe-SW 112, the blocking request reception register 314 of the PCIe-SW 112, and the storage control program 507 of the storage CPU 202 as storage-side processing that is processing of the storage-side management range. .

In S1110, when the endpoint port 301 of the I / F-LSI 105 detects a PCIe failure, it issues an interrupt to the I / F-LSI control program 504. The I / F-LSI control program 504 that has received the interrupt activates the failure processing program 506 in S1120.

Thereafter, in S1130, the failure processing program 506 executes failure information pruning processing for reading each register in the I / F-LSI 105 and acquiring failure information. As a result, the failure processing program 506 can acquire failure information indicating the type of detected PCIe failure and the location and type of other PCIe failures. After that, in S1140, the failure processing program 506 closes (Link パス Disable) the PCIe path including the PCIe failure. In this example, the failure processing program 506 closes the PCIe path of the lane 321 by writing to the PCIe link control register 302 in the endpoint port 301 at least. As a result, the PCIe path enters a link down (communication impossible) state.

After that, in S1150, the failure processing program 506 writes a blocking request for requesting blocking of the PCIe path and issuance of the maintenance notification to the blocking request notification register 304 in the I / F-LSI 105, thereby generating the sideband signal 322. Then, the blocking request is transmitted to the blocking request reception register 314 in the PCIe-SW 112.

The periodic monitoring program 509 of the storage control program 507 of the storage controller 201 executes periodic monitoring that periodically monitors the registers in the storage-side PCIe tree in S1210. Thereafter, in S1220, the regular monitoring program 509 determines whether or not there is a block request in the block request reception register 314.

When it is determined that there is no blocking request (No), the regular monitoring program 509 executes the next regular monitoring after a preset time has elapsed. If it is determined that there is a blocking request (Yes), in S1230, the failure processing program 510 executes failure information pruning processing for reading each register in the storage-side PCIe tree and acquiring failure information. Thereafter, in S1240, the failure processing program 510 closes the PCIe path including the PCIe failure indicated in the failure information. In this example, the failure processing program 510 closes the PCIe path of the lane 321 by writing to the PCIe link control register 312 in at least the downstream port 311. Thereafter, in S 1260, the maintenance notification program 511 transmits a switch module (SWM) maintenance notification indicating the PCIe fault information, maintenance action, and maintenance component type name of the SWM 111 to the management client 50 via the storage SVP 221.

After S1150, in S1160, the failure processing program 506 transmits an error message indicating the PCIe failure to the I / F-LSI driver 501 of the server CPU 102 based on the acquired failure information. Thereafter, in S1170, the path switching program 502 of the I / F-LSI driver 501 switches the path including the PCIe failure indicated in the error message to another path. Thereafter, in S1180, the maintenance notification program 503 of the I / F-LSI driver 501 sends an I / F board maintenance notification indicating the PCIe failure information, maintenance action, and maintenance component type name of the I / F board 104 to the BMC 106 and the server SVP 121. To the management client 50. The management client 50 displays a screen based on the I / F board maintenance report.

According to the first failure processing described above, when the I / F-LSI 105 detects a PCIe failure in the boundary range, the PCIe failure can be notified to the PCIe-SW 112 by using the sideband signal 322. As a result, both the server CPU 102 and the storage CPU 202 can detect a PCIe failure in the boundary range and transmit a maintenance report indicating the failed part to the administrator. Even if the lane 321 has a PCIe failure, the I / F-LSI 105 can notify the PCIe-SW 112 using the sideband signal 322. In addition, since the I / F-LSI 105 and the PCIe-SW 112 block the PCIe path including the PCIe failure, another process can be prevented from using the PCIe path.

Here, the second failure processing when the PCIe-SW 112 in the storage-side management range detects a PCIe failure in the boundary range will be described.

FIG. 7 shows the second failure processing.

This sequence includes, as server side processing, an I / F-LSI driver 501 executed by the server CPU 102, an I / F-LSI control program 504 executed by a processor in the I / F-LSI 105, and an I / F- The operations of the block request reception register 305 in the LSI 105 and the Endpoint port 301 in the I / F-LSI 105 are shown. This sequence further shows the operations of the downstream port 311 of the PCIe-SW 112, the storage CPU 202 that is the RC of the storage-side PCIe tree, and the storage control program 507 of the storage CPU 202 as storage-side processing.

In S2110, when the downstream port 311 of the PCIe-SW 112 detects a PCIe failure, it transmits an error message to the RC 620. The RC 620 that has received the error message issues an interrupt to the storage control program 507. The storage control program 507 that has received the interrupt activates the failure processing program 510 in S2120.

In S2130, the failure processing program 510 executes failure information pruning processing for reading the register in the storage-side PCIe tree and acquiring failure information. After that, in S2140, the failure processing program 510 closes the PCIe path including the PCIe failure indicated in the failure information. In this example, the failure processing program 510 closes the PCIe path of the lane 321 by writing to the PCIe link control register 312 in at least the downstream port 311. As a result, the PCIe path enters a link down (communication impossible) state. After that, in S2150, the failure processing program 510 writes a blocking request for requesting blocking of the PCIe path and issuance of the maintenance notification to the blocking request notification register 315 of the PCIe-SW 112, so that I / F-LSI 105 sends a block request to block request reception register 305.

Thereafter, in S2160, the maintenance notification program 511 transmits the SWM maintenance notification indicating the PCIe fault information, maintenance action, and maintenance part type name of the SWM 111 to the management client 50 via the storage SVP 221. The management client 50 displays a screen based on the SWM maintenance notification.

In step S <b> 2210, the periodic monitoring program 505 of the I / F-LSI control program 504 of the I / F-LSI 105 executes periodic monitoring that periodically monitors the register of the I / F-LSI 105. Thereafter, in S2220, the periodic monitoring program 505 determines whether or not there is a block request in the block request reception register 305.

If it is determined that there is no blocking request (No), the regular monitoring program 505 executes the next regular monitoring after a preset time has elapsed. If it is determined that there is a blocking request (Yes), the failure processing program 506 reads out each register in the I / F-LSI 105 and obtains failure information pruning in S2230 to obtain failure information. After that, in S2240, the failure processing program 506 closes the PCIe path including the PCIe failure. In this example, the failure processing program 506 closes the PCIe path of the lane 321 by writing to the PCIe link control register 302 in the endpoint port 301 at least.

Thereafter, in S2260, the failure processing program 506 transmits an error message indicating the PCIe failure to the I / F-LSI driver 501 of the server CPU 102 based on the acquired failure information. After that, in S2270, the path switching program 502 of the I / F-LSI driver 501 switches the path including the PCIe failure indicated in the error message to another path. Thereafter, in S2280, the maintenance notification program 503 of the I / F-LSI driver 501 sends an I / F board maintenance notification indicating the PCIe fault information, maintenance action, and maintenance component type name of the I / F board 104 to the BMC 106 and the server SVP 121. To the management client 50. The management client 50 displays a screen based on the I / F board maintenance report.

According to the second fault processing described above, when the PCIe-SW 112 detects a PCIe fault in the boundary range, the PCIe fault can be notified to the I / F-LSI 105 by using the sideband signal 323. As a result, both the server CPU 102 and the storage CPU 202 can detect a PCIe failure in the boundary range and transmit a maintenance report indicating the failed part to the administrator. Even if the lane 321 has a PCIe failure, the PCIe-SW 112 can notify the I / F-LSI 105 using the sideband signal 323. In addition, since the I / F-LSI 105 and the PCIe-SW 112 block the PCIe path including the PCIe failure, another process can be prevented from using the PCIe path.

Note that the PCIe wiring 320 between the I / F-LSI 105 and the PCIe-SW 112 may not include the sideband signal 323. In the computer system having this configuration, when the PCIe-SW 112 in the storage management range detects a PCIe failure in the boundary range, the third failure processing is executed instead of the second failure processing.

FIG. 8 shows the third failure processing.

In this third failure process, elements with the same reference numerals as in the second failure process are the same as the elements in the second failure process.

When the downstream port 311 of the PCIe-SW 112 detects a PCIe failure, the storage side processing executes S2110 to S2140 and S2160 similar to the second failure processing.

In S2140, the PCIe path is linked down. In S2170, the endpoint port 301 of the I / F-LSI 105 issues an interrupt to the I / F-LSI control program 504 when detecting the link down.

The I / F-LSI control program 504 that received the interrupt executes the same S2230 to S2260 as in the second failure process. The I / F-LSI driver 501 that has received the error message executes S2270 to S2280 similar to the second failure process.

According to the above third fault processing, the PCIe fault detected by the PCIe-SW 112 can be notified to the I / F-LSI 105 even if the PCIe wiring 320 does not include the sideband signal 323. Thereby, the PCIe device on both sides of the boundary range can detect the PCIe failure. When the I / F-LSI 105 detects a PCIe failure in the boundary range, the computer system having this configuration executes the first failure process.

Note that the PCIe wiring 320 between the I / F-LSI 105 and the PCIe-SW 112 may not include the sideband signal 322. The computer system having this configuration executes the fourth fault process instead of the first fault process.

In the fourth fault process, when the Endpoint port 301 of the I / F-LSI 105 detects a PCIe fault, the server side process executes S1110 to S1140 and S1160 to S1180 similar to the first fault process.

When the PCIe path is linked down by S1140 and the downstream port 311 of the PCIe-SW 112 detects a link down, an error message is transmitted to the RC 620 as in S2110 of the second failure processing. The RC 620 that has received the error message issues an interrupt to the storage control program 507. The storage control program 507 that has received the interrupt executes S1230 to S1260 similar to the first failure process.

According to the above fourth fault processing, the PCIe fault detected by the I / F-LSI 105 can be notified to the PCIe-SW 112 even if the PCIe wiring 320 does not include the sideband signal 322. Thereby, the PCIe device on both sides of the boundary range can detect the PCIe failure. When the PCIe-SW 112 detects a PCIe failure in the boundary range, the computer system having this configuration executes the second failure process.

According to the first failure processing, the PCIe-SW 112 recognizes the PCIe failure notified from the I / F-LSI 105 by the sideband signal 322, and detects an abnormality other than the PCIe failure by link down. These abnormalities can be distinguished. The abnormality other than the PCIe failure to be notified is, for example, when the server unit 101 (server blade) is removed from the server chassis 100 while the power is on, or when the power is forcibly cut off.

Note that the PCIe wiring 320 between the I / F-LSI 105 and the PCIe-SW 112 may not include both the sideband signals 322 and 323. The computer system having this configuration executes the fourth fault process instead of the first fault process, and executes the third fault process instead of the second fault process.

Note that the computer system may combine the first failure processing and the fourth failure processing, or may combine the second failure processing and the third failure processing. For example, even when a failure occurs in the sideband signal, one PCIe device in the boundary range detects the PCIe failure and closes the PCIe, so that the other PCIe device detects the PCIe failure due to link down. be able to.

When a PCIe failure occurs in the boundary range, both the part in the server side management range and the part in the storage side management range become replacement candidates. However, the PCIe failure may be detected only on one PCIe port. Such a PCIe failure is, for example, a Malformed TLP error detected at the port receiving the PCIe packet. In this case, the PCIe port on the opposite side to the PCIe wiring in the boundary range does not detect the PCIe failure. According to the present embodiment, the PCIe device that has detected the PCIe failure in the boundary range notifies the PCIe failure to the PCIe device on the opposite side of the boundary range by changing the state of the PCIe wiring having the PCIe failure. The PCIe device that has detected the PCIe failure by this notification can execute blocking of the PCIe path including the PCIe failure and transmission of a maintenance notification indicating the PCIe failure. As a result, both the server-side management range and the storage-side management range can detect the PCIe failure in the boundary range and notify the management client 50 of it. That is, in a computer system including a server and a storage connected by PCIe, it is possible to reliably identify a faulty part and perform maintenance notification.

The administrator can recognize the exact failure part based on the maintenance report, and can recognize the possibility of parts replacement and recovery. Further, the administrator can perform appropriate maintenance such as replacement of both the server-side management range and the storage-side management range. For example, the administrator can replace the I / F board 104 indicated in the I / F board maintenance report from the server chassis 100 and replace the SWM 111 indicated in the SWM maintenance report from the storage chassis 200. can do. Note that the SWM maintenance notification indicates the PCIe-SW 112, and the PCIe-SW 112 may be replaced.

The computer system of this embodiment controls the power-on of the server chassis 100 and the storage chassis 200. In the present embodiment, elements denoted by the same reference numerals as those in the first embodiment are the same as those in the first embodiment.

As described above, the server chassis 100 operates with power from the server PSU 122, and the storage chassis 200 operates with power from the storage PSU 222. The PCIe-SW 112 belongs to the storage-side management range, but is included in the server chassis 100, so that power is supplied from the server PSU 122.

Due to power recovery after a power failure, the storage controller 201 may be activated and the storage-side management range may be initialized while the PCIe-SW 112 is not activated. In this case, although the SWM 111 belongs to the storage-side management range, the SWM 111 is not activated when the storage controller 201 executes the initial setting because it is arranged in the server housing 100. Therefore, the storage controller 201 recognizes that the PCIe-SW 112 is not connected at the time of initial setting, and issues a configuration check error. The computer system of this embodiment prevents a configuration check error in such a case.

FIG. 9 shows a configuration for controlling the power supply of the PCIe-SW 112.

The server PSU 122 in the server housing 100 includes a main power supply 123 and a sub power supply 124. The SWM 111 in the server housing 100 includes a PCIe-SW 112 and an SWM power supply control IC (Integrated Circuit) 113. The main power supply 123 supplies power from the external power supply to the PCIe-SW 112 under the control of the SWM power supply control IC 113. The sub power supply 124 supplies power from the external power supply to the SWM power supply control IC 113. The SWM power supply control IC 113 activates the PCIe-SW 112.

The storage controller 201 in the storage chassis 200 includes an SWM control unit 205 connected to the storage CPU 202 via the PCIe wiring in addition to the elements of the first embodiment. The SWM control unit 205 includes an SWM control register 206 and an SWM status register 207. The SWM control register 206 indicates an activation request for activating the PCIe-SW 112. The SWM status register 207 includes mounting status information indicating whether or not the SWM 111 is mounted on the server chassis 100, power status information indicating whether or not the SWM power control IC 113 is operating with power from the sub power supply 124, and Stores state information including

The PCIe wiring 401 between the SWM 111 and the storage controller 201 includes a PCIe lane 402 and sideband signals 403, 404, and 405. Lane 402 is a pair of a differential signal for transmission and a differential signal for reception. The sideband signal 403 transmits the activation request written in the SWM control register 206 of the SWM control unit 205 to the SWM power supply control IC 113. The sideband signal 404 transmits power state information from the SWM power supply control IC 113 to the SWM state register 207 of the SWM control unit 205. The sideband signal 405 transmits the mounting state information from the reference potential (ground) of the SWM control unit 205 and the SWM 111 to the SWM state register 207. The PCIe wiring 401 may be a cable or a substrate.

Hereinafter, the power-on process for turning on the computer system will be described.

A description will be given of the first power-on process when the administrator powers on the server chassis 100 and the storage chassis 200 in this order using the management client 50 in normal power-on.

FIG. 10 shows the first part of the first power-on process. FIG. 11 shows a second part following the first part of the first power-on process.

The operating entities in this sequence are the management client 50, the server chassis 100, and the storage chassis 200. The operation entities in the server chassis 100 are the server PSU 122, the server SVP 121, the server unit 101, the PCIe-SW 112, and the SWM power control IC 113. The operation entities in the storage chassis 200 are the SWM control unit 205, the storage control program 507 of the storage CPU 202, the storage SVP 221, and the storage PSU 222.

In S3110, when the administrator turns on the server PSU 122 in the server chassis 100, the server PSU 122 supplies power to the server SVP 121 and the SWM power control IC 113.

When the SWM power supply control IC 113 is activated by power from the sub power supply 124, mounting state information indicating that the SWM 111 is mounted on the server housing 100, and power state information indicating that the SWM power control IC 113 is operating, Is written to the SWM status register 207 via the sideband signals 404 and 405.

Thereafter, in S3120, when the server SVP 121 completes the activation, the server SVP 121 transmits a completion notification indicating the completion of the activation of the server SVP 121 to the management client 50. The management client 50 displays a screen based on the received completion notification.

Thereafter, in S3130, when the administrator turns on the storage PSU 222 in the storage chassis 200 in accordance with the display of the completion notification, the storage PSU 222 supplies power to the storage SVP 221.

Thereafter, in S3140, when the storage SVP 221 completes the startup, the storage SVP 221 transmits a completion notification indicating the completion of the startup of the storage SVP 221 to the management client 50. The management client 50 displays a screen based on the received completion notification.

Thereafter, in S3150, the administrator inputs a CTL power-on instruction for powering on the storage controller 201 to the management client 50 in response to the display of the completion notification. In response to the input, the management client 50 transmits a CTL power-on instruction to the storage SVP 221. Thereafter, in S3160, the storage SVP 221 turns on the storage controller 201 in response to the CTL power-on instruction. Thereafter, in S3170, the storage control program 507 is activated and starts the initial setting. Thereafter, in S3180, the storage control program 507 executes a SWM state check.

In the SWM status check, the storage control program 507 reads the mounting status information and the power status information from the SWM status register 207 and determines whether the SWM power control IC 113 can be used. Here, the storage control program 507 indicates that the mounting status information indicates that the SWM 111 is mounted on the server housing 100 and the power status information indicates that the SWM power control IC 113 is operating. It is determined that the SWM power control IC 113 can be used.

The storage control program 507 determines that the SWM 111 is not installed in the server chassis 100 by the SWM status check, or the SWM 111 is installed in the server chassis 100 and the SWM power control IC 113 is operating. If it is determined that there is no, the SWM state check is repeated at predetermined time intervals. If the SWM state check determines that the SWM 111 is connected to the storage controller 201 and the SWM power supply control IC 113 is operating, the storage control program 507 executes the next S4210.

In S4210, the storage control program 507 writes an activation request for activating the PCIe-SW 112 to the SWM control register 206. The SWM control unit 205 notifies the activation request written in the SWM control register 206 to the SWM power supply control IC 113 via the sideband signal 403. The SWM power control IC 113 activates the PCIe-SW 112 in response to the activation request. The PCIe-SW 112 is activated using the power of the main power supply 123.

Thereafter, in S4220, the storage control program 507 executes the initial setting of the PCIe-SW 112 via the lane 402. Thereafter, when the storage control program 507 completes the initial setting of the PCIe-SW 112 in S4230, the storage SVP 221 is notified of the completion of the initial setting. Thereafter, in S4240, the storage SVP 221 transmits a completion notification indicating completion of activation of the storage controller 201 and the PCIe-SW 112 to the management client 50 in response to the notification of completion of the initial setting. The management client 50 displays a screen based on the received completion notification.

Thereafter, in S4250, the administrator inputs a server unit power-on instruction for powering on the server unit 101 to the management client 50 in accordance with the display of the completion notification. In response to the input, the management client 50 transmits a server unit power-on instruction to the server SVP 121. The server SVP 121 turns on the server unit 101 in response to the server unit power-on instruction.

Thereafter, in S4260, the server unit 101 executes initial setting of the I / F-LSI 105 by the I / F-LSI driver 501. Thereafter, in S4270, when the server unit 101 completes the initial setting, the server unit 101 transmits a completion notification indicating the completion of activation of the server unit 101 to the management client 50 via the server SVP 121. The management client 50 displays a screen based on the received completion notification.

According to the above first power-on process, the storage PSU 222 is activated after the server PSU 122 is activated. As a result, the storage controller 201 can activate the PCIe-SW 112 via the SWM power supply control IC 113 after supplying power from the sub power supply 124 to the SWM power supply control IC 113.

When power is restored after a power failure, the power-on sequence as in the first power-on process is not guaranteed. Accordingly, the second power-on process when power is turned on in the order of the storage chassis 200 and the server chassis 100 will be described.

FIG. 12 shows the first part of the second power-on process. The second part following the first part of the second power-on process is the same as the second part of the first power-on process.

The operating subject in this sequence is the same as in the first power-on process.

For example, when the storage PSU 222 is first activated in S4110 due to power recovery after a power failure, the storage SVP 221 is activated by the power from the storage PSU 222. Thereafter, in S 4120, the storage SVP 221 transmits a completion notification indicating completion of activation of the storage SVP 221 to the management client 50. The management client 50 displays a screen based on the received completion notification.

Thereafter, in S4130, the storage SVP 221 turns on the power of the storage controller 201. Thereafter, in S4140, the storage control program 507 is activated and starts the initial setting. Thereafter, in S4150, the storage control program 507 executes the same SWM status check as in S3180 described above.

When the storage control program 507 determines in S4150 and S4160 that the SWM 111 is connected to the storage controller 201 and the sub power 124 is not supplied to the SWM power control IC 113, the SWM status check is performed at predetermined time intervals. repeat.

Thereafter, when the server PSU 122 is activated in S4170, the server PSU 122 supplies power to the server SVP 121 and the SWM power supply control IC 113. Thereafter, when the server SVP 121 completes the activation in S4180, the server SVP 121 transmits a completion notification indicating the completion of the activation of the server SVP 121 to the management client 50. The management client 50 displays a screen based on the received completion notification.

If the storage control program 507 determines in step S4190 that the SWM 111 is mounted on the server chassis 100 and the SWM power supply control IC 113 is operating, the storage control program 507 uses the SWM control unit 205 via the SWM control unit 205 as described above in step S4210. An instruction to turn on the PCIe-SW 112 is transmitted to the power supply control IC 113. The SWM power control IC 113 turns on the power to the PCIe-SW 112 according to the instruction. The PCIe-SW 112 is activated by the power of the main power supply 123. Subsequent processing is the same as that after S4220 described above.

According to the second power-on process described above, the storage controller 201 monitors the SWM power control IC 113 even when the server PSU 122 is activated after the storage PSU 222 is activated due to power recovery after a power failure. The PCIe-SW 112 can be controlled in response to the activation of the SWM power supply control IC 113. Further, since the power supply of the computer system is divided into the server PSU 122 and the storage PSU 222, it is possible to prevent the occurrence of a configuration check error due to the PCIe-SW recognition failure even when the storage chassis 200 is activated first.

Note that the computer system according to the second embodiment may not include the configuration for each failure processing according to the first embodiment.

The term for the expression of one embodiment of the present invention will be described. The storage device includes a drive 251 and the like. The interface device includes the I / F board 104 or the I / F-LSI 105. The first PCI Express wiring includes a PCIe wiring between the storage CPU 202 and the SWM 111. The second PCI Express wiring includes a PCIe wiring between the SWM 111 and the I / F-LSI 105 and the like. The third PCI Express wiring includes a PCIe wiring between the I / F-LSI 105 and the server CPU 102 and the like. The change process includes a process of transmitting a blocking request via a sideband signal, a process of bringing down a PCIe path, and the like. The server-side message includes an error message from the PCIe device to the server CPU 102 and the like. The storage side message includes an error message from the PCIe device to the storage CPU 202 and the like. The first sideband signal line includes a sideband signal 322 and the like. The second sideband signal line includes a sideband signal 323 and the like. The third sideband signal line includes sideband signals 404, 405 and the like. The fourth sideband signal line includes a sideband signal 403 and the like.

As mentioned above, although embodiment of this invention was described, this is an illustration for description of this invention, Comprising: It is not the meaning which limits the scope of the present invention to the said structure. The present invention can be implemented in various other forms.

DESCRIPTION OF SYMBOLS 50 ... Management client, 100 ... Server housing, 101 ... Server unit, 102 ... CPU, 103 ... Memory, 104 ... I / F board, 105 ... I / F-LSI, 107 ... Memory, 111 ... SWM, 112 ... PCIe -SW, 121 ... SVP, 122 ... PSU, 200 ... storage enclosure, 201 ... storage controller, 202 ... CPU, 203 ... memory, 221 ... SVP, 222 ... PSU, 211 ... BE interface, 250 ... drive enclosure, 251 …drive

Claims

A storage device;
A storage controller connected to the storage device;
A switch module connected to the storage controller via the first PCI Express wiring;
An interface device connected to the switch module via a second PCI Express wiring;
A server processor connected to the interface device via a third PCI Express wiring;
With
The storage controller includes a root complex of the first PCI Express tree,
The server processor includes a Root Complex of a second PCI Express tree,
The switch module belongs to the first PCI Express tree;
The interface device includes a first Endpoint connected to the second PCI Express wiring and belonging to the first PCI Express tree, and a second Endpoint connected to the third PCI Express wiring and belonging to the second PCI Express tree. ,
When the interface device detects the first failure of the second PCI Express wiring, the interface device executes a first change process for changing the state of the second PCI Express wiring, and indicates the first failure A first server side message is sent to the server processor via the third PCI Express wiring;
The storage controller detects the first failure based on a change in the state of the second PCI Express wiring,
The server processor detects the first failure based on the first server-side message;
Computer system.
When the switch module detects a second failure of the second PCI Express wiring, the switch module sends a storage side message indicating the second failure to the storage controller via the first PCI Express wiring. And
The storage controller detects the second failure based on the storage-side message, and executes a second change process for changing the state of the second PCI Express wiring for the switch module,
The interface device detects the second failure based on a change in the state of the second PCI Express wiring, and sends a second server side message indicating the second failure via the third PCI Express wiring. To the server processor
The server processor detects the second failure based on the second server side message;
The computer system according to claim 1.
The second PCI Express wiring includes a PCI Express lane and a first sideband signal line,
In the first change process, the interface device transmits a first failure notification indicating the first failure to the switch module via the first sideband signal line,
The storage controller detects the first failure based on a first failure notification in the switch module;
The computer system according to claim 2.
When the interface device detects the first failure of the second PCI Express wiring, the state of the PCI Express lane of the second PCI Express wiring is changed to a link-down state,
When the storage controller detects the second failure of the second PCI Express wiring, the storage controller changes the state of the PCI Express lane of the second PCI Express wiring to a link-down state with respect to the switch module.
The computer system according to claim 3.
When the interface device detects a third failure of the PCI Express wiring, it stores third failure information indicating the third failure,
The interface device acquires the third failure information when detecting a failure of the second PCI Express wiring, and based on the third failure information, the PCI Express lane of the PCI Express wiring having the third failure Change the status of
When a PCI Express device in the first PCI Express tree detects a fourth failure of PCI Express wiring, it stores fourth failure information indicating the fourth failure,
When the storage controller detects a failure of the second PCI Express wiring, the storage controller acquires the fourth failure information, and based on the fourth failure information, the PCI Express lane of the PCI Express wiring having the fourth failure Change the status of to link-down status,
The computer system according to claim 4.
The second PCI Express wiring further includes a second sideband signal line,
In the second change process, the switch module transmits a second failure notification indicating the second failure to the interface device via the second sideband signal line,
The interface device detects the second failure based on a second failure notification in the interface device;
The computer system according to claim 5.
In the second change process, the switch module changes the state of the second PCI Express wiring to a link-down state,
The interface device detects the second failure when detecting a link down state of the second PCI Express wiring,
The computer system according to claim 5.
A storage management processor connected to the storage controller;
A server management processor connected to the server processor;
Further comprising
When the storage controller detects a failure, the storage management processor receives information indicating the failure detected by the storage controller and causes the display device to display the information.
When the server processor detects a failure, the server-side processor receives information indicating the failure detected by the server processor and displays the information on a display device.
The computer system according to claim 1.
The interface device is connected to the plurality of storage controllers via a plurality of paths;
Each of the plurality of paths includes a PCIe path in the first PCI Express tree and a PCIe path in the second PCI Express tree;
The server processor accesses the storage controller via a specific path among the plurality of paths,
When the server processor detects a failure on the specific path, the specific path is switched to another path among the plurality of paths, and the storage controller is accessed via the switched path.
The computer system according to claim 1.
A plurality of storage controllers including the storage controller;
A plurality of switch modules including the switch module;
One or more interface devices including the interface device;
One or more server processors including the server processor;
With
The plurality of storage controllers are respectively connected to the plurality of switch modules,
Each of the plurality of switch modules is connected to the one or more interface devices;
The one or more interface devices are respectively connected to the one or more server processors;
Each of the one or more interface devices is connected to two or more switch modules of the plurality of switch modules;
The computer system according to claim 9.
A storage power supply circuit for supplying power to the storage controller;
A server power supply circuit for supplying power to the switch module, the interface device, and the server processor;
Further comprising
The computer system according to claim 1.
The switch module is
A PCI Express switch connected to the storage controller and the interface device;
A power control circuit for controlling power supply to the PCI Express switch;
Including
When the power supply control circuit is activated by power from the server power supply circuit, it transmits status information indicating that the power supply control circuit is available to the storage controller via the first PCI Express wiring,
The storage controller, according to the state information, transmits a start instruction for instructing start of the PCI Express switch to the power control circuit via the first PCI Express wiring,
The power supply control circuit activates the PCI Express switch in response to the activation instruction.
The computer system according to claim 11.
The first PCI Express wiring includes a PCI Express lane connecting the storage controller and the PCI Express switch, a third sideband signal line connecting the storage controller and the power control circuit, and the storage controller. And a fourth sideband signal line connecting between the power supply control circuits,
The power supply control circuit transmits the operation information to the storage controller via the third sideband signal line,
The storage controller transmits the activation instruction to the power supply control circuit via the fourth sideband signal line.
The computer system according to claim 12.
A computer system control method comprising:
A storage device, a storage controller connected to the storage device, a switch module connected to the storage controller via a first PCI Express wiring, and an interface connected to the switch module via a second PCI Express wiring When the interface device detects a first failure of the second PCI Express wiring in the computer system, including a device and a server processor connected to the interface device via a third PCI Express wiring , Using the interface device, to execute a first change process to change the state of the second PCI Express wiring, the first server-side message indicating the first failure is sent via the third PCI Express wiring To the server processor
Using the storage controller, based on the change in the state of the second PCI Express wiring, detect the first failure,
Using the server processor to detect the first failure based on the first server side message;
Prepared
The storage controller includes a root complex of the first PCI Express tree,
The server processor includes a Root Complex of a second PCI Express tree,
The switch module belongs to the first PCI Express tree;
The interface device includes a first Endpoint connected to the second PCI Express wiring and belonging to the first PCI Express tree, and a second Endpoint connected to the third PCI Express wiring and belonging to the second PCI Express tree. ,
Control method.