WO2016157511A1 - Low noise amplifier, and ultrasonic probe and diagnostic device using same - Google Patents

Abstract

The LNA has a sampling switch as a load. A method to reduce the ON-resistance of the sampling switch is to connect a source follower circuit to the output stage to lower the common voltage of output signals while lowering the output impedance, but this method leads to a problem regarding increase in power consumption. In order to solve this problem, a common node of a differential transistor pair constituting a differential amplifier at the first stage of the LNA is connected to a node shared by drain terminals of transistors constituting a differential source follower at the second stage. Thus, the source follower current at the second stage is reused by the differential amplifier at the first stage.

Description

Low noise amplifier, ultrasonic probe and diagnostic device using the same

The present invention relates to a receiving amplifier that is mounted on an electronic circuit, particularly an ultrasonic probe that is a component of an ultrasonic diagnostic apparatus, and amplifies an electric signal from a piezoelectric vibrator.

2. Description of the Related Art A medical ultrasonic diagnostic apparatus that inspects the inside of a human body by transmitting an ultrasonic wave into the human body and receiving a signal reflected from a component inside the body is known. In such an ultrasonic device, the received ultrasonic signal is converted from sound pressure to an electrical signal by a transducer array composed of a plurality of piezoelectric vibrators (transducers), and the reception delay amount in the array is adjusted. It is known to adjust the focus point. As a method of delaying a received signal, there are a method such as an analog beamformer that delays an analog signal as it is, and a digital beamformer that performs analog-digital conversion and performs delay addition in the state of a digital signal. As an example of an analog beamformer, a method of delaying an analog voltage output by sequentially sampling an input voltage by a plurality of parallel sampling circuits and delaying a read timing is known. Even in the case of analog-digital conversion, it is common to digitize after holding the analog voltage once using a sample hold circuit. A low noise amplifier (LNA) is installed between the delay adder circuit and the transducer, and is used to amplify an input signal and drive a delay adder circuit in the subsequent stage. The received signal converted by the transducer exists from a weak signal reflected from the deepest part of the human body to a relatively large signal reflected from the vicinity of the body surface. Therefore, since the LNA transmits the weakest signal at the deepest part to the subsequent circuit with a sufficient S / N ratio, the LNA is required to have a low intrinsic noise and a sufficient gain, and the signal from the vicinity of the body surface. A wide dynamic range that does not saturate even when a signal is received is required. In addition, since a large number of receiving circuits are required corresponding to the transducer array, it is also required to reduce the circuit area and power consumption.

JP2012-070282

In an apparatus having a circuit that samples a voltage at a subsequent stage of the receiving LNA, such as an ultrasonic diagnostic apparatus, in order to charge the sampling capacitor at a sufficient speed with respect to the sampling rate, the output impedance of the LNA is lowered, The on-resistance needs to be lowered. When the sampling switch is NMOS, it is desirable that the output voltage of the LNA operate in a low range in order to reduce the on-resistance. On the other hand, from the viewpoint of signal amplification, the use of NMOS as the LNA amplification MOS is more advantageous than the use of PMOS from the viewpoint of area and mutual conductance. In such a case, the center voltage of the output signal may be increased, and it is desirable to perform a DC level shift that lowers the center voltage. By having a source follower circuit in the output stage of the LNA, these requirements can be satisfied, but the problem is that the power consumption increases.

By connecting the common node of the differential MOS pair constituting the differential amplifier of the LNA first stage to the common drain terminal of the MOS constituting the second stage differential source follower, the second stage source follower current is supplied to the first stage differential amplifier. Reuse even with differential amplifiers.

According to the above-described means, since the current can be reused without using a special capacitance or inductance element, an increase in power consumption can be prevented, and the amount of current flowing in the first stage amplifier circuit can be reduced without reducing the LNA. It is possible to add a source follower circuit to the output of. Therefore, it is possible to reduce the output impedance and the on-resistance of the sampling switch while maintaining the amplification gain and noise performance of the first stage of the LNA, which were the initial problems.

According to another aspect of the present invention, a transducer that performs both electro-acoustic and acoustic-electrical conversion is configured, a vibrator having a first terminal connected to the ground (reference potential point), and a second of the vibrator. This is an ultrasonic diagnostic apparatus having a transmitter connected to the terminal and a receiver connected to the second terminal of the transducer. The receiver has a differential output amplifier having a single-ended input connected to the second terminal of the transducer via a duplex switch.

FIG. 6 is a diagram illustrating Example 1; FIG. 6 is a diagram for explaining an operation related to a differential amplifier portion of the first embodiment. FIG. 3 is a diagram for explaining an operation related to the source follower circuit according to the first embodiment. FIG. 6 is a diagram illustrating Example 2. FIG. 6 is a diagram illustrating Example 3; FIG. 6 is a diagram illustrating a sampling mechanism according to a third embodiment. FIG. 6 is a diagram illustrating a sampling switch according to a third embodiment. FIG. 10 is a diagram for explaining the operation of the third embodiment. FIG. 6 is a diagram illustrating Example 4; FIG. 6 is a diagram illustrating Example 5; FIG. 10 is a diagram illustrating a configuration of a subarray according to a fifth embodiment.

FIG. 1 shows an embodiment of an amplifier circuit according to the first embodiment.

In the following description, the transistor is assumed to be a MOSFET, but there is no problem even if a bipolar transistor is used instead. In that case, the gate terminal, the source terminal, and the drain terminal of the transistor described below are respectively a base terminal, What is necessary is just to replace as an emitter terminal and a collector terminal. In addition, the usage of the NMOS transistors and PMOS transistors described in the following embodiments is complementary, and it can be obtained in advance that the same effect can be obtained by replacing all NMOS with PMOS and PMOS with NMOS. It should be noted.

In this embodiment, the source terminals of the transistors 101 and 102 and the drain terminals of the transistors 103 and 105 are all connected to the common node A by wiring, and the drain terminals of the transistors 101 and 102 are connected to the drain terminals of the transistors 101 and 102, respectively. A load circuit 105 is connected.
Further, current sources 106 and 107 are connected to the source terminals of the transistors 103 and 104, respectively.

The gate terminal of the transistor 101 is connected to the positive input terminal inp, and the gate terminal of the transistor 102 is connected to the negative input terminal inn.
The source terminal of the transistor 103 is connected to the positive output terminal outp, and the source terminal of the transistor 104 is connected to the negative output terminal outn. The load circuit 105 is connected to a positive power source 108, and the current sources 106 and 107 are connected to a negative power source 109. The negative power source 109 may be grounded.

The following describes the operation of the above circuit.

When differential signals are input to the transistors 103 and 104, the current generated in association with the signals input to inp2 and inn2 cancels between the differentials at the node A, so that the AC voltage signal at the node A is affected. Not give.

On the other hand, the direct current sum of the current sources 106 and 107 biasing the 103 and 104 flows through the node A as a direct current. Therefore, when the node A is viewed from the transistors 101 and 102 side, it can be seen that the circuit operates as an equivalent circuit as shown in FIG.

Here, the resistor 203 has impedances 103 and 104 viewed from the 101 and 102 sides in FIG. 1, and the equivalent circuit in FIG. 2 operates as a differential amplifier having outp1 and outn1 as output terminals.

Next, the influence of the AC voltage at the node A in FIG. 1 on the outputs of the transistors 103 and 104 will be described. Assuming that the AC signal source 301 as shown in FIG. 3 is connected to the node A instead of the transistors 101 and 102, the influence of the AC signal source 301 appears equally as a common mode voltage at the outp2 and outn2 nodes. Therefore, it is canceled between differentials.

Further, when the AC signal source 301 is excluded, the transistor 303 operates as a source follower circuit biased by the current source 306 and the voltage source 302 with respect to the input signal to the input terminal inp2. The same applies to 304, 305, and 302. Therefore, the transistors 103 and 104 and the current sources 106 and 107 in FIG. 1 can operate as a differential source follower circuit.

As described above, in the connection relationship of FIG. 1, two circuits of the differential amplifier and the source follower circuit operate by the pair of current sources 106 and 107.

In the following, the effect of this embodiment will be described.

When configuring a circuit having a differential amplifier and a differential source follower, it is common to have independent current sources for each. At this time, if the currents flowing through the respective current sources are ISC [A] and ISF [A], a total amount of current (ISC + 2 * ISF) [A] is required.
On the other hand, in this embodiment, since the ISF [A] biases the transistor of the differential amplifier via the transistor constituting the source follower, the differential amplifier is operated by biasing with 2 * ISF [A]. In this case, two circuits can be operated with a current of 2 * ISF [A] in total, and power consumption corresponding to ISC [A] can be reduced.

In this way, the concept of current reuse that uses the current of one circuit block as the bias current of another circuit block is, for example, as disclosed in [Patent Document 1]. For example, it is used for the source grounding circuit of the next stage.

However, in the disclosed example, a special capacitive element is required to show the source terminal of the next stage transistor as ground (DC voltage).

In order to secure a capacitance value necessary for canceling the AC component, a relatively large occupied area is required in the integrated circuit, so that it is difficult to realize in applications where a large number of elements are mounted in the integrated circuit.

Further, in [Non-patent Document 1] in which current reuse is performed between a differential amplifier and a source follower circuit, an alternating current component is inserted by inserting an inductance component into a direct current path shared by the first stage transistor and the next stage transistor. Is prevented from being transmitted.

However, in a frequency band of several MHz or less, for example, the inductance value necessary to block the AC component becomes very large, from several hundred uH to several mH, and such a huge inductance component is formed in the integrated circuit. Difficult to do.

In this embodiment, in the differential source follower circuit, paying attention to the fact that the drain terminals of the transistors constituting the source follower circuit cancel each other out as an AC signal, the common terminal of the differential amplifiers uses the drain terminal of the source follower as a DC bias point. By using it as a source terminal, no special capacitance or inductance component is required, and the current reuse of the differential amplifier and the source follower circuit is realized, and the circuit is mounted with high density in the integrated circuit. It becomes possible to do.

FIG. 4 shows an embodiment of an amplifier circuit according to the second embodiment.

In the second embodiment, in addition to the first embodiment, the current source 410 is connected to the common node A and the negative power source 409, and the current source 411 is connected to the common node A and the positive power source 408. Yes. Here, only one of the current source 410 and the current source 411 may be present, or both may be present. Here, the current value of 410 is I1, and the current value of 411 is I2.

In the following, the effect of this embodiment will be described.

In the first embodiment, since the transistors 103 and 104 constituting the source follower and the transistors 101 and 102 constituting the differential amplifier are biased by the common bias current sources 106 and 107, respectively, the respective bias currents are set independently. I can't. In other words, if the bias current of the differential amplifier is ISC and the bias current on one side of the source follower is ISF, the relationship is ISC = 2 * ISF.

Therefore, according to the configuration of the second embodiment, since ISC + I2 = I1 + 2 * ISF, ISC and ISF can be freely set by appropriately selecting I1 and I2 (however, ISC, ISF, I1 and I2 are all current values of 0 or more). This allows you to increase the ISF to reduce the output impedance of the source follower, but when individual design events occur, such as when you want to reduce the gain of the differential amplifier, design each block independently. Can be done.

FIG. 5 shows an embodiment of a two-stage amplifier according to the third embodiment.

In the third embodiment, in addition to the first embodiment, the drain terminals of the transistors 501 and 502 constituting the differential amplifier are connected to the gate terminals of the transistors 503 and 504 constituting the source follower circuit, respectively. . The output nodes of the source follower are connected to sampling switches 510 and 511, respectively, and a sampling capacitor 512 is connected to the outputs of the sampling switches 510 and 511. Both sampling switches 510 and 511 are controlled by a control signal φ.

The following describes the operation of this embodiment.

Fig. 6 shows the transient response on the time axis of the voltage across the control signal and sampling capacity. A waveform 601 is a time waveform of the voltage Vc [V] across the sampling capacitor, and a waveform 602 is a time waveform of a control signal for turning on and off the sampling switch. At time 0 seconds, when the voltage across the sampling capacitor is 0 [V] and the differential voltage output from the source follower circuit is V0 [V], the control signal 602 changes from Voff [V] to Von [V]. The charging and discharging of the sampling capacitor 512 starts from the moment of transition, and Vc ideally approaches the input voltage V0.

The control signal φ transitions to Voff [V] at a finite time T [seconds], and the sampling period is terminated. At this time, the difference ΔV [V] between the input voltage V0 and the sampling capacitance voltage Vc appears as an error in the output. Here, when the output impedance of the LNA is Ro [ohm], the output impedance of the sampling switch is Ron [ohm], and the capacitance value of the sampling capacitor is Cs [F], Vc when viewed from the output end of the LNA is a primary transient response. The transfer function Z (jω) is expressed by Equation 1.

(Equation 1)
Z (jω) = 1 / (1 + jω / ω_C)

Here, j is an imaginary unit, and ω is each frequency of the input signal. Further, ωc [rad] is a constant represented by Equation 2.

(Equation 2)
ω_C = 1 / (2π (R_O + R_ON) C_S)

Therefore, the time response of Vc can be expressed as Equation 3.

(Equation 3)
V_C (t) = V_0 (1-e ^ (-ω_C (t-t_1))))

From this, the error ΔV is obtained as shown in Equation 4.

(Equation 4)
ΔV = V_0−V_C (t_2) = V_0−V_0 (1-e ^ (− ω_C (t−t_1))) = e ^ (− ω_C T)

Therefore, ωc may be designed based on Equation 2 so that ΔV is sufficiently smaller than a desired error for a given sampling period T [seconds]. The above formula shows that the error ΔV decreases as Ro and Ron decrease.

Next, the relationship between the output voltage range of the LNA and the switch resistance Ron will be described.

When the sampling switch is realized by a transistor, a CMOS switch using a PMOS transistor 701 and an NMOS transistor 702 can be used as shown in FIG. The two terminals other than the gate terminals 701 and 702 are connected to either the input terminal or the output terminal, respectively, and the control signal φ is input to the gate 702, and a signal obtained by logically inverting the control signal φ is 701. It is input to the gate.

As described at the beginning, an NMOS transistor only switch has a high on-resistance when the input voltage is high, and a PMOS transistor alone has a high on-resistance when the input voltage is low.

Therefore, it is generally known to use both NMOS and PMOS as shown in FIG. 7A to reduce the on-resistance in both the high and low input voltage regions.

However, depending on the specifications of the semiconductor process, only a transistor with a high threshold can be used. In this case, both the MOS transistors 701 and 702 have high on-resistance in the vicinity of the center of the positive and negative power supplies. As shown in FIG. 4, a region having a high on-resistance is generated.

FIG. 8 shows the relationship between the signal of each node and the on-resistance of the sampling switch in this embodiment.

801 is a signal input to inp1 in FIG. 5, 802 and 803 are signals observed at nodes P1 and N1, respectively, and 804 and 805 are signals observed at nodes P2 and N2.

The signals of P1 and N1 ideally pass through the source follower circuit, the common mode voltage is shifted, and the AC component is output as it is.

As a result, the output signals 804 and 805 can be output in a region with a low on-resistance as indicated by 806 in the right diagram of FIG. 8, and it is not necessary to use a PMOS transistor for the sampling switch.

In the present embodiment, even when a differential AC signal as a pair is input to the transistors 501 and 502 or when an AC signal is input to only one side of the input terminal, there is no difference between the drain terminals of 501 and 502. Dynamic AC signal is output.

Therefore, as in the first embodiment, the first-stage differential amplifier and the latter-stage source follower operate in a state where the bias current sources 506 and 507 are shared, and the power is reduced compared to the case where each has a current source independently. It is possible.

FIG. 9 shows an embodiment of a two-stage amplifier according to the fourth embodiment.

In the fourth embodiment, resistors 911 and 912, transistors 913 and 914, and a common mode feedback circuit 905 are connected as an example of the load circuit of the transistors 101 and 102 in the first embodiment.

In this embodiment, the nodes to which the transistors 901 and 902 are connected are referred to as a node P1 and a node N1, respectively. The resistors 911 and 912 share a node on one side, and the unshared side is connected to the node P1 and the node N1, respectively. Transistors 913 and 914 have drain terminals connected to node P1 and node N1, respectively, gate terminals connected to a common node, and source terminals connected to a positive power supply 908. The node shared by the resistors 911 and 912 is connected to the input of the common mode feedback circuit 905, and the output of the common mode feedback circuit 905 is input to the gate terminals of the transistors 913 and 914. The nodes P1 and N1 are connected to the capacitors 915 and 916, respectively. The terminals of the capacitors 915 and 916 that are not connected to the nodes P1 and N1 are connected to the gate terminals of the transistors 903 and 904, respectively.

Further, resistors 917 and 918 are connected to the gate terminals of the transistors 903 and 904, respectively, and terminals on the opposite side of 917 and 918 are connected to power supplies 919 and 920, respectively.

The operation of this embodiment is described below.

In the fourth embodiment, it is necessary to appropriately set the bias voltages of the transistors 913 and 914. When the resistors 911 and 912 have the same resistance value, the common voltage of P1 and N1 is applied to the common node of both companies. The common mode feedback circuit 905 inputs the common voltage of the P1 and N1 nodes to the common mode feedback circuit 905 and performs feedback connection to the gates of 913 and 914, so that the common mode feedback circuit 905 has an appropriate common voltage for P1 and N1. The gate voltages of the transistors 913 and 914 are automatically searched.

Capacitors 915 and 916 separate the output node of the differential amplifier and the input node of the source follower circuit in a DC manner, and the DC bias point of the input node of the source follower circuit is determined by the output voltage values of the voltage sources 919 and 920. .

FIG. 10 shows an embodiment of an ultrasonic diagnostic apparatus according to the fifth embodiment.

FIG. 10 shows a system configuration diagram of an ultrasonic diagnostic apparatus to which the present invention is applied. In recent years, an ultrasonic diagnostic apparatus capable of obtaining a three-dimensional stereoscopic image has been developed, and inspection efficiency can be improved by obtaining a tomographic image by specifying an arbitrary cross section from the three-dimensional stereoscopic image. For three-dimensional imaging, it is necessary to change the transducers in the ultrasonic probe from the conventional one-dimensional array to the two-dimensional array, and the number of transducers is 2 compared to the conventional ultrasonic probe. Increases to the power. In this case, since it is impossible to increase the number of cables connecting the ultrasonic probe and the main unit by the square, the received signal with the number reduced by phasing addition in the ultrasonic probe is reduced. It must be transferred to the main unit via a cable.

FIG. 10 shows an ultrasonic probe having a two-dimensional array transducer and a system configuration. In the ultrasonic probe 1000, a transmission / reception circuit 1002 is arranged for each transducer 1001, and reception outputs are added by an addition circuit 1003 and sent to an AFE (analog front end) 1004 of the main unit. A grouping unit of transducer channels to be added is called a subarray 1005. Each subarray 1005 has a subarray control logic circuit 1006 for controlling the subarray. The subarray is implemented by a configuration in which a plurality of transducers 1001 are connected to an IC 1007 (indicated by a dotted line) including a plurality of subarrays 1005 including a transmission / reception circuit 1002, an adder circuit 1003, and a subarray control logic circuit 1006.

The processor 1009 in the main body device 1008 sends a control signal to the control logic circuit 1010 of the IC 1007 in the ultrasonic probe 1000, and the IC control logic circuit 1010 controls transmission / reception switching and the like accordingly. For example, the transmission / reception switching can be controlled collectively by the subarray 1005 to reduce the number of control signals in the IC control logic circuit and IC. Alternatively, as shown in FIG. 10, a sub-array control logic circuit 1006 can be arranged for each sub-array, and control can be hierarchized to control each transmission / reception circuit 1002 independently from the sub-array control logic circuit 1006 with fine granularity.

FIG. 11 shows the configuration in the subarray 1005. The transmission / reception circuit 1002 per transducer is composed of a high voltage MOS, and generates a high voltage signal to drive the transducer 1001. The transmission circuit 1100 is turned off during transmission, protects the LNA from the high voltage signal, and is turned on during reception. And a transmission / reception separation switch 1101 for passing an electrical signal from the vibrator, a low-pressure reception LNA 1102, a beam forming by delaying the transmission signal, and a delay circuit 1103 for delaying the reception signal to perform phasing. . The received signals phased by the minute delay circuit 1103 are added by the adder circuit 1003 and transferred to the main unit. In FIG. 11, as an example of control, a gain control logic circuit 1104 is prepared for each column of the transducer array, and the LNA gain is independently controlled for each column. As a result, it is possible to control to lower the LNA gain in units of columns as going to the left and right outside of the array. Also in this example, parts other than the vibrator 1001 are integrated as an IC.

Here, the reception LNA 1102 includes a differential amplifier that amplifies the single-ended input from the vibrator described in the first to fifth embodiments, and outputs a differential signal.

According to the embodiment of the present invention described above, an LNA that amplifies an electric signal from an ultrasonic transducer constituting a transducer that performs both electro-acoustic and acoustic-electric conversion, and performs single-ended-differential conversion. In this case, the current can be reused without using a special capacitor or inductance element, so that an increase in power consumption can be prevented and the source follower can be added to the output of the LNA without reducing the amount of current flowing through the first stage amplifier circuit. It is possible to add a circuit.

This makes it possible to reduce the output impedance and the on-resistance of the sampling switch while maintaining the amplification gain and noise performance of the first stage of the LNA, so that the current and area of the LNA are not increased. In addition, it can contribute to the improvement of the image quality in the deep part of the living body.

Also, since the differential amplification type LNA is used, the influence of the power supply noise wraparound from the digital circuit to the analog circuit can be reduced by a high power supply voltage fluctuation rejection ratio, so that analog / digital mixed mounting of the integrated circuit becomes possible. Complex control logic of ultrasonic beam forming, focusing, and phasing can be integrated on one chip together with analog circuits for transmission and reception, and the mounting space and cost of the ultrasonic probe and the main unit can be reduced.

The present invention is not limited to the above-described embodiment, and includes various modifications. For example, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace the configurations of other embodiments with respect to a part of the configurations of the embodiments.

101 ... Transistor, 102 ... Transistor, 103 ... Transistor, 104 ... Transistor, 105 ... Load circuit, 106 ... Bias current source, 107 ... Bias current source, 108 ... -Positive power supply, 109 ... Negative power supply, 201 ... Transistor, 202 ... Transistor, 203 ... Equivalent resistance, 204 ... Equivalent current source, 205 ... Load circuit, 206 ... Positive Power source, 207 ... Negative power source, 301 ... Equivalent AC signal source, 302 ... Equivalent DC bias, 303 ... Transistor, 304 ... Transistor, 305 ... Bias current source, 306 ... Bias current source, 307 ... Negative power supply, 401 ... Transistor, 402 ... Transition 403 ... transistor 404 ... transistor 405 ... load circuit 406 ... bias current source 407 ... bias current source 408 ... positive power source 409 ... negative power source 410, current source, 411, current source, 501 ... transistor, 502 ... transistor, 503 ... transistor, 504 ... transistor, 505 ... load circuit, 506 ... Bias current source, 507 ... Bias current source, 508 ... Positive power supply, 509 ... Negative power supply, 510 ... Sampling switch, 511 ... Sampling switch, 512 ... Sampling capacity, 601 ...・ Sampling capacity terminal complete voltage waveform, 602 ... Sampling switch control 701 ... PMOS transistor, 702 ... NMOS transistor, 703 ... On resistance of CMOS switch, 801 ... Input signal, 802 ... Negative output signal of differential amplifier, 803 ... Positive output signal of differential amplifier, 804 ... LNA negative output signal, 805 ... LNA positive output signal, 806 ... On-resistance of CMOS switch, 901 ... Transistor, 902 ... Transistor, 903 ... Transistor, 904 ... Transistor, 905 ... Common mode feedback circuit, 906 ... Bias current source, 907 ... Bias current source, 908 ... Positive power supply, 909 ... Negative power supply 911 ... Load resistance, 912 ... Load resistance, 913 ... Transitions 914 ... transistor, 915 ... DC blocking capacity, 916 ... DC blocking capacity, 917 ... resistance, 918 ... resistance, 919 ... power supply, 920 ... power supply, 1000 ..Ultrasonic probe, 1001... Transducer, 1002... Transceiver circuit, 1003... Adder circuit, 1004... Analog front end, 1005. Circuit, 1007 ... IC, 1008 ... Main unit, 1009 ... Processor, 1010 ... Control logic circuit, 1100 ... Transmission circuit, 1101 ... Transmission / reception separation switch, 1102 ... Reception LNA DESCRIPTION OF SYMBOLS 1103 ... Minute delay circuit, 1104 ... Gain control logic circuit

Claims (16)

1. A pair of two transistors 1 and 2 whose source terminals are connected to each other, a differential amplifier composed of a load circuit connected to the respective drain terminals of the transistors 1 and 2, and the drain terminals are connected to each other In a differential source follower circuit comprising a set of two transistors 3 and 4 and a current source 1 and a current source 2 connected to the transistors 3 and 4, respectively, the transistors 1 and 2 A low-noise amplifier characterized in that a node to which each source terminal is connected and a node to which each drain terminal of the transistors 3 and 4 is connected are the same.
2. 2. The low noise amplifier according to claim 1, wherein drain terminals of a set of two transistors 1 constituting the differential amplifier are connected to a gate terminal of a transistor 3 constituting the differential source follower circuit. The drain terminal of the transistor is connected to the gate terminal of the transistor 4 constituting the differential source follower circuit.
3. 2. The low noise amplifier according to claim 1, wherein a current source different from the current source constituting the differential amplifier is connected to a node to which the source terminals of the transistors 1 and 2 constituting the differential amplifier are connected. A low noise amplifier characterized by being connected.
4. 2. The low noise amplifier according to claim 1, comprising an input terminal and an output terminal, and a signal obtained by adding an AC electrical signal input to the input terminal and a DC voltage signal that is the same as or different from the DC voltage input to the input terminal. The DC voltage shift circuit 1 is connected to the drain terminal of the transistor 1 constituting the differential amplifier, and the DC voltage shift circuit 2 having the same function as the DC voltage shift circuit 1 is connected to the differential terminal. A low noise amplifier characterized by being connected to a drain terminal of a transistor 2 constituting the amplifier.
5. 2. The low noise amplifier according to claim 1, wherein a capacitor terminal 1-1 of a capacitor element 1 having a capacitor terminal 1-1 and a capacitor terminal 1-2 is connected to a drain terminal of the transistor 1 constituting the differential amplifier. A bias circuit 1 that applies a DC voltage to the capacitance terminal 1-2 of the capacitive element 1 is connected to a gate terminal of the transistor 3 that constitutes the differential source follower circuit, and a drain terminal of the transistor 2 that constitutes the differential amplifier. Are connected to a capacitor terminal 2-1 of a capacitor element 2 having a capacitor terminal 2-1 and a capacitor terminal 2-2, and a bias circuit 2 for applying a DC voltage to the capacitor terminal 2-2 of the capacitor element 2 and the differential source A low-noise amplifier characterized in that the gate terminal of a transistor 4 constituting a follower circuit is connected.
6. 6. The low noise amplifier according to claim 5, wherein the bias circuit 1 and the bias circuit 2 are a bias circuit including a resistance element having a terminal 1 and a terminal 2 and a power supply circuit for supplying a DC voltage, A power supply circuit in the bias circuit is connected to a terminal 1 of the resistor element, and a terminal 2 of the resistor element is used as an output.
7. 2. The low noise amplifier according to claim 1, wherein an input terminal of the sample circuit 1 holding an input voltage is connected to a source terminal of the transistor 3 constituting the differential source follower circuit, and the differential source follower circuit is provided. A low-noise amplifier characterized in that the input terminal of the sample circuit 1 that holds the input voltage is connected to the source terminal of the transistor 4 that constitutes the transistor.
8. A sound wave oscillator and an amplifier for amplifying an electric signal from the sound wave oscillator are mounted, and the amplifier includes a pair of transistors 1 and 2 whose source terminals are connected to each other, and the transistor 1 and the transistor A differential amplifier composed of a load circuit connected to each of the two drain terminals, a set of two transistors 3 and 4 whose drain terminals are connected to each other, and the transistor 3 and the transistor 4 respectively. In the differential source follower circuit composed of the current source 1 and the current source 2, the node to which the source terminals of the transistors 1 and 2 are connected and the drain terminals of the transistors 3 and 4 are connected. An ultrasonic probe characterized by having identical nodes.
9. The ultrasonic probe according to claim 8, wherein drain terminals of a set of two transistors 1 constituting the differential amplifier are connected to gate terminals of transistors 3 constituting the differential source follower circuit, An ultrasonic probe, wherein a drain terminal of the transistor 2 is connected to a gate terminal of the transistor 4 constituting the differential source follower circuit.
10. 9. The ultrasonic probe according to claim 8, wherein a node connected to a source terminal of each of the transistors 1 and 2 constituting the differential amplifier is different from a current source constituting the differential amplifier. An ultrasonic probe, characterized in that a current source is connected.
11. 9. The ultrasonic probe according to claim 8, comprising an input terminal and an output terminal, wherein an AC electrical signal input to the input terminal and a DC voltage signal that is the same as or different from the DC voltage input to the input terminal are added. The DC voltage shift circuit 1 is connected to the drain terminal of the transistor 1 constituting the differential amplifier, and the DC voltage shift circuit 2 having the same function as the DC voltage shift circuit 1 An ultrasonic probe connected to a drain terminal of a transistor 2 constituting a differential amplifier.
12. 9. The ultrasonic probe according to claim 8, wherein a capacitor terminal 1-1 of a capacitor element 1 having a capacitor terminal 1-1 and a capacitor terminal 1-2 is connected to a drain terminal of the transistor 1 constituting the differential amplifier. The bias circuit 1 for applying a DC voltage to the capacitance terminal 1-2 of the capacitive element 1 and the gate terminal of the transistor 3 constituting the differential source follower circuit are connected, and the transistor 2 constituting the differential amplifier is connected. The capacitance terminal 2-1 of the capacitive element 2 having the capacitive terminal 2-1 and the capacitive terminal 2-2 is connected to the drain terminal, and the bias circuit 2 for applying a DC voltage to the capacitive terminal 2-2 of the capacitive element 2 and the differential An ultrasonic probe, wherein a gate terminal of a transistor 4 constituting the source follower circuit is connected.
13. 13. The ultrasonic probe according to claim 12, wherein the bias circuit 1 and the bias circuit 2 are a bias circuit including a resistance element having a terminal 1 and a terminal 2 and a power supply circuit for applying a DC voltage, An ultrasonic probe, wherein a power supply circuit in the bias circuit is connected to a terminal 1 of a resistance element in the bias circuit, and a terminal 2 of the resistance element is used as an output.
14. 9. The low noise amplifier according to claim 8, wherein an input terminal of the sample circuit 1 that holds an input voltage is connected to a source terminal of the transistor 3 that constitutes the differential source follower circuit, and the differential source follower circuit. An ultrasonic probe, characterized in that the input terminal of the sample circuit 1 that holds the input voltage is connected to the source terminal of the transistor 4 that constitutes the above.
15. A transducer that performs both electro-acoustic and acoustic-electrical conversion, a vibrator having a first terminal connected to a ground, a transmitter connected to a second terminal of the vibrator, and the vibration A receiver connected to a second terminal of the child, the receiver comprising a set of two transistors 1 and 2 whose source terminals are connected to each other, and each of the transistors 1 and 2 A differential amplifier comprising a load circuit connected to the drain terminal; a set of two transistors 3 and 4 whose drain terminals are connected to each other; and a current source 1 connected to each of the transistors 3 and 4 In the differential source follower circuit comprising the current source 2 and the current source 2, the source terminals of the transistors 1 and 2 are connected to each other. And has a node the transistor 3 and the ultrasonic diagnostic apparatus nodes respective drain terminals of the transistor 4 is connected, characterized in that it comprises an amplifier is the same.
16. The ultrasonic diagnostic apparatus according to claim 15, comprising a plurality of sets of the vibrator, transmitter, and receiver, wherein the plurality of transmitters and receivers are mounted on a single IC. Diagnostic device.
    

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