WO2016144368A1

WO2016144368A1 - Frequency of a clock signal

Info

Publication number: WO2016144368A1
Application number: PCT/US2015/020280
Authority: WO
Inventors: John A WICKERAAD
Original assignee: Hewlett Packard Enterprise Development Lp
Priority date: 2015-03-12
Filing date: 2015-03-12
Publication date: 2016-09-15

Abstract

Examples disclosed herein relate, in one aspect, to an electronic device. The electronic device may include a plurality of processors and a clock generator. The clock generator may provide a clock signal to the plurality of processors, and obtain workload information indicative of workloads of each of the plurality of processors. Based on the workload information, the clock generator may determine whether to change a frequency of the clock signal, where changing the frequency may include increasing or decreasing the frequency. The clock generator may then change the frequency based on the determination.

Description

FREQUENCY OF A CLOCK SIGNAL

BACKGROUND

[0001 ] An electronic device may include a number of processors processing data simultaneously. The amount of data being processed by each processor may be nonuniform and different processors may experience peak workloads at different times. Accordingly, at a given point in time, some processors may be busy (e.g., working at their capacity) while others may be idle or have small workloads.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The following detailed description references the drawings, wherein:

[0003] FIG. 1 is a block diagram of an example electronic device;

[0004] FIG. 2 is a block diagram of another example electronic device; and

[0005] FIG. 3 is a flowchart of an example method for changing a frequency of a clock signal.

DETAILED DESCRIPTION

[0006] As mentioned above, an electronic device may include a number of processors that may sometimes process data in parallel. The processors may be similar or different in type, function, and processing power. Some processors may be arranged in pipeline configuration where an output of one processor is connected to an input of another processor. Accordingly, in some examples, a workload of one processor may change over time, and at a given point of time workloads of different processors may be different. The speed at which each processor operates and processes data may be determined, at least in part, by a frequency of a clock signal driving the processor. A higher clock frequency may increase a processor's performance and computational capacity, allowing the processor to process more data per unit of time, and to avoid loss of data and other undesirable effects during peak workloads. However, a higher clock frequency may also cause higher power consumption and heat generation by the processor.

[0007] Examples disclosed herein describe, among other things, an electronic device. The electronic device may include, among other things, a plurality of processors and a clock generator. The clock generator may provide a clock signal to the plurality of processors, and obtain workload information indicative of workloads of each of the plurality of processors. Based on the workload information, the clock generator may determine whether to change a frequency of the clock signal, where changing the frequency may include increasing or decreasing the frequency. The clock generator may then change the frequency based on the determination.

[0008] FIG. 1 is a block diagram of an example electronic device 100. Electronic device 100 may include any type of electronic devices or combinations thereof. For example, electronic device 100 may be a network device (e.g., a network switch, a network router, etc.) to receive and/or send network packets from and/or to one or more networks. Other examples of electronic device 100 include a server, a desktop computer, a notebook computer, a tablet computer, a mobile phone, a smartphone, a gaming device, a printing device, and so forth.

[0009] In some examples, electronic device 100 may include a plurality of (e.g., two or more) processors 120. In the example illustrated in FIG. 1 , electronic device 100 includes N processors 120, referred to as processors 120-1 - 120-N. Each processor 120 may include one or multiple processors, such as central processing units (CPUs), semiconductor-based microprocessors, hardware state machines, graphics processing units (GPUs), field-programmable gate arrays (FPGAs), or other electronic circuitry, which may be integrated in a single device or distributed across devices. In some examples, each processor 120 may also be implemented as a combination of hardware and programming, as will be further discussed below. Any two processors 120 may be similar or different in terms of their type, function, processing power, and other characteristics. For example, one processor 120 may be dedicated to communicating with and receiving data (e.g., network packets) from other electronic devices; another processor 120 may be dedicated to processing (e.g., checking for errors, updating the data and/or its header information, etc.) the received data; another processor 120 may be dedicated to obtaining the processed data and to communicating with and sending the processed data to other electronic devices; and so forth. In some examples, one or more processors 120 may be dedicated to implementing routing protocols, scanning data for viruses, performing Quality of Service (QoS), performing Access Control Lists (ACLs) lookups, and the like.

[0010] Accordingly, any processor 120 may be coupled to one or more other processors 120, and may transfer information to and/or from one or more other processors 120. In some examples, one or more processors 120 may be able to receive input data from one or more other electronic devices through one or more input ports of electronic device 100, and/or to send output data to one or more other electronic devices through one or more output ports of electronic device 100. As mentioned above, in some examples, some or all processors 120 may be working and processing data simultaneously.

[001 1 ] In some examples, electronic device 100 may include a clock generator 1 10. Clock generator 1 10 may include any type of circuitry capable of generating one or more clock signals, where each clock signal may be characterized by a particular frequency. In some examples, clock generator 1 10 may include or be coupled to one or more phase-locked loop (PLL) modules. In some examples, clock generator 1 10 may also be implemented as a combination of hardware and programming, as will be further discussed below.

[0012] In some examples, clock generator 1 10 may generate and provide a clock signal 140 to a plurality of processors 120, where the plurality may include two or more, or all of processors 120 within electronic device 100. Specifically, in some examples, a clock output of clock generator 1 10 may be electronically coupled (e.g., via a wire) to clock inputs of a plurality of processors 120. In other examples, clock generator 1 10 may generate and provide different clock signals to different groups of processors 120.

[0013] Clock signal 140 may have a certain frequency that, in some examples, may be changed by clock generator 1 10. For example, clock generator 1 10 may increase or decrease the frequency of clock signal 140, as will be discussed below. In some examples, clock generator 1 10 may set or change the frequency of clock signal 140 to any frequency from a plurality of (e.g., two or more) predefined frequencies. The plurality of predefined frequencies may be stored, for example, in one or more volatile and/or non-volatile memories. For example, the predefined frequencies may be stored in a plurality of registers accessible by clock generator 140. In some examples, the plurality of predefined frequencies may be modified, for example, by one or more processors 120. In some examples, the plurality of predefined frequencies may include a maximum frequency (e.g., 2GHz) and frequencies corresponding to the maximum frequency being divided by whole numbers (dividers). To illustrate, the plurality of predefined frequencies may include the following frequencies: 2GHz, 1 GHz, 666.66MHz, 500MHz, 400MHz, 333.33MHz, 285.71 MHz, 250Mhz, 222.22MHz, 200MHz, etc.

[0014] In some examples, at any given point in time, each processor 120 may have a particular workload. A processor's workload may represent, for example, what amount or percentage of the processor's resources (e.g., memory, processing power, etc.) is being utilized at a given point in time. The workload may also represent, for example, the amount of data that is ready to be processed by the processor, e.g., the amount of unprocessed data being stored in the processor's input queue (e.g., a first-in-first-out (FIFO) buffer) or the input queue's level of fullness. The workload may also represent, for example, the amount of data stored in the processor's output queue (e.g., a FIFO buffer) or the output queue's level of fullness. The workload may be measured, for example, in a number of bytes, data packets, average size of a data packet, a ratio of used memory to total memory, a ratio of non-idle processing cycles to a total number of processing cycles, or using any other suitable measure.

[0015] In some examples, each processor 120 may be associated with a predefined workload threshold. The workload threshold may be expressed in absolute values or as a percentage of the maximum workload (e.g., of total capacity) of the respective processor 120. The workload threshold may represent, for example, a level of workload (e.g., 90% of the total capacity) that is so close to the maximum capacity of the processor, that the processor is likely to soon reach the maximum capacity, which may cause various undesirable effects, such as data being delayed, corrupted, or lost. In some examples, different processors 120 may be associated with different workload thresholds. In other examples, all processors 120 may be associated with the same workload threshold. The workload threshold associated with each processor 120 may be hard-wired in circuitry or stored in a volatile and/or non-volatile memory, in which case the threshold may be configurable and modifiable.

[0016] In some examples, each processor 120 may be associated with a plurality of (e.g., two or more) predefined workload thresholds. For example, each processor 120 may be associated with a "non-critical" workload threshold (e.g., 80% of the maximum capacity) and a "critical" workload threshold (e.g., 95% of the maximum capacity). In these examples, too, each processor 120 may be associated with the same plurality of thresholds or with a different plurality of thresholds, and the thresholds may be hard-wired or stored in a memory.

[0017] In some examples, clock generator 1 10 may obtain workload information associated with each processor 120. The workload information may include, for example, the current (real-time) workload of each processor 120; the maximum capacity of each processor 120; the ratio of the workload to the maximum capacity, the availability of each processor 120 (e.g., reversely related to its workload); the workload threshold(s) associated with each processor 120; whether or not the some processors' workloads have reached or exceeded any of their thresholds; or any combination of these and other parameters related to and describing workloads of processors 120.

[0018] In some examples, clock generator 1 10 may obtain some or all of the workload information directly from processors 120. For example, clock generator 1 10 may be electronically coupled via a workload signal 130 (e.g., 130-1 , 130-2, ... 130-N) to each processor 120 (e.g., 120-1 , 120-2, ... 120-N, respectively). Each workload signal may include, for example, one or more wires carrying digital or analog signals. Using the workload signal, each processor 120 may send some or all of the workload information to clock generator 1 10. For example, the workload signal may indicate (e.g., using one wire) whether or not the workload of the respective processor 120 has reached or exceeded a particular (e.g., "critical" or "non-critical") predefined threshold. Alternatively or in addition, the workload signal may represent the ratio of the processor's workload to the processor's maximum capacity. Alternatively or in addition, the workload signal may indicate whether or not a clock frequency provided to the respective processor 120 needs to be increased (e.g., increased to the next frequency from the plurality of predefined frequencies). Alternatively or in addition, the workload signal may indicate whether or not a clock frequency provided to the respective processor 120 needs to be maximized (e.g., increased to the highest frequency from the plurality of predefined frequencies). Alternatively or in addition, the workload signal may indicate whether or not a clock frequency provided to the respective processor 120 may be decreased (e.g., decreased to one frequency below the present frequency in the plurality of frequencies).

[0019] In some examples, some or all of the workload information may be sent from processors 120 to clock generator 1 10 via other modules (not shown in FIG. 1 for brevity). In some examples, some or all of the workload information may be stored and periodically updated in a volatile and/or non-volatile memory (e.g., by processors 120 or other modules monitoring workloads of processors 120), and clock generator 1 10 may read the workload information from the memory. [0020] Based on the workload information, clock generator 1 10 may, in some examples, determine whether to change (e.g., increase or decrease) the frequency of clock signal 140, and then to change it in accordance with the determination. In some examples, clock generator 1 10 may increase the frequency when the workload information indicates that at least one processor 120 has a workload that equals or exceeds a predefined workload threshold associated with that processor. As discussed above, workload information of each processor 120 may explicitly indicate (e.g., via a dedicated signal or bit) that the threshold is reached or exceeded and/or that the clock frequency needs to be increased. Alternatively or in addition, the workload information may indicate the amount of workload, the workload threshold, the maximum capacity, and include other information based on which clock generator 1 10 may determine that the workload threshold was reached or exceeded.

[0021 ] In some examples, when clock generator 1 10 determines that a "non- critical" workload threshold of at least one processor 120 was reached or exceeded (but the "critical" workload was not), clock generator 1 10 may increase the frequency of clock signal 140 to the next frequency from the set of predefined frequencies. Increasing the frequency may help reduce the workload of all processors 120, including the processor whose workload reached the threshold. Sometimes, however, increasing the frequency may not reduce the workload of that processor to a level below the workload threshold, or may not reduce it sufficiently fast. Accordingly, in some examples, after increasing the frequency, clock generator 1 10 may receive another (updated) workload information indicating that the workload of the processor is still above the threshold. Upon receiving such information, clock generator 1 10 may increase the frequency to the next level again. It is therefore appreciated that the mechanism described above may be repeated until no processors 120 have workloads above their respective thresholds or until the frequency reaches its maximum possible value. Because the reduction in workload may not be instantaneous, in some examples, clock generator 1 10 may wait a predefined interval of time (e.g., 10 s, 100 s, 1 ms, etc.) before determining again whether the frequency needs to be increased again. The predefined interval of time may be configurable, and may be stored, for example, in a register or any other type of volatile or non-volatile memory.

[0022] Alternatively or in addition, in some examples, when clock generator 1 10 determines that a "critical" workload threshold of at least one processor 120 was reached or exceeded, clock generator 1 10 may increase the frequency of clock signal 140 to the maximum possible frequency, such as the highest frequency among the plurality of predefined frequencies. This may help address a situation in which the workload of a processor increased rapidly and is close to reaching the processor's capacity or has already reached it, in which case increasing the frequency gradually, one level at a time (as discussed above), may not resolve the situation as quickly as maximizing the frequency may.

[0023] In some examples, clock generator 1 10 may also determine that the frequency of clock signal 140 may be decreased, and decrease the frequency based on the determination. For example, clock generator 1 10 may determine that the frequency may be decreased after a predefined period of time (e.g., 1 second) during which no processor 120 had a workload exceeding a predefined threshold (e.g., a non-critical workload threshold) associated therewith. Based on that determination, in some examples, clock generator 1 10 may decrease the frequency of clock signal 140 by one level, e.g., to the nearest lower frequency among the plurality of predefined frequencies.

[0024] FIG. 2 illustrates another example of electronic device 100. In the example illustrated in FIG. 2, electronic device 100 also includes a plurality of data ports 150. Each port 150 may be an input and/or output port, a digital port (e.g., an Ethernet port, a USB port, etc.), an analog port, or any other type of port capable of receiving and/or transmitting data. Ports 150 may be connected to inputs or outputs of any processor(s) 120. In the example illustrated in FIG. 2, all ports 150 are connected at least to processor 120-1 . [0025] In some examples, each data port 150 may be associated with a data speed. The data speed associated with the port may correspond to that port's predefined maximum speed (e.g., 1 Gb/s, 10Gb/s, 40Gb/s, 100Gb/s, etc.) at which the port is capable of operating. In some examples, the data speed associated with port 150 may correspond to a speed that is lower than the ports maximum speed. For example, the data speed of a particular port 150 may correspond to the speed that was established (agreed upon) during a handshake protocol between electronic device 100 and another device connected to the particular port 150.

[0026] In some examples, each port 150 may be associated with a state, such as an active state and an inactive state. In some examples, port 150 is active when it is connected to another device and is inactive when it is not connected to another device. In other examples, e.g., if port 150 is an Energy-Efficient Ethernet (EEE) port, the port may be considered active when it is not in a "sleep" mode (irrespective of whether it is connected to another device), and is considered inactive when it is in a "sleep" mode.

[0027] In some examples, ports 150 may be divided into groups 160, such that each port 150 may be associated with a group of one or more ports 150. In FIG. 2, for example, two ports 150 are in group 160A and three other ports 150 are in group 160B. In some examples, ports 150 are associated with groups 160 such the combined maximum speeds of all ports within the group do not exceed a predefined speed threshold. In some examples, all data ports 150 of electronic device 100 may be associated with one group.

[0028] In some examples, clock generator 1 10 may determine a minimum frequency below which the frequency of clock signal 140 may not be decreased. In some examples, the minimum frequency may be determined by clock generator 1 10 based on the data speeds of one or more data ports 150. For example, clock generator 1 10 may determine, for each group 160, a combined data speed of all active (or not inactive) ports 150 within the group at a given time. It is appreciated that the combined data speed for a certain group 160 may change when an active port 150 within that group becomes inactive or when an inactive port 150 within that group becomes active. After determining the combined data speed for each group 160, clock generator 1 10 may determine the maximum combined data speed among all groups 160. Clock generator 1 10 may then translate the maximum combined data speed into the minimum frequency, for example, using one or more predefined (e.g., configurable) look-up tables, and/or using one or more predefined formula. In some examples, higher maximum combined data speeds may be translated into higher minimum frequencies, and vice versa.

[0029] As discussed above, in some examples, clock generator 1 10 may maintain the frequency of clock signal 140 at least at the determined minimum frequency. For example, when clock generator 1 10 determines based on the workload information that the frequency of clock signal 140 may be decreased (as discussed above) to a lower frequency, clock generator 1 10 may compare the lower frequency to the minimum frequency and change the frequency of clock signal 140 to the lower frequency only if the lower frequency is equal or above the minimum frequency.

[0030] In some examples, clock generator 1 10 may calculate a new minimum frequency either periodically or whenever any of ports 150 change their status from active to inactive or vice versa. After calculating the new minimum frequency, clock generator may determine whether the current frequency of clock signal 140 is at or above the new minimum frequency, and if it is not, clock generator 1 10 may increase the frequency of clock signal 140 to the new minimum frequency. In some examples, the above-discussed functionality of determining the maximum combined data speed and/or translating it into the minimum frequency may be performed by one or more modules (not shown) other than clock generator 1 10, and the module(s) may provide the resulting minimum frequency to clock generator 1 10 and provide the updated minimum frequency when it changes.

[0031 ] As mentioned above, in some examples, processors 120 and clock generator 1 10 may each be implemented as any combination of hardware and programming. The programming may include processor executable instructions stored on a tangible, non-transitory computer readable medium and the hardware may include a processing resource for executing those instructions. The processing resource, for example, may include one or multiple processors (e.g., central processing units (CPUs), semiconductor-based microprocessors, graphics processing units (GPUs), field-programmable gate arrays (FPGAs) configured to retrieve and execute instructions, or other electronic circuitry), which may be integrated in a single device or distributed across devices. The computer readable medium can be said to store program instructions that when executed by the processor resource implement the functionality of the respective component. The computer readable medium may be integrated in the same device as the processor resource or it may be separate but accessible to that device and the processor resource. In one example, the program instructions can be part of an installation package that when installed can be executed by the processor resource to implement the corresponding component. In this case, the computer readable medium may be a portable medium such as a CD, DVD, or flash drive or a memory maintained by a server from which the installation package can be downloaded and installed. In another example, the program instructions may be part of an application or applications already installed, and the computer readable medium may include integrated memory such as a hard drive, solid state drive, or the like.

[0032] FIG. 3 is a flowchart of an example method 300 for changing a frequency of a clock signal. Method 300 may be described below as being executed or performed by a computing device, for example, electronic device 100. Other suitable systems and/or computing devices may be used as well. Method 300 may be implemented in the form of executable instructions stored on at least one non- transitory machine-readable storage medium of the computing device and executed by at least one processor of the client device. Alternatively or in addition, method 300 may be implemented in the form of electronic circuitry (e.g., hardware). In alternate examples of the present disclosure, one or more or blocks of method 300 may be executed substantially concurrently or in a different order than shown in FIG. 3. In alternate examples of the present disclosure, method 300 may include more or less blocks than are shown in FIG. 3. In some examples, one or more of the blocks of method 300 may, at certain times, be ongoing and/or may repeat.

[0033] At block 310, method 300 may obtain data via one or more data ports of an electronic device. As discussed above, in some examples the data may include a plurality of network packets. At block 320, the method may process the data by a plurality of processors coupled to and driven by a clock signal. At block 330, the method may process the data by the plurality of processors. At block 340, the method may monitor workloads associated with each of the plurality of processors. At block 350, the method may increase a frequency of the clock signal based on a determination that a workload associated with at least one of the plurality of processors exceeds a predefined workload threshold.

In some examples, as discussed above, the method may also decrease the frequency of the clock signal based on a determination that workloads of all of the plurality of processors did not exceed the predefined workload threshold for a predefined period of time. In some examples, as discussed above, each data port may be associated with a data speed, and the method may also obtain a minimum frequency associated with a combined data speed of data ports that are active, and maintain the frequency of the clock signal at least at the minimum frequency.

Claims

1 . An electronic device comprising:

a plurality of processors; and

a clock generator to:

provide a clock signal to the plurality of processors,

obtain workload information indicative of workloads of each of the plurality of processors,

based on the workload information, determine whether to change a frequency of the clock signal, wherein changing the frequency comprises one of increasing the frequency and decreasing the frequency, and

change the frequency based on the determination.

2. The electronic device of claim 1 , wherein the clock generator is to increase the frequency based on a determination that the workload of at least one processor from the plurality of processors exceeds a predefined workload threshold associated with the processor.

3. The electronic device of claim 2, wherein the clock generator is to decrease the frequency based on a determination that workloads of all of the plurality of processors have not exceeded their respective predefined workload thresholds for a predefined period of time.

4. The electronic device of claim 2, wherein the processor comprises a memory buffer, and wherein the workload represents at least a fullness level of the buffer.

5. The electronic device of claim 1 , the clock generator is to: increase the frequency to a first frequency value based on a deternnination that the workload of at least one processor from the plurality of processors exceeds a first predefined workload threshold associated with the processor, and

increase the frequency to a predefined maximum frequency value based on a determination that the workload of at least one processor from the plurality of processors exceeds a second predefined workload threshold associated with the processor, wherein the first frequency value is lower than the second frequency value, and the first predefined workload threshold is lower than the second predefined workload threshold.

6. The electronic device of claim 1 , further comprising a plurality of data ports, each data port being associated with a data speed, wherein the clock generator is further to:

obtain a minimum frequency associated with a combined data speed of all active data ports within the plurality of data ports; and

maintain the frequency of the clock signal at least at the minimum frequency.

7. The electronic device of claim 1 , wherein at least one of the processors is to process network packets.

8. A method comprising:

obtaining data via one or more data ports of an electronic device comprising a plurality of processors, wherein the plurality of processors are driven to a clock signal;

processing the data by the plurality of processors;

monitoring workloads associated with each of the plurality of processors; and based on a determination that a workload associated with at least one of the plurality of processors exceeds a predefined workload threshold, increasing a frequency of the clock signal.

9. The method of claim 8, further comprising:

based on a determination that workloads of all of the plurality of processors did not exceed the predefined workload threshold for a predefined period of time, decreasing the frequency of the clock signal;

10. The method of claim 8, wherein the data comprises a plurality of network packets.

1 1 . The method of claim 8, wherein each data port is associated with a data speed, the method further comprising:

obtaining a minimum frequency associated with a combined data speed of data ports that are active; and

maintaining the frequency of the clock signal at least at the minimum frequency.

12. An electronic device comprising:

a plurality of processors, each processor comprising a clock input; and a clock generator comprising a clock output coupled to the clock inputs of the plurality of processors, and a plurality of workload inputs, each workload input being coupled to one of the plurality of processors, wherein the clock generator is to:

provide a clock signal to the clock output,

obtain, at each workload input, a workload signal associated with a workload of the processor coupled to the workload input,

based at least on the workload signals, determine whether a frequency of the clock signal is to be increased, and increase the frequency of the clock signal based on the determination.

13. The electronic device of claim 12, wherein the clock generator is further to:

based at least on the workload signals, determine whether the frequency of the clock signal is to be decreased; and

decrease the frequency of the clock signal based on the determination.

14. The electronic device of claim 12, wherein each workload signal indicates whether a workload of the processor coupled to the workload input through which the workload signal was received exceeds a predefined workload threshold associated with the processor.

15. The electronic device of claim 12, wherein the clock generator is to:

increase the frequency to a first frequency based on a determination that a workload of at least one processor from the plurality of processors exceeds a first predefined threshold; and

increase the frequency to a second frequency based on a determination that a workload of at least one processor from the plurality of processors exceeds a second predefined threshold, wherein the first frequency is lower than the second frequency and the first predefined threshold is lower than the second predefined threshold.