WO2016131247A1 - 一种用于虚拟机的高性能定时器实现方法、虚拟机 - Google Patents

一种用于虚拟机的高性能定时器实现方法、虚拟机 Download PDF

Info

Publication number
WO2016131247A1
WO2016131247A1 PCT/CN2015/089282 CN2015089282W WO2016131247A1 WO 2016131247 A1 WO2016131247 A1 WO 2016131247A1 CN 2015089282 W CN2015089282 W CN 2015089282W WO 2016131247 A1 WO2016131247 A1 WO 2016131247A1
Authority
WO
WIPO (PCT)
Prior art keywords
timer
virtual machine
core
write
hardware
Prior art date
Application number
PCT/CN2015/089282
Other languages
English (en)
French (fr)
Inventor
李凯航
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2016131247A1 publication Critical patent/WO2016131247A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Definitions

  • the present invention relates to the field of high-performance timing of virtual machines, and in particular, to a high-performance timer implementation method and a virtual machine for a virtual machine.
  • virtual machine performance is a key indicator that everyone pays attention to. Whether a virtual machine can have the same performance as a physical machine is a difficult problem that has long been difficult to solve in the virtualization field, and embedded virtual Due to the high real-time requirements of its bearer services, the performance requirements of virtualization are more demanding, and the most critical one affecting the virtual machine running metrics is the virtual machine timer accuracy problem.
  • the existing embedded virtualization high-precision timer processing flow is: GuestOS configuration offset is 0x380 Timer Initial Count register timing value; hardware write 0x380 register generates VM_Exit to Hypervisor to decode the instruction and write to the real hardware register; the system is returned by Hypervisor Go to GuestOS to continue running; high-precision timer timing to hardware-generated interrupt occurs.
  • VM_Exit to Hypervisor handles the interrupt and converts the interrupt into a virtual interrupt injected into the GuestOS IDT interrupt processing flow.
  • the embodiment of the invention provides a high-performance timer implementation method and a virtual machine for a virtual machine, so as to solve the problem that the virtual machine timer has poor precision.
  • Embodiments of the present invention provide a high-performance timer implementation method for a virtual machine, including: a partition Guest generates a timing request, and writes a timing value to a high-precision timer register 0x380; the partition CPU captures a write 0x380 register privileged instruction operation, VM_Exit is generated to the Hypervisor for processing; the embedded Hypervisor is added to the timer configuration message by the CPU to obtain the write register offset and the write value, and is sent to the high-speed communication queue; the high-precision timer module obtains the timer configuration message from the high-speed communication queue. And write to the hardware core register.
  • the method when there are multiple partitions, the method further includes: the embedded hypervisor will initiate a register write operation.
  • the method further includes: notifying the high-precision timer module that the write register operation is completed; and the high-precision timer module receiving the notification from the high-speed communication queue. Get the timer configuration packet.
  • the high-precision timer module writes the timer configuration message to the hardware core register, including: the high-precision timer module parses the timer configuration message, acquires the write register offset and the write value, and determines the timer. The offset and timing values are written to the hardware Core timer.
  • the method when there are multiple partitions, the method further includes: the high-precision timer module parses the timer configuration message, acquires the write register offset and the write value, and the core id of the partition VCPU that initiates the register write operation. Corresponding hardware posted Interrupt descriptor address, with the timer offset and timing value stored in the virtual machine timer model of the core id and hardware posted Interrupt descriptor address of the VCPU; the minimum timing value found is written to the hardware Core timer .
  • the method further includes: determining whether the hardware Core timer is in an untimed state; if the hardware Core timer is in an untimed state, the high precision timer module searches the virtual machine timer data model to find the minimum The timing value is written to the hardware Core timer; if the hardware Core timer is in the timing state, the hardware Core timer is not written.
  • the method further includes: the core of the deployed partition virtual machine is turned off by the hypervisor.
  • the method further includes: selecting a core, and running the embedded hypervisor high-precision timer module at the core.
  • the method further includes: constructing a high-speed communication channel between each partition virtual machine and the high-precision timer module in the embedded hypervisor software layer.
  • the method further includes: the hardware Core timer sends an interrupt notification to the high-precision timer module when the timing arrives, and the high-precision timer module writes the high-precision timer interrupt flag to the partition PI descriptor to the partition core. Send a PI physical interrupt.
  • the method when there are multiple partitions, the method further includes: the high-precision timer module acquires the core id of the VCPU of the virtual machine and the virtual machine PI descriptor address information from the virtual machine timer model, according to The acquired virtual machine PI descriptor address writes a high-precision timer interrupt flag to the corresponding PI descriptor, and sends a PI physical interrupt to the corresponding core according to the acquired core id of the VCPU.
  • the method further includes: the high-precision timer module deletes the partition timer data that has completed the timer interrupt injection from the virtual machine timer model, and reads the next minimum timing value from the virtual machine timer data model, Write the next minimum timing value of the read virtual machine to the hardware Core timer.
  • An embodiment of the present invention provides a virtual machine, including: a partition guestOS for generating a timing request, writing a timing value to a high-precision timer register 0x380; and a partitioning CPU, configured to capture a write 0x380 register privileged instruction operation, generating VM_Exit to Hypervisor processing; embedded Hypervisor, set to acquire write register offset and write value by CPU to add to timer configuration message, send to high-speed communication queue; high-precision timer module, set to get from high-speed communication queue The timer configures the message and writes it to the hardware core register.
  • the embedded hypervisor when there are multiple partitions, is further configured to integrate the core id of the partition VCPU that initiates the register write operation, the corresponding hardware posted Interrupt descriptor address, and add to the timer configuration message. .
  • the embedded hypervisor is further configured to notify the high-precision timer module that the write register operation is completed; the high-precision timer module is further configured to receive the notification. Then, the timer configuration packet is obtained from the high-speed communication queue.
  • the high-precision timer module is configured to parse the timer configuration message, obtain the write register offset and the write value, determine the timer offset and the timing value, and write the hardware Core timer.
  • the high-precision timer module is further configured to parse the timer configuration message, obtain the write register offset and the write value, and the core id of the partition VCPU that initiates the register write operation.
  • the high-precision timer module is further configured to determine whether the hardware Core timer is in an untimed state; if the hardware Core timer is in an untimed state, the virtual machine timer data model is searched, and the minimum value to be found is found. The timing value is written to the hardware Core timer; if the hardware Core timer is in the timing state, the hardware Core timer is not written.
  • the core of the deployed partition virtual machine is also set to turn off the high precision timer through the hypervisor.
  • the embedded hypervisor is further configured to select a core, and the embedded hypervisor high-precision timer module is run at the core.
  • the embedded hypervisor is further configured to construct a high-speed communication channel between each partition virtual machine and the high-precision timer module at the software layer.
  • the hardware Core timer is further configured to send a interrupt notification to the high-precision timer module when the timing is reached; the high-precision timer module is further configured to write high-precision timing to the partition PI descriptor.
  • the interrupt flag sends a PI physical interrupt to the partition core.
  • the high-precision timer module is further configured to acquire the core id and virtual machine PI descriptor address information of the VCPU of the virtual machine from the virtual machine timer model, according to The acquired virtual machine PI descriptor address writes a high-precision timer interrupt flag to the corresponding PI descriptor, and sends a PI physical interrupt to the corresponding core according to the acquired core id of the VCPU.
  • the high-precision timer module is further configured to delete the partition timer data that has completed the timer interrupt injection from the virtual machine timer model, and read the next minimum timing value from the virtual machine timer data model. Will read The virtual machine's next minimum timing value is written to the hardware Core timer.
  • the embodiment of the present invention provides a new high-performance timer implementation method.
  • the hardware does not need to write the 0x380 register to generate a VM_Exit to the Hypervisor as in the prior art. After decoding, it is written into the real hardware register. Thus, GuestOS writes 0x380 register without software decoding.
  • the hardware decodes the instruction and directly transfers the register offset address and write value to the Hypervisor in the VM_Exit event, essentially eliminating it.
  • Intel Posted Interrupt hardware virtualization mechanism will automatically complete the interrupt injection of high-precision timers of different partition virtual machines according to the above configuration. In this process, no VM_Exit or Hypervisor intervention interrupt processing will be generated, so the performance can be consistent with the physical machine. s level.
  • FIG. 1 is a schematic structural diagram of a virtual machine according to a first embodiment of the present invention.
  • FIG. 2 is a flowchart of a method for implementing a high performance timer according to a second embodiment of the present invention
  • FIG. 3 is a flowchart of a method for implementing a high performance timer according to a third embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a virtual machine according to a first embodiment of the present invention.
  • the virtual machine 1 provided by the present invention includes:
  • Partition GuestOS11 set to generate timing requirements, write timing values to high precision timer register 0x380;
  • Partition CPU12 set to capture write 0x380 register privileged instruction operations, generate VM_Exit to Hypervisor processing;
  • the embedded Hypervisor 13 is set to be added to the timer configuration message by the CPU to obtain the write register offset and the write value, and sent to the high speed communication queue;
  • the high-precision timer module 14 is configured to acquire a timer configuration message from the high-speed communication queue and write it to the hardware core register 15;
  • the hardware core register 15 is set to execute a timer.
  • the embedded Hypervisor 13 in the above embodiment is also set to The core id of the partition VCPU that initiates the register write operation, the corresponding hardware posted Interrupt descriptor address are integrated, and added to the timer configuration message.
  • the embedded hypervisor 13 in the above embodiment is further configured to notify the high precision timer module that the write register operation is completed; the high precision timer module is further configured to After receiving the notification, the timer configuration packet is obtained from the high speed communication queue.
  • the high-precision timer module 14 in the above embodiment is configured to parse the timer configuration message, obtain the write register offset and the write value, determine the timer offset and the timing value, and write the hardware Core timing. Device.
  • the high-precision timer module 14 in the above embodiment is further configured to parse the timer configuration message, obtain the write register offset and the write value, and initiate the register write operation.
  • the core id where the VCPU is located, the corresponding hardware posted Interrupt descriptor address, the timer offset and the timing value are stored in the virtual machine timer model by the core id of the VCPU and the hardware posted Interrupt descriptor address; the minimum timing value is found. Enter the hardware Core timer 15.
  • the high-precision timer module 14 in the above embodiment is further configured to determine whether the hardware Core timer 15 is in an untimed state; if the hardware Core timer is in an untimed state, look up the virtual machine timer data model. The minimum timing value found is written to the hardware Core timer; if the hardware Core timer is in the timing state, the hardware Core timer is not written.
  • the core of the deployed partition virtual machine in the above embodiment is also set to turn off the high precision timer through the Hypervisor 13.
  • the embedded Hypervisor 13 in the above embodiment is further configured to select a core at which to run the embedded Hypervisor high precision timer module 14.
  • the embedded Hypervisor 13 in the above embodiment is further configured to build a high speed communication channel between each partitioned virtual machine and the high precision timer module 14 at the software layer.
  • the hardware Core timer 15 in the above embodiment is further configured to send a interrupt notification to the high precision timer module 14 when the timing is reached; the high precision timer module 14 is also set to the partition PI.
  • the descriptor writes a high-precision timer interrupt flag and sends a PI physical interrupt to the partition core.
  • the high-precision timer module 14 in the above embodiment is further configured to acquire the core id and virtual machine PI description of the VCPU of the virtual machine from the virtual machine timer model.
  • the address information is written to the corresponding PI descriptor according to the acquired virtual machine PI descriptor address, and the PI physical interrupt is transmitted to the corresponding core according to the acquired core id of the VCPU.
  • the high-precision timer module 14 in the above embodiment is further configured to delete the partition timer data that has completed the timer interrupt injection from the virtual machine timer model, and read from the virtual machine timer data model. A minimum timing value that writes the next minimum value of the read virtual machine to the hardware Core timer.
  • FIG. 2 is a flowchart of a method for implementing a high-performance timer according to a second embodiment of the present invention. As shown in FIG. 2, in the embodiment, the high-performance timer implementation method provided by the present invention includes the following steps:
  • the partition GuestOS generates a timing request, and writes a timing value to the high-precision timer register 0x380;
  • the partition CPU captures the write 0x380 register privileged instruction operation, and generates VM_Exit to the hypervisor for processing;
  • S203 the embedded hypervisor acquires the write register offset and the write value by using the CPU, and adds the message to the timer configuration message, and sends the message to the high-speed communication queue.
  • the high-precision timer module acquires a timer configuration message from the high-speed communication queue and writes it to the hardware core register.
  • the method in the above embodiment further includes: the embedded hypervisor integrates the core id of the partition VCPU that initiates the register write operation, and the corresponding hardware posted Interrupt descriptor address, and adds to Timer configuration message.
  • the method in the foregoing embodiment further includes: notifying the high-precision timer module that the write register operation is completed; after receiving the notification, the high-precision timer module receives the notification. Obtain timer configuration packets from the high-speed communication queue.
  • the high-precision timer module in the above embodiment writes the timer configuration message to the hardware core register, including: the high-precision timer module parses the timer configuration message, and acquires the write register offset and the write value. Determine the timer offset and timing value and write to the hardware Core timer.
  • the method in the foregoing embodiment further includes: the high-precision timer module parses the timer configuration message, acquires a write register offset and a write value, and initiates a register write operation.
  • the core id where the VCPU is located, the corresponding hardware posted Interrupt descriptor address, the timer offset and the timing value are stored in the virtual machine timer model by the core id of the VCPU and the hardware posted Interrupt descriptor address; the minimum timing value is found. Enter the hardware Core timer.
  • the method in the foregoing embodiment further includes: determining whether the hardware Core timer is in an untimed state; if the hardware Core timer is in an untimed state, the high precision timer module looks up the virtual machine timer data model, The found minimum timing value is written to the hardware Core timer; if the hardware Core timer is in the timing state, the hardware Core timer is not written.
  • the method in the above embodiment further includes: deploying a core of the partitioned virtual machine to close the high precision timer through the hypervisor.
  • the method in the above embodiment further includes: selecting a core, and running the embedded hypervisor high precision timer module at the core.
  • the method in the above embodiment further includes: constructing a high-speed communication channel between each partition virtual machine and the high-precision timer module in the embedded hypervisor software layer.
  • the method in the foregoing embodiment further includes: the hardware Core timer sends an interrupt notification to the high precision timer module when the timing arrives, and the high precision timer module writes the high precision timer interrupt to the partition PI descriptor. Flag, sends a PI physical interrupt to the partition core.
  • the method in the foregoing embodiment further includes: the high-precision timer module acquires the core id of the VCPU of the virtual machine and the virtual machine PI description from the virtual machine timer model. The address information is written to the corresponding PI descriptor according to the acquired virtual machine PI descriptor address, and the PI physical interrupt is transmitted to the corresponding core according to the acquired core id of the VCPU.
  • the method in the foregoing embodiment further includes: the high-precision timer module deletes the partition timer data that has completed the timer interrupt injection from the virtual machine timer model, and reads the data from the virtual machine timer data model. A minimum timing value that writes the next minimum value of the read virtual machine to the hardware Core timer.
  • FIG. 3 is a flowchart of a method for implementing a high-performance timer according to a third embodiment of the present invention. As shown in FIG. 3, in the embodiment, the method for implementing the high-performance timer provided by the present invention includes the following steps:
  • the core of the deployed partition virtual machine is turned off by the hypervisor to prevent high-precision timers from being generated.
  • the module Separating a core to run the embedded hypervisor high-precision timer module, and starting the core high-precision timer hardware function, the module provides a clock source for different partition high-precision timers;
  • the embedded Hypervisor configures the partitioned virtual machine hardware APIC Register Virtualization function. The purpose is to let GuestOS write 0x380 registers without software decoding. The hardware will decode the instructions and directly transfer the register offset address and write value to the Hypervisor in the VM_Exit event. Processing, essentially eliminating the time bottleneck caused by software instruction decoding;
  • S302 The partition generates a timer configuration packet.
  • the embedded Hypervisor captures the guest OS's 0x380 register write operation and does not directly write to the current core hardware register. Instead, it writes the timing value, the current core id, and the corresponding posted Interrupt descriptor address to the high-precision timer module through the high-speed communication channel.
  • this step includes:
  • the high-precision GuestOS generates timing requirements to write timing values to the high-precision timer register 0x380;
  • the CPU hardware captures the write 0x380 register privileged instruction operation to generate VM_Exit to the Hypervisor for processing;
  • the embedded Hypervisor obtains the write register offset and the write value through the CPU hardware and integrates the core id of the partition VCPU that initiates the register write operation with the corresponding hardware posted Interrupt descriptor address, and then sends the packet to the high speed through the timer configuration message.
  • the embedded hypervisor sends an event notification to the high precision timer module to write the register operation.
  • the high-precision timer module obtains timer configuration messages from the high-speed communication queue.
  • the high-precision timer module receives high-precision timer messages from each partition virtual machine configuration from the high-speed communication channel, updates the internal data model, performs calculation and analysis, and finally completes the configuration of the core hardware high-precision timer in which the high-precision timer module is located. .
  • this step includes:
  • the high-precision timer module receives the notification of the hypervisor message event channel, and proves that the virtual machine partition has written the high-precision timer timing message at this time, and prepares to read the timing message content from the communication queue;
  • the high-precision timer module parses the message event information to obtain a high-speed communication queue number, and reads a high-precision timer timing message written by the virtual machine partition from the queue;
  • the high-precision timer module analyzes the read virtual machine configuration timer message, and stores the coreid and hardware posted Interrupt descriptor address of the VCPU in the message to the virtual machine timer data by using the timer offset and the timing value as an index. model;
  • the high-precision timer module searches the virtual machine timer data model, and writes the found minimum timing value to the hardware Core timer; if the current hardware Core timer is in the timing state, the current timer is not performed. Write operation of the hardware Core timer.
  • the core hardware high-precision timer of the high-precision timer module triggers the high-precision timer module to run after timing.
  • the internal data model is used to find the translated address and core id of the partitioned virtual machine that needs to be processed periodically. After the data is found, the data is first posted.
  • the Interrupt descriptor writes the high-precision timer interrupt flag, and then sends the posted Interrupt inter-core interrupt to the corresponding core id.
  • the Intel Posted Interrupt hardware virtualization mechanism automatically performs interrupt injection for the high-precision timers of different partition virtual machines according to the above configuration. No VM_Exit or Hypervisor intervention interrupt processing will be generated in this process, so the performance can reach the level consistent with the physical machine.
  • this step includes:
  • the hardware Core timer is timed to send an interrupt notification high-precision timer module
  • the high-precision timer module obtains the relevant virtual machine coreid and PI description from the virtual machine timer data model. Address information;
  • the hardware will automatically read the high-precision timer interrupt flag from the PI descriptor and automatically generate a high-precision timer interrupt and jump to the GuestOS interrupt processing routine to execute, the entire process will not generate VM_Exit, Therefore, the performance is exactly the same as the physical machine.
  • the high-precision timer module deletes the partition timer data that has completed the timer interrupt injection from the virtual machine timer model, and reads the next minimum timing value from the virtual machine timer data model; the high-precision timer module will read the virtual The machine's next minimum timing value is written to the hardware Core high-precision timer.
  • the high-precision timer module after the timer expires, the high-precision timer module first writes a high-precision timer interrupt flag to the posted Interrupt descriptor, and then sends a posted Interrupt inter-core interrupt to the corresponding core id, Intel Posted Interrupt hardware.
  • the virtualization mechanism automatically performs interrupt injection for high-precision timers of different partition VMs according to the above configuration. In this process, no VM_Exit or Hypervisor intervention interrupt processing is generated, so the performance can reach the level consistent with the physical machine.
  • the core of the deployed partition virtual machine is turned off by the hypervisor to prevent unnecessary external interrupts from being generated;
  • a core running embedded hypervisor high-precision timer module is separately separated, and the core high-precision timer hardware function is started, and the module provides a clock source for different partition high-precision timers;
  • a high-speed communication channel between each partition virtual machine and a high-precision timer module is constructed in the embedded hypervisor software layer, and a writing mechanism of different partition 0x380 register timing values to the high-precision timer module is provided.
  • the foregoing technical solution provided by the present invention can be applied to a process of implementing a high-performance timer.
  • the hardware does not need to write VM_Exit to the 0x380 register as in the prior art.
  • the Hypervisor decodes the instruction and writes it to the real hardware register.
  • the GuestOS writes the 0x380 register without software decoding.
  • the hardware decodes the instruction and directly transfers the register offset address and write value to the Hypervisor in the VM_Exit event.
  • the high-precision timer module first writes the high-precision timer interrupt flag to the posted Interrupt descriptor, and then sends the posted Interrupt to the corresponding core id.
  • Inter-core interrupt Intel Posted Interrupt hardware virtualization mechanism will automatically complete the interrupt injection of high-precision timers of different partition virtual machines according to the above configuration. In this process, no VM_Exit or Hypervisor intervention interrupt processing will be generated, so the performance can be achieved. One with the physical machine s level.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Computer And Data Communications (AREA)

Abstract

一种用于虚拟机的高性能定时器实现方法、虚拟机，该方法包括：分区GuestOS产生定时要求，向高精度定时器寄存器0x380写定时值（S201）；分区CPU捕获写0x380寄存器特权指令操作，产生VM_Exit到Hypervisor处理（S202）；嵌入式Hypervisor通过CPU获取写寄存器偏移和写入值添加至定时器配置报文，发送至高速通讯队列（S203）；高精度定时器模块从高速通讯队列中获取定时器配置报文，并写入硬件core寄存器（S204）。通过该方法的实施，在生成定时器配置报文并写入定时器的过程中，硬件会进行指令解码并直接将寄存器偏移地址和写入值传递给Hypervisor处理，从本质上消除了软件指令解码产生的时间瓶颈。

Description

一种用于虚拟机的高性能定时器实现方法、虚拟机 技术领域
本发明涉及虚拟机高性能定时领域，尤其涉及一种用于虚拟机的高性能定时器实现方法、虚拟机。
背景技术
目前在虚拟化领域的应用中，虚拟机性能是大家普遍关注的一个关键指标，一台虚拟机能否具有和物理机相同的性能是虚拟化领域长期以来比较难以解决的难题，而嵌入式虚拟化由于其承载业务具有高实时性要求的特性，因此对虚拟化后的各项性能指标要求更为苛刻，而影响虚拟机运行指标中最为关键的一个就是虚拟机定时器精度问题。
现有嵌入式虚拟化高精度定时器处理流程是：GuestOS配置偏移为0x380的Timer Initial Count寄存器定时值；硬件写0x380寄存器产生VM_Exit到Hypervisor进行指令解码后写入真实硬件寄存器；系统由Hypervisor返回到GuestOS继续运行；高精度定时器定时到硬件产生中断发生VM_Exit到Hypervisor处理中断后将该中断转换为虚拟中断注入GuestOS的IDT中断处理流程。
该方法存在影响嵌入式虚拟机高精度定时器性能的关键因素有两个方面：第一是每次向0x380寄存器写定时值会产生一次VM_Exit到Hypervisor处理产生指令解码操作形成性能瓶颈；第二是当定时到时高精度定时器会发出中断产生VM_Exit到Hypervisor处理后再注入中断到GuestOS IDT中断处理例程，这个过程增加了VM_Exit到Hypervisor切换和硬件中断处理开销，对于虚拟机定时器精度有较大的性能影响。
因此，如何提供一种具备较高定时器精度的高性能定时器实现方法，是本领域技术人员亟待解决的技术问题。
发明内容
本发明实施例提供了一种用于虚拟机的高性能定时器实现方法、虚拟机，以解决虚拟机定时器精度差的问题。
本发明实施例提供了一种用于虚拟机的高性能定时器实现方法，其包括：分区GuestOS产生定时要求，向高精度定时器寄存器0x380写定时值；分区CPU捕获写0x380寄存器特权指令操作，产生VM_Exit到Hypervisor处理；嵌入式Hypervisor通过CPU获取写寄存器偏移和写入值添加至定时器配置报文，发送至高速通讯队列；高精度定时器模块从高速通讯队列中获取定时器配置报文，并写入硬件core寄存器。
在本发明实施例中，当存在多个分区时，还包括：嵌入式Hypervisor将发起寄存器写操 作的分区VCPU所在的core id、对应硬件Posted Interrupt描述符地址整合，并添加至定时器配置报文。
在本发明实施例中，在将定时器配置报文发送至高速通讯队列之后，还包括:通知高精度定时器模块写寄存器操作完成；高精度定时器模块在收到通知后，从高速通讯队列中获取定时器配置报文。
在本发明实施例中，高精度定时器模块将定时器配置报文写入硬件core寄存器包括：高精度定时器模块解析定时器配置报文，获取写寄存器偏移和写入值，确定定时器偏移及定时值，写入硬件Core定时器。
在本发明实施例中，当存在多个分区时，还包括：高精度定时器模块解析定时器配置报文，获取写寄存器偏移和写入值、发起寄存器写操作的分区VCPU所在的core id、对应硬件Posted Interrupt描述符地址，以定时器偏移及定时值为VCPU所在的core id、硬件Posted Interrupt描述符地址存储到虚拟机定时器模型；找出的最小定时值写入硬件Core定时器。
在本发明实施例中，还包括：判断硬件Core定时器是否处于非定时状态；如果硬件Core定时器处于非定时状态，则高精度定时器模块查找虚拟机定时器数据模型，将找出的最小定时值写入硬件Core定时器；如果硬件Core定时器处于定时状态，不进行硬件Core定时器的写入操作。
在本发明实施例中，还包括：部署分区虚拟机的core通过Hypervisor关闭高精度定时器。
在本发明实施例中，还包括：选择一core，在core该运行嵌入式Hypervisor高精度定时器模块。
在本发明实施例中，还包括：在嵌入式Hypervisor软件层构建各个分区虚拟机与高精度定时器模块之间的高速通讯通道。
在本发明实施例中，还包括：硬件Core定时器在定时到达时，发送中断通知至高精度定时器模块，高精度定时器模块向分区PI描述符写入高精度定时器中断标志，向分区core发送PI物理中断。
在本发明实施例中，当存在多个分区时，还包括：高精度定时器模块从虚拟机定时器模型中获取定时到的虚拟机的VCPU的core id及虚拟机PI描述符地址信息，根据获取的虚拟机PI描述符地址向对应的PI描述符写入高精度定时器中断标志，根据获取的VCPU的core id向对应的core发送PI物理中断。
在本发明实施例中，还包括：高精度定时器模块从虚拟机定时器模型中删除已经完成定时中断注入的分区定时器数据，并从虚拟机定时器数据模型读取下一个最小定时值，将读取的虚拟机下一个最小定时值写入硬件Core定时器。
本发明实施例提供了一种虚拟机，其包括：分区GuestOS，用于产生定时要求，向高精度定时器寄存器0x380写定时值；分区CPU，设置为捕获写0x380寄存器特权指令操作，产生 VM_Exit到Hypervisor处理；嵌入式Hypervisor，设置为通过CPU获取写寄存器偏移和写入值添加至定时器配置报文，发送至高速通讯队列；高精度定时器模块，设置为从高速通讯队列中获取定时器配置报文，并写入硬件core寄存器。
在本发明实施例中，当存在多个分区时，嵌入式Hypervisor还设置为将发起寄存器写操作的分区VCPU所在的core id、对应硬件Posted Interrupt描述符地址整合，并添加至定时器配置报文。
在本发明实施例中，嵌入式Hypervisor在将定时器配置报文发送至高速通讯队列之后，还设置为通知高精度定时器模块写寄存器操作完成；高精度定时器模块还设置为在收到通知后，从高速通讯队列中获取定时器配置报文。
在本发明实施例中，高精度定时器模块设置为解析定时器配置报文，获取写寄存器偏移和写入值，确定定时器偏移及定时值，写入硬件Core定时器。
在本发明实施例中，当存在多个分区时，高精度定时器模块还设置为解析定时器配置报文，获取写寄存器偏移和写入值、发起寄存器写操作的分区VCPU所在的core id、对应硬件Posted Interrupt描述符地址，以定时器偏移及定时值为VCPU所在的core id、硬件Posted Interrupt描述符地址存储到虚拟机定时器模型；找出的最小定时值写入硬件Core定时器。
在本发明实施例中，高精度定时器模块还设置为判断硬件Core定时器是否处于非定时状态；如果硬件Core定时器处于非定时状态，则查找虚拟机定时器数据模型，将找出的最小定时值写入硬件Core定时器；如果硬件Core定时器处于定时状态，不进行硬件Core定时器的写入操作。
在本发明实施例中，部署分区虚拟机的core还设置为通过Hypervisor关闭高精度定时器。
在本发明实施例中，嵌入式Hypervisor还设置为选择一core，在core该运行嵌入式Hypervisor高精度定时器模块。
在本发明实施例中，嵌入式Hypervisor还设置为在软件层构建各个分区虚拟机与高精度定时器模块之间的高速通讯通道。
在本发明实施例中，硬件Core定时器还设置为硬件Core定时器在定时到达时，发送中断通知至高精度定时器模块；高精度定时器模块还设置为向分区PI描述符写入高精度定时器中断标志，向分区core发送PI物理中断。
在本发明实施例中，当存在多个分区时，高精度定时器模块还设置为从虚拟机定时器模型中获取定时到的虚拟机的VCPU的core id及虚拟机PI描述符地址信息，根据获取的虚拟机PI描述符地址向对应的PI描述符写入高精度定时器中断标志，根据获取的VCPU的core id向对应的core发送PI物理中断。
在本发明实施例中，高精度定时器模块还设置为从虚拟机定时器模型中删除已经完成定时中断注入的分区定时器数据，并从虚拟机定时器数据模型读取下一个最小定时值，将读取 的虚拟机下一个最小定时值写入硬件Core定时器。
本发明实施例的有益效果：
本发明实施例提供了一种新的高性能定时器实现方法，在生成定时器配置报文并写入定时器的过程中，不需要像现有技术那样硬件写0x380寄存器产生VM_Exit到Hypervisor进行指令解码后写入真实硬件寄存器，这样，GuestOS写0x380寄存器不需要软件进行指令解码，硬件会进行指令解码并直接在VM_Exit事件中将寄存器偏移地址和写入值传递给Hypervisor处理，从本质上消除了软件指令解码产生的时间瓶颈；进一步的，在定时器到达后，高精度定时器模块先向Posted Interrupt descriptor写入高精度定时器中断标志，然后向对应的core id发送Posted Interrupt核间中断，Intel Posted Interrupt硬件虚拟化机制会自动根据上述配置完成对不同分区虚拟机高精度定时器的中断注入，此过程中不会产生任何VM_Exit也不需要Hypervisor介入中断处理，因此性能可以达到与物理机一致的水平。
附图说明
图1为本发明第一实施例提供的虚拟机的结构示意图；
图2为本发明第二实施例提供的高性能定时器实现方法的流程图；
图3为本发明第三实施例提供的高性能定时器实现方法的流程图。
具体实施方式
现通过具体实施方式结合附图的方式对本发明做出进一步的诠释说明。
第一实施例：
图1为本发明第一实施例提供的虚拟机的结构示意图，由图1可知，在本实施例中，本发明提供的虚拟机1包括：
分区GuestOS11，设置为产生定时要求，向高精度定时器寄存器0x380写定时值；
分区CPU12，设置为捕获写0x380寄存器特权指令操作，产生VM_Exit到Hypervisor处理；
嵌入式Hypervisor13，设置为通过CPU获取写寄存器偏移和写入值添加至定时器配置报文，发送至高速通讯队列；
高精度定时器模块14，设置为从高速通讯队列中获取定时器配置报文，并写入硬件core寄存器15；
硬件core寄存器15设置为执行定时器。
在一些实施例中，当存在多个分区时，上述实施例中的嵌入式Hypervisor13还设置为将 发起寄存器写操作的分区VCPU所在的core id、对应硬件Posted Interrupt描述符地址整合，并添加至定时器配置报文。
在一些实施例中，上述实施例中的嵌入式Hypervisor13在将定时器配置报文发送至高速通讯队列之后，还设置为通知高精度定时器模块写寄存器操作完成；高精度定时器模块还设置为在收到通知后，从高速通讯队列中获取定时器配置报文。
在一些实施例中，上述实施例中的高精度定时器模块14设置为解析定时器配置报文，获取写寄存器偏移和写入值，确定定时器偏移及定时值，写入硬件Core定时器。
在一些实施例中，当存在多个分区时，上述实施例中的高精度定时器模块14还设置为解析定时器配置报文，获取写寄存器偏移和写入值、发起寄存器写操作的分区VCPU所在的core id、对应硬件Posted Interrupt描述符地址，以定时器偏移及定时值为VCPU所在的core id、硬件Posted Interrupt描述符地址存储到虚拟机定时器模型；找出的最小定时值写入硬件Core定时器15。
在一些实施例中，上述实施例中的高精度定时器模块14还设置为判断硬件Core定时器15是否处于非定时状态；如果硬件Core定时器处于非定时状态，则查找虚拟机定时器数据模型，将找出的最小定时值写入硬件Core定时器；如果硬件Core定时器处于定时状态，不进行硬件Core定时器的写入操作。
在一些实施例中，上述实施例中的部署分区虚拟机的core还设置为通过Hypervisor13关闭高精度定时器。
在一些实施例中，上述实施例中的嵌入式Hypervisor13还设置为选择一core，在core该运行嵌入式Hypervisor高精度定时器模块14。
在一些实施例中，上述实施例中的嵌入式Hypervisor13还设置为在软件层构建各个分区虚拟机与高精度定时器模块14之间的高速通讯通道。
在一些实施例中，上述实施例中的硬件Core定时器15还设置为硬件Core定时器在定时到达时，发送中断通知至高精度定时器模块14；高精度定时器模块14还设置为向分区PI描述符写入高精度定时器中断标志，向分区core发送PI物理中断。
在一些实施例中，当存在多个分区时，上述实施例中的高精度定时器模块14还设置为从虚拟机定时器模型中获取定时到的虚拟机的VCPU的core id及虚拟机PI描述符地址信息，根据获取的虚拟机PI描述符地址向对应的PI描述符写入高精度定时器中断标志，根据获取的VCPU的core id向对应的core发送PI物理中断。
在一些实施例中，上述实施例中的高精度定时器模块14还设置为从虚拟机定时器模型中删除已经完成定时中断注入的分区定时器数据，并从虚拟机定时器数据模型读取下一个最小定时值，将读取的虚拟机下一个最小定时值写入硬件Core定时器。
第二实施例：
图2为本发明第二实施例提供的高性能定时器实现方法的流程图，由图2可知，在本实施例中，本发明提供的高性能定时器实现方法包括以下步骤：
S201：分区GuestOS产生定时要求，向高精度定时器寄存器0x380写定时值；
S202：分区CPU捕获写0x380寄存器特权指令操作，产生VM_Exit到Hypervisor处理；
S203：嵌入式Hypervisor通过CPU获取写寄存器偏移和写入值添加至定时器配置报文，发送至高速通讯队列；
S204：高精度定时器模块从高速通讯队列中获取定时器配置报文，并写入硬件core寄存器。
在一些实施例中，当存在多个分区时，上述实施例中的方法还包括：嵌入式Hypervisor将发起寄存器写操作的分区VCPU所在的core id、对应硬件Posted Interrupt描述符地址整合，并添加至定时器配置报文。
在一些实施例中，上述实施例中的方法在将定时器配置报文发送至高速通讯队列之后，还包括:通知高精度定时器模块写寄存器操作完成；高精度定时器模块在收到通知后，从高速通讯队列中获取定时器配置报文。
在一些实施例中，上述实施例中的高精度定时器模块将定时器配置报文写入硬件core寄存器包括：高精度定时器模块解析定时器配置报文，获取写寄存器偏移和写入值，确定定时器偏移及定时值，写入硬件Core定时器。
在一些实施例中，当存在多个分区时，上述实施例中的方法还包括：高精度定时器模块解析定时器配置报文，获取写寄存器偏移和写入值、发起寄存器写操作的分区VCPU所在的core id、对应硬件Posted Interrupt描述符地址，以定时器偏移及定时值为VCPU所在的core id、硬件Posted Interrupt描述符地址存储到虚拟机定时器模型；找出的最小定时值写入硬件Core定时器。
在一些实施例中，上述实施例中的方法还包括：判断硬件Core定时器是否处于非定时状态；如果硬件Core定时器处于非定时状态，则高精度定时器模块查找虚拟机定时器数据模型，将找出的最小定时值写入硬件Core定时器；如果硬件Core定时器处于定时状态，不进行硬件Core定时器的写入操作。
在一些实施例中，上述实施例中的方法还包括：部署分区虚拟机的core通过Hypervisor关闭高精度定时器。
在一些实施例中，上述实施例中的方法还包括：选择一core，在core该运行嵌入式Hypervisor高精度定时器模块。
在一些实施例中，上述实施例中的方法还包括：在嵌入式Hypervisor软件层构建各个分区虚拟机与高精度定时器模块之间的高速通讯通道。
在一些实施例中，上述实施例中的方法还包括：硬件Core定时器在定时到达时，发送中断通知至高精度定时器模块，高精度定时器模块向分区PI描述符写入高精度定时器中断标志，向分区core发送PI物理中断。
在一些实施例中，当存在多个分区时，上述实施例中的方法还包括：高精度定时器模块从虚拟机定时器模型中获取定时到的虚拟机的VCPU的core id及虚拟机PI描述符地址信息，根据获取的虚拟机PI描述符地址向对应的PI描述符写入高精度定时器中断标志，根据获取的VCPU的core id向对应的core发送PI物理中断。
在一些实施例中，上述实施例中的方法还包括：高精度定时器模块从虚拟机定时器模型中删除已经完成定时中断注入的分区定时器数据，并从虚拟机定时器数据模型读取下一个最小定时值，将读取的虚拟机下一个最小定时值写入硬件Core定时器。
现结合具体应用场景对本发明做进一步的诠释说明。
第三实施例：
图3为本发明第三实施例提供的高性能定时器实现方法的流程图，由图3可知，在本实施例中，本发明提供的高性能定时器实现方法包括以下步骤：
S301：虚拟机初始化。
初始化包括以下步骤：
部署分区虚拟机的core通过Hypervisor关闭高精度定时器，防止产生不必要的外部中断影响；
单独分离出一个core运行嵌入式Hypervisor高精度定时器模块，启动该core高精度定时器硬件功能，该模块为不同分区高精度定时器提供时钟源；
在嵌入式Hypervisor软件层构建各个分区虚拟机与高精度定时器模块之间的高速通讯通道，提供不同分区0x380寄存器定时值向高精度定时器模块的写入机制；
嵌入式Hypervisor配置分区虚拟机硬件APIC Register Virtualization功能，目的是让GuestOS写0x380寄存器不需要软件进行指令解码，硬件会进行指令解码并直接在VM_Exit事件中将寄存器偏移地址和写入值传递给Hypervisor处理，从本质上消除了软件指令解码产生的时间瓶颈；
S302：分区生成定时器配置报文。
嵌入式Hypervisor捕获GuestOS对0x380寄存器写处理操作并不直接写入当前core的硬件寄存器，而是通过高速通讯通道将定时值、当前core id及对应的Posted Interrupt descriptor地址写入高精度定时器模块。
具体的，本步骤包括：
高精GuestOS产生定时要求向高精度定时器寄存器0x380写定时值；
CPU硬件捕获写0x380寄存器特权指令操作产生VM_Exit到Hypervisor处理；
嵌入式Hypervisor通过CPU硬件获取写寄存器偏移和写入值并将发起寄存器写操作的分区VCPU所在的core id和对应的硬件Posted Interrupt描述符地址整合后，通过定时器配置报文打包发送到高速通讯队列；
嵌入式Hypervisor发送事件通知高精度定时器模块写寄存器操作完成；
高精度定时器模块从高速通讯队列中获取定时器配置报文。
S303：将定时值写入硬件core定时器。
高精度定时器模块从高速通讯通道接收来自各个分区虚拟机配置的高精度定时器报文，更新内部数据模型，并进行计算与分析最后完成高精度定时器模块所在core硬件高精度定时器的配置。
具体的，本步骤包括：
高精度定时器模块收到Hypervisor消息事件通道通知，证明此时已经有虚拟机分区写入高精度定时器定时报文，准备从通讯队列读取定时报文内容；
高精度定时器模块解析消息事件信息获取高速通讯队列号，并从队列中读取虚拟机分区写入的高精度定时器定时报文；
高精度定时器模块分析读取的虚拟机配置定时器报文，以定时器偏移及定时值为索引将报文中的VCPU运行的coreid、硬件Posted Interrupt描述符地址存储到虚拟机定时器数据模型；
如果当前硬件Core定时器处于非定时状态则高精度定时器模块查找虚拟机定时器数据模型，将找出的最小定时值写入硬件Core定时器；如果当前硬件Core定时器处于定时状态，不进行硬件Core定时器的写入操作。
S304：硬件core定时器定时到达，产生中断。
高精度定时器模块所在的core硬件高精度定时器定时到后触发高精度定时器模块运行，通过内部数据模型查找需要定时处理的分区虚拟机Posted Interrupt descriptor地址和core id，找到数据后先向Posted Interrupt descriptor写入高精度定时器中断标志，然后向对应的core id发送Posted Interrupt核间中断，Intel Posted Interrupt硬件虚拟化机制会自动根据上述配置完成对不同分区虚拟机高精度定时器的中断注入，此过程中不会产生任何VM_Exit也不需要Hypervisor介入中断处理，因此性能可以达到与物理机一致的水平
具体的，本步骤包括：
硬件Core定时器定时到发中断通知高精度定时器模块；
高精度定时器模块从虚拟机定时器数据模型中获取定时到的相关虚拟机coreid及PI描述 符地址信息；
根据从数据模型中获取的虚拟机PI描述符地址向对应的PI描述符写入高精度定时器中断标志；
根据从数据模型中获取的VCPU的coreid向该core发送PI物理中断；
当软件Hypervisor完成本步骤后，硬件会自动从PI描述符中读取高精度定时器中断标志并自动产生高精度定时器中断并跳转到GuestOS中断处理例程执行，整个过程不会产生VM_Exit，因此性能与物理机完全一致。
S305：在硬件core定时器写入下一定时信息。
高精度定时器模块从虚拟机定时器模型中删除已经完成定时中断注入的分区定时器数据，并从虚拟机定时器数据模型读取下一个最小定时值；高精度定时器模块将读取的虚拟机下一个最小定时值写入硬件Core高精度定时器。
综上可知，通过本发明的实施，至少存在以下有益效果：
在生成定时器配置报文并写入定时器的过程中，不需要像现有技术那样硬件写0x380寄存器产生VM_Exit到Hypervisor进行指令解码后写入真实硬件寄存器，这样，GuestOS写0x380寄存器不需要软件进行指令解码，硬件会进行指令解码并直接在VM_Exit事件中将寄存器偏移地址和写入值传递给Hypervisor处理，从本质上消除了软件指令解码产生的时间瓶颈；
在本发明实施例中，在定时器定时到后，高精度定时器模块先向Posted Interrupt descriptor写入高精度定时器中断标志，然后向对应的core id发送Posted Interrupt核间中断，Intel Posted Interrupt硬件虚拟化机制会自动根据上述配置完成对不同分区虚拟机高精度定时器的中断注入，此过程中不会产生任何VM_Exit也不需要Hypervisor介入中断处理，因此性能可以达到与物理机一致的水平；
在本发明实施例中，部署分区虚拟机的core通过Hypervisor关闭高精度定时器，防止产生不必要的外部中断影响；
在本发明实施例中，单独分离出一个core运行嵌入式Hypervisor高精度定时器模块，启动该core高精度定时器硬件功能，该模块为不同分区高精度定时器提供时钟源；
在本发明实施例中，在嵌入式Hypervisor软件层构建各个分区虚拟机与高精度定时器模块之间的高速通讯通道，提供不同分区0x380寄存器定时值向高精度定时器模块的写入机制。
以上仅是本发明的具体实施方式而已，并非对本发明做任何形式上的限制，凡是依据本发明的技术实质对以上实施方式所做的任意简单修改、等同变化、结合或修饰，均仍属于本发明技术方案的保护范围。
工业实用性
本发明提供的上述技术方案，可以应用于高性能定时器实现的过程中，在生成定时器配置报文并写入定时器的过程中，不需要像现有技术那样硬件写0x380寄存器产生VM_Exit到Hypervisor进行指令解码后写入真实硬件寄存器，这样，GuestOS写0x380寄存器不需要软件进行指令解码，硬件会进行指令解码并直接在VM_Exit事件中将寄存器偏移地址和写入值传递给Hypervisor处理，从本质上消除了软件指令解码产生的时间瓶颈；进一步的，在定时器定时到后，高精度定时器模块先向Posted Interrupt descriptor写入高精度定时器中断标志，然后向对应的core id发送Posted Interrupt核间中断，Intel Posted Interrupt硬件虚拟化机制会自动根据上述配置完成对不同分区虚拟机高精度定时器的中断注入，此过程中不会产生任何VM_Exit也不需要Hypervisor介入中断处理，因此性能可以达到与物理机一致的水平。

Claims (24)

  1. 一种用于虚拟机的高性能定时器实现方法，包括：
    分区GuestOS产生定时要求，向高精度定时器寄存器0x380写定时值；
    分区CPU捕获写0x380寄存器特权指令操作，产生VM_Exit到Hypervisor处理；
    嵌入式Hypervisor通过CPU获取写寄存器偏移和写入值添加至定时器配置报文，发送至高速通讯队列；
    高精度定时器模块从所述高速通讯队列中获取所述定时器配置报文，并写入硬件core寄存器。
  2. 如权利要求1所述的高性能定时器实现方法，其中，当存在多个分区时，还包括：嵌入式Hypervisor将发起寄存器写操作的分区VCPU所在的core id、对应硬件Posted Interrupt描述符地址整合，并添加至定时器配置报文。
  3. 如权利要求1所述的高性能定时器实现方法，其中，在将定时器配置报文发送至高速通讯队列之后，还包括:通知所述高精度定时器模块写寄存器操作完成；所述高精度定时器模块在收到通知后，从所述高速通讯队列中获取所述定时器配置报文。
  4. 如权利要求1所述的高性能定时器实现方法，其中，所述高精度定时器模块将所述定时器配置报文写入硬件core寄存器包括：所述高精度定时器模块解析所述定时器配置报文，获取所述写寄存器偏移和写入值，确定定时器偏移及定时值，写入所述硬件Core定时器。
  5. 如权利要求4所述的高性能定时器实现方法，其中，当存在多个分区时，还包括：所述高精度定时器模块解析所述定时器配置报文，获取所述写寄存器偏移和写入值、发起寄存器写操作的分区VCPU所在的core id、对应硬件Posted Interrupt描述符地址，以定时器偏移及定时值为所述VCPU所在的core id、硬件Posted Interrupt描述符地址存储到虚拟机定时器模型；找出的最小定时值写入所述硬件Core定时器。
  6. 如权利要求5所述的高性能定时器实现方法，其中，还包括：判断所述硬件Core定时器是否处于非定时状态；如果所述硬件Core定时器处于非定时状态，则所述高精度定时器模块查找虚拟机定时器数据模型，将找出的最小定时值写入硬件Core定时器；如果所述硬件Core定时器处于定时状态，不进行所述硬件Core定时器的写入操作。
  7. 如权利要求1所述的高性能定时器实现方法，其中，还包括：部署分区虚拟机的core通过Hypervisor关闭高精度定时器。
  8. 如权利要求1所述的高性能定时器实现方法，其中，还包括：选择一core，在core中运行嵌入式Hypervisor和高精度定时器模块。
  9. 如权利要求1所述的高性能定时器实现方法，其中，还包括：在嵌入式Hypervisor软件层构建各个分区虚拟机与高精度定时器模块之间的高速通讯通道。
  10. 如权利要求1至9任一项所述的高性能定时器实现方法，其中，还包括：所述硬件Core 定时器在定时到达时，发送中断通知至所述高精度定时器模块，所述高精度定时器模块向分区PI描述符写入高精度定时器中断标志，向分区core发送PI物理中断。
  11. 如权利要求10所述的高性能定时器实现方法，其中，当存在多个分区时，还包括：所述高精度定时器模块从虚拟机定时器模型中获取定时到的虚拟机的VCPU的core id及虚拟机PI描述符地址信息，根据获取的虚拟机PI描述符地址向对应的PI描述符写入高精度定时器中断标志，根据获取的VCPU的core id向对应的core发送PI物理中断。
  12. 如权利要求11所述的高性能定时器实现方法，其中，还包括：所述高精度定时器模块从所述虚拟机定时器模型中删除已经完成定时中断注入的分区定时器数据，并从虚拟机定时器数据模型读取下一个最小定时值，将读取的虚拟机下一个最小定时值写入所述硬件Core定时器。
  13. 一种虚拟机，包括：
    分区GuestOS，设置为产生定时要求，向高精度定时器寄存器0x380写定时值；
    分区CPU，设置为捕获写0x380寄存器特权指令操作，产生VM_Exit到Hypervisor处理；
    嵌入式Hypervisor，设置为通过CPU获取写寄存器偏移和写入值添加至定时器配置报文，发送至高速通讯队列；
    高精度定时器模块，设置为从所述高速通讯队列中获取所述定时器配置报文，并写入硬件core寄存器。
  14. 如权利要求13所述的虚拟机，其中，当存在多个分区时，所述嵌入式Hypervisor还设置为将发起寄存器写操作的分区VCPU所在的core id、对应硬件Posted Interrupt描述符地址整合，并添加至定时器配置报文。
  15. 如权利要求13所述的虚拟机，其中，所述嵌入式Hypervisor在将定时器配置报文发送至高速通讯队列之后，还设置为通知所述高精度定时器模块写寄存器操作完成；所述高精度定时器模块还设置为在收到通知后，从所述高速通讯队列中获取所述定时器配置报文。
  16. 如权利要求13所述的虚拟机，其中，所述高精度定时器模块设置为解析所述定时器配置报文，获取所述写寄存器偏移和写入值，确定定时器偏移及定时值，写入所述硬件Core定时器。
  17. 如权利要求16所述的虚拟机，其中，当存在多个分区时，所述高精度定时器模块还设置为解析所述定时器配置报文，获取所述写寄存器偏移和写入值、发起寄存器写操作的分区VCPU所在的core id、对应硬件Posted Interrupt描述符地址，以定时器偏移及定时值为所述VCPU所在的core id、硬件Posted Interrupt描述符地址存储到虚拟机定时器模型；找出的最小定时值写入所述硬件Core定时器。
  18. 如权利要求17所述的虚拟机，其中，所述高精度定时器模块还设置为判断所述硬件Core 定时器是否处于非定时状态；如果所述硬件Core定时器处于非定时状态，则查找虚拟机定时器数据模型，将找出的最小定时值写入硬件Core定时器；如果所述硬件Core定时器处于定时状态，不进行所述硬件Core定时器的写入操作。
  19. 如权利要求13所述的虚拟机，其中，部署分区虚拟机的core还设置为通过Hypervisor关闭高精度定时器。
  20. 如权利要求13所述的虚拟机，其中，所述嵌入式Hypervisor还设置为选择一core，在core中运行嵌入式Hypervisor和高精度定时器模块。
  21. 如权利要求13所述的虚拟机，其中，所述嵌入式Hypervisor还设置为在软件层构建各个分区虚拟机与高精度定时器模块之间的高速通讯通道。
  22. 如权利要求13至21任一项所述的虚拟机，其中，所述硬件Core定时器还设置为所述硬件Core定时器在定时到达时，发送中断通知至所述高精度定时器模块；所述高精度定时器模块还设置为向分区PI描述符写入高精度定时器中断标志，向分区core发送PI物理中断。
  23. 如权利要求22所述的虚拟机，其中，当存在多个分区时，所述高精度定时器模块还设置为从虚拟机定时器模型中获取定时到的虚拟机的VCPU的core id及虚拟机PI描述符地址信息，根据获取的虚拟机PI描述符地址向对应的PI描述符写入高精度定时器中断标志，根据获取的VCPU的core id向对应的core发送PI物理中断。
  24. 如权利要求23所述的虚拟机，其中，所述高精度定时器模块还设置为从所述虚拟机定时器模型中删除已经完成定时中断注入的分区定时器数据，并从虚拟机定时器数据模型读取下一个最小定时值，将读取的虚拟机下一个最小定时值写入所述硬件Core定时器。
PCT/CN2015/089282 2015-07-30 2015-09-09 一种用于虚拟机的高性能定时器实现方法、虚拟机 WO2016131247A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510458635.0A CN106406974B (zh) 2015-07-30 2015-07-30 一种用于虚拟机的高性能定时器实现方法、虚拟机
CN201510458635.0 2015-07-30

Publications (1)

Publication Number Publication Date
WO2016131247A1 true WO2016131247A1 (zh) 2016-08-25

Family

ID=56689235

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/089282 WO2016131247A1 (zh) 2015-07-30 2015-09-09 一种用于虚拟机的高性能定时器实现方法、虚拟机

Country Status (2)

Country Link
CN (1) CN106406974B (zh)
WO (1) WO2016131247A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108196934A (zh) * 2016-12-08 2018-06-22 阿里巴巴集团控股有限公司 一种定时器的定时设置方法、装置和虚拟化设备
CN108241522A (zh) * 2016-12-27 2018-07-03 阿里巴巴集团控股有限公司 虚拟化环境中的睡眠状态切换方法、装置及电子设备

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108512780B (zh) * 2017-02-28 2020-12-15 华为技术有限公司 定时器实现方法及相关装置
CN112817701B (zh) * 2021-02-25 2024-03-12 北京火山引擎科技有限公司 定时器处理方法、装置、电子设备和计算机可读介质
CN114489816B (zh) * 2021-12-22 2024-05-14 瑞芯微电子股份有限公司 定时器装置和提供定时的方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1855085A (zh) * 2005-04-20 2006-11-01 国际商业机器公司 用于在多处理器计算机中提供有效虚拟时基的方法和设备
CN1928769A (zh) * 2005-09-09 2007-03-14 国际商业机器公司 用于tod－时钟导引的系统和方法
CN104239181A (zh) * 2013-06-24 2014-12-24 国际商业机器公司 累计用于电子系统的硬件计数的方法和电子系统

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8365168B1 (en) * 2007-07-09 2013-01-29 Parallels IP Holdings GmbH Method and system for processing isochronous data packets using virtual USB controller, and placing the isochronous data packets into a look-ahead queue having a plurality of blank packets
CN103049331B (zh) * 2012-12-06 2015-09-23 华中科技大学 一种虚拟功能的动态调度方法
CN103197971B (zh) * 2013-04-22 2016-11-23 哈尔滨工业大学 Windows操作系统Pentium Ⅳ架构下高精度低CPU占用率定时器的实现方法
US20150169339A1 (en) * 2013-12-13 2015-06-18 International Business Machines Corporation Determining Horizontal Scaling Pattern for a Workload
CN104598294B (zh) * 2015-01-07 2021-11-26 乾云数创(山东)信息技术研究院有限公司 用于移动设备的高效安全的虚拟化方法及其设备

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1855085A (zh) * 2005-04-20 2006-11-01 国际商业机器公司 用于在多处理器计算机中提供有效虚拟时基的方法和设备
CN1928769A (zh) * 2005-09-09 2007-03-14 国际商业机器公司 用于tod－时钟导引的系统和方法
CN104239181A (zh) * 2013-06-24 2014-12-24 国际商业机器公司 累计用于电子系统的硬件计数的方法和电子系统

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108196934A (zh) * 2016-12-08 2018-06-22 阿里巴巴集团控股有限公司 一种定时器的定时设置方法、装置和虚拟化设备
CN108196934B (zh) * 2016-12-08 2022-04-26 阿里巴巴集团控股有限公司 一种定时器的定时设置方法、装置和虚拟化设备
CN108241522A (zh) * 2016-12-27 2018-07-03 阿里巴巴集团控股有限公司 虚拟化环境中的睡眠状态切换方法、装置及电子设备
CN108241522B (zh) * 2016-12-27 2022-05-17 阿里巴巴集团控股有限公司 虚拟化环境中的睡眠状态切换方法、装置及电子设备

Also Published As

Publication number Publication date
CN106406974B (zh) 2020-07-17
CN106406974A (zh) 2017-02-15

Similar Documents

Publication Publication Date Title
WO2016131247A1 (zh) 一种用于虚拟机的高性能定时器实现方法、虚拟机
TWI547876B (zh) 虛擬環境之中斷處理方法與系統
US10331468B2 (en) Techniques for routing service chain flow packets between virtual machines
US10509673B2 (en) Synchronous user space function execution from a kernel context
TWI501102B (zh) 虛擬時間控制裝置、方法及電腦程式產品
US10678583B2 (en) Guest controlled virtual device packet filtering
US11113089B2 (en) Sharing data via virtual machine to host device bridging
US11537430B1 (en) Wait optimizer for recording an order of first entry into a wait mode by a virtual central processing unit
US9697041B2 (en) Method for dynamic interrupt balanced mapping based on current scheduling states of VCPUs
CN114218133A (zh) 一种数据传输方法及装置
US10346330B2 (en) Updating virtual machine memory by interrupt handler
US20160253196A1 (en) Optimized extended context management for virtual machines
US20210334228A1 (en) Managing network interface controller-generated interrupts
RU2635044C2 (ru) Режим слежения в устройстве обработки в системах трассировки команд
US9824225B1 (en) Protecting virtual machines processing sensitive information
WO2022247698A1 (zh) 资源配置方法和装置、电子设备及计算机可读存储介质
US9898307B2 (en) Starting application processors of a virtual machine
CN114499945A (zh) 一种虚拟机的入侵检测方法及装置
US8453149B2 (en) Efficient multi-core processing of events
KR101387986B1 (ko) 가상화 장치
CN109284178A (zh) 一种基于kvm虚拟化的中断透传方法及装置
CN108196934A (zh) 一种定时器的定时设置方法、装置和虚拟化设备
US20170149698A1 (en) Implicit dynamic receive queue steering for unidirectional flows in virtualized systems
CN102609299A (zh) 虚拟化系统及其创建方法、装置
JP6510430B2 (ja) トレースデータ編集装置及び方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15882386

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15882386

Country of ref document: EP

Kind code of ref document: A1