WO2016099150A1 - Thin-film transistor array substrate - Google Patents

Thin-film transistor array substrate Download PDF

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Publication number
WO2016099150A1
WO2016099150A1 PCT/KR2015/013802 KR2015013802W WO2016099150A1 WO 2016099150 A1 WO2016099150 A1 WO 2016099150A1 KR 2015013802 W KR2015013802 W KR 2015013802W WO 2016099150 A1 WO2016099150 A1 WO 2016099150A1
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Prior art keywords
layer
active layer
film transistor
thin film
intermediate layer
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PCT/KR2015/013802
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French (fr)
Korean (ko)
Inventor
백주혁
배종욱
오새룬터
이도형
박태욱
Original Assignee
엘지디스플레이 주식회사
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Application filed by 엘지디스플레이 주식회사 filed Critical 엘지디스플레이 주식회사
Priority to GB1705910.6A priority Critical patent/GB2548721B/en
Priority to US15/531,952 priority patent/US10192957B2/en
Priority to CN201580065784.9A priority patent/CN107004721B/en
Priority to JP2017518092A priority patent/JP6398000B2/en
Priority to DE112015005620.3T priority patent/DE112015005620B4/en
Priority claimed from KR1020150179783A external-priority patent/KR102518392B1/en
Publication of WO2016099150A1 publication Critical patent/WO2016099150A1/en
Priority to US16/210,934 priority patent/US10692975B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to a thin film transistor array substrate.
  • the importance of the flat panel display (FPD) has increased with the development of multimedia.
  • liquid crystal display (LCD), plasma display panel (PDP), field emission display (FED), organic light emitting device (Organic Light Emitting Device) Various displays have been put into practical use.
  • the organic light emitting display device has a high response time with a response speed of 1 ms or less, low power consumption, and no self-emission, thus having no problem in viewing angle.
  • the passive matrix method forms the anode and the cathode so as to be orthogonal and selects a line
  • the active matrix method drives the thin film transistor to each pixel electrode and is driven according to the voltage maintained by the capacitor capacitance connected to the gate electrode of the thin film transistor. That's the way it is.
  • the active layer of the thin film transistor is mainly formed of amorphous silicon or polycrystalline silicon, amorphous silicon has the advantage of simple film forming process and low production cost, but there is a problem that the electrical reliability is not secured.
  • polycrystalline silicon is very difficult to apply a large area due to high process temperature, there is a problem that the uniformity according to the crystallization method is not secured.
  • the active layer is formed of an oxide semiconductor
  • the thin film transistor including the oxide semiconductor active layer may be formed in various structures. Among them, a coplanar or an etch stopper structure is widely used due to device characteristics.
  • FIG. 1 is a cross-sectional view illustrating a thin film transistor having a conventional coplanar structure
  • FIG. 2 is a view schematically illustrating an atomic diffusion phenomenon
  • FIG. 3 is a cross-sectional image of a thin film transistor.
  • a light blocking film 20 is positioned on a substrate 15, and a buffer layer 25 is positioned on a light blocking film 20.
  • the active layer 30 of the oxide semiconductor is formed on the buffer layer 25, and the gate insulating layer 35 and the gate electrode 40 are positioned thereon.
  • An interlayer insulating layer 45 is disposed on the gate electrode 40, and the thin film transistor 10 is formed by connecting the source electrode 50a and the drain electrode 50b to the active layer 30, respectively.
  • the gate insulating layer 35, and the gate electrode 40 are formed in the thin film transistor, a plurality of subsequent heat treatment processes are performed. As shown in FIG. 2, when a subsequent heat treatment process is performed, an atomic diffusion phenomenon in which hydrogen or oxygen atoms of the gate insulating layer 35 diffuse into the active layer 30 occurs. Referring to FIG. 3, the region A of the active layer is In 11 Ga 1 Zn 0 . 9 O has an atomic ratio of 23 .8 and the B region is In 6 . 4 Ga 1 Zn 1 . It is measured that the atomic ratio of 3 O 13 .6 , the oxygen content at the interface between the active layer 30 and the gate insulating film 35 is increased.
  • oxygen in an unbound state is excessively present.
  • Oxygen is stabilized when it has two electrons, but the unbonded portion collects one electron moving in the channel of the active layer 30, thereby degrading the characteristics of the device.
  • the present invention provides a thin film transistor array substrate that can prevent degradation of the device and improve reliability.
  • a thin film transistor array substrate includes an active layer, an intermediate layer, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode and a drain electrode.
  • the active layer is located on the substrate and the gate insulating film is located on the active layer.
  • the gate electrode is located on the gate insulating film, and the interlayer insulating film is located on the gate electrode.
  • the source electrode and the drain electrode are located on the interlayer insulating film and are respectively connected to the active layer.
  • the intermediate layer is located between the active layer and the gate insulating film, and is made of an oxide semiconductor containing a Group 4 element.
  • the thin film transistor array substrate includes a gate electrode, a gate insulating film, an intermediate layer, an active layer, an etch stopper, a source electrode, and a drain electrode.
  • the gate electrode is located on the substrate and the gate insulating film is located on the gate electrode.
  • the active layer is located on the gate insulating film, and the etch stopper is located on the active layer.
  • the source electrode and the drain electrode are located on the etch stopper and are respectively connected to the active layer.
  • the intermediate layer is located between the active layer and the gate insulating film, and is made of an oxide semiconductor containing a Group 4 element.
  • the thin film transistor array substrate includes a substrate, an active layer, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode.
  • the active layer is located on the substrate and includes a lower active layer and an intermediate layer.
  • the gate insulating film is located on the active layer.
  • the gate electrode is located on the gate insulating film.
  • the interlayer insulating film is located on the gate electrode.
  • the source electrode and the drain electrode are located on the interlayer insulating film and are respectively connected to the active layer.
  • the intermediate layer is made of an oxide semiconductor containing a Group 4 element.
  • an intermediate layer including a Group 4 element is provided between the gate insulating film and the active layer, thereby preventing hydrogen or oxygen atoms of the gate insulating film from diffusing into the active layer by the heat treatment process, thereby preventing deterioration of the device.
  • the present invention can form an intermediate layer containing a silicon element between the active layer and the gate insulating film, thereby preventing the positive bias temperature stress degradation due to excess oxygen.
  • 1 is a cross-sectional view showing a thin film transistor having a conventional coplanar structure.
  • FIG. 2 is a diagram schematically illustrating an atomic diffusion phenomenon.
  • 3 is a cross-sectional image of a thin film transistor.
  • FIG. 4 is a diagram schematically illustrating an oxygen non-bonding state.
  • FIG. 5 is a view showing a thin film transistor array substrate according to a first embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a thin film transistor array substrate according to a second embodiment of the present invention.
  • FIG. 7 is a cross-sectional view illustrating a thin film transistor array substrate according to a third embodiment of the present invention.
  • FIG. 8 is a cross-sectional view illustrating a thin film transistor array substrate according to a fourth embodiment of the present invention.
  • FIG. 9 is a view illustrating a display device including a thin film transistor array substrate according to a first embodiment of the present invention.
  • FIGS. 10A to 10E are diagrams illustrating processes of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.
  • FIG. 11A to 11H are views illustrating a method of manufacturing a thin film transistor array substrate according to a third embodiment, according to processes.
  • 12A to 12F illustrate a method of manufacturing a thin film transistor array substrate according to a fourth embodiment of the present invention.
  • Figure 13 is a graph showing the results through the back scattering analysis method of the thin film transistor prepared according to the first embodiment of the present invention.
  • FIG. 14 is a graph showing the results of the backscattering analysis of the thin film transistor prepared according to the third embodiment of the present invention.
  • FIG. 15 is a graph showing drain current curves for a gate-source voltage of a thin film transistor according to Comparative Example 1.
  • FIG. 16 is a graph showing drain current curves for a gate-source voltage of a thin film transistor according to Comparative Example 2.
  • FIG. 17 is a graph showing drain current curves for a gate-source voltage of a thin film transistor according to Comparative Example 3.
  • FIG. 17 is a graph showing drain current curves for a gate-source voltage of a thin film transistor according to Comparative Example 3.
  • FIG. 18 is a graph showing drain current curves for a gate-source voltage of a thin film transistor according to Example 1 of the present invention.
  • FIG. 19 is a graph showing drain current curves for a gate-source voltage of a thin film transistor according to Comparative Example 4.
  • Example 20 is a graph showing drain current curves for a gate-source voltage of a thin film transistor according to Example 2 of the present invention.
  • FIG. 21 is a graph showing drain current curves of a gate-source voltage of a thin film transistor according to Comparative Example 5 of the present invention.
  • FIG. 22 is a graph showing drain current curves for a gate-source voltage of a thin film transistor according to Comparative Example 6 of the present invention.
  • FIG. 23 is a graph showing drain current curves for a gate-source voltage of a thin film transistor according to Example 3 of the present invention.
  • FIG. 24 is a graph showing the current change rate of the thin film transistor according to the third embodiment of the present invention.
  • 25 is a graph showing the amount of excess oxygen in the intermediate layer according to the silicon content of the intermediate layer in the thin film transistor prepared according to Example 4.
  • FIG. 26 is a graph illustrating the amount of excess oxygen in the intermediate layer according to the hydrogen content of the intermediate layer in the thin film transistor prepared according to Example 4 and the positive bias temperture stress according to the same.
  • FIG. 27 is a graph illustrating transcurves, threshold voltages, charge mobility, and drain-induced barrier lowering (DIBL) after varying the thickness of an intermediate layer to 50 kV, 100 kV, and 150 kV in the thin film transistor prepared according to Example 4.
  • DIBL drain-induced barrier lowering
  • FIG. 5 is a cross-sectional view illustrating a thin film transistor array substrate according to a first embodiment of the present invention.
  • the thin film transistor array substrate 100 is a thin film transistor having a coplanar type structure in which a gate electrode is positioned on an active layer.
  • the light blocking film 120 is positioned on the substrate 110.
  • the substrate 110 is made of transparent or opaque glass, plastic or metal.
  • the light blocking film 120 is for blocking external light from being incident therein and is made of a material capable of blocking light.
  • the light shielding film 120 is made of a material having a low reflectance, and includes, for example, resin or amorphous silicon (a-Si), germanium (Ge), tantalum oxide (TaOx), It may be made of a semiconductor-based material such as copper oxide (CuOx).
  • the buffer layer 130 is positioned on the entire substrate 110 on which the light blocking film 120 is located.
  • the buffer layer 130 is formed to protect the thin film transistor formed in a subsequent process from impurities such as alkali ions flowing out of the substrate 110 or lower layers, and is formed of silicon oxide (SiOx), silicon nitride (SiNx), or the like. It is made of multilayers.
  • the active layer 140 including the channel region CH and the conductorization region CP is positioned on the buffer layer 130.
  • the active layer 140 is made of an oxide semi-conductor.
  • An oxide semiconductor is, for example, an amorphous zinc oxide-based semiconductor.
  • an a-IGZO semiconductor is sputtered using a composite target of gallium oxide (Ga 2 O 3 ), indium oxide (In 2 O 3 ), and zinc oxide (ZnO). formed by a sputtering method.
  • chemical vapor deposition such as chemical vapor deposition or atomic layer deposition (ALD) may be used.
  • the semiconductor can be deposited.
  • the active layer 140 of the present invention is not limited to the zinc oxide semiconductor.
  • impurities are doped on both sides of the active layer 140 to provide a source region and a drain region.
  • the gate insulating layer 150 is positioned on the active layer 140.
  • the gate insulating layer 150 is formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.
  • the gate insulating layer 150 corresponds to the gate electrode 160 positioned on the upper portion and has a similar size. Thus, the gate insulating layer 150 insulates the gate electrode 160 from the active layer 140.
  • the gate electrode 160 is positioned on the gate insulating layer 150.
  • the gate electrode 160 includes copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and tantalum (Ta). And it consists of a single layer or a multilayer of any one or an alloy thereof selected from the group consisting of tungsten (W).
  • the gate electrode 160 is positioned to correspond to the channel region CH of the active layer 140.
  • An interlayer insulating layer 170 is positioned on the substrate 110 on which the gate electrode 160 is formed.
  • the interlayer insulating film 170 is formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.
  • the interlayer insulating layer 170 may include contact holes 175a and 175b exposing source and drain regions on both sides of the active layer 140.
  • the source electrode 180a and the drain electrode 180b are positioned on the interlayer insulating layer 170.
  • the source electrode 180a and the drain electrode 180b may be formed of a single layer or a multilayer.
  • molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), Nickel (Ni), neodymium (Nd) and copper (Cu) may be made of any one or an alloy thereof selected from the group consisting of.
  • the source electrode 180a and the drain electrode 180b are connected to the source region and the drain region of the active layer 140 through contact holes 175a and 175b formed in the interlayer insulating layer 170, respectively. Accordingly, the thin film transistor array substrate 100 according to the embodiment of the present invention is constructed.
  • the intermediate layer 145 is positioned between the active layer 140 and the gate insulating layer 150.
  • the intermediate layer 145 is positioned between the active layer 140 and the gate insulating layer 150 to form a barrier that prevents hydrogen or oxygen atoms of the gate insulating layer 150 from diffusing into the active layer 140 in a subsequent heat treatment process. Play a role.
  • the intermediate layer 145 is made of an oxide semiconductor containing a Group 4 element.
  • the intermediate layer 145 of the present invention includes indium, gallium, and zinc, and include Group 4 elements such as titanium (Ti), zirconium (Zr), silicon (Si), germanium (Ge), tin (Sn), It may further include lead (Pb).
  • the intermediate layer 145 is made of indium, gallium, zinc and silicon oxide.
  • the intermediate layer 145 has an atomic ratio of indium, gallium, and zinc of 1.1: 1: 1, respectively, while maintaining a pseudo ternary system.
  • the atomic ratio of the intermediate layer 145 is In 1 . 1 Ga 1 Zn 1 Si (0.5 to 2) O (7.3 to 8.15) .
  • the amount of indium occupies an atomic ratio of 100 to 110% with respect to the indium of the lower active layer 140
  • silicon, a Group 4 element occupies an atomic ratio of 50 to 200% with respect to zinc of the intermediate layer 145.
  • the atomic ratio of the Group 4 elements included in the intermediate layer 145 may gradually decrease from the interface adjacent to the gate insulating layer 150 to the interface adjacent to the active layer 140.
  • the atomic ratio of silicon may decrease gradually from 200% to 50% relative to the atomic ratio of zinc.
  • the intermediate layer 145 is made of a thickness of 40 to 70 ⁇ .
  • the thickness of the intermediate layer 145 is less than 40 GPa, it is difficult to function as a diffusion barrier to block elements diffused from the gate insulating layer 150.
  • the thickness of the intermediate layer 145 exceeds 70 GPa, the active layer 140 ), The charge mobility is reduced by affecting the channel. Therefore, the intermediate layer 145 of the present invention is made of a thickness of 40 to 70 ⁇ .
  • the intermediate layer 145 of the present invention contains a Group 4 element, for example silicon, in the film, the bond of the Group 4 element forms a strong double bond, which makes it thermally stable. Therefore, since the intermediate layer 145 can be provided between the active layer 140 and the gate insulating film 150 to prevent the diffusion of light elements without affecting the electrical characteristics of the device, the gate insulating film 150 is formed by the heat treatment process. There is an advantage of preventing the deterioration of the device by preventing the diffusion of hydrogen or oxygen atoms.
  • the intermediate layer 145 is illustrated and described as being located only in a region contacting the channel region CH and the gate insulating layer 150 of the active layer 140, the intermediate layer 145 is not limited thereto. It may be located in the entire area of the active layer 140.
  • FIG. 6 is a view showing a thin film transistor array substrate according to a second embodiment of the present invention.
  • the thin film transistor array substrate 200 is a thin film transistor having an etch stopper structure, in which a gate electrode is positioned under the active layer and an etch stopper is provided on the active layer. .
  • the gate electrode 220 is positioned on the substrate 210.
  • the substrate 110 is made of transparent or opaque glass, plastic or metal.
  • the gate electrode 220 includes copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and tantalum (Ta). And it consists of a single layer or a multilayer of any one or an alloy thereof selected from the group consisting of tungsten (W).
  • the gate insulating layer 230 is positioned on the gate electrode 220.
  • the gate insulating film 230 is formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.
  • the gate insulating layer 230 insulates the gate electrode 220 disposed below.
  • the active layer 250 including the channel region CH is positioned on the gate insulating layer 230.
  • the active layer 250 is an oxide semi-conductor, and an amorphous zinc oxide-based composite semiconductor, in particular, a-IGZO semiconductor, has gallium oxide (Ga 2 O 3 ), indium oxide (In 2 O 3 ), and zinc oxide (ZnO). It may be formed by a sputtering method using a composite target of the), in addition to the chemical vapor deposition method such as chemical vapor deposition or atomic layer deposition (ALD) may be used.
  • ALD atomic layer deposition
  • the atomic ratio of gallium, indium, zinc is 1: 1: 1, 2: 2: 1, 3: 2: 1, and 4: 2: 1 using an amorphous zinc target using a composite oxide target
  • An oxide composite semiconductor can be deposited.
  • impurities are doped on both sides of the active layer 250 to provide a source region and a drain region, and a source region and a drain region are provided.
  • An etch stopper 260 is positioned on the active layer 250.
  • the etch stopper 260 prevents the active layer 250 from being damaged in the etching process of the source electrode and the drain electrode, which will be described later.
  • the etch stopper 260 is positioned to correspond to the channel region CH of the active layer 250.
  • the etch stopper 260 is made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.
  • the source electrode 270a and the drain electrode 270b are positioned on the etch stopper 260, the active layer 250, and the gate insulating layer 230.
  • the source electrode 270a and the drain electrode 270b may be formed of a single layer or a multilayer.
  • molybdenum (Mo) aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), Nickel (Ni), neodymium (Nd) and copper (Cu) may be made of any one or an alloy thereof selected from the group consisting of.
  • the source electrode 270a and the drain electrode 270b are connected to the source region and the drain region of the active layer 250, respectively. Accordingly, the thin film transistor array substrate 200 according to the embodiment of the present invention is constructed.
  • the intermediate layer 240 is positioned between the active layer 250 and the gate insulating layer 230.
  • the intermediate layer 240 is positioned between the active layer 250 and the gate insulating layer 230, and serves as a barrier to prevent hydrogen or oxygen atoms of the gate insulating layer 230 from diffusing into the active layer 250 in a subsequent heat treatment process.
  • the intermediate layer 240 is made of an oxide semiconductor containing a Group 4 element.
  • the intermediate layer 240 of the present invention includes indium, gallium, and zinc, and include Group 4 elements such as titanium (Ti), zirconium (Zr), silicon (Si), germanium (Ge), tin (Sn), It may further include lead (Pb).
  • the intermediate layer 240 is made of indium, gallium, zinc and silicon oxide.
  • the intermediate layer 240 has an atomic ratio of 0.8: 1: 1 indium, gallium and zinc, respectively, while maintaining a pseudo ternary system.
  • the atomic ratio of the intermediate layer 240 is In 0 . 8 made of a Ga 1 Zn 1 Si 0 .5 O ( 4.2 ⁇ 4.7).
  • the amount of indium occupies an atomic ratio of 80 to 90% with respect to the indium of the lower active layer 250
  • silicon, a Group 4 element occupies an atomic ratio of 50% with respect to zinc of the intermediate layer 240.
  • the atomic ratio of the Group 4 elements included in the intermediate layer 240 may gradually decrease as the surface of the Group 4 element is moved from the interface adjacent to the gate insulating layer 230 to the interface adjacent to the active layer 250.
  • the atomic ratio of silicon may decrease gradually from 200% to 50% relative to the atomic ratio of zinc.
  • the intermediate layer 240 is made of a thickness of 50 to 100 ⁇ .
  • the thickness of the intermediate layer 145 is less than 50 GPa, it is difficult to function as a diffusion barrier to block elements diffused from the gate insulating film 230.
  • the thickness of the intermediate layer 240 exceeds 100 GPa, the active layer 250 ), The charge mobility is reduced by affecting the channel. Therefore, the intermediate layer 240 of the present invention is made of a thickness of 50 to 100 ⁇ .
  • the intermediate layer 240 of the present invention includes a Group 4 element, for example, silicon in the film, the bond of the Group 4 element forms a strong double bond, thereby making it thermally stable. Therefore, by providing the intermediate layer 240 between the active layer 250 and the gate insulating film 230, the hydrogen or oxygen atoms of the gate insulating film 230 can be prevented from being diffused by the heat treatment process to prevent deterioration of the device. There is an advantage to that.
  • the intermediate layer 240 is illustrated and described as being located only in the entire bottom surface of the active layer 250 and the region in contact with the gate insulating layer 230, the present invention is not limited thereto, and the intermediate layer 240 is the active layer 250. It may be positioned only in the region in contact with the channel region CH and the gate insulating layer 230.
  • FIG. 7 is a diagram illustrating a thin film transistor array substrate according to a third embodiment of the present invention.
  • the thin film transistor array substrate 300 is a thin film transistor having a coplanar type structure in which a gate electrode is positioned on an active layer.
  • the light blocking film 320 is positioned on the substrate 310.
  • the substrate 310 is made of transparent or opaque glass, plastic or metal.
  • the light blocking film 320 is for blocking external light from entering the inside, and is made of a material capable of blocking light.
  • the light shielding film 320 is made of a material having a low reflectance, and includes, for example, resin or amorphous silicon (a-Si), germanium (Ge), tantalum oxide (TaOx), It may be made of a semiconductor-based material such as copper oxide (CuOx).
  • the buffer layer 330 is disposed on the entire substrate 310 where the light blocking film 320 is located.
  • the buffer layer 330 is formed to protect the thin film transistor formed in a subsequent process from impurities such as alkali ions flowing out of the substrate 310 or lower layers, and is formed of silicon oxide (SiOx), silicon nitride (SiNx), or the like. It is made of multilayers.
  • An active layer 340 including a channel region CH and a conductorization region CP is positioned on the buffer layer 330.
  • the active layer 340 includes a lower active layer 342 and an intermediate layer 344.
  • the lower active layer 342 forms a lower portion of the active layer 340 and contacts the buffer layer 330, and the intermediate layer 344 forms an upper portion of the active layer 340.
  • the lower active layer 342 and the gate insulating layer 350 Located in between.
  • the lower active layer 342 is made of an oxide semi-conductor.
  • An oxide semiconductor is, for example, an amorphous zinc oxide-based semiconductor.
  • an a-IGZO semiconductor is sputtered using a composite target of gallium oxide (Ga 2 O 3 ), indium oxide (In 2 O 3 ), and zinc oxide (ZnO). formed by a sputtering method.
  • chemical vapor deposition such as chemical vapor deposition or atomic layer deposition (ALD) may be used.
  • the semiconductor can be deposited.
  • the active layer of the present invention is not limited to the zinc oxide semiconductor.
  • impurities are doped on both sides of the active layer 340 to include a source region and a drain region.
  • the intermediate layer 344 is positioned between the lower active layer 342 and the gate insulating layer 350 to prevent diffusion of hydrogen or oxygen atoms of the gate insulating layer 350 into the active layer 340 in a subsequent heat treatment process. Plays a role.
  • the intermediate layer 344 is made of an oxide semiconductor containing a Group 4 element.
  • the intermediate layer 344 of the present invention includes indium, gallium, and zinc, and include Group 4 elements such as titanium (Ti), zirconium (Zr), silicon (Si), germanium (Ge), tin (Sn), It may further include lead (Pb).
  • interlayer 344 is made of indium, gallium, zinc and silicon oxide.
  • the intermediate layer 344 has an atomic ratio of indium, gallium, and zinc of 1.1: 1: 1, respectively, while maintaining a pseudo ternary system.
  • the atomic ratio of the intermediate layer 344 is composed of In 5 Ga 1 Zn 1 Si (12 to 13) O 35 .
  • the amount of indium in the intermediate layer 344 occupies an atomic ratio of 4 to 6 times the gallium of the lower active layer 342, and the silicon in the Group 4 element is 12 to 13 times the gallium of the intermediate layer 344. Occupies the atomic ratio of.
  • the amount of oxygen in the intermediate layer 344 occupies 0 to 9% of the oxide forming composition of the three-element water system and the Group 4 element.
  • the atomic ratio of the Group 4 element, for example, silicon (Si) included in the intermediate layer 344 may be gradually decreased from the interface adjacent to the gate insulating layer 350 to the interface adjacent to the lower active layer 342.
  • the atomic ratio of silicon may decrease gradually from six to four times the atomic ratio of gallium.
  • the intermediate layer 344 is made of a thickness of 50 to 100 ⁇ .
  • the thickness of the intermediate layer 344 is less than 50 GPa, it is difficult to function as a diffusion barrier to block elements diffused from the gate insulating film 350.
  • the thickness of the intermediate layer 350 exceeds 100 GPa, the channel is affected. Given this, the charge mobility decreases. Therefore, the intermediate layer 344 of the present invention has a thickness of 50 to 100 mm 3.
  • the intermediate layer 344 of the present invention contains a group 4 element, for example silicon, in the film, and thus becomes stable thermally because the bond of the group 4 element forms a strong double bond. Therefore, since the intermediate layer 344 is provided between the active layer 340 and the gate insulating film 350 to prevent the diffusion of light elements without affecting the electrical characteristics of the device, the gate insulating film 350 is formed by the heat treatment process. There is an advantage of preventing the deterioration of the device by preventing the diffusion of hydrogen or oxygen atoms.
  • the intermediate layer 344 is illustrated and described as being located in the entire area of the lower active layer 342, the present invention is not limited thereto.
  • the intermediate layer 344 may be formed only in the channel region CH of the active layer 340. It may be located.
  • the gate insulating layer 350 is positioned on the active layer 340.
  • the gate insulating film 350 is formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.
  • the gate insulating layer 350 corresponds to the gate electrode 360 positioned on the upper portion and has a similar size. Thus, the gate insulating layer 350 insulates the gate electrode 360 from the active layer 340.
  • the gate electrode 360 is positioned on the gate insulating layer 350.
  • the gate electrode 160 includes copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and tantalum (Ta). And it consists of a single layer or a multilayer of any one or an alloy thereof selected from the group consisting of tungsten (W).
  • the gate electrode 360 is positioned to correspond to the channel region CH of the active layer
  • An interlayer insulating layer 370 is positioned on the substrate 310 on which the gate electrode 360 is formed.
  • the interlayer insulating film 370 is formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.
  • the interlayer insulating layer 370 includes contact holes 375a and 375b exposing source and drain regions on both sides of the active layer 340.
  • the source electrode 380a and the drain electrode 380b are positioned on the interlayer insulating layer 370.
  • the source electrode 380a and the drain electrode 380b may be formed of a single layer or a multilayer.
  • molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), Nickel (Ni), neodymium (Nd) and copper (Cu) may be made of any one or an alloy thereof selected from the group consisting of.
  • the source electrode 380a and the drain electrode 380b are connected to the source region and the drain region of the active layer 340 through contact holes 375a and 375b formed in the interlayer insulating layer 370, respectively.
  • the passivation layer 385 is positioned on the substrate 310 on which the source electrode 380a and the drain electrode 380b are positioned.
  • the passivation film 385 protects and insulates the thin film transistors below.
  • the passivation film 385 is formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof, and includes a via hole 387 exposing the drain electrode 380b.
  • the pixel electrode 390 is positioned on the passivation film 385. The pixel electrode 390 is connected to the drain electrode 380b through the via hole 387 to receive a data voltage.
  • the pixel electrode 390 is made of transparent indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or the like. Accordingly, the thin film transistor array substrate 300 according to the third embodiment of the present invention is constructed.
  • FIG. 8 is a cross-sectional view illustrating a thin film transistor array substrate according to a fourth embodiment of the present invention.
  • the thin film transistor array substrate 400 according to the fourth embodiment of the present invention is a thin film transistor having a coplanar structure, in which a gate electrode is positioned on an active layer.
  • the thin film transistor array substrate 400 according to the fourth embodiment of the present invention will not be described in detail with respect to the same components as the thin film transistor array substrate 100 according to the first embodiment.
  • the light blocking film 420 is positioned on the substrate 410, and the buffer layer 430 is positioned on the entire substrate 410 on which the light blocking film 420 is located.
  • An active layer 440 including a channel region CH and a conductorization region CP is positioned on the buffer layer 430.
  • the active layer 440 is made of an oxide semi-conductor.
  • An oxide semiconductor is, for example, an amorphous zinc oxide-based semiconductor.
  • an a-IGZO semiconductor is sputtered using a composite target of gallium oxide (Ga 2 O 3 ), indium oxide (In 2 O 3 ), and zinc oxide (ZnO). formed by a sputtering method.
  • the semiconductor can be deposited.
  • the active layer 440 of the present invention is not limited to the zinc oxide semiconductor.
  • impurities are doped on both sides of the active layer 440 to provide a source region and a drain region.
  • the gate insulating layer 450 is positioned on the active layer 440, and the gate electrode 460 is positioned on the gate insulating layer 450.
  • the gate electrode 460 is positioned to correspond to the channel region CH of the active layer 440.
  • An interlayer insulating layer 470 is disposed on the substrate 410 on which the gate electrode 460 is formed, and the interlayer insulating layer 470 includes contact holes 475a exposing source and drain regions on both sides of the active layer 440. 475b).
  • the source electrode 480a and the drain electrode 480b are positioned on the interlayer insulating film 470, and the source electrode 480a and the drain electrode 480b are formed through the contact holes 475a and 475b formed in the interlayer insulating film 470. It is connected to the source region and the drain region of the active layer 440, respectively. Accordingly, the thin film transistor array substrate 400 according to the fourth embodiment of the present invention is constructed.
  • excess oxygen diffused from the gate insulating layer 450 may be present at an interface between the active layer 440 and the gate insulating layer 450 by a subsequent heat treatment process.
  • the oxygen content at the interface between the active layer 440 and the gate insulating film 450 increases, positive bias temporal stress deterioration occurs.
  • the oxygen content decreases the conduction of the semiconductor device occurs. To deteriorate the characteristics of the device.
  • an intermediate layer 445 is formed between the active layer 440 and the gate insulating layer 450.
  • the intermediate layer 445 serves to prevent the positive bias temperture stress degradation and to prevent the device from conducting.
  • the intermediate layer 445 is formed of an oxide semiconductor containing a Group 4 element to remove excess oxygen present at the interface between the active layer 440 and the gate insulating layer 450, that is, the intermediate layer 445.
  • the intermediate layer 445 of the present invention includes indium, gallium, and zinc, and include Group 4 elements such as titanium (Ti), zirconium (Zr), silicon (Si), germanium (Ge), tin (Sn), It may further include lead (Pb).
  • the intermediate layer 145 is made of indium, gallium, zinc and silicon oxide.
  • the intermediate layer 445 includes a Group 4 element, preferably a silicon (Si) element, silicon may be bonded to the unbound oxygen to reduce the amount of unbound oxygen. That is, by including the Group 4 element in the intermediate layer 445, the excess oxygen can be removed to prevent the positive bias temperature stress degradation.
  • the content of silicon element may be 2.9 to 3.2 ⁇ 10 22 cm ⁇ 3 .
  • the excess oxygen present in the intermediate layer 445 may be combined with silicon to reduce the amount of excess oxygen to prevent the positive bias temperature stress degradation. have.
  • the content of the silicon element of the intermediate layer 445 is 3.2 ⁇ 10 22 cm ⁇ 3 or less, the amount of excess oxygen present in the intermediate layer 445 is reduced too much, so that the device becomes a conductor and the characteristics of the thin film transistor are deteriorated. Can be prevented.
  • the intermediate layer 445 of the present invention contains a certain amount of hydrogen, so that the electrons can not be bonded by bonding hydrogen to the unbound oxygen. That is, some excess oxygen is present in the intermediate layer 445, but hydrogen is bonded to the excess oxygen, so that the electrons of the active layer are not bonded to the excess oxygen, thereby preventing the occurrence of the positive bias temperature stress degradation.
  • the amount of excess oxygen in the intermediate layer 445 is defined as the amount of oxygen relative to the metal. Since the intermediate layer 445 is made of indium, gallium, zinc, and oxygen and silicon is added, the intermediate layer 445 may include indium, gallium, zinc, silicon, and oxygen.
  • x is greater than y when the amount of oxygen actually measured in the intermediate layer 445 is x, oxygen is excessively present, and when y is greater than x, oxygen is insufficient.
  • the intermediate layer 445 may include as much hydrogen as the amount of excess oxygen remaining in the intermediate layer 445, and the hydrogen content may be 1.2 to 1.6 ⁇ 10 21 cm ⁇ 3 .
  • the content of hydrogen depends on the content of the above-described silicon element, for example, if the content of silicon element is 2.9 ⁇ 10 22 cm ⁇ 3 , the content of hydrogen may be 1.6 ⁇ 10 21 cm ⁇ 3 , and the silicon If the content of the element is 3.2 ⁇ 10 22 cm ⁇ 3 , the content of hydrogen may be 1.2 ⁇ 10 21 cm ⁇ 3 . That is, when a silicon element is added in a predetermined amount in the intermediate layer 445, hydrogen is added by the amount of excess oxygen remaining.
  • the intermediate layer 445 may include as much hydrogen as the amount of excess oxygen remaining in the intermediate layer 445, and the hydrogen content may be 1.2 to 1.6 ⁇ 10 21 cm ⁇ 3 .
  • the content of hydrogen depends on the content of the above-described silicon element, for example, if the content of silicon element is 2.9 ⁇ 10 22 cm ⁇ 3 , the content of hydrogen may be 1.6 ⁇ 10 21 cm ⁇ 3 , and the silicon If the content of the element is 3.2 ⁇ 10 22 cm ⁇ 3 , the content of hydrogen may be 1.2 ⁇ 10 21 cm ⁇ 3 . That is, when a silicon element is added in a predetermined amount in the intermediate layer 445, hydrogen is added by the amount of excess oxygen remaining.
  • Table 1 is a table showing the threshold voltage and the positive bias temperature stress of the thin film transistor according to the amount of oxygen in the interlayer.
  • the device when the amount of oxygen in the intermediate layer is reduced to 100% or less, the device becomes a conductor and no threshold voltage appears, and the positive bias temperture stress is not measured. On the other hand, if the amount of oxygen in the interlayer is more than 100% of the metal, the threshold voltage increases and the positive bias temperature stress also increases.
  • the intermediate layer 445 of the present invention is made of a thickness of 50 to 100 ⁇ . If the thickness of the intermediate layer 445 is 50 GPa or more, the intermediate layer 445 may serve as a diffusion barrier to block elements such as oxygen diffused from the gate insulating film 450. If the thickness of the intermediate layer 445 is 100 GPa or less, the intermediate layer 445 may be used. It can act as a channel of the active layer 440 to prevent the device from deteriorating. Therefore, the intermediate layer 445 of the present invention has a thickness of 50 to 100 kPa.
  • the thin film transistor array substrate according to the fourth embodiment of the present invention may form an intermediate layer including silicon elements between the active layer and the gate insulating layer, thereby preventing the positive bias temperature stress degradation due to excess oxygen. .
  • the intermediate layer 445 is illustrated and described as being located only in an area in contact with the channel region CH and the gate insulating layer 450 of the active layer 440, the intermediate layer 445 is not limited thereto. It may be located in the entire area of the active layer 440.
  • FIG. 9 is a diagram illustrating a display device including a thin film transistor array substrate according to a first embodiment of the present invention.
  • the description of the above-described thin film transistor array substrate will be omitted, and the organic light emitting display device will be described as an example of the display device.
  • the present invention is not limited to the organic light emitting display device, and can be used for flat panel display devices such as liquid crystal display devices.
  • a thin film transistor TFT including an active layer 140, a gate electrode 160, a source electrode 180a, and a drain electrode 180b is positioned on the substrate 110.
  • the organic insulating layer 190 is disposed on them.
  • the organic insulating layer 190 may be made of organic materials such as photo acryl, polyimide, benzocyclobutene resin, and acrylate resin.
  • the organic insulating layer 190 includes a via hole 195 that exposes the drain electrode 180b of the thin film transistor TFT.
  • the pixel electrode 285 is positioned on the organic insulating layer 190.
  • the pixel electrode 285 may be formed of a transparent conductive film.
  • the transparent conductive film may be a transparent and conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • high reflectance such as aluminum (Al), aluminum-nedium (Al-Nd), silver (Ag), silver alloy (Ag alloy), etc., is formed on the lower portion of the transparent conductive film.
  • It may further include a reflective metal film having a property of, it may be made of a structure of a transparent conductive film / reflective metal film / transparent conductive film.
  • the pixel electrode 285 may have a structure of, for example, ITO / Ag / ITO.
  • the pixel electrode 285 is connected to the drain electrode 180b through a via hole 195 provided in the organic insulating layer 190.
  • the bank layer 287 exposing the pixel electrode 285 is disposed on the pixel electrode 285.
  • the bank layer 287 defines a pixel and insulates the pixel electrode 285.
  • the bank layer 287 is made of an organic material such as polyimide, benzocyclobutene series resin, and acrylate.
  • the bank layer 287 includes an opening 288 exposing the pixel electrode 285.
  • the organic layer 290 is disposed on the pixel electrode 285 and the bank layer 287.
  • the organic layer 290 may include at least a light emitting layer, and may further include a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer.
  • the opposite electrode 295 is positioned on the organic layer 290.
  • the counter electrode 295 may be made of silver (Ag), magnesium (Mg), calcium (Ca), or the like as metals having a low work function.
  • an organic light emitting diode OLED including the pixel electrode 285, the organic layer 290, and the counter electrode 295 is configured. Accordingly, the organic light emitting display device 280 including the thin film transistor TFT and the organic light emitting diode OLED is formed on the substrate 110.
  • the thin film transistor having the coplanar structure according to the first embodiment will be described as an example, but the present invention can be applied to the etch stopper structure according to the second embodiment.
  • FIGS. 10A to 10E are diagrams illustrating processes of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.
  • Semiconductor-based materials such as germanium (Ge), tantalum oxide (TaOx), and copper oxide (CuOx) are formed and patterned using a mask to form the light shielding film 120.
  • the light blocking film 120 is formed for each region where an active layer will be formed later.
  • the present invention is not limited thereto, and the light blocking film 120 may be formed on the entire surface of the substrate 110.
  • silicon oxide (SiOx) or silicon nitride (SiNx) is deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or sputtering deposition on the substrate 110 on which the light shielding film 120 is formed.
  • the buffer layer 130 is formed.
  • the oxide semiconductor layer is sputtered onto the substrate 110 on which the buffer layer 130 is formed by using a composite target of indium oxide (In 2 O 3 ), tin oxide (SnO), and zinc oxide (ZnO). Laminated.
  • the oxide semiconductor layer is patterned using a mask to form the active layer 140.
  • the active layer 140 may be formed using a chemical vapor deposition method such as chemical vapor deposition or atomic layer deposition (ALD). At this time, the active layer 140 is formed to correspond to the light shielding film 120 formed on the substrate 110, so that light incident from the bottom does not reach the active layer 140 to prevent the leakage current caused by light. prevent.
  • ALD atomic layer deposition
  • sputtering is performed on the substrate 110 on which the active layer 140 is formed using a composite target of indium oxide (In 2 O 3 ), tin oxide (SnO), and zinc oxide (ZnO).
  • the oxide semiconductor layer 147 is laminated by the method.
  • silicon oxide (SiOx) or silicon nitride (SiNx) is deposited by CVD, PECVD, or sputtering deposition to form an insulating layer 152.
  • the gate electrode 160 is formed by etching the metal layer 162 using the photoresist pattern PR as a mask.
  • the metal layer 162 is etched by wet etching using an etchant capable of etching the material.
  • the insulating layer 152 is etched using the photoresist pattern PR to form the gate insulating layer 150.
  • the insulating layer 152 is etched by a plasma etching process using a gas such as argon (Ar), and is formed in a similar size along the gate electrode 160 positioned on the insulating layer 152.
  • Ar argon
  • the insulating layer 152 is etched in the plasma etching process, when the oxide semiconductor layer 147 and the active layer 140 are exposed, the etching process is performed on the oxide semiconductor layer 147 and the active layer 140 for a predetermined time.
  • the active layer 140 is conductored.
  • the channel region CH of the active layer 140 corresponding to the region where the gate electrode 160 and the gate insulating layer 150 are located is formed, and the conductive region except for the channel region CH of the active layer 140 is formed. (CP) is formed.
  • the oxide semiconductor layer 147 exposed by the gate insulating layer 150 is etched to form an intermediate layer 145. Accordingly, the gate electrode 160, the gate insulating layer 150, and the intermediate layer 145 are formed on the channel region CH of the active layer 140 in a similar size. Thereafter, the photoresist pattern PR is stripped and removed.
  • an interlayer insulating layer 170 is formed by depositing silicon oxide (SiOx) or silicon nitride (SiNx) on the substrate 110 on which the gate electrode 160 is formed by CVD, PECVD, or sputter deposition. do.
  • the interlayer insulating layer 170 is etched to form contact holes 175a and 175b exposing the conductive region CP, which is part of both sides of the active layer 140.
  • the source electrode 180a and the drain electrode 180b are formed by stacking and patterning any one or an alloy thereof.
  • the source electrode 180a and the drain electrode 180b are connected to the active layer 140 through contact holes 175a and 175b formed in the interlayer insulating layer 170, respectively. Accordingly, a thin film transistor TFT including the active layer 140, the intermediate layer 145, the gate electrode 160, the source electrode 180a, and the drain electrode 180b is formed.
  • FIG. 11A to 11H are views illustrating a method of manufacturing a thin film transistor array substrate according to a process, according to a third embodiment of the present invention.
  • Semiconductor-based materials such as germanium (Ge), tantalum oxide (TaOx), and copper oxide (CuOx) are formed and patterned using a mask to form a light shielding film 320.
  • the light blocking film 320 is formed for each region where an active layer will be formed later.
  • the present invention is not limited thereto, and the light blocking film 320 may be formed on the entire surface of the substrate 310.
  • silicon oxide (SiOx) or silicon nitride (SiNx) is deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or sputtering deposition on the substrate 310 on which the light blocking film 320 is formed.
  • the buffer layer 330 is formed.
  • the first oxide semiconductor is sputtered by using a composite target of indium oxide (In 2 O 3 ), tin oxide (SnO), and zinc oxide (ZnO) on the substrate 310 on which the buffer layer 330 is formed.
  • Layer 332 is stacked.
  • the second oxide semiconductor layer 334 is stacked by sputtering using a composite target of indium oxide (In 2 O 3 ), tin oxide (SnO), silicon oxide (SiOx), and zinc oxide (ZnO). do.
  • the first oxide semiconductor layer 332 and the second oxide semiconductor layer 334 are patterned using a mask to form an active layer 340 including a lower active layer 342 and an intermediate layer 344.
  • the active layer 340 may be formed using a chemical vapor deposition method such as chemical vapor deposition or atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the active layer 340 is formed to correspond to the light shielding film 320 formed on the substrate 310, so that the light incident from the bottom does not reach the active layer 340 to prevent the leakage current caused by the light is generated. prevent.
  • an insulating layer 352 is formed by depositing silicon oxide (SiOx) or silicon nitride (SiNx) on a substrate 310 on which the active layer 340 is formed by CVD, PECVD, or sputter deposition. . Subsequently, copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Sp) are deposited on the insulating layer 352. Nd), tantalum (Ta), and tungsten (W) may be deposited by depositing any one or alloys thereof to form the metal layer 354.
  • a photoresist is applied on the metal layer 354, and the photoresist is exposed and developed to form a photoresist pattern PR.
  • the photoresist pattern PR is formed to correspond to the region where the channel region of the active layer 340 is to be formed.
  • the gate electrode 360 is formed by etching the metal layer 354 using the photoresist pattern PR as a mask.
  • the metal layer 360 is etched by wet etching using an etchant capable of etching the material.
  • the insulating layer 352 is etched using the photoresist pattern PR to form the gate insulating layer 350.
  • the insulating layer 352 is etched by a plasma etching process using a gas such as argon (Ar), and is formed in a similar size along the gate electrode 360 positioned on the insulating layer 352.
  • the active layer 340 is conductive by performing a predetermined time etching process on the active layer 340. That is, when the plasma etching process is performed on the active layer 340, oxygen in the active layer 340 is released and impurities are injected to improve conductivity.
  • the channel region CH of the active layer 340 corresponding to the region where the gate electrode 360 and the gate insulating layer 350 are located is formed, and the conductive region except for the channel region CH of the active layer 340 is formed. (CP) is formed. Therefore, the gate electrode 360 and the gate insulating film 350 are formed on the channel region CH of the active layer 340 in a similar size. Thereafter, the photoresist pattern PR is stripped and removed.
  • an interlayer insulating layer 370 is formed by depositing silicon oxide (SiOx) or silicon nitride (SiNx) on a substrate 310 on which the gate electrode 360 is formed by CVD, PECVD, or sputtering deposition. do.
  • the interlayer insulating layer 370 is etched to form contact holes 375a and 375b exposing the conductive region CP, which is part of both sides of the active layer 340.
  • the source electrode 380a and the drain electrode 380b are formed by stacking and patterning any one or an alloy thereof.
  • the source electrode 380a and the drain electrode 380b are connected to the active layer 340 through the contact holes 375a and 375b formed in the interlayer insulating layer 370, respectively. Accordingly, a thin film transistor TFT including an active layer 340 including a lower active layer 342 and an intermediate layer 344, a gate electrode 360, a source electrode 380a, and a drain electrode 380b is formed. .
  • the passivation film 385 is formed by depositing silicon oxide (SiOx) or silicon nitride (SiNx) on the substrate 310 on which the thin film transistor (TFT) is formed by CVD, PECVD, or sputtering deposition. Form.
  • the passivation film 385 is etched to form a via hole 387 exposing a part of the drain electrode 385b.
  • the ITO, IZO, ITZO, ZnO, and the like are stacked and patterned on the substrate 310 to form the pixel electrode 390. Accordingly, the thin film transistor array substrate according to the third embodiment of the present invention is manufactured.
  • FIGS. 12A to 12F are diagrams illustrating processes of manufacturing a thin film transistor array substrate according to a fourth embodiment of the present invention.
  • Semiconductor-based materials such as germanium (Ge), tantalum oxide (TaOx), and copper oxide (CuOx) are formed and patterned using a mask to form a light shielding film 420.
  • the light blocking film 420 is formed for each region where an active layer will be formed later.
  • the present invention is not limited thereto, and the light blocking film 420 may be formed on the entire surface of the substrate 410.
  • silicon oxide (SiOx) or silicon nitride (SiNx) is deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or sputtering deposition on the substrate 410 on which the light shielding film 420 is formed.
  • the buffer layer 430 is formed.
  • the oxide semiconductor layer is sputtered onto the substrate 410 on which the buffer layer 430 is formed by using a composite target of indium oxide (In 2 O 3 ), tin oxide (SnO), and zinc oxide (ZnO). Laminated.
  • the oxide semiconductor layer is patterned using a mask to form the active layer 440.
  • the active layer 440 may be formed using a chemical vapor deposition method such as chemical vapor deposition or atomic layer deposition (ALD). At this time, the active layer 440 is formed to correspond to the light shielding film 420 formed on the substrate 410, so that light incident from the bottom does not reach the active layer 440 to prevent leakage current caused by light. prevent.
  • ALD atomic layer deposition
  • an oxide layer 447 and an insulating layer 452 are deposited by depositing silicon oxide (SiOx) or silicon nitride (SiNx) on the substrate 410 on which the active layer 440 is formed by CVD and PECVD deposition methods. ).
  • the oxide layer 447 is formed on the surface of the active layer 440.
  • the argon (Ar) and oxygen (O) gases are controlled in the CVD process of forming the insulating layer 452, the materials of the active layer and silicon are mixed. Can be formed.
  • copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), and nickel are used as a sputtering deposition method on the insulating layer 452.
  • Ni neodymium (Nd), tantalum (Ta), and tungsten (W) any one selected from the group consisting of or alloys thereof are deposited to form a metal layer 462.
  • a photoresist is applied on the metal layer 462, exposed and developed to form a photoresist pattern, and the metal layer 462 is etched using the photoresist pattern as a mask to form a gate electrode. 460 is formed.
  • the metal layer 462 is etched by wet etching using an etchant capable of etching the material.
  • the insulating layer 452 is etched using the gate electrode 460 to form the gate insulating layer 450.
  • the insulating layer 452 is etched by a plasma etching process using a gas such as argon (Ar), and is formed in a similar size along the gate electrode 460 disposed on the insulating layer 452.
  • argon Ar
  • the oxide layer 447 and the active layer 440 are exposed, the oxide layer 447 and the active layer 440 are etched for a predetermined time to be active.
  • Conduct layer 440 is etched using the gate electrode 460 to form the gate insulating layer 450.
  • the channel region CH of the active layer 440 corresponding to the region where the gate electrode 460 and the gate insulating layer 450 are located is formed, and the conductive region except for the channel region CH of the active layer 440 is formed. (CP) is formed.
  • the oxide layer 447 exposed by the gate insulating layer 450 is etched to form an intermediate layer 445. Accordingly, the gate electrode 460, the gate insulating layer 450, and the intermediate layer 445 are formed on the channel region CH of the active layer 440 in a similar size.
  • an interlayer insulating layer 470 is formed by depositing silicon oxide (SiOx) or silicon nitride (SiNx) on a substrate 410 on which the gate electrode 460 is formed by CVD, PECVD, or sputter deposition. do.
  • the interlayer insulating layer 470 is etched to form contact holes 475a and 475b exposing the conductive region CP, which is a part of both sides of the active layer 440.
  • the source electrode 480a and the drain electrode 480b are formed by stacking and patterning any one or an alloy thereof.
  • the source electrode 480a and the drain electrode 480b are connected to the active layer 440 through the contact holes 475a and 475b formed in the interlayer insulating layer 470, respectively.
  • a thin film transistor TFT including an active layer 440, an intermediate layer 445, a gate electrode 460, a source electrode 480a, and a drain electrode 480b is formed.
  • Figure 13 is a graph showing the results through the back scattering analysis method of the thin film transistor prepared according to the first embodiment of the present invention
  • Figure 14 is a back scattering analysis method of the thin film transistor prepared according to the third embodiment of the present invention It is a graph showing the result through.
  • a stacked structure of an active layer, an intermediate layer, and a gate insulating layer was analyzed by a backscattering spectrometry (RBS), and all of silicon (Si), which is a Group 4 element, was included.
  • silicon (Si), which is a Group 4 element was also included in the stacked structure of the active layer including the lower active layer and the intermediate layer and the gate insulating layer.
  • the presence of this Group 4 element means that the bond of Group 4 element forms a strong covalent bond, which reduces the metal non-bonding state and has more thermally stable characteristics.
  • silicon (Si) may be present in a ratio of 50 to 200% relative to the atomic ratio of zinc in the layer.
  • the thin film transistor of the present invention will be described in detail in the following examples.
  • the embodiment disclosed below is only one embodiment of the present invention and the present invention is not limited to the following embodiments.
  • a buffer layer of SiO 2 was formed on the glass substrate, an active layer consisting of an atomic ratio of In 1 Ga 1 Zn 1 O 4 was formed on the buffer layer, and a gate insulating film of SiO 2 was formed on the active layer.
  • a gate electrode was formed of molybdenum on the gate insulating film, an interlayer insulating film of SiO 2 was formed, and a source electrode and a drain electrode were formed of aluminum to prepare a thin film transistor.
  • the thin film transistor was manufactured by changing only the intermediate layer formed by sputtering to an thickness of 30 kPa having an atomic ratio of 4 O 5 .
  • the thin film transistor was manufactured by changing only the intermediate layer formed by sputtering to an thickness of 90 kPa having an atomic ratio of 5 O 9 .
  • FIG. 15 is a graph illustrating drain current curves of a gate-source voltage of a thin film transistor according to Comparative Example 1
  • FIG. 16 is a graph illustrating drain current curves of a gate-source voltage of a thin film transistor according to Comparative Example 2
  • FIG. 17 is a graph illustrating drain current curves of a gate-source voltage of a thin film transistor according to Comparative Example 3
  • FIG. 18 illustrates a drain current curve of gate-source voltage of a thin film transistor according to Example 1 of the present invention. It is a graph.
  • the threshold voltage, slope, and charge mobility of the thin film transistors according to Comparative Example 1 and Example 1 were measured and shown in Table 2 below.
  • the gate-source voltage was shifted to the positive side, and the threshold voltage was 4.2V, the slope was 0.21, and the charge mobility was 4.4 cm 2 / Vs.
  • the intermediate layer is In 1 . 3 Ga 1 Zn 1 Si 0 .
  • Comparative Example 2 which had a thickness of 30 mA with an atomic ratio of 4 O 5, the gate-source voltage was shifted toward the negative side.
  • the intermediate layer is In 0 . 9 Ga 1 Zn 1 Si 2 .
  • Comparative Example 3 which has a thickness of 90 ⁇ with an atomic ratio of 5 O 9 , a phenomenon in which the driving voltage Vds crosses the current-voltage curve between 0.1 V and 10 V occurs when the device is driven, and the channel layer of the device is not uniform. It can be seen that it is not formed.
  • the intermediate layer is In 1 . 1 Ga 1 Zn 1 Si 0 .
  • a gate electrode was formed of molybdenum on the glass substrate, and a gate insulating film of SiO 2 was formed. Then, an active layer composed of an atomic ratio of In 1 Ga 1 Zn 1 O 4 was formed, and an etch stopper of SiO 2 was formed on the active layer. Next, a thin film transistor was manufactured by forming a source electrode and a drain electrode from aluminum.
  • FIGS. 19 and 20 Drain currents for the gate-source voltages of the thin film transistors manufactured according to Comparative Example 4 and Example 2 were measured and shown in FIGS. 19 and 20, respectively.
  • FIG. 19 is a graph illustrating drain current curves of gate-source voltages of a thin film transistor according to Comparative Example 4
  • FIG. 20 illustrates drain current curves of gate-source voltages of a thin film transistor according to Example 2 of the present invention. It is a graph.
  • the threshold voltage, the slope and the charge mobility of the thin film transistors according to Comparative Example 4 and Example 2 were measured and shown in Table 3 below.
  • the threshold voltage was 8.19 V
  • the slope was 0.39
  • the charge mobility was 8.1 cm 2 / Vs.
  • the middle layer is In 1 . 1 Ga 1 Zn 1 Si 0 .
  • the threshold voltage is 0.6V and the charge carrier mobility is also 10.1cm2 / Vs
  • the slope is indicated as 0.3, was improved remarkably the characteristics of the thin film transistor.
  • a buffer layer of SiO 2 was formed on the glass substrate, a lower active layer having an atomic ratio of In 4 Ga 1 Zn 3 O 16 .5 was formed on the buffer layer to a thickness of 240 ⁇ , and Si 10 In 5 was formed on the lower active layer.
  • An intermediate layer consisting of an atomic ratio of Ga 1 Zn 1 O 35 was formed to a thickness of 40 GPa to form an active layer.
  • a gate insulating film of SiO 2 was formed on the active layer, a gate electrode was formed of molybdenum on the gate insulating film, an interlayer insulating film of SiO 2 was formed, and a source electrode and a drain electrode were formed of aluminum to prepare a thin film transistor.
  • a thin film transistor was manufactured by only forming an intermediate layer having an atomic ratio of Si 15 In 5 Ga 1 Zn 1 O 35 to a thickness of 120 GPa to form an active layer.
  • a thin film transistor was manufactured by forming an intermediate layer having an atomic ratio of 5 In 5 Ga 1 Zn 1 O 35 to a thickness of 70 kHz, except that only an active layer was formed.
  • FIG. 21 is a graph illustrating drain current curves of a gate-source voltage of a thin film transistor according to Comparative Example 5
  • FIG. 22 is a graph illustrating drain current curves of a gate-source voltage of a thin film transistor according to Comparative Example 6.
  • FIG. 23 is a graph illustrating drain current curves of a gate-source voltage of a thin film transistor according to Example 3.
  • the threshold voltage, current change rate, charge mobility, positive bias temperature stress (PBTS), current stress (CS), and negative bias temperature stress of the thin film transistor according to the third embodiment described above. (negative bias temperature stress, NBTS) was measured and shown in Table 4 below, and the rate of change of the current was measured and shown in FIG.
  • Example 3 Threshold Voltage (V) -0.1 Current rate of change (@ 860nA) 0.13% Charge mobility (cm2 / Vs) 28.4 PBTS ( ⁇ Vth) 0.8 CS ( ⁇ Vgs) 0.1 NBTS (( ⁇ Vth) -0.04
  • Comparative Example 5 having an intermediate layer having a thickness of 40 ⁇ s with an atomic ratio of Si 10 In 5 Ga 1 Zn 1 O 35 showed that the dispersion of the gate-source voltage was large, resulting in severe nonuniformity of the device.
  • Comparative Example 6 in which the intermediate layer was formed to a thickness of 120 ⁇ s at an atomic ratio of Si 15 In 5 Ga 1 Zn 1 O 35 showed that the gates did not control too many carriers.
  • the intermediate layer is Si 12 .
  • Example 3 formed with a thickness of 70 kW with an atomic ratio of 5 In 5 Ga 1 Zn 1 O 35 , has a threshold voltage of -0.1 V, a current variation rate of 0.13%, a charge mobility of 28.4 cm 2 / Vs, and a PBTS of 0.8 V, NBTS is -.0.04V and CS is 0.1V, which shows the excellent characteristics of the thin film transistor.
  • a buffer layer of SiO 2 was formed on the glass substrate, an active layer consisting of an atomic ratio of In 4 Ga 1 Zn 3 O 16 .5 was formed on the buffer layer to a thickness of 240 ⁇ s, and an intermediate layer was formed to a thickness of 50 ⁇ s on the active layer. Formed.
  • a gate insulating film of SiO 2 was formed on the intermediate layer, a gate electrode was formed of molybdenum on the gate insulating film, an interlayer insulating film of SiO 2 was formed, and a source electrode and a drain electrode were formed of aluminum to prepare a thin film transistor.
  • the amount of excess oxygen in the intermediate layer according to the silicon content of the intermediate layer was shown in FIG. 25, and the amount of excess oxygen in the intermediate layer according to the hydrogen content of the intermediate layer was measured and thus the positive bias temper.
  • the Razer stress is measured and shown in FIG. 26, and the thickness of the intermediate layer is changed to 50 kV, 100 kPa and 150 kPa, respectively, and the transcurve, threshold voltage, charge mobility and drain-induced barrier lowering (DIBL) are measured and shown in FIG. 27. It was.
  • the positive bias temperature stress of the thin film transistors prepared according to Example 4 and Comparative Example 7 was measured and shown in FIG. 28.
  • the amount of excess oxygen in the intermediate layer appears to be about 100%.
  • the content of the silicon element in the middle layer is reduced, the amount of excess oxygen increases, resulting in positive bias temperature stress degradation, and when the content of the silicon element in the middle layer is increased, the amount of excess oxygen is reduced, resulting in the conductor.
  • the content of the silicon element of the intermediate layer 2.9 to 3.2 ⁇ 10 22 cm - it can be seen that it is possible to form a three, preventing the conductor screen of the positive bias tempering racheo stress deteriorates the element.
  • the threshold voltage was 0.35V
  • the charge mobility was 9.97 cm 2 / vs
  • the DIBL was 0.11V.
  • the threshold voltage was 0.56V
  • the charge mobility was 10.95 cm 2 / vs
  • the DIBL was -0.02V.
  • the thickness of the intermediate layer was 150 kV
  • the threshold voltage was 1.6V
  • the charge mobility was 6.25 cm 2 / vs
  • the DIBL was -1.75V. From this result, it can be seen that when the thickness of the intermediate layer exceeds 100 mW, the threshold voltage increases, the charge mobility decreases, and the DIBL decreases.
  • the thin film transistor according to Comparative Example 7 significantly increases the positive bias temperature stress as the stress time increases, but the thin film transistor according to the fourth embodiment has a positive bias temperture stress as the stress time increases.
  • the degree of increase was significantly smaller than that of Comparative Example 7.
  • the thin film transistor including the intermediate layer of the present invention can reduce the positive bias temperature stress deterioration, thereby improving the reliability of the device.
  • the present invention provides an intermediate layer containing a Group 4 element between the gate insulating film and the active layer, thereby preventing the element from deteriorating by preventing diffusion of hydrogen or oxygen atoms of the gate insulating film into the active layer by a heat treatment process. There is an advantage that can be prevented.
  • the present invention can form an intermediate layer containing a silicon element between the active layer and the gate insulating film, thereby preventing the positive bias temperature stress degradation due to excess oxygen.
  • the present invention can be applied to various display devices such as an organic light emitting display device, a liquid crystal display device, an electrophoretic display device, an inorganic light emitting display device, and can be applied to a TV, a mobile device, a monitor, a smart device, and the like.
  • display devices such as an organic light emitting display device, a liquid crystal display device, an electrophoretic display device, an inorganic light emitting display device, and can be applied to a TV, a mobile device, a monitor, a smart device, and the like.
  • the present invention is not limited thereto and may be applied to any device capable of displaying an image.

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Abstract

A thin-film transistor array substrate according to one embodiment of the present invention comprises: an active layer; a middle layer; a gate insulation film; a gate electrode; an interlayer insulation film; a source electrode; and a drain electrode. The active layer is positioned on the substrate and the gate insulation film is positioned on the active layer. The gate electrode is positioned on the gate insulation film and the interlayer insulation film is positioned on the gate electrode. The source electrode and drain electrode are positioned on the interlayer insulation film and are connected to the active layer. The middle layer is positioned between the active layer and gate insulation film and is made of oxide semiconductor comprising Group IV elements.

Description

박막트랜지스터 어레이 기판Thin Film Transistor Array Board
본 발명은 박막트랜지스터 어레이 기판에 관한 것이다.The present invention relates to a thin film transistor array substrate.
최근, 표시장치(FPD: Flat Panel Display)는 멀티미디어의 발달과 함께 그 중요성이 증대되고 있다. 이에 부응하여 액정표시장치(Liquid Crystal Display : LCD), 플라즈마 디스플레이 패널(Plasma Display Panel: PDP), 전계방출표시장치(Field Emission Display: FED), 유기전계발광표시장치(Organic Light Emitting Device) 등과 같은 여러 가지의 디스플레이가 실용화되고 있다. 이들 중, 유기전계발광표시장치는 응답속도가 1ms 이하로서 고속의 응답속도를 가지며, 소비 전력이 낮고, 자체 발광이므로 시야각에 문제가 없어서, 차세대 표시장치로 주목받고 있다.Recently, the importance of the flat panel display (FPD) has increased with the development of multimedia. In response, such as liquid crystal display (LCD), plasma display panel (PDP), field emission display (FED), organic light emitting device (Organic Light Emitting Device) Various displays have been put into practical use. Among them, the organic light emitting display device has a high response time with a response speed of 1 ms or less, low power consumption, and no self-emission, thus having no problem in viewing angle.
표시장치를 구동하는 방식에는 수동 매트릭스(passive matrix) 방식과 박막 트랜지스터(thin film transistor)를 이용한 능동 매트릭스(active matrix) 방식이 있다. 수동 매트릭스 방식은 양극과 음극을 직교하도록 형성하고 라인을 선택하여 구동하는데 비해, 능동 매트릭스 방식은 박막트랜지스터를 각 화소 전극에 연결하고 박막트랜지스터의 게이트 전극에 연결된 커패시터 용량에 의해 유지된 전압에 따라 구동하는 방식이다.There are two methods of driving the display device, a passive matrix method and an active matrix method using a thin film transistor. The passive matrix method forms the anode and the cathode so as to be orthogonal and selects a line, whereas the active matrix method drives the thin film transistor to each pixel electrode and is driven according to the voltage maintained by the capacitor capacitance connected to the gate electrode of the thin film transistor. That's the way it is.
박막트랜지스터는 이동도, 누설전류 등과 같은 기본적인 박막트랜지스터의 특성뿐만 아니라, 오랜 수명을 유지할 수 있는 내구성 및 전기적 신뢰성이 매우 중요하다. 여기서, 박막트랜지스터의 액티브층은 주로 비정질 실리콘 또는 다결정 실리콘으로 형성되는데, 비정질 실리콘은 성막 공정이 간단하고 생산 비용이 적게 드는 장점이 있지만 전기적 신뢰성이 확보되지 못하는 문제가 있다. 또한 다결정 실리콘은 높은 공정 온도로 인하여 대면적 응용이 매우 곤란하며, 결정화 방식에 따른 균일도가 확보되지 못하는 문제점이 있다.In the thin film transistor, not only the characteristics of the basic thin film transistor such as mobility and leakage current, but also durability and electrical reliability for maintaining a long life is very important. Here, the active layer of the thin film transistor is mainly formed of amorphous silicon or polycrystalline silicon, amorphous silicon has the advantage of simple film forming process and low production cost, but there is a problem that the electrical reliability is not secured. In addition, polycrystalline silicon is very difficult to apply a large area due to high process temperature, there is a problem that the uniformity according to the crystallization method is not secured.
한편, 산화물 반도체로 액티브층을 형성할 경우, 낮은 온도에서 성막하여도 높은 이동도를 얻을 수 있으며 산소의 함량에 따라 저항의 변화가 커서 원하는 물성을 얻기가 매우 용이하기 때문에 최근 박막트랜지스터로의 응용에 있어 큰 관심을 끌고 있다. 특히, 액티브층에 사용될 수 있는 산화물 반도체로는 아연 산화물(ZnO), 인듐 아연 산화물(InZnO) 또는 인듐 갈륨 아연 산화물(InGaZnO4) 등을 그 예로 들 수 있다. 산화물 반도체 액티브층을 포함하는 박막트랜지스터는 다양한 구조로 이루어질 수 있으나, 이 중 코플라나(Coplanar) 또는 에치 스토퍼(etch stopper) 구조 등이 소자 특성 상 많이 사용되고 있다. On the other hand, when the active layer is formed of an oxide semiconductor, it is possible to obtain high mobility even when the film is formed at a low temperature, and it is very easy to obtain desired properties due to the large change in resistance depending on the oxygen content. Is attracting great attention. In particular, examples of the oxide semiconductor that can be used for the active layer include zinc oxide (ZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO 4 ), and the like. The thin film transistor including the oxide semiconductor active layer may be formed in various structures. Among them, a coplanar or an etch stopper structure is widely used due to device characteristics.
도 1은 종래 코플라나 구조의 박막트랜지스터를 나타낸 단면도이고, 도 2는 원자 확산 현상을 모식화한 도면이며, 도 3은 박막트랜지스터의 단면 이미지이다. 도 1을 참조하면, 기판(15) 상에 차광막(20)이 위치하고, 차광막(20) 상에 버퍼층(25)이 위치한다. 버퍼층(25) 상에 산화물 반도체의 액티브층(30)이 형성되고, 그 위에 게이트 절연막(35)과 게이트 전극(40)이 위치한다. 게이트 전극(40) 상에 층간 절연막(45)이 위치하고 소스 전극(50a)과 드레인 전극(50b)이 액티브층(30)에 각각 연결되어 박막트랜지스터(10)가 구성된다. 상기 박막트랜지스터는 액티브층(30), 게이트 절연막(35) 및 게이트 전극(40)이 형성된 후, 후속 열처리 공정이 다수 수행된다. 도 2에 도시된 바와 같이, 후속 열처리 공정이 수행되면, 게이트 절연막(35)의 수소나 산소 원자가 액티브층(30)으로 확산되는 원자 확산 현상이 발생한다. 도 3을 참조하면, 액티브층의 A영역은 In11Ga1Zn0 . 9O23 .8의 원자비를 가지고 B 영역은 In6 . 4Ga1Zn1 . 3O13 .6의 원자비를 가지는 것으로 측정되어, 액티브층(30)과 게이트 절연막(35)의 계면에 산소의 함량이 높아지게 된다.1 is a cross-sectional view illustrating a thin film transistor having a conventional coplanar structure, FIG. 2 is a view schematically illustrating an atomic diffusion phenomenon, and FIG. 3 is a cross-sectional image of a thin film transistor. Referring to FIG. 1, a light blocking film 20 is positioned on a substrate 15, and a buffer layer 25 is positioned on a light blocking film 20. The active layer 30 of the oxide semiconductor is formed on the buffer layer 25, and the gate insulating layer 35 and the gate electrode 40 are positioned thereon. An interlayer insulating layer 45 is disposed on the gate electrode 40, and the thin film transistor 10 is formed by connecting the source electrode 50a and the drain electrode 50b to the active layer 30, respectively. After the active layer 30, the gate insulating layer 35, and the gate electrode 40 are formed in the thin film transistor, a plurality of subsequent heat treatment processes are performed. As shown in FIG. 2, when a subsequent heat treatment process is performed, an atomic diffusion phenomenon in which hydrogen or oxygen atoms of the gate insulating layer 35 diffuse into the active layer 30 occurs. Referring to FIG. 3, the region A of the active layer is In 11 Ga 1 Zn 0 . 9 O has an atomic ratio of 23 .8 and the B region is In 6 . 4 Ga 1 Zn 1 . It is measured that the atomic ratio of 3 O 13 .6 , the oxygen content at the interface between the active layer 30 and the gate insulating film 35 is increased.
도 4를 참조하면, 액티브층(30)과 게이트 절연막(35)의 계면에 산소의 함량이 높아지면, 미결합된 상태의 산소가 과잉으로 존재하게 된다. 산소는 전자 2개를 가질 경우 안정화되나, 전자가 미결합된 부분이 액티브층(30)의 채널에서 이동하는 전자를 1개 포집하게 되어 소자의 특성이 열화되는 문제가 있다. Referring to FIG. 4, when the oxygen content is increased at the interface between the active layer 30 and the gate insulating layer 35, oxygen in an unbound state is excessively present. Oxygen is stabilized when it has two electrons, but the unbonded portion collects one electron moving in the channel of the active layer 30, thereby degrading the characteristics of the device.
본 발명은 소자의 열화를 방지하고 신뢰성을 개선할 수 있는 박막트랜지스터 어레이 기판을 제공한다.The present invention provides a thin film transistor array substrate that can prevent degradation of the device and improve reliability.
상기한 목적을 달성하기 위해, 본 발명의 일 실시예에 따른 박막트랜지스터 어레이 기판은 액티브층, 중간층, 게이트 절연막, 게이트 전극, 층간 절연막, 소스 전극 및 드레인 전극을 포함한다. 액티브층은 기판 상에 위치하고, 게이트 절연막은 액티브층 상에 위치한다. 게이트 전극은 게이트 절연막 상에 위치하고, 층간 절연막은 게이트 전극 상에 위치한다. 소스 전극과 드레인 전극은 층간 절연막 상에 위치하여 액티브층에 각각 연결된다. 중간층은 액티브층과 게이트 절연막 사이에 위치하며, 4족 원소를 포함하는 산화물 반도체로 이루어진다.In order to achieve the above object, a thin film transistor array substrate according to an embodiment of the present invention includes an active layer, an intermediate layer, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode and a drain electrode. The active layer is located on the substrate and the gate insulating film is located on the active layer. The gate electrode is located on the gate insulating film, and the interlayer insulating film is located on the gate electrode. The source electrode and the drain electrode are located on the interlayer insulating film and are respectively connected to the active layer. The intermediate layer is located between the active layer and the gate insulating film, and is made of an oxide semiconductor containing a Group 4 element.
또한, 본 발명의 일 실시예에 따른 박막트랜지스터 어레이 기판은 게이트 전극, 게이트 절연막, 중간층, 액티브층, 에치 스토퍼, 소스 전극 및 드레인 전극을 포함한다. 게이트 전극은 기판 상에 위치하고, 게이트 절연막은 게이트 전극 상에 위치한다. 액티브층은 게이트 절연막 상에 위치하고, 에치 스토퍼는 액티브층 상에 위치한다. 소스 전극과 드레인 전극은 에치 스토퍼 상에 위치하며, 액티브층에 각각 연결된다. 중간층은 액티브층과 게이트 절연막 사이에 위치하며, 4족 원소를 포함하는 산화물 반도체로 이루어진다.In addition, the thin film transistor array substrate according to an embodiment of the present invention includes a gate electrode, a gate insulating film, an intermediate layer, an active layer, an etch stopper, a source electrode, and a drain electrode. The gate electrode is located on the substrate and the gate insulating film is located on the gate electrode. The active layer is located on the gate insulating film, and the etch stopper is located on the active layer. The source electrode and the drain electrode are located on the etch stopper and are respectively connected to the active layer. The intermediate layer is located between the active layer and the gate insulating film, and is made of an oxide semiconductor containing a Group 4 element.
또한, 본 발명의 일 실시예에 따른 박막트랜지스터 어레이 기판은 기판, 액티브층, 게이트 절연막, 게이트 전극, 층간 절연막, 소스 전극 및 드레인 전극을 포함한다. 액티브층은 기판 상에 위치하며, 하부 액티브층과 중간층을 포함한다. 게이트 절연막은 액티브층 상에 위치한다. 게이트 전극은 게이트 절연막 상에 위치한다. 층간 절연막은 게이트 전극 상에 위치한다. 소스 전극 및 드레인 전극은 층간 절연막 상에 위치하며, 액티브층에 각각 연결된다. 중간층은 4족 원소를 포함하는 산화물 반도체로 이루어진다.In addition, the thin film transistor array substrate according to an embodiment of the present invention includes a substrate, an active layer, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode. The active layer is located on the substrate and includes a lower active layer and an intermediate layer. The gate insulating film is located on the active layer. The gate electrode is located on the gate insulating film. The interlayer insulating film is located on the gate electrode. The source electrode and the drain electrode are located on the interlayer insulating film and are respectively connected to the active layer. The intermediate layer is made of an oxide semiconductor containing a Group 4 element.
본 발명은 게이트 절연막과 액티브층 사이에 4족 원소를 포함하는 중간층을 구비함으로써, 열처리 공정에 의해 게이트 절연막의 수소나 산소 원자가 액티브층으로 확산되는 것을 방지하여 소자가 열화되는 것을 방지할 수 있는 이점이 있다.According to the present invention, an intermediate layer including a Group 4 element is provided between the gate insulating film and the active layer, thereby preventing hydrogen or oxygen atoms of the gate insulating film from diffusing into the active layer by the heat treatment process, thereby preventing deterioration of the device. There is this.
또한, 본 발명은 액티브층과 게이트 절연막 사이에 실리콘 원소를 포함하는 중간층을 형성하여, 과잉 산소로 인한 포지티브 바이어스 템퍼라처 스트레스 열화를 방지할 수 있다. In addition, the present invention can form an intermediate layer containing a silicon element between the active layer and the gate insulating film, thereby preventing the positive bias temperature stress degradation due to excess oxygen.
또한, 중간층에 남아있는 과잉 산소의 양에 대응하는 만큼의 수소를 포함하여 과잉 산소가 전자를 포집하는 것을 막아 포지티브 바이어스 템퍼라처 스트레스 열화를 방지할 수 있다.In addition, it is possible to prevent excess oxygen from trapping electrons by including hydrogen corresponding to the amount of excess oxygen remaining in the intermediate layer, thereby preventing the positive bias temperture stress degradation.
도 1은 종래 코플라나 구조의 박막트랜지스터를 나타낸 단면도.1 is a cross-sectional view showing a thin film transistor having a conventional coplanar structure.
도 2는 원자 확산 현상을 모식화한 도면.2 is a diagram schematically illustrating an atomic diffusion phenomenon.
도 3은 박막트랜지스터의 단면 이미지.3 is a cross-sectional image of a thin film transistor.
도 4는 산소 미결합 상태를 모식화하여 나타낸 도면.4 is a diagram schematically illustrating an oxygen non-bonding state.
도 5는 본 발명의 제1 실시예에 따른 박막트랜지스터 어레이 기판을 나타낸 도면.5 is a view showing a thin film transistor array substrate according to a first embodiment of the present invention.
도 6은 본 발명의 제2 실시예에 따른 박막트랜지스터 어레이 기판을 나타낸 단면도. 6 is a cross-sectional view illustrating a thin film transistor array substrate according to a second embodiment of the present invention.
도 7은 본 발명의 제3 실시예에 따른 박막트랜지스터 어레이 기판을 나타낸 단면도. 7 is a cross-sectional view illustrating a thin film transistor array substrate according to a third embodiment of the present invention.
도 8은 본 발명의 제4 실시예에 따른 박막트랜지스터 어레이 기판을 나타낸 단면도. 8 is a cross-sectional view illustrating a thin film transistor array substrate according to a fourth embodiment of the present invention.
도 9는 본 발명의 제1 실시예에 따른 박막트랜지스터 어레이 기판을 포함하는 표시장치를 나타낸 도면.9 is a view illustrating a display device including a thin film transistor array substrate according to a first embodiment of the present invention.
도 10a 내지 도 10e는 본 발명의 제1 실시예에 따른 박막트랜지스터 어레이 기판의 제조방법을 공정별로 나타낸 도면.10A to 10E are diagrams illustrating processes of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.
도 11a 내지 도 11h는 본 발명의 제3 실시예에 따른 박막트랜지스터 어레이 기판의 제조방법을 공정별로 나타낸 도면.11A to 11H are views illustrating a method of manufacturing a thin film transistor array substrate according to a third embodiment, according to processes.
도 12a 내지 도 12f는 본 발명의 제4 실시예에 따른 박막트랜지스터 어레이 기판의 제조방법을 공정별로 나타낸 도면.12A to 12F illustrate a method of manufacturing a thin film transistor array substrate according to a fourth embodiment of the present invention.
도 13은 본 발명의 제1 실시예에 따라 제조된 박막트랜지스터의 후방 산란 분석법을 통한 결과를 나타낸 그래프.Figure 13 is a graph showing the results through the back scattering analysis method of the thin film transistor prepared according to the first embodiment of the present invention.
도 14는 본 발명의 제3 실시예에 따라 제조된 박막트랜지스터의 후방 산란 분석법을 통한 결과를 나타낸 그래프.14 is a graph showing the results of the backscattering analysis of the thin film transistor prepared according to the third embodiment of the present invention.
도 15는 비교예 1에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프.FIG. 15 is a graph showing drain current curves for a gate-source voltage of a thin film transistor according to Comparative Example 1. FIG.
도 16은 비교예 2에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프.FIG. 16 is a graph showing drain current curves for a gate-source voltage of a thin film transistor according to Comparative Example 2. FIG.
도 17은 비교예 3에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프.FIG. 17 is a graph showing drain current curves for a gate-source voltage of a thin film transistor according to Comparative Example 3. FIG.
도 18은 본 발명의 실시예 1에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프.FIG. 18 is a graph showing drain current curves for a gate-source voltage of a thin film transistor according to Example 1 of the present invention; FIG.
도 19는 비교예 4에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프.19 is a graph showing drain current curves for a gate-source voltage of a thin film transistor according to Comparative Example 4. FIG.
도 20은 본 발명의 실시예 2에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프.20 is a graph showing drain current curves for a gate-source voltage of a thin film transistor according to Example 2 of the present invention.
도 21은 본 발명의 비교예 5에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프.FIG. 21 is a graph showing drain current curves of a gate-source voltage of a thin film transistor according to Comparative Example 5 of the present invention. FIG.
도 22는 본 발명의 비교예 6에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프.FIG. 22 is a graph showing drain current curves for a gate-source voltage of a thin film transistor according to Comparative Example 6 of the present invention. FIG.
도 23은 본 발명의 실시예 3에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프.FIG. 23 is a graph showing drain current curves for a gate-source voltage of a thin film transistor according to Example 3 of the present invention; FIG.
도 24는 본 발명의 실시예 3에 따른 박막트랜지스터의 전류 변화율을 나타낸 그래프.24 is a graph showing the current change rate of the thin film transistor according to the third embodiment of the present invention.
도 25는 실시예 4에 따라 제조된 박막트랜지스터에서 중간층의 실리콘 함량에 따른 중간층 내의 과잉 산소 양을 측정하여 나타낸 그래프.25 is a graph showing the amount of excess oxygen in the intermediate layer according to the silicon content of the intermediate layer in the thin film transistor prepared according to Example 4.
도 26은 실시예 4에 따라 제조된 박막트랜지스터에서 중간층의 수소 함량에 따른 중간층 내의 과잉 산소 양을 측정하고 그에 따른 포지티브 바이어스 템퍼라처 스트레스를 측정하여 나타낸 그래프.FIG. 26 is a graph illustrating the amount of excess oxygen in the intermediate layer according to the hydrogen content of the intermediate layer in the thin film transistor prepared according to Example 4 and the positive bias temperture stress according to the same.
도 27은 실시예 4에 따라 제조된 박막트랜지스터에서 중간층의 두께를 각각 50Å, 100Å, 150Å으로 달리한 후 트랜스커브, 문턱전압, 전하이동도 및 DIBL(Drain-Induced Barrier Lowering)을 측정하여 나타낸 그래프.FIG. 27 is a graph illustrating transcurves, threshold voltages, charge mobility, and drain-induced barrier lowering (DIBL) after varying the thickness of an intermediate layer to 50 kV, 100 kV, and 150 kV in the thin film transistor prepared according to Example 4. FIG. .
도 28은 실시예 4 및 비교예 7에 따라 제조된 박막트랜지스터의 포지티브 바이어스 템퍼라처 스트레스를 측정하여 나타낸 그래프.28 is a graph showing the measurement of the positive bias temperture stress of the thin film transistors prepared according to Example 4 and Comparative Example 7.
이하, 첨부한 도면을 참조하여 본 발명의 일 실시 예들을 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 5는 본 발명의 제1 실시예에 따른 박막트랜지스터 어레이 기판을 나타낸 단면도이다. 5 is a cross-sectional view illustrating a thin film transistor array substrate according to a first embodiment of the present invention.
도 5를 참조하면, 본 발명의 제1 실시예에 따른 박막트랜지스터 어레이 기판(100)은 코플라나(coplanar type) 구조의 박막트랜지스터로 게이트 전극이 액티브층의 상부에 위치하는 구조이다. Referring to FIG. 5, the thin film transistor array substrate 100 according to the first embodiment of the present invention is a thin film transistor having a coplanar type structure in which a gate electrode is positioned on an active layer.
보다 자세하게는, 기판(110) 상에 차광막(120)이 위치한다. 기판(110)은 투명하거나 불투명한 유리, 플라스틱 또는 금속으로 이루어진다. 차광막(120)은 외부 광이 내부로 입사되는 것을 차단하기 위한 것으로, 광을 차단할 수 있는 재료로 이루어진다. 차광막(120)은 낮은 반사율을 가지는 재료로 이루어지며, 예를 들어, 카본 블랙 등의 흑색을 나타내는 재료를 포함하는 수지 또는 비정질 실리콘(a-Si), 게르마늄(Ge), 산화탄탈륨(TaOx), 산화구리(CuOx) 등의 반도체 계열의 재료로 이루어질 수 있다. 차광막(120)이 위치한 기판(110) 전체에 버퍼층(130)이 위치한다. 버퍼층(130)은 기판(110) 또는 하부의 층들에서 유출되는 알칼리 이온 등과 같은 불순물로부터 후속 공정에서 형성되는 박막트랜지스터를 보호하기 위해 형성하는 것으로, 실리콘 산화물(SiOx), 실리콘 질화물(SiNx) 또는 이들의 다층으로 이루어진다. In more detail, the light blocking film 120 is positioned on the substrate 110. The substrate 110 is made of transparent or opaque glass, plastic or metal. The light blocking film 120 is for blocking external light from being incident therein and is made of a material capable of blocking light. The light shielding film 120 is made of a material having a low reflectance, and includes, for example, resin or amorphous silicon (a-Si), germanium (Ge), tantalum oxide (TaOx), It may be made of a semiconductor-based material such as copper oxide (CuOx). The buffer layer 130 is positioned on the entire substrate 110 on which the light blocking film 120 is located. The buffer layer 130 is formed to protect the thin film transistor formed in a subsequent process from impurities such as alkali ions flowing out of the substrate 110 or lower layers, and is formed of silicon oxide (SiOx), silicon nitride (SiNx), or the like. It is made of multilayers.
상기 버퍼층(130) 상에 채널 영역(CH)과 도체화 영역(CP)을 포함하는 액티브층(140)이 위치한다. 액티브층(140)은 산화물 반도체(Oxide semi-conductor)로 이루어진다. 산화물 반도체는 예를 들어 비정질 아연 산화물계 반도체로, 특히 a-IGZO 반도체는 갈륨산화물(Ga2O3), 인듐산화물(In2O3) 및 아연산화물(ZnO)의 복합체 타겟을 이용하여 스퍼터링(sputtering) 방법에 의해 형성된다. 이외에도 화학기상증착이나 원자증착(Atomic Layer Deposition; ALD) 등의 화학적 증착방법을 이용할 수도 있다. 여기서, 본 발명의 실시예의 경우에는 갈륨, 인듐, 아연의 원자비가 각각 1:1:1, 2:2:1, 3:2:1 및 4:2:1인 산화물 타겟을 사용하여 아연 산화물계 반도체를 증착할 수 있다. 그러나, 본 발명의 액티브층(140)은 아연 산화물계 반도체에 한정되지 않는다. 또한, 도시하지 않았지만 액티브층(140)의 양측에는 불순물이 도핑되어 소스 영역과 드레인 영역이 구비된다. The active layer 140 including the channel region CH and the conductorization region CP is positioned on the buffer layer 130. The active layer 140 is made of an oxide semi-conductor. An oxide semiconductor is, for example, an amorphous zinc oxide-based semiconductor. In particular, an a-IGZO semiconductor is sputtered using a composite target of gallium oxide (Ga 2 O 3 ), indium oxide (In 2 O 3 ), and zinc oxide (ZnO). formed by a sputtering method. In addition, chemical vapor deposition such as chemical vapor deposition or atomic layer deposition (ALD) may be used. Here, in the case of the embodiment of the present invention, the zinc oxide type using an oxide target of the gallium, indium, zinc atomic ratio of 1: 1: 1, 2: 2: 1, 3: 2: 1 and 4: 2: 1, respectively The semiconductor can be deposited. However, the active layer 140 of the present invention is not limited to the zinc oxide semiconductor. Although not shown, impurities are doped on both sides of the active layer 140 to provide a source region and a drain region.
상기 액티브층(140) 상에 게이트 절연막(150)이 위치한다. 게이트 절연막(150)은 실리콘 산화막(SiOx), 실리콘 질화막(SiNx) 또는 이들의 다층으로 이루어진다. 게이트 절연막(150)은 상부에 위치한 게이트 전극(160)과 대응되며 유사한 크기로 이루어진다. 따라서, 게이트 절연막(150)은 게이트 전극(160)과 액티브층(140)을 절연시킨다. 게이트 절연막(150) 상에 게이트 전극(160)이 위치한다. 게이트 전극(160)은 구리(Cu), 몰리브덴(Mo), 알루미늄(Al), 크롬(Cr), 금(Au), 티타늄(Ti), 니켈(Ni), 네오디뮴(Nd), 탄탈륨(Ta) 및 텅스텐(W)로 이루어진 군에서 선택된 어느 하나 또는 이들의 합금의 단층이나 다층으로 이루어진다. 게이트 전극(160)은 상기 액티브층(140)의 채널 영역(CH)에 대응되게 위치한다.The gate insulating layer 150 is positioned on the active layer 140. The gate insulating layer 150 is formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof. The gate insulating layer 150 corresponds to the gate electrode 160 positioned on the upper portion and has a similar size. Thus, the gate insulating layer 150 insulates the gate electrode 160 from the active layer 140. The gate electrode 160 is positioned on the gate insulating layer 150. The gate electrode 160 includes copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and tantalum (Ta). And it consists of a single layer or a multilayer of any one or an alloy thereof selected from the group consisting of tungsten (W). The gate electrode 160 is positioned to correspond to the channel region CH of the active layer 140.
상기 게이트 전극(160)이 형성된 기판(110) 상에 층간 절연막(170)이 위치한다. 층간 절연막(170)은 실리콘 산화막(SiOx), 실리콘 질화막(SiNx) 또는 이들의 다층으로 이루어진다. 또한, 층간 절연막(170)은 액티브층(140)의 양측의 소스 영역 및 드레인 영역을 노출하는 콘택홀들(175a, 175b)이 구비된다. 층간 절연막(170) 상에 소스 전극(180a)과 드레인 전극(180b)이 위치한다. 소스 전극(180a) 및 드레인 전극(180b)은 단일층 또는 다층으로 이루어질 수 있으며, 단일층일 경우에는 몰리브덴(Mo), 알루미늄(Al), 크롬(Cr), 금(Au), 티타늄(Ti), 니켈(Ni), 네오디뮴(Nd) 및 구리(Cu)로 이루어진 군에서 선택된 어느 하나 또는 이들의 합금으로 이루어질 수 있다. 또한, 소스 전극(180a) 및 드레인 전극(180b)이 다층일 경우에는 몰리브덴/알루미늄-네오디뮴, 몰리브덴/알루미늄 또는 티타늄/알루미늄의 2중층이거나 몰리브덴/알루미늄-네오디뮴/몰리브덴, 몰리브덴/알루미늄/몰리브덴 또는 티타늄/알루미늄/티타늄의 3중층으로 이루어질 수 있다. 소스 전극(180a)과 드레인 전극(180b)은 층간 절연막(170)에 형성된 콘택홀들(175a, 175b)을 통해 액티브층(140)의 소스 영역 및 드레인 영역에 각각 접속된다. 따라서, 본 발명의 일 실시예에 따른 박막트랜지스터 어레이 기판(100)이 구성된다.An interlayer insulating layer 170 is positioned on the substrate 110 on which the gate electrode 160 is formed. The interlayer insulating film 170 is formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof. In addition, the interlayer insulating layer 170 may include contact holes 175a and 175b exposing source and drain regions on both sides of the active layer 140. The source electrode 180a and the drain electrode 180b are positioned on the interlayer insulating layer 170. The source electrode 180a and the drain electrode 180b may be formed of a single layer or a multilayer. In the case of a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), Nickel (Ni), neodymium (Nd) and copper (Cu) may be made of any one or an alloy thereof selected from the group consisting of. In the case where the source electrode 180a and the drain electrode 180b are multilayered, a double layer of molybdenum / aluminum-neodymium, molybdenum / aluminum or titanium / aluminum, or molybdenum / aluminum-neodymium / molybdenum, molybdenum / aluminum / molybdenum or titanium It may consist of a triple layer of aluminum / titanium. The source electrode 180a and the drain electrode 180b are connected to the source region and the drain region of the active layer 140 through contact holes 175a and 175b formed in the interlayer insulating layer 170, respectively. Accordingly, the thin film transistor array substrate 100 according to the embodiment of the present invention is constructed.
한편, 본 발명의 제1 실시예에서는 액티브층(140)과 게이트 절연막(150) 사이에 중간층(145)이 위치한다.Meanwhile, in the first embodiment of the present invention, the intermediate layer 145 is positioned between the active layer 140 and the gate insulating layer 150.
중간층(145)은 액티브층(140)과 게이트 절연막(150) 사이에 위치하여, 후속 열처리 공정에서 게이트 절연막(150)의 수소나 산소 원자가 액티브층(140)으로 확산되는 것을 막는 배리어(barrier)의 역할을 한다. 원자의 확산을 막기 위해, 중간층(145)은 4족 원소를 포함하는 산화물 반도체로 이루어진다. 예를 들어, 본 발명의 중간층(145)은 인듐, 갈륨, 아연을 포함하며, 4족 원소인 티타늄(Ti), 지르코늄(Zr), 실리콘(Si), 게르마늄(Ge), 주석(Sn), 납(Pb) 등을 더 포함할 수 있다. 바람직하게 중간층(145)은 인듐, 갈륨, 아연 및 실리콘 산화물로 이루어진다. 여기서, 중간층(145)은 수도 3원소 시스템(pseudo ternary system)을 유지하면서 인듐, 갈륨 및 아연의 원자비가 각각 1.1:1:1로 이루어진다. The intermediate layer 145 is positioned between the active layer 140 and the gate insulating layer 150 to form a barrier that prevents hydrogen or oxygen atoms of the gate insulating layer 150 from diffusing into the active layer 140 in a subsequent heat treatment process. Play a role. In order to prevent the diffusion of atoms, the intermediate layer 145 is made of an oxide semiconductor containing a Group 4 element. For example, the intermediate layer 145 of the present invention includes indium, gallium, and zinc, and include Group 4 elements such as titanium (Ti), zirconium (Zr), silicon (Si), germanium (Ge), tin (Sn), It may further include lead (Pb). Preferably, the intermediate layer 145 is made of indium, gallium, zinc and silicon oxide. Here, the intermediate layer 145 has an atomic ratio of indium, gallium, and zinc of 1.1: 1: 1, respectively, while maintaining a pseudo ternary system.
본 발명의 실시예에 따른 중간층(145)의 원자비는 In1 . 1Ga1Zn1Si(0.5~2)O(7.3~8.15)로 이루어진다. 여기서, 인듐의 양은 하부 액티브층(140)의 인듐에 대해 100 내지 110%의 원자 비율을 차지하고, 4족 원소인 실리콘은 중간층(145)의 아연에 대해 50 내지 200%의 원자 비율을 차지한다. 또한, 중간층(145) 내에 포함된 4족 원소의 원자 비율은 게이트 절연막(150)에 인접한 계면부터 액티브층(140)에 인접한 계면으로 내려갈수록 점진적으로 감소할 수 있다. 예를 들어, 실리콘의 원자 비율이 아연의 원자 비율에 대해 200%에서 50%까지 점진적으로 감소할 수 있다. The atomic ratio of the intermediate layer 145 according to the embodiment of the present invention is In 1 . 1 Ga 1 Zn 1 Si (0.5 to 2) O (7.3 to 8.15) . Here, the amount of indium occupies an atomic ratio of 100 to 110% with respect to the indium of the lower active layer 140, and silicon, a Group 4 element, occupies an atomic ratio of 50 to 200% with respect to zinc of the intermediate layer 145. In addition, the atomic ratio of the Group 4 elements included in the intermediate layer 145 may gradually decrease from the interface adjacent to the gate insulating layer 150 to the interface adjacent to the active layer 140. For example, the atomic ratio of silicon may decrease gradually from 200% to 50% relative to the atomic ratio of zinc.
한편, 중간층(145)은 40 내지 70Å의 두께로 이루어진다. 여기서, 중간층(145)의 두께가 40Å 미만이면, 게이트 절연막(150)으로부터 확산되는 원소들을 차단하는 확산방지막으로서 역할을 수행하기가 어렵고, 중간층(145)의 두께가 70Å 초과하면, 액티브층(140)의 채널에 영향을 주어 전하 이동도가 감소되는 현상이 발생한다. 따라서, 본 발명의 중간층(145)은 40 내지 70Å의 두께로 이루어진다. On the other hand, the intermediate layer 145 is made of a thickness of 40 to 70Å. Here, when the thickness of the intermediate layer 145 is less than 40 GPa, it is difficult to function as a diffusion barrier to block elements diffused from the gate insulating layer 150. When the thickness of the intermediate layer 145 exceeds 70 GPa, the active layer 140 ), The charge mobility is reduced by affecting the channel. Therefore, the intermediate layer 145 of the present invention is made of a thickness of 40 to 70Å.
본 발명의 중간층(145)은 막내에 4족 원소 예를 들어 실리콘을 포함하고 있어, 4족 원소의 결합이 강한 이중 결합을 형성하기 때문에 열적으로 안정적이게 된다. 그러므로, 액티브층(140)과 게이트 절연막(150) 사이에 소자의 전기적 특성에는 영향을 주지 않고 경원소의 확산만을 방지할 수 있는 중간층(145)을 구비함으로써, 열처리 공정에 의해 게이트 절연막(150)의 수소나 산소 원자가 확산되는 것을 방지하여 소자가 열화되는 것을 방지할 수 있는 이점이 있다. Since the intermediate layer 145 of the present invention contains a Group 4 element, for example silicon, in the film, the bond of the Group 4 element forms a strong double bond, which makes it thermally stable. Therefore, since the intermediate layer 145 can be provided between the active layer 140 and the gate insulating film 150 to prevent the diffusion of light elements without affecting the electrical characteristics of the device, the gate insulating film 150 is formed by the heat treatment process. There is an advantage of preventing the deterioration of the device by preventing the diffusion of hydrogen or oxygen atoms.
한편, 본 발명에서는 중간층(145)이 액티브층(140)의 채널 영역(CH)과 게이트 절연막(150)에 컨택하는 영역에만 위치하는 것으로 도시하고 설명하였지만, 이에 한정되지 않으며, 중간층(145)은 액티브층(140)의 전체 영역에도 위치할 수 있다.Meanwhile, in the present invention, although the intermediate layer 145 is illustrated and described as being located only in a region contacting the channel region CH and the gate insulating layer 150 of the active layer 140, the intermediate layer 145 is not limited thereto. It may be located in the entire area of the active layer 140.
도 6은 본 발명의 제2 실시예에 따른 박막트랜지스터 어레이 기판을 나타낸 도면이다.6 is a view showing a thin film transistor array substrate according to a second embodiment of the present invention.
도 6을 참조하면, 본 발명의 제2 실시예에 따른 박막트랜지스터 어레이 기판(200)은 에치 스토퍼 구조의 박막트랜지스터로 게이트 전극이 액티브층의 하부에 위치하고 액티브층 상부에 에치 스토퍼가 구비된 구조이다. Referring to FIG. 6, the thin film transistor array substrate 200 according to the second embodiment of the present invention is a thin film transistor having an etch stopper structure, in which a gate electrode is positioned under the active layer and an etch stopper is provided on the active layer. .
보다 자세하게는, 기판(210) 상에 게이트 전극(220)이 위치한다. 기판(110)은 투명하거나 불투명한 유리, 플라스틱 또는 금속으로 이루어진다. 게이트 전극(220)은 구리(Cu), 몰리브덴(Mo), 알루미늄(Al), 크롬(Cr), 금(Au), 티타늄(Ti), 니켈(Ni), 네오디뮴(Nd), 탄탈륨(Ta) 및 텅스텐(W)로 이루어진 군에서 선택된 어느 하나 또는 이들의 합금의 단층이나 다층으로 이루어진다. 게이트 전극(220) 상에 게이트 절연막(230)이 위치한다. 게이트 절연막(230)은 실리콘 산화막(SiOx), 실리콘 질화막(SiNx) 또는 이들의 다층으로 이루어진다. 게이트 절연막(230)은 하부에 위치한 게이트 전극(220)을 절연시킨다. In more detail, the gate electrode 220 is positioned on the substrate 210. The substrate 110 is made of transparent or opaque glass, plastic or metal. The gate electrode 220 includes copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and tantalum (Ta). And it consists of a single layer or a multilayer of any one or an alloy thereof selected from the group consisting of tungsten (W). The gate insulating layer 230 is positioned on the gate electrode 220. The gate insulating film 230 is formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof. The gate insulating layer 230 insulates the gate electrode 220 disposed below.
상기 게이트 절연막(230) 상에 채널 영역(CH)을 포함하는 액티브층(250)이 위치한다. 액티브층(250)은 산화물 반도체(Oxide semi-conductor)로 비정질 아연 산화물계 복합 반도체, 특히 a-IGZO 반도체는 갈륨산화물(Ga2O3), 인듐산화물(In2O3) 및 아연산화물(ZnO)의 복합체 타겟을 이용하여 스퍼터링(sputtering) 방법에 의해 형성될 수 있으며, 이외에도 화학기상증착이나 원자증착(Atomic Layer Deposition; ALD) 등의 화학적 증착방법을 이용할 수도 있다. 여기서, 본 발명의 실시예의 경우에는 갈륨, 인듐, 아연의 원자비가 각각 1:1:1, 2:2:1, 3:2:1 및 4:2:1인 복합 산화물 타겟을 사용하여 비정질 아연 산화물계 복합 반도체를 증착할 수 있다. 도시하지 않았지만 액티브층(250)의 양측에는 불순물이 도핑되어 소스 영역과 드레인 영역이 구비되고, 소스 영역과 드레인 영역이 구비된다. The active layer 250 including the channel region CH is positioned on the gate insulating layer 230. The active layer 250 is an oxide semi-conductor, and an amorphous zinc oxide-based composite semiconductor, in particular, a-IGZO semiconductor, has gallium oxide (Ga 2 O 3 ), indium oxide (In 2 O 3 ), and zinc oxide (ZnO). It may be formed by a sputtering method using a composite target of the), in addition to the chemical vapor deposition method such as chemical vapor deposition or atomic layer deposition (ALD) may be used. In the case of the embodiment of the present invention, the atomic ratio of gallium, indium, zinc is 1: 1: 1, 2: 2: 1, 3: 2: 1, and 4: 2: 1 using an amorphous zinc target using a composite oxide target An oxide composite semiconductor can be deposited. Although not shown, impurities are doped on both sides of the active layer 250 to provide a source region and a drain region, and a source region and a drain region are provided.
상기 액티브층(250) 상에 에치 스토퍼(260)가 위치한다. 에치 스토퍼(260)는 후술하는 소스 전극과 드레인 전극의 식각 공정에서 액티브층(250)이 손상되는 것을 방지하는 것으로, 액티브층(250)의 채널 영역(CH)에 대응되게 위치한다. 에치 스토퍼(260)는 실리콘 산화막(SiOx), 실리콘 질화막(SiNx) 또는 이들의 다층으로 이루어진다. An etch stopper 260 is positioned on the active layer 250. The etch stopper 260 prevents the active layer 250 from being damaged in the etching process of the source electrode and the drain electrode, which will be described later. The etch stopper 260 is positioned to correspond to the channel region CH of the active layer 250. The etch stopper 260 is made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.
에치 스토퍼(260), 액티브층(250) 및 게이트 절연막(230) 상에 소스 전극(270a)과 드레인 전극(270b)이 위치한다. 소스 전극(270a) 및 드레인 전극(270b)은 단일층 또는 다층으로 이루어질 수 있으며, 단일층일 경우에는 몰리브덴(Mo), 알루미늄(Al), 크롬(Cr), 금(Au), 티타늄(Ti), 니켈(Ni), 네오디뮴(Nd) 및 구리(Cu)로 이루어진 군에서 선택된 어느 하나 또는 이들의 합금으로 이루어질 수 있다. 또한, 소스 전극(270a) 및 드레인 전극(270b)이 다층일 경우에는 몰리브덴/알루미늄-네오디뮴, 몰리브덴/알루미늄 또는 티타늄/알루미늄의 2중층이거나 몰리브덴/알루미늄-네오디뮴/몰리브덴, 몰리브덴/알루미늄/몰리브덴 또는 티타늄/알루미늄/티타늄의 3중층으로 이루어질 수 있다. 소스 전극(270a)과 드레인 전극(270b)은 액티브층(250)의 소스 영역 및 드레인 영역에 각각 접속된다. 따라서, 본 발명의 일 실시예에 따른 박막트랜지스터 어레이 기판(200)이 구성된다.The source electrode 270a and the drain electrode 270b are positioned on the etch stopper 260, the active layer 250, and the gate insulating layer 230. The source electrode 270a and the drain electrode 270b may be formed of a single layer or a multilayer. In the case of a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), Nickel (Ni), neodymium (Nd) and copper (Cu) may be made of any one or an alloy thereof selected from the group consisting of. In the case where the source electrode 270a and the drain electrode 270b are multilayered, a double layer of molybdenum / aluminum-neodymium, molybdenum / aluminum or titanium / aluminum, or molybdenum / aluminum-neodymium / molybdenum, molybdenum / aluminum / molybdenum or titanium It may consist of a triple layer of aluminum / titanium. The source electrode 270a and the drain electrode 270b are connected to the source region and the drain region of the active layer 250, respectively. Accordingly, the thin film transistor array substrate 200 according to the embodiment of the present invention is constructed.
한편, 본 발명의 제2 실시예에서는 액티브층(250)과 게이트 절연막(230) 사이에 중간층(240)이 위치한다.Meanwhile, in the second embodiment of the present invention, the intermediate layer 240 is positioned between the active layer 250 and the gate insulating layer 230.
중간층(240)은 액티브층(250)과 게이트 절연막(230) 사이에 위치하여, 후속 열처리 공정에서 게이트 절연막(230)의 수소나 산소 원자가 액티브층(250)으로 확산되는 것을 막는 배리어의 역할을 한다. 원자의 확산을 막기 위해, 중간층(240)은 4족 원소를 포함하는 산화물 반도체로 이루어진다. 예를 들어, 본 발명의 중간층(240)은 인듐, 갈륨, 아연을 포함하며, 4족 원소인 티타늄(Ti), 지르코늄(Zr), 실리콘(Si), 게르마늄(Ge), 주석(Sn), 납(Pb) 등을 더 포함할 수 있다. 바람직하게 중간층(240)은 인듐, 갈륨, 아연 및 실리콘 산화물로 이루어진다. 여기서, 중간층(240)은 수도 3원소 시스템(pseudo ternary system)을 유지하면서 인듐, 갈륨 및 아연의 원자비가 각각 0.8:1:1로 이루어진다. The intermediate layer 240 is positioned between the active layer 250 and the gate insulating layer 230, and serves as a barrier to prevent hydrogen or oxygen atoms of the gate insulating layer 230 from diffusing into the active layer 250 in a subsequent heat treatment process. . In order to prevent the diffusion of atoms, the intermediate layer 240 is made of an oxide semiconductor containing a Group 4 element. For example, the intermediate layer 240 of the present invention includes indium, gallium, and zinc, and include Group 4 elements such as titanium (Ti), zirconium (Zr), silicon (Si), germanium (Ge), tin (Sn), It may further include lead (Pb). Preferably, the intermediate layer 240 is made of indium, gallium, zinc and silicon oxide. Here, the intermediate layer 240 has an atomic ratio of 0.8: 1: 1 indium, gallium and zinc, respectively, while maintaining a pseudo ternary system.
본 발명의 실시예에 따른 중간층(240)의 원자비는 In0 . 8Ga1Zn1Si0 .5O(4.2~4.7)로 이루어진다. 여기서, 인듐의 양은 하부 액티브층(250)의 인듐에 대해 80 내지 90%의 원자 비율을 차지하고, 4족 원소인 실리콘은 중간층(240)의 아연에 대해 50%의 원자 비율을 차지한다. 또한, 중간층(240) 내에 포함된 4족 원소의 원자 비율은 게이트 절연막(230)에 인접한 계면부터 액티브층(250)에 인접한 계면으로 올라갈수록 점진적으로 감소할 수 있다. 예를 들어, 실리콘의 원자 비율이 아연의 원자 비율에 대해 200%에서 50%까지 점진적으로 감소할 수 있다. The atomic ratio of the intermediate layer 240 according to the embodiment of the present invention is In 0 . 8 made of a Ga 1 Zn 1 Si 0 .5 O ( 4.2 ~ 4.7). Here, the amount of indium occupies an atomic ratio of 80 to 90% with respect to the indium of the lower active layer 250, and silicon, a Group 4 element, occupies an atomic ratio of 50% with respect to zinc of the intermediate layer 240. In addition, the atomic ratio of the Group 4 elements included in the intermediate layer 240 may gradually decrease as the surface of the Group 4 element is moved from the interface adjacent to the gate insulating layer 230 to the interface adjacent to the active layer 250. For example, the atomic ratio of silicon may decrease gradually from 200% to 50% relative to the atomic ratio of zinc.
한편, 중간층(240)은 50 내지 100Å의 두께로 이루어진다. 여기서, 중간층(145)의 두께가 50Å 미만이면, 게이트 절연막(230)으로부터 확산되는 원소들을 차단하는 확산방지막으로서 역할을 수행하기가 어렵고, 중간층(240)의 두께가 100Å 초과하면, 액티브층(250)의 채널에 영향을 주어 전하 이동도가 감소되는 현상이 발생한다. 따라서, 본 발명의 중간층(240)은 50 내지 100Å의 두께로 이루어진다. On the other hand, the intermediate layer 240 is made of a thickness of 50 to 100Å. Here, when the thickness of the intermediate layer 145 is less than 50 GPa, it is difficult to function as a diffusion barrier to block elements diffused from the gate insulating film 230. When the thickness of the intermediate layer 240 exceeds 100 GPa, the active layer 250 ), The charge mobility is reduced by affecting the channel. Therefore, the intermediate layer 240 of the present invention is made of a thickness of 50 to 100Å.
본 발명의 중간층(240)은 막내에 4족 원소 예를 들어 실리콘을 포함하고 있어, 4족 원소의 결합이 강한 이중 결합을 형성하기 때문에 열적으로 안정적이게 된다. 그러므로, 액티브층(250)과 게이트 절연막(230) 사이에 중간층(240)을 구비함으로써, 열처리 공정에 의해 게이트 절연막(230)의 수소나 산소 원자가 확산되는 것을 방지하여 소자가 열화되는 것을 방지할 수 있는 이점이 있다. Since the intermediate layer 240 of the present invention includes a Group 4 element, for example, silicon in the film, the bond of the Group 4 element forms a strong double bond, thereby making it thermally stable. Therefore, by providing the intermediate layer 240 between the active layer 250 and the gate insulating film 230, the hydrogen or oxygen atoms of the gate insulating film 230 can be prevented from being diffused by the heat treatment process to prevent deterioration of the device. There is an advantage to that.
본 발명에서는 중간층(240)이 액티브층(250)의 밑면 전체와 게이트 절연막(230)에 컨택하는 영역에만 위치하는 것으로 도시하고 설명하였지만, 이에 한정되지 않으며, 중간층(240)은 액티브층(250)의 채널 영역(CH)과 게이트 절연막(230)에 컨택하는 영역에만 위치할 수도 있다. In the present invention, although the intermediate layer 240 is illustrated and described as being located only in the entire bottom surface of the active layer 250 and the region in contact with the gate insulating layer 230, the present invention is not limited thereto, and the intermediate layer 240 is the active layer 250. It may be positioned only in the region in contact with the channel region CH and the gate insulating layer 230.
도 7은 본 발명의 제3 실시예에 따른 박막트랜지스터 어레이 기판을 나타낸 도면이다.7 is a diagram illustrating a thin film transistor array substrate according to a third embodiment of the present invention.
도 7을 참조하면, 본 발명의 제3 실시예에 따른 박막트랜지스터 어레이 기판(300)은 코플라나(coplanar type) 구조의 박막트랜지스터로 게이트 전극이 액티브층의 상부에 위치하는 구조이다. Referring to FIG. 7, the thin film transistor array substrate 300 according to the third embodiment of the present invention is a thin film transistor having a coplanar type structure in which a gate electrode is positioned on an active layer.
보다 자세하게는, 기판(310) 상에 차광막(320)이 위치한다. 기판(310)은 투명하거나 불투명한 유리, 플라스틱 또는 금속으로 이루어진다. 차광막(320)은 외부 광이 내부로 입사되는 것을 차단하기 위한 것으로, 광을 차단할 수 있는 재료로 이루어진다. 차광막(320)은 낮은 반사율을 가지는 재료로 이루어지며, 예를 들어, 카본 블랙 등의 흑색을 나타내는 재료를 포함하는 수지 또는 비정질 실리콘(a-Si), 게르마늄(Ge), 산화탄탈륨(TaOx), 산화구리(CuOx) 등의 반도체 계열의 재료로 이루어질 수 있다. 차광막(320)이 위치한 기판(310) 전체에 버퍼층(330)이 위치한다. 버퍼층(330)은 기판(310) 또는 하부의 층들에서 유출되는 알칼리 이온 등과 같은 불순물로부터 후속 공정에서 형성되는 박막트랜지스터를 보호하기 위해 형성하는 것으로, 실리콘 산화물(SiOx), 실리콘 질화물(SiNx) 또는 이들의 다층으로 이루어진다. In more detail, the light blocking film 320 is positioned on the substrate 310. The substrate 310 is made of transparent or opaque glass, plastic or metal. The light blocking film 320 is for blocking external light from entering the inside, and is made of a material capable of blocking light. The light shielding film 320 is made of a material having a low reflectance, and includes, for example, resin or amorphous silicon (a-Si), germanium (Ge), tantalum oxide (TaOx), It may be made of a semiconductor-based material such as copper oxide (CuOx). The buffer layer 330 is disposed on the entire substrate 310 where the light blocking film 320 is located. The buffer layer 330 is formed to protect the thin film transistor formed in a subsequent process from impurities such as alkali ions flowing out of the substrate 310 or lower layers, and is formed of silicon oxide (SiOx), silicon nitride (SiNx), or the like. It is made of multilayers.
상기 버퍼층(330) 상에 채널 영역(CH)과 도체화 영역(CP)을 포함하는 액티브층(340)이 위치한다. 본 발명의 제3 실시예에서 액티브층(340)은 하부 액티브층(342) 및 중간층(344)을 포함한다. 하부 액티브층(342)은 액티브층(340) 하부를 이루며 버퍼층(330)에 컨택하게 위치하고, 중간층(344)은 액티브층(340)의 상부를 이루며 하부 액티브층(342)과 게이트 절연막(350) 사이에 위치한다.An active layer 340 including a channel region CH and a conductorization region CP is positioned on the buffer layer 330. In a third embodiment of the present invention, the active layer 340 includes a lower active layer 342 and an intermediate layer 344. The lower active layer 342 forms a lower portion of the active layer 340 and contacts the buffer layer 330, and the intermediate layer 344 forms an upper portion of the active layer 340. The lower active layer 342 and the gate insulating layer 350 Located in between.
하부 액티브층(342)은 산화물 반도체(Oxide semi-conductor)로 이루어진다. 산화물 반도체는 예를 들어 비정질 아연 산화물계 반도체로, 특히 a-IGZO 반도체는 갈륨산화물(Ga2O3), 인듐산화물(In2O3) 및 아연산화물(ZnO)의 복합체 타겟을 이용하여 스퍼터링(sputtering) 방법에 의해 형성된다. 이외에도 화학기상증착이나 원자증착(Atomic Layer Deposition; ALD) 등의 화학적 증착방법을 이용할 수도 있다. 여기서, 본 발명의 실시예의 경우에는 갈륨, 인듐, 아연의 원자비가 각각 1:1:1, 2:2:1, 3:2:1 및 4:2:1인 산화물 타겟을 사용하여 아연 산화물계 반도체를 증착할 수 있다. 그러나, 본 발명의 액티브층은 아연 산화물계 반도체에 한정되지 않는다. 또한, 도시하지 않았지만 액티브층(340)의 양측에는 불순물이 도핑되어 소스 영역과 드레인 영역이 구비된다. The lower active layer 342 is made of an oxide semi-conductor. An oxide semiconductor is, for example, an amorphous zinc oxide-based semiconductor. In particular, an a-IGZO semiconductor is sputtered using a composite target of gallium oxide (Ga 2 O 3 ), indium oxide (In 2 O 3 ), and zinc oxide (ZnO). formed by a sputtering method. In addition, chemical vapor deposition such as chemical vapor deposition or atomic layer deposition (ALD) may be used. Here, in the case of the embodiment of the present invention, the zinc oxide type using an oxide target of the gallium, indium, zinc atomic ratio of 1: 1: 1, 2: 2: 1, 3: 2: 1 and 4: 2: 1, respectively The semiconductor can be deposited. However, the active layer of the present invention is not limited to the zinc oxide semiconductor. Although not shown, impurities are doped on both sides of the active layer 340 to include a source region and a drain region.
중간층(344)은 하부 액티브층(342)과 게이트 절연막(350) 사이에 위치하여, 후속 열처리 공정에서 게이트 절연막(350)의 수소나 산소 원자가 액티브층(340)으로 확산되는 것을 막는 배리어(barrier)의 역할을 한다. 원자의 확산을 막기 위해, 중간층(344)은 4족 원소를 포함하는 산화물 반도체로 이루어진다. 예를 들어, 본 발명의 중간층(344)은 인듐, 갈륨, 아연을 포함하며, 4족 원소인 티타늄(Ti), 지르코늄(Zr), 실리콘(Si), 게르마늄(Ge), 주석(Sn), 납(Pb) 등을 더 포함할 수 있다. 바람직하게 중간층(344)은 인듐, 갈륨, 아연 및 실리콘 산화물로 이루어진다. 중간층(344)은 수도 3원소 시스템(pseudo ternary system)을 유지하면서 인듐, 갈륨 및 아연의 원자비가 각각 1.1:1:1로 이루어진다.The intermediate layer 344 is positioned between the lower active layer 342 and the gate insulating layer 350 to prevent diffusion of hydrogen or oxygen atoms of the gate insulating layer 350 into the active layer 340 in a subsequent heat treatment process. Plays a role. To prevent the diffusion of atoms, the intermediate layer 344 is made of an oxide semiconductor containing a Group 4 element. For example, the intermediate layer 344 of the present invention includes indium, gallium, and zinc, and include Group 4 elements such as titanium (Ti), zirconium (Zr), silicon (Si), germanium (Ge), tin (Sn), It may further include lead (Pb). Preferably, interlayer 344 is made of indium, gallium, zinc and silicon oxide. The intermediate layer 344 has an atomic ratio of indium, gallium, and zinc of 1.1: 1: 1, respectively, while maintaining a pseudo ternary system.
본 발명의 실시예에 따른 중간층(344)의 원자비는 In5Ga1Zn1Si(12~13)O35로 이루어진다. 여기서, 중간층(344)의 인듐의 양은 하부 액티브층(342)의 갈륨에 대해 4배 내지 6배의 원자 비율을 차지하고, 4족 원소인 실리콘은 중간층(344)의 갈륨에 대해 12배 내지 13배의 원자 비율을 차지한다. 또한, 중간층(344)의 산소의 양은 수도 3원소 시스템 및 4족 원소의 산화물(oxdie) 형성 조성보다 0 내지 9%를 차지한다. 또한, 중간층(344) 내에 포함된 4족 원소 예를 들어 실리콘(Si)의 원자 비율은 게이트 절연막(350)에 인접한 계면부터 하부 액티브층(342)에 인접한 계면으로 내려갈수록 점진적으로 감소할 수 있다. 예를 들어, 실리콘의 원자 비율이 갈륨의 원자 비율에 대해 6배에서 4배까지 점진적으로 감소할 수 있다.The atomic ratio of the intermediate layer 344 according to the embodiment of the present invention is composed of In 5 Ga 1 Zn 1 Si (12 to 13) O 35 . Herein, the amount of indium in the intermediate layer 344 occupies an atomic ratio of 4 to 6 times the gallium of the lower active layer 342, and the silicon in the Group 4 element is 12 to 13 times the gallium of the intermediate layer 344. Occupies the atomic ratio of. In addition, the amount of oxygen in the intermediate layer 344 occupies 0 to 9% of the oxide forming composition of the three-element water system and the Group 4 element. In addition, the atomic ratio of the Group 4 element, for example, silicon (Si) included in the intermediate layer 344 may be gradually decreased from the interface adjacent to the gate insulating layer 350 to the interface adjacent to the lower active layer 342. . For example, the atomic ratio of silicon may decrease gradually from six to four times the atomic ratio of gallium.
한편, 중간층(344)은 50 내지 100Å의 두께로 이루어진다. 여기서, 중간층(344)의 두께가 50Å 미만이면, 게이트 절연막(350)으로부터 확산되는 원소들을 차단하는 확산방지막으로서 역할을 수행하기가 어렵고, 중간층(350)의 두께가 100Å 초과하면, 채널에 영향을 주어 전하 이동도가 감소되는 현상이 발생한다. 따라서, 본 발명의 중간층(344)은 50 내지 100Å의 두께로 이루어진다. On the other hand, the intermediate layer 344 is made of a thickness of 50 to 100Å. Here, when the thickness of the intermediate layer 344 is less than 50 GPa, it is difficult to function as a diffusion barrier to block elements diffused from the gate insulating film 350. When the thickness of the intermediate layer 350 exceeds 100 GPa, the channel is affected. Given this, the charge mobility decreases. Therefore, the intermediate layer 344 of the present invention has a thickness of 50 to 100 mm 3.
본 발명의 중간층(344)은 막내에 4족 원소 예를 들어 실리콘을 포함하고 있어, 4족 원소의 결합이 강한 이중 결합을 형성하기 때문에 열적으로 안정적이게 된다. 그러므로, 액티브층(340)과 게이트 절연막(350) 사이에 소자의 전기적 특성에는 영향을 주지 않고 경원소의 확산만을 방지할 수 있는 중간층(344)을 구비함으로써, 열처리 공정에 의해 게이트 절연막(350)의 수소나 산소 원자가 확산되는 것을 방지하여 소자가 열화되는 것을 방지할 수 있는 이점이 있다. The intermediate layer 344 of the present invention contains a group 4 element, for example silicon, in the film, and thus becomes stable thermally because the bond of the group 4 element forms a strong double bond. Therefore, since the intermediate layer 344 is provided between the active layer 340 and the gate insulating film 350 to prevent the diffusion of light elements without affecting the electrical characteristics of the device, the gate insulating film 350 is formed by the heat treatment process. There is an advantage of preventing the deterioration of the device by preventing the diffusion of hydrogen or oxygen atoms.
한편, 본 발명에서는 중간층(344)이 하부 액티브층(342)의 전체 영역에 위치하는 것으로 도시하고 설명하였지만, 이에 한정되지 않으며, 중간층(344)은 액티브층(340)의 채널 영역(CH)에만 위치할 수도 있다. Meanwhile, in the present invention, although the intermediate layer 344 is illustrated and described as being located in the entire area of the lower active layer 342, the present invention is not limited thereto. The intermediate layer 344 may be formed only in the channel region CH of the active layer 340. It may be located.
상기 액티브층(340) 상에 게이트 절연막(350)이 위치한다. 게이트 절연막(350)은 실리콘 산화막(SiOx), 실리콘 질화막(SiNx) 또는 이들의 다층으로 이루어진다. 게이트 절연막(350)은 상부에 위치한 게이트 전극(360)과 대응되며 유사한 크기로 이루어진다. 따라서, 게이트 절연막(350)은 게이트 전극(360)과 액티브층(340)을 절연시킨다. 게이트 절연막(350) 상에 게이트 전극(360)이 위치한다. 게이트 전극(160)은 구리(Cu), 몰리브덴(Mo), 알루미늄(Al), 크롬(Cr), 금(Au), 티타늄(Ti), 니켈(Ni), 네오디뮴(Nd), 탄탈륨(Ta) 및 텅스텐(W)로 이루어진 군에서 선택된 어느 하나 또는 이들의 합금의 단층이나 다층으로 이루어진다. 게이트 전극(360)은 상기 액티브층(340)의 채널 영역(CH)에 대응되게 위치한다.The gate insulating layer 350 is positioned on the active layer 340. The gate insulating film 350 is formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof. The gate insulating layer 350 corresponds to the gate electrode 360 positioned on the upper portion and has a similar size. Thus, the gate insulating layer 350 insulates the gate electrode 360 from the active layer 340. The gate electrode 360 is positioned on the gate insulating layer 350. The gate electrode 160 includes copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and tantalum (Ta). And it consists of a single layer or a multilayer of any one or an alloy thereof selected from the group consisting of tungsten (W). The gate electrode 360 is positioned to correspond to the channel region CH of the active layer 340.
상기 게이트 전극(360)이 형성된 기판(310) 상에 층간 절연막(370)이 위치한다. 층간 절연막(370)은 실리콘 산화막(SiOx), 실리콘 질화막(SiNx) 또는 이들의 다층으로 이루어진다. 또한, 층간 절연막(370)은 액티브층(340)의 양측의 소스 영역 및 드레인 영역을 노출하는 콘택홀들(375a, 375b)이 구비된다. 층간 절연막(370) 상에 소스 전극(380a)과 드레인 전극(380b)이 위치한다. 소스 전극(380a) 및 드레인 전극(380b)은 단일층 또는 다층으로 이루어질 수 있으며, 단일층일 경우에는 몰리브덴(Mo), 알루미늄(Al), 크롬(Cr), 금(Au), 티타늄(Ti), 니켈(Ni), 네오디뮴(Nd) 및 구리(Cu)로 이루어진 군에서 선택된 어느 하나 또는 이들의 합금으로 이루어질 수 있다. 또한, 소스 전극(380a) 및 드레인 전극(380b)이 다층일 경우에는 몰리브덴/알루미늄-네오디뮴, 몰리브덴/알루미늄 또는 티타늄/알루미늄의 2중층이거나 몰리브덴/알루미늄-네오디뮴/몰리브덴, 몰리브덴/알루미늄/몰리브덴 또는 티타늄/알루미늄/티타늄의 3중층으로 이루어질 수 있다. 소스 전극(380a)과 드레인 전극(380b)은 층간 절연막(370)에 형성된 콘택홀들(375a, 375b)을 통해 액티브층(340)의 소스 영역 및 드레인 영역에 각각 접속된다. An interlayer insulating layer 370 is positioned on the substrate 310 on which the gate electrode 360 is formed. The interlayer insulating film 370 is formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof. In addition, the interlayer insulating layer 370 includes contact holes 375a and 375b exposing source and drain regions on both sides of the active layer 340. The source electrode 380a and the drain electrode 380b are positioned on the interlayer insulating layer 370. The source electrode 380a and the drain electrode 380b may be formed of a single layer or a multilayer. In the case of a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), Nickel (Ni), neodymium (Nd) and copper (Cu) may be made of any one or an alloy thereof selected from the group consisting of. In the case where the source electrode 380a and the drain electrode 380b are multilayered, a double layer of molybdenum / aluminum-neodymium, molybdenum / aluminum or titanium / aluminum, or molybdenum / aluminum-neodymium / molybdenum, molybdenum / aluminum / molybdenum or titanium It may consist of a triple layer of aluminum / titanium. The source electrode 380a and the drain electrode 380b are connected to the source region and the drain region of the active layer 340 through contact holes 375a and 375b formed in the interlayer insulating layer 370, respectively.
상기 소스 전극(380a)과 드레인 전극(380b)이 위치한 기판(310) 상에 패시베이션막(385)이 위치한다. 패시베이션막(385)은 하부의 박막트랜지스터를 보호하며 이들을 절연시키는 역할을 한다. 패시베이션막(385)은 실리콘 산화막(SiOx), 실리콘 질화막(SiNx) 또는 이들의 다층으로 이루어지고, 드레인 전극(380b)을 노출하는 비어홀(387)이 구비된다. 패시베이션막(385) 상에 화소 전극(390)이 위치한다. 화소 전극(390)은 비어홀(387)을 통해 드레인 전극(380b)에 연결되어 데이터 전압을 공급받는다. 화소 전극(390)은 투명하면서 도전성이 우수한 ITO(indium tin oxide), IZO(indium zinc oxide), ITZO(indium tin zinc oxide) 등으로 이루어진다. 따라서, 본 발명의 제3 실시예에 따른 박막트랜지스터 어레이 기판(300)이 구성된다.The passivation layer 385 is positioned on the substrate 310 on which the source electrode 380a and the drain electrode 380b are positioned. The passivation film 385 protects and insulates the thin film transistors below. The passivation film 385 is formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof, and includes a via hole 387 exposing the drain electrode 380b. The pixel electrode 390 is positioned on the passivation film 385. The pixel electrode 390 is connected to the drain electrode 380b through the via hole 387 to receive a data voltage. The pixel electrode 390 is made of transparent indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or the like. Accordingly, the thin film transistor array substrate 300 according to the third embodiment of the present invention is constructed.
도 8은 본 발명의 제4 실시예에 따른 박막트랜지스터 어레이 기판을 나타낸 단면도이다. 8 is a cross-sectional view illustrating a thin film transistor array substrate according to a fourth embodiment of the present invention.
도 8을 참조하면, 본 발명의 제4 실시예에 따른 박막트랜지스터 어레이 기판(400)은 코플라나 구조의 박막트랜지스터로 게이트 전극이 액티브층의 상부에 위치하는 구조이다. 본 발명의 제4 실시예에 따른 박막트랜지스터 어레이 기판(400)은 전술한 제1 실시예에 따른 박막트랜지스터 어레이 기판(100)과 동일한 구성요소에 대해 자세한 설명을 생략한다. Referring to FIG. 8, the thin film transistor array substrate 400 according to the fourth embodiment of the present invention is a thin film transistor having a coplanar structure, in which a gate electrode is positioned on an active layer. The thin film transistor array substrate 400 according to the fourth embodiment of the present invention will not be described in detail with respect to the same components as the thin film transistor array substrate 100 according to the first embodiment.
보다 자세하게는, 기판(410) 상에 차광막(420)이 위치하고, 차광막(420)이 위치한 기판(410) 전체에 버퍼층(430)이 위치한다. 상기 버퍼층(430) 상에 채널 영역(CH)과 도체화 영역(CP)을 포함하는 액티브층(440)이 위치한다. 액티브층(440)은 산화물 반도체(Oxide semi-conductor)로 이루어진다. 산화물 반도체는 예를 들어 비정질 아연 산화물계 반도체로, 특히 a-IGZO 반도체는 갈륨산화물(Ga2O3), 인듐산화물(In2O3) 및 아연산화물(ZnO)의 복합체 타겟을 이용하여 스퍼터링(sputtering) 방법에 의해 형성된다. 이외에도 화학기상증착이나 원자증착(Atomic Layer Deposition; ALD) 등의 화학적 증착방법을 이용할 수도 있다. 여기서, 본 발명의 실시예의 경우에는 갈륨, 인듐, 아연의 원자비가 각각 1:1:1, 2:2:1, 3:2:1 및 4:2:1인 산화물 타겟을 사용하여 아연 산화물계 반도체를 증착할 수 있다. 그러나, 본 발명의 액티브층(440)은 아연 산화물계 반도체에 한정되지 않는다. 또한, 도시하지 않았지만 액티브층(440)의 양측에는 불순물이 도핑되어 소스 영역과 드레인 영역이 구비된다. In more detail, the light blocking film 420 is positioned on the substrate 410, and the buffer layer 430 is positioned on the entire substrate 410 on which the light blocking film 420 is located. An active layer 440 including a channel region CH and a conductorization region CP is positioned on the buffer layer 430. The active layer 440 is made of an oxide semi-conductor. An oxide semiconductor is, for example, an amorphous zinc oxide-based semiconductor. In particular, an a-IGZO semiconductor is sputtered using a composite target of gallium oxide (Ga 2 O 3 ), indium oxide (In 2 O 3 ), and zinc oxide (ZnO). formed by a sputtering method. In addition, chemical vapor deposition such as chemical vapor deposition or atomic layer deposition (ALD) may be used. Here, in the case of the embodiment of the present invention, the zinc oxide type using an oxide target of the gallium, indium, zinc atomic ratio of 1: 1: 1, 2: 2: 1, 3: 2: 1 and 4: 2: 1, respectively The semiconductor can be deposited. However, the active layer 440 of the present invention is not limited to the zinc oxide semiconductor. Although not shown, impurities are doped on both sides of the active layer 440 to provide a source region and a drain region.
상기 액티브층(440) 상에 게이트 절연막(450)이 위치하고, 게이트 절연막(450) 상에 게이트 전극(460)이 위치한다. 게이트 전극(460)은 상기 액티브층(440)의 채널 영역(CH)에 대응되게 위치한다. 상기 게이트 전극(460)이 형성된 기판(410) 상에 층간 절연막(470)이 위치하고, 층간 절연막(470)은 액티브층(440)의 양측의 소스 영역 및 드레인 영역을 노출하는 콘택홀들(475a, 475b)이 구비된다. 층간 절연막(470) 상에 소스 전극(480a)과 드레인 전극(480b)이 위치하고, 소스 전극(480a)과 드레인 전극(480b)은 층간 절연막(470)에 형성된 콘택홀들(475a, 475b)을 통해 액티브층(440)의 소스 영역 및 드레인 영역에 각각 접속된다. 따라서, 본 발명의 제4 실시예에 따른 박막트랜지스터 어레이 기판(400)이 구성된다.The gate insulating layer 450 is positioned on the active layer 440, and the gate electrode 460 is positioned on the gate insulating layer 450. The gate electrode 460 is positioned to correspond to the channel region CH of the active layer 440. An interlayer insulating layer 470 is disposed on the substrate 410 on which the gate electrode 460 is formed, and the interlayer insulating layer 470 includes contact holes 475a exposing source and drain regions on both sides of the active layer 440. 475b). The source electrode 480a and the drain electrode 480b are positioned on the interlayer insulating film 470, and the source electrode 480a and the drain electrode 480b are formed through the contact holes 475a and 475b formed in the interlayer insulating film 470. It is connected to the source region and the drain region of the active layer 440, respectively. Accordingly, the thin film transistor array substrate 400 according to the fourth embodiment of the present invention is constructed.
한편, 액티브층(440)과 게이트 절연막(450)의 계면에는 후속 열처리 공정에 의해 게이트 절연막(450)에서 확산된 과잉 산소가 존재할 수 있다. 액티브층(440)과 게이트 절연막(450)의 계면에 존재하는 산소는 함량이 많아지면 포지티브 바이어스 템퍼라처 스트레스(positive bias temperature stress) 열화가 발생하게 되고, 함량이 적으면 반도체 소자의 도체화 현상이 발생하여 소자의 특성이 떨어지게 된다.Meanwhile, excess oxygen diffused from the gate insulating layer 450 may be present at an interface between the active layer 440 and the gate insulating layer 450 by a subsequent heat treatment process. When the oxygen content at the interface between the active layer 440 and the gate insulating film 450 increases, positive bias temporal stress deterioration occurs. When the oxygen content decreases, the conduction of the semiconductor device occurs. To deteriorate the characteristics of the device.
본 발명에서는 액티브층(440)과 게이트 절연막(450) 사이에 중간층(445)을 형성한다. 중간층(445)은 포지티브 바이어스 템퍼라처 스트레스 열화를 방지하고, 소자의 도체화를 방지하는 역할을 한다. 중간층(445)은 액티브층(440)과 게이트 절연막(450)의 계면 즉, 중간층(445)에 존재하는 과잉 산소를 제거하기 위해, 4족 원소를 포함하는 산화물 반도체로 이루어진다. 예를 들어, 본 발명의 중간층(445)은 인듐, 갈륨, 아연을 포함하며, 4족 원소인 티타늄(Ti), 지르코늄(Zr), 실리콘(Si), 게르마늄(Ge), 주석(Sn), 납(Pb) 등을 더 포함할 수 있다. 바람직하게 중간층(145)은 인듐, 갈륨, 아연 및 실리콘 산화물로 이루어진다. 중간층(445)에 4족 원소 바람직하게 실리콘(Si) 원소를 포함하면, 미결합 상태의 산소들에 실리콘이 결합되어 미결합 상태의 산소들의 양을 줄일 수 있다. 즉, 중간층(445)에 4족 원소를 포함함으로써, 과잉 산소를 제거하여 포지티브 바이어스 템퍼라처 스트레스 열화를 방지할 수 있다.In the present invention, an intermediate layer 445 is formed between the active layer 440 and the gate insulating layer 450. The intermediate layer 445 serves to prevent the positive bias temperture stress degradation and to prevent the device from conducting. The intermediate layer 445 is formed of an oxide semiconductor containing a Group 4 element to remove excess oxygen present at the interface between the active layer 440 and the gate insulating layer 450, that is, the intermediate layer 445. For example, the intermediate layer 445 of the present invention includes indium, gallium, and zinc, and include Group 4 elements such as titanium (Ti), zirconium (Zr), silicon (Si), germanium (Ge), tin (Sn), It may further include lead (Pb). Preferably, the intermediate layer 145 is made of indium, gallium, zinc and silicon oxide. When the intermediate layer 445 includes a Group 4 element, preferably a silicon (Si) element, silicon may be bonded to the unbound oxygen to reduce the amount of unbound oxygen. That is, by including the Group 4 element in the intermediate layer 445, the excess oxygen can be removed to prevent the positive bias temperature stress degradation.
본 발명의 중간층(445)에서 실리콘 원소의 함량은 2.9 내지 3.2×1022㎝-3일 수 있다. 여기서, 중간층(445)의 실리콘 원소의 함량이 2.9×1022㎝-3 이상이면 중간층(445)에 존재하는 과잉 산소와 실리콘을 결합시켜 과잉 산소의 양을 줄여 포지티브 바이어스 템퍼라처 스트레스 열화을 방지할 수 있다. 또한, 중간층(445)의 실리콘 원소의 함량이 3.2×1022㎝-3 이하이면, 중간층(445)에 존재하는 과잉 산소의 양이 너무 많이 줄어들어 소자가 도체화되어 박막트랜지스터의 특성이 저하되는 문제를 방지할 수 있다.In the intermediate layer 445 of the present invention, the content of silicon element may be 2.9 to 3.2 × 10 22 cm −3 . Herein, when the content of the silicon element of the intermediate layer 445 is 2.9 × 10 22 cm −3 or more, the excess oxygen present in the intermediate layer 445 may be combined with silicon to reduce the amount of excess oxygen to prevent the positive bias temperature stress degradation. have. In addition, when the content of the silicon element of the intermediate layer 445 is 3.2 × 10 22 cm −3 or less, the amount of excess oxygen present in the intermediate layer 445 is reduced too much, so that the device becomes a conductor and the characteristics of the thin film transistor are deteriorated. Can be prevented.
그리고, 중간층(445)에 4족 원소를 포함하여, 미결합 상태의 산소들의 양을 줄인다해도 일부 미결합 상태의 산소들이 남아있을 수 있다. 남아있는 미결합 상태의 산소들은 포지티브 바이어스 템퍼라처 스트레스 열화에 영향을 미친다. 따라서, 본 발명의 중간층(445)은 일정 양의 수소를 포함하여, 미결합 상태의 산소들에 수소를 결합시켜 전자가 결합될 수 없도록 한다. 즉, 중간층(445)에 일부 과잉 산소가 존재하나 이 과잉 산소들에 수소가 결합되어, 액티브층의 전자가 과잉 산소에 결합되지 못하므로 포지티브 바이어스 템퍼라처 스트레스 열화의 발생을 방지한다.And, by including the Group 4 element in the intermediate layer 445, even if the amount of unbound oxygen is reduced, some unbound oxygen may remain. The remaining unbound oxygen affects the positive bias temperature stress degradation. Therefore, the intermediate layer 445 of the present invention contains a certain amount of hydrogen, so that the electrons can not be bonded by bonding hydrogen to the unbound oxygen. That is, some excess oxygen is present in the intermediate layer 445, but hydrogen is bonded to the excess oxygen, so that the electrons of the active layer are not bonded to the excess oxygen, thereby preventing the occurrence of the positive bias temperature stress degradation.
중간층(445)의 과잉 산소의 양은 금속 대비 산소의 양으로 정의한다. 중간층(445)은 인듐, 갈륨, 아연, 산소로 이루어지고 실리콘 원소가 첨가되었으므로, 인듐, 갈륨, 아연, 실리콘 및 산소를 포함할 수 있다. 중간층(445)은 InaGabZncSidOy로 표시될 수 있고, 원소의 원자비가 인듐이 1.5, 아연이 1, 갈륨이 1.5, 실리콘이 2이므로, Y=1.5a+1.5b+1c+2d로 나타낼 수 있다. 여기서, 중간층(445)의 실제 측정된 산소의 양이 x일 경우 x가 y보다 크면 산소가 과잉 존재하는 것이고 y가 x보다 크면 산소가 부족한 것이다. 따라서, 중간층(445)은 중간층(445)에 남아있는 과잉 산소의 양만큼의 수소를 포함할 수 있으며, 수소의 함량은 1.2 내지 1.6×1021㎝-3일 수 있다. 이 수소의 함량은 전술한 실리콘 원소의 함량에 따라 달라지는 것으로, 예를 들어, 실리콘 원소의 함량이 2.9 ×1022㎝-3이면, 수소의 함량은 1.6×1021㎝-3일 수 있고, 실리콘 원소의 함량이 3.2×1022㎝-3이면, 수소의 함량은 1.2×1021㎝-3일 수 있다. 즉, 중간층(445) 내에서 실리콘 원소를 일정 함량으로 첨가하였을 때, 남아있는 과잉 산소의 양만큼 수소를 첨가하는 것이다. The amount of excess oxygen in the intermediate layer 445 is defined as the amount of oxygen relative to the metal. Since the intermediate layer 445 is made of indium, gallium, zinc, and oxygen and silicon is added, the intermediate layer 445 may include indium, gallium, zinc, silicon, and oxygen. The intermediate layer 445 may be represented by In a Ga b Zn c Si d O y , and since the atomic ratio of the element is 1.5 indium, 1 zinc, 1 gallium 1.5, and 2 silicon, Y = 1.5a + 1.5b + It may be represented by 1c + 2d. Here, when x is greater than y when the amount of oxygen actually measured in the intermediate layer 445 is x, oxygen is excessively present, and when y is greater than x, oxygen is insufficient. Accordingly, the intermediate layer 445 may include as much hydrogen as the amount of excess oxygen remaining in the intermediate layer 445, and the hydrogen content may be 1.2 to 1.6 × 10 21 cm −3 . The content of hydrogen depends on the content of the above-described silicon element, for example, if the content of silicon element is 2.9 × 10 22 cm −3 , the content of hydrogen may be 1.6 × 10 21 cm −3 , and the silicon If the content of the element is 3.2 × 10 22 cm −3 , the content of hydrogen may be 1.2 × 10 21 cm −3 . That is, when a silicon element is added in a predetermined amount in the intermediate layer 445, hydrogen is added by the amount of excess oxygen remaining.
따라서, 중간층(445)은 중간층(445)에 남아있는 과잉 산소의 양만큼의 수소를 포함할 수 있으며, 수소의 함량은 1.2 내지 1.6×1021㎝-3일 수 있다. 이 수소의 함량은 전술한 실리콘 원소의 함량에 따라 달라지는 것으로, 예를 들어, 실리콘 원소의 함량이 2.9 ×1022㎝-3이면, 수소의 함량은 1.6×1021㎝-3일 수 있고, 실리콘 원소의 함량이 3.2×1022㎝-3이면, 수소의 함량은 1.2×1021㎝-3일 수 있다. 즉, 중간층(445) 내에서 실리콘 원소를 일정 함량으로 첨가하였을 때, 남아있는 과잉 산소의 양만큼 수소를 첨가하는 것이다. Accordingly, the intermediate layer 445 may include as much hydrogen as the amount of excess oxygen remaining in the intermediate layer 445, and the hydrogen content may be 1.2 to 1.6 × 10 21 cm −3 . The content of hydrogen depends on the content of the above-described silicon element, for example, if the content of silicon element is 2.9 × 10 22 cm −3 , the content of hydrogen may be 1.6 × 10 21 cm −3 , and the silicon If the content of the element is 3.2 × 10 22 cm −3 , the content of hydrogen may be 1.2 × 10 21 cm −3 . That is, when a silicon element is added in a predetermined amount in the intermediate layer 445, hydrogen is added by the amount of excess oxygen remaining.
하기 표 1은 중간층에서 금속 대비 산소의 양에 따른 박막트랜지스터의 문턱전압과 포지티브 바이어스 템퍼라처 스트레스를 나타낸 표이다.Table 1 is a table showing the threshold voltage and the positive bias temperature stress of the thin film transistor according to the amount of oxygen in the interlayer.
금속 대비 산소의 양(%)% Of oxygen relative to metal 문턱전압(Vth(V)Threshold Voltage (Vth (V) 포지티브 바이어스 템퍼라처 스트레스(PBTS, △Vth(V))Positive Bias Temperature Stress (PBTS, ΔVth (V))
8989 도체화Conductorization --
9090 도체화Conductorization --
9494 도체화Conductorization --
101.2101.2 0.690.69 0.210.21
101.3101.3 0.720.72 0.350.35
112112 0.880.88 2.612.61
상기 표 1을 참조하면, 중간층에서 금속 대비 산소의 양이 100% 이하로 줄어들면 소자가 도체화되어 문턱전압이 나타나지 않고, 포지티브 바이어스 템퍼라처 스트레스 또한 측정되지 않는다. 반면, 중간층에서 금속 대비 산소의 양이 100% 이상으로 늘어나면 문턱전압이 증가하고 포지티브 바이어스 템퍼라처 스트레스 또한 증가된다.Referring to Table 1, when the amount of oxygen in the intermediate layer is reduced to 100% or less, the device becomes a conductor and no threshold voltage appears, and the positive bias temperture stress is not measured. On the other hand, if the amount of oxygen in the interlayer is more than 100% of the metal, the threshold voltage increases and the positive bias temperature stress also increases.
이 결과를 통해, 중간층의 금속 대비 산소의 양 즉 과잉 산소의 양이 작을수록 포지티브 바이어스 템퍼라처 스트레스에 의한 열화 현상을 방지할 수 있어, 소자의 신뢰성을 개선시킬 수 있다.As a result, the smaller the amount of oxygen relative to the metal of the intermediate layer, that is, the amount of excess oxygen, can prevent deterioration due to the positive bias temperature stress, thereby improving the reliability of the device.
한편, 본 발명의 중간층(445)은 50 내지 100Å의 두께로 이루어진다. 여기서, 중간층(445)의 두께가 50Å 이상이면, 게이트 절연막(450)으로부터 확산되는 산소 등의 원소들을 차단하는 확산방지막으로서 작용할 수 있고, 중간층(445)의 두께가 100Å 이하이면, 중간층(445)이 액티브층(440)의 채널로 작용하여 소자가 열화되는 것을 방지할 수 있다. 따라서, 본 발명의 중간층(445)은 50 내지 100Å의 두께로 이루어진다. On the other hand, the intermediate layer 445 of the present invention is made of a thickness of 50 to 100Å. If the thickness of the intermediate layer 445 is 50 GPa or more, the intermediate layer 445 may serve as a diffusion barrier to block elements such as oxygen diffused from the gate insulating film 450. If the thickness of the intermediate layer 445 is 100 GPa or less, the intermediate layer 445 may be used. It can act as a channel of the active layer 440 to prevent the device from deteriorating. Therefore, the intermediate layer 445 of the present invention has a thickness of 50 to 100 kPa.
상기와 같이, 본 발명의 제4 실시예에 따른 박막트랜지스터 어레이 기판은 액티브층과 게이트 절연막 사이에 실리콘 원소를 포함하는 중간층을 형성하여, 과잉 산소로 인한 포지티브 바이어스 템퍼라처 스트레스 열화를 방지할 수 있다. 또한, 중간층에 남아있는 과잉 산소의 양에 대응하는 만큼의 수소를 포함하여 과잉 산소가 전자를 포집하는 것을 막아 포지티브 바이어스 템퍼라처 스트레스 열화를 방지할 수 있다.As described above, the thin film transistor array substrate according to the fourth embodiment of the present invention may form an intermediate layer including silicon elements between the active layer and the gate insulating layer, thereby preventing the positive bias temperature stress degradation due to excess oxygen. . In addition, it is possible to prevent excess oxygen from trapping electrons by including hydrogen corresponding to the amount of excess oxygen remaining in the intermediate layer, thereby preventing the positive bias temperture stress degradation.
한편, 본 발명에서는 중간층(445)이 액티브층(440)의 채널 영역(CH)과 게이트 절연막(450)에 컨택하는 영역에만 위치하는 것으로 도시하고 설명하였지만, 이에 한정되지 않으며, 중간층(445)은 액티브층(440)의 전체 영역에도 위치할 수 있다.Meanwhile, in the present invention, although the intermediate layer 445 is illustrated and described as being located only in an area in contact with the channel region CH and the gate insulating layer 450 of the active layer 440, the intermediate layer 445 is not limited thereto. It may be located in the entire area of the active layer 440.
도 9는 본 발명의 제1 실시예에 따른 박막트랜지스터 어레이 기판을 포함하는 표시장치를 나타낸 도면이다. 하기에서는 전술한 박막트랜지스터 어레이 기판에 대한 설명을 생략하고, 표시장치의 예로 유기발광표시장치에 대해 설명하기로 한다. 다만, 본 발명은 유기발광표시장치에 한정되지 않으며, 액정표시장치 등의 평판표시장치에 사용가능하다.9 is a diagram illustrating a display device including a thin film transistor array substrate according to a first embodiment of the present invention. Hereinafter, the description of the above-described thin film transistor array substrate will be omitted, and the organic light emitting display device will be described as an example of the display device. However, the present invention is not limited to the organic light emitting display device, and can be used for flat panel display devices such as liquid crystal display devices.
도 9를 참조하면, 기판(110) 상에 액티브층(140), 게이트 전극(160), 소스 전극(180a) 및 드레인 전극(180b)을 포함하는 박막트랜지스터(TFT)가 위치한다. 이들 상에 유기절연막(190)이 위치한다. 유기절연막(190)은 포토아크릴(photo acryl), 폴리이미드(polyimide), 벤조사이클로부틴계 수지(benzocyclobutene resin), 아크릴레이트계 수지(acrylate) 등의 유기물로 이루어질 수 있다. 상기 유기절연막(190)에는 박막트랜지스터(TFT)의 드레인 전극(180b)을 노출하는 비어홀(195)이 구비된다. Referring to FIG. 9, a thin film transistor TFT including an active layer 140, a gate electrode 160, a source electrode 180a, and a drain electrode 180b is positioned on the substrate 110. The organic insulating layer 190 is disposed on them. The organic insulating layer 190 may be made of organic materials such as photo acryl, polyimide, benzocyclobutene resin, and acrylate resin. The organic insulating layer 190 includes a via hole 195 that exposes the drain electrode 180b of the thin film transistor TFT.
상기 유기절연막(190) 상에 화소 전극(285)이 위치한다. 화소 전극(285)은 투명도전막으로 이루어질 수 있다. 투명도전막은 ITO(Indium Tin Oxide) 또는 IZO(Indium Zinc Oxide)와 같은 투명하면서도 도전성을 가진 재료일 수 있다. 여기서, 유기발광표시장치가 전면발광형 구조로 형성될 경우 투명도전막의 하부에 알루미늄(Al), 알루미늄-네오디움(Al-Nd), 은(Ag), 은 합금(Ag alloy) 등과 같은 고반사율의 특성을 갖는 반사금속막을 더 포함할 수 있고, 투명도전막/반사금속막/투명도전막의 구조로 이루어질 수 있다. 바람직하게 화소 전극(285)은 예를 들어 ITO/Ag/ITO의 구조로 이루어질 수 있다. 화소 전극(285)은 유기절연막(190)에 구비된 비어홀(195)을 통해 드레인 전극(180b)에 연결된다. The pixel electrode 285 is positioned on the organic insulating layer 190. The pixel electrode 285 may be formed of a transparent conductive film. The transparent conductive film may be a transparent and conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). In the case where the organic light emitting display device is formed as a top emission type structure, high reflectance such as aluminum (Al), aluminum-nedium (Al-Nd), silver (Ag), silver alloy (Ag alloy), etc., is formed on the lower portion of the transparent conductive film. It may further include a reflective metal film having a property of, it may be made of a structure of a transparent conductive film / reflective metal film / transparent conductive film. Preferably, the pixel electrode 285 may have a structure of, for example, ITO / Ag / ITO. The pixel electrode 285 is connected to the drain electrode 180b through a via hole 195 provided in the organic insulating layer 190.
화소 전극(285) 상에 화소 전극(285)을 노출하는 뱅크층(287)이 위치한다. 뱅크층(287)은 화소를 정의하며 화소 전극(285)을 절연시키는 것으로 폴리이미드(polyimide), 벤조사이클로부틴계 수지(benzocyclobutene series resin), 아크릴레이트(acrylate) 등의 유기물로 이루어진다. 뱅크층(287)은 화소 전극(285)을 노출하는 개구부(288)를 포함한다. 화소 전극(285)과 뱅크층(287) 상에 유기막층(290)이 위치한다. 유기막층(290)은 적어도 발광층을 포함하며, 정공주입층, 정공수송층, 전자수송층 또는 전자주입층을 더 포함할 수 있다. 유기막층(290) 상에 대향 전극(295)이 위치한다. 대향 전극(295)은 일함수가 낮은 금속들로 은(Ag), 마그네슘(Mg), 칼슘(Ca) 등을 사용할 수 있다. 이에 따라, 화소 전극(285), 유기막층(290) 및 대향 전극(295)으로 구성된 유기발광 다이오드(OLED)가 구성된다. 따라서, 기판(110) 상에 박막트랜지스터(TFT)와 유기발광 다이오드(OLED)가 구비된 유기발광표시장치(280)가 구성된다.The bank layer 287 exposing the pixel electrode 285 is disposed on the pixel electrode 285. The bank layer 287 defines a pixel and insulates the pixel electrode 285. The bank layer 287 is made of an organic material such as polyimide, benzocyclobutene series resin, and acrylate. The bank layer 287 includes an opening 288 exposing the pixel electrode 285. The organic layer 290 is disposed on the pixel electrode 285 and the bank layer 287. The organic layer 290 may include at least a light emitting layer, and may further include a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer. The opposite electrode 295 is positioned on the organic layer 290. The counter electrode 295 may be made of silver (Ag), magnesium (Mg), calcium (Ca), or the like as metals having a low work function. As a result, an organic light emitting diode OLED including the pixel electrode 285, the organic layer 290, and the counter electrode 295 is configured. Accordingly, the organic light emitting display device 280 including the thin film transistor TFT and the organic light emitting diode OLED is formed on the substrate 110.
이하, 전술한 본 발명의 실시예에 따른 박막트랜지스터 어레이 기판의 제조방법에 대해 설명하기로 한다. 하기에서는 전술한 제1 실시예에 따른 코플라나 구조의 박막트랜지스터를 예로 설명하나, 본 발명은 제2 실시예에 따른 에치 스토퍼 구조에도 적용 가능하다.Hereinafter, a method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention will be described. Hereinafter, the thin film transistor having the coplanar structure according to the first embodiment will be described as an example, but the present invention can be applied to the etch stopper structure according to the second embodiment.
도 10a 내지 도 10e는 본 발명의 제1 실시예에 따른 박막트랜지스터 어레이 기판의 제조방법을 공정별로 나타낸 도면이다. 10A to 10E are diagrams illustrating processes of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.
도 10a를 참조하면, 투명하거나 불투명한 유리, 플라스틱 또는 금속으로 이루어지며 평탄도가 유지되는 기판(110) 상에 카본 블랙 등의 흑색을 나타내는 재료를 포함하는 수지 또는 비정질 실리콘(a-Si), 게르마늄(Ge), 산화탄탈륨(TaOx), 산화구리(CuOx) 등의 반도체 계열의 재료를 형성하고 마스크를 이용하여 패터닝하여 차광막(120)을 형성한다. 차광막(120)은 추후 액티브층이 형성될 영역마다 형성된다. 그러나, 본 발명에서는 이에 한정되지 않으며, 차광막(120)이 기판(110) 전면에 형성될 수도 있다.Referring to FIG. 10A, a resin or amorphous silicon (a-Si) including a material showing black, such as carbon black, on a substrate 110 made of transparent or opaque glass, plastic, or metal, and having a flatness maintained, Semiconductor-based materials such as germanium (Ge), tantalum oxide (TaOx), and copper oxide (CuOx) are formed and patterned using a mask to form the light shielding film 120. The light blocking film 120 is formed for each region where an active layer will be formed later. However, the present invention is not limited thereto, and the light blocking film 120 may be formed on the entire surface of the substrate 110.
이어, 차광막(120)이 형성된 기판(110) 상에 CVD(Chemical Vapor Deposition), PECVD(Plasma Enhanced Chemical Vapor Deposition), 스퍼터링(sputtering) 증착 방법으로 실리콘 산화물(SiOx) 또는 실리콘 질화물(SiNx)을 증착하여 버퍼층(130)을 형성한다. 그리고, 버퍼층(130)이 형성된 기판(110) 상에 인듐산화물(In2O3), 주석산화물(SnO) 및 아연산화물(ZnO)의 복합체 타겟을 이용하여 스퍼터링(sputtering) 방법으로 산화물 반도체층을 적층한다. 이어, 마스크를 이용하여 산화물 반도체층을 패터닝하여 액티브층(140)을 형성한다. 액티브층(140)은 이외에도 화학기상증착이나 원자증착(Atomic Layer Deposition; ALD) 등의 화학적 증착방법을 이용하여 형성할 수도 있다. 이때, 액티브층(140)은 기판(110) 상에 형성된 차광막(120)에 대응되도록 형성하여, 하부로부터 입사되는 광이 액티브층(140)에 도달하지 못하도록 하여 광에 의한 누설전류가 발생하는 것을 방지한다.Subsequently, silicon oxide (SiOx) or silicon nitride (SiNx) is deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or sputtering deposition on the substrate 110 on which the light shielding film 120 is formed. The buffer layer 130 is formed. The oxide semiconductor layer is sputtered onto the substrate 110 on which the buffer layer 130 is formed by using a composite target of indium oxide (In 2 O 3 ), tin oxide (SnO), and zinc oxide (ZnO). Laminated. Subsequently, the oxide semiconductor layer is patterned using a mask to form the active layer 140. In addition, the active layer 140 may be formed using a chemical vapor deposition method such as chemical vapor deposition or atomic layer deposition (ALD). At this time, the active layer 140 is formed to correspond to the light shielding film 120 formed on the substrate 110, so that light incident from the bottom does not reach the active layer 140 to prevent the leakage current caused by light. prevent.
다음 도 10b를 참조하면, 액티브층(140)이 형성된 기판(110) 상에 인듐산화물(In2O3), 주석산화물(SnO) 및 아연산화물(ZnO)의 복합체 타겟을 이용하여 스퍼터링(sputtering) 방법으로 산화물 반도체층(147)을 적층한다. 이어, CVD, PECVD 또는 스퍼터링 증착 방법으로 실리콘 산화물(SiOx) 또는 실리콘 질화물(SiNx)을 증착하여 절연층(152)을 형성한다. 이어, 절연층(152) 상에 스퍼터링 증착방법으로 구리(Cu), 몰리브덴(Mo), 알루미늄(Al), 크롬(Cr), 금(Au), 티타늄(Ti), 니켈(Ni), 네오디뮴(Nd), 탄탈륨(Ta) 및 텅스텐(W)로 이루어진 군에서 선택된 어느 하나 또는 이들의 합금을 증착하여 금속층(162)을 형성한다. 이어, 금속층(162) 상에 포토레지스트(photoresist)를 도포하고 이를 노광 및 현상하여 포토레지스트 패턴(PR)을 형성한다. 이때, 포토레지스트 패턴(PR)은 액티브층(140)의 채널 영역이 형성될 영역과 대응되도록 형성한다. Next, referring to FIG. 10B, sputtering is performed on the substrate 110 on which the active layer 140 is formed using a composite target of indium oxide (In 2 O 3 ), tin oxide (SnO), and zinc oxide (ZnO). The oxide semiconductor layer 147 is laminated by the method. Subsequently, silicon oxide (SiOx) or silicon nitride (SiNx) is deposited by CVD, PECVD, or sputtering deposition to form an insulating layer 152. Subsequently, copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Sp) are deposited on the insulating layer 152. Nd), tantalum (Ta), and tungsten (W) may be deposited by depositing any one or alloys thereof to form the metal layer 162. Next, a photoresist is applied on the metal layer 162, and the photoresist is exposed and developed to form a photoresist pattern PR. In this case, the photoresist pattern PR is formed to correspond to the region where the channel region of the active layer 140 is to be formed.
다음, 도 10c를 참조하면, 포토레지스트 패턴(PR)을 마스크로 하여 상기 금속층(162)을 식각하여 게이트 전극(160)을 형성한다. 이때, 상기 금속층(162)은 해당 재료를 식각할 수 있는 식각액을 이용하여 습식 식각(wet etching)법으로 식각한다. Next, referring to FIG. 10C, the gate electrode 160 is formed by etching the metal layer 162 using the photoresist pattern PR as a mask. In this case, the metal layer 162 is etched by wet etching using an etchant capable of etching the material.
다음, 도 10d를 참조하면, 포토레지스트 패턴(PR)을 이용하여 절연층(152)을 식각하여 게이트 절연막(150)을 형성한다. 이때, 절연층(152)은 아르곤(Ar) 등의 가스를 이용한 플라즈마 식각 공정으로 식각되고, 절연층(152)의 상부에 위치한 게이트 전극(160)을 따라 유사한 크기로 형성된다. 그리고, 플라즈마 식각 공정에서 절연층(152)이 다 식각되면 산화물 반도체층(147)과 액티브층(140)이 노출되면, 산화물 반도체층(147)과 액티브층(140)에 일정 시간 식각 공정을 수행하여 액티브층(140)을 도체화한다. 즉, 액티브층(140)에 플라즈마 식각 공정이 수행되면, 액티브층(140) 내의 산소가 빠져나가고 불순물이 주입되어 도전 특성이 향상된다. 따라서, 게이트 전극(160) 및 게이트 절연막(150)이 위치한 영역과 대응되는 액티브층(140)의 채널 영역(CH)이 형성되고, 액티브층(140)의 채널 영역(CH)을 제외한 도체화 영역(CP)이 형성된다. 그리고, 게이트 절연막(150)에 의해 노출된 산화물 반도체층(147)을 식각하여 중간층(145)을 형성한다. 따라서, 게이트 전극(160), 게이트 절연막(150) 및 중간층(145)은 유사한 크기로 액티브층(140)의 채널 영역(CH) 상에 형성된다. 이후, 포토레지스트 패턴(PR)을 스트립하여 제거한다. Next, referring to FIG. 10D, the insulating layer 152 is etched using the photoresist pattern PR to form the gate insulating layer 150. In this case, the insulating layer 152 is etched by a plasma etching process using a gas such as argon (Ar), and is formed in a similar size along the gate electrode 160 positioned on the insulating layer 152. When the insulating layer 152 is etched in the plasma etching process, when the oxide semiconductor layer 147 and the active layer 140 are exposed, the etching process is performed on the oxide semiconductor layer 147 and the active layer 140 for a predetermined time. The active layer 140 is conductored. That is, when the plasma etching process is performed on the active layer 140, oxygen in the active layer 140 is released and impurities are injected to improve conductivity. Accordingly, the channel region CH of the active layer 140 corresponding to the region where the gate electrode 160 and the gate insulating layer 150 are located is formed, and the conductive region except for the channel region CH of the active layer 140 is formed. (CP) is formed. The oxide semiconductor layer 147 exposed by the gate insulating layer 150 is etched to form an intermediate layer 145. Accordingly, the gate electrode 160, the gate insulating layer 150, and the intermediate layer 145 are formed on the channel region CH of the active layer 140 in a similar size. Thereafter, the photoresist pattern PR is stripped and removed.
다음, 도 10e를 참조하면, 게이트 전극(160)이 형성된 기판(110) 상에 CVD, PECVD 또는 스퍼터링 증착 방법으로 실리콘 산화물(SiOx) 또는 실리콘 질화물(SiNx)을 증착하여 층간 절연막(170)을 형성한다. 그리고, 층간 절연막(170)을 식각하여 액티브층(140)의 양측 일부인 도체화 영역(CP)을 노출하는 콘택홀들(175a, 175b)을 형성한다. 그리고, 기판(110) 상에 몰리브덴(Mo), 알루미늄(Al), 크롬(Cr), 금(Au), 티타늄(Ti), 니켈(Ni), 네오디뮴(Nd) 및 구리(Cu)로 이루어진 군에서 선택된 어느 하나 또는 이들의 합금을 적층하고 패터닝하여 소스 전극(180a)과 드레인 전극(180b)을 형성한다. 이때, 소스 전극(180a)과 드레인 전극(180b)은 층간 절연막(170)에 형성된 콘택홀들(175a, 175b)을 통해 액티브층(140)에 각각 연결된다. 따라서, 액티브층(140), 중간층(145), 게이트 전극(160), 소스 전극(180a) 및 드레인 전극(180b)을 포함하는 박막트랜지스터(TFT)가 형성된다.Next, referring to FIG. 10E, an interlayer insulating layer 170 is formed by depositing silicon oxide (SiOx) or silicon nitride (SiNx) on the substrate 110 on which the gate electrode 160 is formed by CVD, PECVD, or sputter deposition. do. The interlayer insulating layer 170 is etched to form contact holes 175a and 175b exposing the conductive region CP, which is part of both sides of the active layer 140. And, on the substrate 110, a group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). The source electrode 180a and the drain electrode 180b are formed by stacking and patterning any one or an alloy thereof. In this case, the source electrode 180a and the drain electrode 180b are connected to the active layer 140 through contact holes 175a and 175b formed in the interlayer insulating layer 170, respectively. Accordingly, a thin film transistor TFT including the active layer 140, the intermediate layer 145, the gate electrode 160, the source electrode 180a, and the drain electrode 180b is formed.
한편, 도 11a 내지 도 11h는 본 발명의 제3 실시예에 따른 박막트랜지스터 어레이 기판의 제조방법을 공정별로 나타낸 도면이다. 11A to 11H are views illustrating a method of manufacturing a thin film transistor array substrate according to a process, according to a third embodiment of the present invention.
도 11a를 참조하면, 투명하거나 불투명한 유리, 플라스틱 또는 금속으로 이루어지며 평탄도가 유지되는 기판(310) 상에 카본 블랙 등의 흑색을 나타내는 재료를 포함하는 수지 또는 비정질 실리콘(a-Si), 게르마늄(Ge), 산화탄탈륨(TaOx), 산화구리(CuOx) 등의 반도체 계열의 재료를 형성하고 마스크를 이용하여 패터닝하여 차광막(320)을 형성한다. 차광막(320)은 추후 액티브층이 형성될 영역마다 형성된다. 그러나, 본 발명에서는 이에 한정되지 않으며, 차광막(320)이 기판(310) 전면에 형성될 수도 있다.Referring to FIG. 11A, a resin or amorphous silicon (a-Si) including a material showing black, such as carbon black, on a substrate 310 made of transparent or opaque glass, plastic, or metal, and having flatness maintained, Semiconductor-based materials such as germanium (Ge), tantalum oxide (TaOx), and copper oxide (CuOx) are formed and patterned using a mask to form a light shielding film 320. The light blocking film 320 is formed for each region where an active layer will be formed later. However, the present invention is not limited thereto, and the light blocking film 320 may be formed on the entire surface of the substrate 310.
이어, 차광막(320)이 형성된 기판(310) 상에 CVD(Chemical Vapor Deposition), PECVD(Plasma Enhanced Chemical Vapor Deposition), 스퍼터링(sputtering) 증착 방법으로 실리콘 산화물(SiOx) 또는 실리콘 질화물(SiNx)을 증착하여 버퍼층(330)을 형성한다. 그리고, 버퍼층(330)이 형성된 기판(310) 상에 인듐산화물(In2O3), 주석산화물(SnO) 및 아연산화물(ZnO)의 복합체 타겟을 이용하여 스퍼터링(sputtering) 방법으로 제1 산화물 반도체층(332)을 적층한다. 그리고, 인듐산화물(In2O3), 주석산화물(SnO), 실리콘산화물(SiOx) 및 아연산화물(ZnO)의 복합체 타겟을 이용하여 스퍼터링(sputtering) 방법으로 제2 산화물 반도체층(334)을 적층한다.Subsequently, silicon oxide (SiOx) or silicon nitride (SiNx) is deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or sputtering deposition on the substrate 310 on which the light blocking film 320 is formed. The buffer layer 330 is formed. The first oxide semiconductor is sputtered by using a composite target of indium oxide (In 2 O 3 ), tin oxide (SnO), and zinc oxide (ZnO) on the substrate 310 on which the buffer layer 330 is formed. Layer 332 is stacked. The second oxide semiconductor layer 334 is stacked by sputtering using a composite target of indium oxide (In 2 O 3 ), tin oxide (SnO), silicon oxide (SiOx), and zinc oxide (ZnO). do.
도 11b를 참조하면, 마스크를 이용하여 제1 산화물 반도체층(332) 및 제2 산화물 반도체층(334)을 패터닝하여, 하부 액티브층(342) 및 중간층(344)을 포함하는 액티브층(340)을 형성한다. 액티브층(340)은 이외에도 화학기상증착이나 원자증착(Atomic Layer Deposition; ALD) 등의 화학적 증착방법을 이용하여 형성할 수도 있다. 이때, 액티브층(340)은 기판(310) 상에 형성된 차광막(320)에 대응되도록 형성하여, 하부로부터 입사되는 광이 액티브층(340)에 도달하지 못하도록 하여 광에 의한 누설전류가 발생하는 것을 방지한다.Referring to FIG. 11B, the first oxide semiconductor layer 332 and the second oxide semiconductor layer 334 are patterned using a mask to form an active layer 340 including a lower active layer 342 and an intermediate layer 344. To form. In addition, the active layer 340 may be formed using a chemical vapor deposition method such as chemical vapor deposition or atomic layer deposition (ALD). At this time, the active layer 340 is formed to correspond to the light shielding film 320 formed on the substrate 310, so that the light incident from the bottom does not reach the active layer 340 to prevent the leakage current caused by the light is generated. prevent.
다음 도 11c를 참조하면, 액티브층(340)이 형성된 기판(310) 상에 CVD, PECVD 또는 스퍼터링 증착 방법으로 실리콘 산화물(SiOx) 또는 실리콘 질화물(SiNx)을 증착하여 절연층(352)을 형성한다. 이어, 절연층(352) 상에 스퍼터링 증착방법으로 구리(Cu), 몰리브덴(Mo), 알루미늄(Al), 크롬(Cr), 금(Au), 티타늄(Ti), 니켈(Ni), 네오디뮴(Nd), 탄탈륨(Ta) 및 텅스텐(W)로 이루어진 군에서 선택된 어느 하나 또는 이들의 합금을 증착하여 금속층(354)을 형성한다. 이어, 금속층(354) 상에 포토레지스트(photoresist)를 도포하고 이를 노광 및 현상하여 포토레지스트 패턴(PR)을 형성한다. 이때, 포토레지스트 패턴(PR)은 액티브층(340)의 채널 영역이 형성될 영역과 대응되도록 형성한다. Next, referring to FIG. 11C, an insulating layer 352 is formed by depositing silicon oxide (SiOx) or silicon nitride (SiNx) on a substrate 310 on which the active layer 340 is formed by CVD, PECVD, or sputter deposition. . Subsequently, copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Sp) are deposited on the insulating layer 352. Nd), tantalum (Ta), and tungsten (W) may be deposited by depositing any one or alloys thereof to form the metal layer 354. Next, a photoresist is applied on the metal layer 354, and the photoresist is exposed and developed to form a photoresist pattern PR. In this case, the photoresist pattern PR is formed to correspond to the region where the channel region of the active layer 340 is to be formed.
다음, 도 11d를 참조하면, 포토레지스트 패턴(PR)을 마스크로 하여 상기 금속층(354)을 식각하여 게이트 전극(360)을 형성한다. 이때, 상기 금속층(360)은 해당 재료를 식각할 수 있는 식각액을 이용하여 습식 식각(wet etching)법으로 식각한다. Next, referring to FIG. 11D, the gate electrode 360 is formed by etching the metal layer 354 using the photoresist pattern PR as a mask. In this case, the metal layer 360 is etched by wet etching using an etchant capable of etching the material.
다음, 도 11e를 참조하면, 포토레지스트 패턴(PR)을 이용하여 절연층(352)을 식각하여 게이트 절연막(350)을 형성한다. 이때, 절연층(352)은 아르곤(Ar) 등의 가스를 이용한 플라즈마 식각 공정으로 식각되고, 절연층(352)의 상부에 위치한 게이트 전극(360)을 따라 유사한 크기로 형성된다. 그리고, 플라즈마 식각 공정에서 절연층(352)이 다 식각되어 액티브층(340)이 노출되면, 액티브층(340)에 일정 시간 식각 공정을 수행하여 액티브층(340)을 도체화한다. 즉, 액티브층(340)에 플라즈마 식각 공정이 수행되면, 액티브층(340) 내의 산소가 빠져나가고 불순물이 주입되어 도전 특성이 향상된다. 따라서, 게이트 전극(360) 및 게이트 절연막(350)이 위치한 영역과 대응되는 액티브층(340)의 채널 영역(CH)이 형성되고, 액티브층(340)의 채널 영역(CH)을 제외한 도체화 영역(CP)이 형성된다. 따라서, 게이트 전극(360), 게이트 절연막(350)은 유사한 크기로 액티브층(340)의 채널 영역(CH) 상에 형성된다. 이후, 포토레지스트 패턴(PR)을 스트립하여 제거한다. Next, referring to FIG. 11E, the insulating layer 352 is etched using the photoresist pattern PR to form the gate insulating layer 350. In this case, the insulating layer 352 is etched by a plasma etching process using a gas such as argon (Ar), and is formed in a similar size along the gate electrode 360 positioned on the insulating layer 352. When the insulating layer 352 is etched and the active layer 340 is exposed in the plasma etching process, the active layer 340 is conductive by performing a predetermined time etching process on the active layer 340. That is, when the plasma etching process is performed on the active layer 340, oxygen in the active layer 340 is released and impurities are injected to improve conductivity. Accordingly, the channel region CH of the active layer 340 corresponding to the region where the gate electrode 360 and the gate insulating layer 350 are located is formed, and the conductive region except for the channel region CH of the active layer 340 is formed. (CP) is formed. Therefore, the gate electrode 360 and the gate insulating film 350 are formed on the channel region CH of the active layer 340 in a similar size. Thereafter, the photoresist pattern PR is stripped and removed.
다음, 도 11f를 참조하면, 게이트 전극(360)이 형성된 기판(310) 상에 CVD, PECVD 또는 스퍼터링 증착 방법으로 실리콘 산화물(SiOx) 또는 실리콘 질화물(SiNx)을 증착하여 층간 절연막(370)을 형성한다. Next, referring to FIG. 11F, an interlayer insulating layer 370 is formed by depositing silicon oxide (SiOx) or silicon nitride (SiNx) on a substrate 310 on which the gate electrode 360 is formed by CVD, PECVD, or sputtering deposition. do.
이어, 도 11g를 참조하면, 그리고, 층간 절연막(370)을 식각하여 액티브층(340)의 양측 일부인 도체화 영역(CP)을 노출하는 콘택홀들(375a, 375b)을 형성한다. 그리고, 기판(310) 상에 몰리브덴(Mo), 알루미늄(Al), 크롬(Cr), 금(Au), 티타늄(Ti), 니켈(Ni), 네오디뮴(Nd) 및 구리(Cu)로 이루어진 군에서 선택된 어느 하나 또는 이들의 합금을 적층하고 패터닝하여 소스 전극(380a)과 드레인 전극(380b)을 형성한다. 이때, 소스 전극(380a)과 드레인 전극(380b)은 층간 절연막(370)에 형성된 콘택홀들(375a, 375b)을 통해 액티브층(340)에 각각 연결된다. 따라서, 하부 액티브층(342)과 중간층(344)을 포함하는 액티브층(340), 게이트 전극(360), 소스 전극(380a) 및 드레인 전극(380b)을 포함하는 박막트랜지스터(TFT)가 형성된다.Subsequently, referring to FIG. 11G, the interlayer insulating layer 370 is etched to form contact holes 375a and 375b exposing the conductive region CP, which is part of both sides of the active layer 340. The group of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) on the substrate 310. The source electrode 380a and the drain electrode 380b are formed by stacking and patterning any one or an alloy thereof. In this case, the source electrode 380a and the drain electrode 380b are connected to the active layer 340 through the contact holes 375a and 375b formed in the interlayer insulating layer 370, respectively. Accordingly, a thin film transistor TFT including an active layer 340 including a lower active layer 342 and an intermediate layer 344, a gate electrode 360, a source electrode 380a, and a drain electrode 380b is formed. .
마지막으로, 도 11h를 참조하면, 박막트랜지스터(TFT)가 형성된 기판(310) 상에 CVD, PECVD 또는 스퍼터링 증착 방법으로 실리콘 산화물(SiOx) 또는 실리콘 질화물(SiNx)을 증착하여 패시베이션막(385)을 형성한다. 그리고, 패시베이션막(385)을 식각하여 드레인 전극(385b)의 일부를 노출하는 비어홀(387)을 형성한다. 그리고, 기판(310) 상에 ITO, IZO, ITZO, ZnO 등을 적층하고 패터닝하여 화소 전극(390)을 형성한다. 따라서, 본 발명의 제3 실시예에 따른 박막트랜지스터 어레이 기판이 제조된다.Finally, referring to FIG. 11H, the passivation film 385 is formed by depositing silicon oxide (SiOx) or silicon nitride (SiNx) on the substrate 310 on which the thin film transistor (TFT) is formed by CVD, PECVD, or sputtering deposition. Form. The passivation film 385 is etched to form a via hole 387 exposing a part of the drain electrode 385b. The ITO, IZO, ITZO, ZnO, and the like are stacked and patterned on the substrate 310 to form the pixel electrode 390. Accordingly, the thin film transistor array substrate according to the third embodiment of the present invention is manufactured.
도 12a 내지 도 12f는 본 발명의 제4 실시예에 따른 박막트랜지스터 어레이 기판의 제조방법을 공정별로 나타낸 도면이다.12A to 12F are diagrams illustrating processes of manufacturing a thin film transistor array substrate according to a fourth embodiment of the present invention.
도 12a를 참조하면, 투명하거나 불투명한 유리, 플라스틱 또는 금속으로 이루어지며 평탄도가 유지되는 기판(410) 상에 카본 블랙 등의 흑색을 나타내는 재료를 포함하는 수지 또는 비정질 실리콘(a-Si), 게르마늄(Ge), 산화탄탈륨(TaOx), 산화구리(CuOx) 등의 반도체 계열의 재료를 형성하고 마스크를 이용하여 패터닝하여 차광막(420)을 형성한다. 차광막(420)은 추후 액티브층이 형성될 영역마다 형성된다. 그러나, 본 발명에서는 이에 한정되지 않으며, 차광막(420)이 기판(410) 전면에 형성될 수도 있다.Referring to FIG. 12A, a resin or amorphous silicon (a-Si) including a material showing black, such as carbon black, is formed on a substrate 410 made of transparent or opaque glass, plastic, or metal, and having flatness maintained. Semiconductor-based materials such as germanium (Ge), tantalum oxide (TaOx), and copper oxide (CuOx) are formed and patterned using a mask to form a light shielding film 420. The light blocking film 420 is formed for each region where an active layer will be formed later. However, the present invention is not limited thereto, and the light blocking film 420 may be formed on the entire surface of the substrate 410.
이어, 차광막(420)이 형성된 기판(410) 상에 CVD(Chemical Vapor Deposition), PECVD(Plasma Enhanced Chemical Vapor Deposition), 스퍼터링(sputtering) 증착 방법으로 실리콘 산화물(SiOx) 또는 실리콘 질화물(SiNx)을 증착하여 버퍼층(430)을 형성한다. 그리고, 버퍼층(430)이 형성된 기판(410) 상에 인듐산화물(In2O3), 주석산화물(SnO) 및 아연산화물(ZnO)의 복합체 타겟을 이용하여 스퍼터링(sputtering) 방법으로 산화물 반도체층을 적층한다. 이어, 마스크를 이용하여 산화물 반도체층을 패터닝하여 액티브층(440)을 형성한다. 액티브층(440)은 이외에도 화학기상증착이나 원자증착(Atomic Layer Deposition; ALD) 등의 화학적 증착방법을 이용하여 형성할 수도 있다. 이때, 액티브층(440)은 기판(410) 상에 형성된 차광막(420)에 대응되도록 형성하여, 하부로부터 입사되는 광이 액티브층(440)에 도달하지 못하도록 하여 광에 의한 누설전류가 발생하는 것을 방지한다.Subsequently, silicon oxide (SiOx) or silicon nitride (SiNx) is deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or sputtering deposition on the substrate 410 on which the light shielding film 420 is formed. The buffer layer 430 is formed. The oxide semiconductor layer is sputtered onto the substrate 410 on which the buffer layer 430 is formed by using a composite target of indium oxide (In 2 O 3 ), tin oxide (SnO), and zinc oxide (ZnO). Laminated. Subsequently, the oxide semiconductor layer is patterned using a mask to form the active layer 440. In addition, the active layer 440 may be formed using a chemical vapor deposition method such as chemical vapor deposition or atomic layer deposition (ALD). At this time, the active layer 440 is formed to correspond to the light shielding film 420 formed on the substrate 410, so that light incident from the bottom does not reach the active layer 440 to prevent leakage current caused by light. prevent.
다음 도 12b를 참조하면, 액티브층(440)이 형성된 기판(410) 상에 CVD, PECVD 증착 방법으로 실리콘 산화물(SiOx) 또는 실리콘 질화물(SiNx)을 증착하여 산화물층(447)과 절연층(452)을 형성한다. 산화물층(447)은 액티브층(440)의 표면에 형성되는데, 절연층(452)을 형성하는 CVD 공정에서 아르곤(Ar)과 산소(O) 가스를 조절하면 액티브층의 물질들과 실리콘이 혼합되어 형성될 수 있다. Next, referring to FIG. 12B, an oxide layer 447 and an insulating layer 452 are deposited by depositing silicon oxide (SiOx) or silicon nitride (SiNx) on the substrate 410 on which the active layer 440 is formed by CVD and PECVD deposition methods. ). The oxide layer 447 is formed on the surface of the active layer 440. When the argon (Ar) and oxygen (O) gases are controlled in the CVD process of forming the insulating layer 452, the materials of the active layer and silicon are mixed. Can be formed.
이어, 도 12c를 참조하면, 절연층(452) 상에 스퍼터링 증착방법으로 구리(Cu), 몰리브덴(Mo), 알루미늄(Al), 크롬(Cr), 금(Au), 티타늄(Ti), 니켈(Ni), 네오디뮴(Nd), 탄탈륨(Ta) 및 텅스텐(W)로 이루어진 군에서 선택된 어느 하나 또는 이들의 합금을 증착하여 금속층(462)을 형성한다. Next, referring to FIG. 12C, copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), and nickel are used as a sputtering deposition method on the insulating layer 452. (Ni), neodymium (Nd), tantalum (Ta), and tungsten (W) any one selected from the group consisting of or alloys thereof are deposited to form a metal layer 462.
다음 도 12d를 참조하면, 금속층(462) 상에 포토레지스트(photoresist)를 도포하고 이를 노광 및 현상하여 포토레지스트 패턴을 형성하고, 포토레지스트 패턴을 마스크로 하여 상기 금속층(462)을 식각하여 게이트 전극(460)을 형성한다. 이때, 상기 금속층(462)은 해당 재료를 식각할 수 있는 식각액을 이용하여 습식 식각(wet etching)법으로 식각한다. Next, referring to FIG. 12D, a photoresist is applied on the metal layer 462, exposed and developed to form a photoresist pattern, and the metal layer 462 is etched using the photoresist pattern as a mask to form a gate electrode. 460 is formed. In this case, the metal layer 462 is etched by wet etching using an etchant capable of etching the material.
다음, 도 12e를 참조하면, 게이트 전극(460)을 이용하여 절연층(452)을 식각하여 게이트 절연막(450)을 형성한다. 이때, 절연층(452)은 아르곤(Ar) 등의 가스를 이용한 플라즈마 식각 공정으로 식각되고, 절연층(452)의 상부에 위치한 게이트 전극(460)을 따라 유사한 크기로 형성된다. 그리고, 플라즈마 식각 공정에서 절연층(452)이 다 식각되면 산화물층(447)과 액티브층(440)이 노출되면, 산화물층(447)과 액티브층(440)에 일정 시간 식각 공정을 수행하여 액티브층(440)을 도체화한다. 즉, 액티브층(440)에 플라즈마 식각 공정이 수행되면, 액티브층(440) 내의 산소가 빠져나가고 불순물이 주입되어 도전 특성이 향상된다. 따라서, 게이트 전극(460) 및 게이트 절연막(450)이 위치한 영역과 대응되는 액티브층(440)의 채널 영역(CH)이 형성되고, 액티브층(440)의 채널 영역(CH)을 제외한 도체화 영역(CP)이 형성된다. 그리고, 게이트 절연막(450)에 의해 노출된 산화물층(447)을 식각하여 중간층(445)을 형성한다. 따라서, 게이트 전극(460), 게이트 절연막(450) 및 중간층(445)은 유사한 크기로 액티브층(440)의 채널 영역(CH) 상에 형성된다.Next, referring to FIG. 12E, the insulating layer 452 is etched using the gate electrode 460 to form the gate insulating layer 450. In this case, the insulating layer 452 is etched by a plasma etching process using a gas such as argon (Ar), and is formed in a similar size along the gate electrode 460 disposed on the insulating layer 452. When the insulating layer 452 is etched in the plasma etching process, when the oxide layer 447 and the active layer 440 are exposed, the oxide layer 447 and the active layer 440 are etched for a predetermined time to be active. Conduct layer 440. That is, when the plasma etching process is performed on the active layer 440, oxygen in the active layer 440 is released and impurities are injected to improve conductivity. Accordingly, the channel region CH of the active layer 440 corresponding to the region where the gate electrode 460 and the gate insulating layer 450 are located is formed, and the conductive region except for the channel region CH of the active layer 440 is formed. (CP) is formed. The oxide layer 447 exposed by the gate insulating layer 450 is etched to form an intermediate layer 445. Accordingly, the gate electrode 460, the gate insulating layer 450, and the intermediate layer 445 are formed on the channel region CH of the active layer 440 in a similar size.
다음, 도 12f를 참조하면, 게이트 전극(460)이 형성된 기판(410) 상에 CVD, PECVD 또는 스퍼터링 증착 방법으로 실리콘 산화물(SiOx) 또는 실리콘 질화물(SiNx)을 증착하여 층간 절연막(470)을 형성한다. 그리고, 층간 절연막(470)을 식각하여 액티브층(440)의 양측 일부인 도체화 영역(CP)을 노출하는 콘택홀들(475a, 475b)을 형성한다. 그리고, 기판(410) 상에 몰리브덴(Mo), 알루미늄(Al), 크롬(Cr), 금(Au), 티타늄(Ti), 니켈(Ni), 네오디뮴(Nd) 및 구리(Cu)로 이루어진 군에서 선택된 어느 하나 또는 이들의 합금을 적층하고 패터닝하여 소스 전극(480a)과 드레인 전극(480b)을 형성한다. 이때, 소스 전극(480a)과 드레인 전극(480b)은 층간 절연막(470)에 형성된 콘택홀들(475a, 475b)을 통해 액티브층(440)에 각각 연결된다. 따라서, 액티브층(440), 중간층(445), 게이트 전극(460), 소스 전극(480a) 및 드레인 전극(480b)을 포함하는 박막트랜지스터(TFT)가 형성된다.Next, referring to FIG. 12F, an interlayer insulating layer 470 is formed by depositing silicon oxide (SiOx) or silicon nitride (SiNx) on a substrate 410 on which the gate electrode 460 is formed by CVD, PECVD, or sputter deposition. do. The interlayer insulating layer 470 is etched to form contact holes 475a and 475b exposing the conductive region CP, which is a part of both sides of the active layer 440. And, on the substrate 410, a group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) The source electrode 480a and the drain electrode 480b are formed by stacking and patterning any one or an alloy thereof. In this case, the source electrode 480a and the drain electrode 480b are connected to the active layer 440 through the contact holes 475a and 475b formed in the interlayer insulating layer 470, respectively. Accordingly, a thin film transistor TFT including an active layer 440, an intermediate layer 445, a gate electrode 460, a source electrode 480a, and a drain electrode 480b is formed.
한편, 도 13은 본 발명의 제1 실시예에 따라 제조된 박막트랜지스터의 후방 산란 분석법을 통한 결과를 나타낸 그래프이고, 도 14는 본 발명의 제3 실시예에 따라 제조된 박막트랜지스터의 후방 산란 분석법을 통한 결과를 나타낸 그래프이다.On the other hand, Figure 13 is a graph showing the results through the back scattering analysis method of the thin film transistor prepared according to the first embodiment of the present invention, Figure 14 is a back scattering analysis method of the thin film transistor prepared according to the third embodiment of the present invention It is a graph showing the result through.
도 13을 참조하면, 액티브층, 중간층 및 게이트 절연막의 적층 구조를 후방 산란 분석법(Rutherford Backscattering Spectrometry, RBS)으로 분석해본 바, 모두 4족 원소인 실리콘(Si)이 포함되어 있었다. 또한, 도 14를 참조하면, 하부 액티브층과 중간층을 포함하는 액티브층, 게이트 절연막의 적층 구조도 모두 4족 원소인 실리콘(Si)이 포함되어 있었다. 이 4족 원소의 존재는 4족 원소의 결합이 강한 공유 결합을 형성해, 금속 비결합 상태를 줄이며 열적으로 보다 안정적인 특성을 가지는 것을 의미한다. 따라서, 후속 공정에서 올 수 있는 원자 확산을 방지할 수 있다. 특히, 실리콘(Si)은 층 내의 아연의 원자비율 대비 50 내지 200%의 비율로 존재할 수 있다.Referring to FIG. 13, a stacked structure of an active layer, an intermediate layer, and a gate insulating layer was analyzed by a backscattering spectrometry (RBS), and all of silicon (Si), which is a Group 4 element, was included. Referring to FIG. 14, silicon (Si), which is a Group 4 element, was also included in the stacked structure of the active layer including the lower active layer and the intermediate layer and the gate insulating layer. The presence of this Group 4 element means that the bond of Group 4 element forms a strong covalent bond, which reduces the metal non-bonding state and has more thermally stable characteristics. Thus, it is possible to prevent atomic diffusion that may come in subsequent processes. In particular, silicon (Si) may be present in a ratio of 50 to 200% relative to the atomic ratio of zinc in the layer.
이하, 본 발명의 박막트랜지스터에 관하여 하기 실시예에서 상술하기로 한다. 다만, 하기에 개시되는 실시예는 본 발명의 일 실시예일 뿐 본 발명이 하기의 실시예에 한정되는 것은 아니다.Hereinafter, the thin film transistor of the present invention will be described in detail in the following examples. However, the embodiment disclosed below is only one embodiment of the present invention and the present invention is not limited to the following embodiments.
실험 1 : 코플라나 박막트랜지스터Experiment 1: Coplana Thin Film Transistor
<비교예 1>Comparative Example 1
유리 기판 상에 SiO2의 버퍼층을 형성하고, 버퍼층 상에 In1Ga1Zn1O4의 원자비로 이루어진 액티브층을 형성하고, 액티브층 상에 SiO2의 게이트 절연막을 형성하였다. 게이트 절연막 상에 몰리브덴으로 게이트 전극을 형성하고, SiO2의 층간 절연막을 형성한 다음, 알루미늄으로 소스 전극과 드레인 전극을 형성하여 박막트랜지스터를 제조하였다.A buffer layer of SiO 2 was formed on the glass substrate, an active layer consisting of an atomic ratio of In 1 Ga 1 Zn 1 O 4 was formed on the buffer layer, and a gate insulating film of SiO 2 was formed on the active layer. A gate electrode was formed of molybdenum on the gate insulating film, an interlayer insulating film of SiO 2 was formed, and a source electrode and a drain electrode were formed of aluminum to prepare a thin film transistor.
<비교예 2>Comparative Example 2
전술한 비교예 1과 동일한 공정 조건 하에, 액티브층과 게이트 절연막 사이에 In1 . 3Ga1Zn1Si0 . 4O5의 원자비로 이루어진 중간층을 30Å의 두께로 스퍼터링하여 형성한 것만을 달리하여 박막트랜지스터를 제조하였다. Under the same process conditions as those of Comparative Example 1 described above, In 1 . 3 Ga 1 Zn 1 Si 0 . The thin film transistor was manufactured by changing only the intermediate layer formed by sputtering to an thickness of 30 kPa having an atomic ratio of 4 O 5 .
<비교예 3>Comparative Example 3
전술한 비교예 1과 동일한 공정 조건 하에, 액티브층과 게이트 절연막 사이에 In0 . 9Ga1Zn1Si2 . 5O9의 원자비로 이루어진 중간층을 90Å의 두께로 스퍼터링하여 형성한 것만을 달리하여 박막트랜지스터를 제조하였다. Under the same process conditions as those of Comparative Example 1 described above, In 0 . 9 Ga 1 Zn 1 Si 2 . The thin film transistor was manufactured by changing only the intermediate layer formed by sputtering to an thickness of 90 kPa having an atomic ratio of 5 O 9 .
<실시예 1><Example 1>
전술한 비교예 1과 동일한 공정 조건 하에, 액티브층과 게이트 절연막 사이에 In1 . 1Ga1Zn1Si0 . 9O7 .8의 원자비로 이루어진 중간층을 60Å의 두께로 스퍼터링하여 형성한 것만을 달리하여 박막트랜지스터를 제조하였다. Under the same process conditions as those of Comparative Example 1 described above, In 1 . 1 Ga 1 Zn 1 Si 0 . 9 O by an intermediate layer consisting of an atomic ratio of 0.8 7 different only formed by sputtering to a thickness of 60Å to prepare a thin film transistor.
전술한 비교예 1, 2, 3 및 실시예 1에 따라 제조된 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류를 측정하여 도 15 내지 도 18에 각각 나타내었다. 도 15는 비교예 1에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프이고, 도 16은 비교예 2에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프이며, 도 17은 비교예 3에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프이고, 도 18은 본 발명의 실시예 1에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프이다. 또한, 전술한 비교예 1과 실시예 1에 따른 박막트랜지스터의 문턱전압, 기울기 및 전하 이동도를 측정하여 하기 표 2에 나타내었다.Drain currents for the gate-source voltages of the thin film transistors manufactured according to Comparative Examples 1, 2, 3, and Example 1 were measured and shown in FIGS. 15 to 18, respectively. FIG. 15 is a graph illustrating drain current curves of a gate-source voltage of a thin film transistor according to Comparative Example 1, and FIG. 16 is a graph illustrating drain current curves of a gate-source voltage of a thin film transistor according to Comparative Example 2; FIG. 17 is a graph illustrating drain current curves of a gate-source voltage of a thin film transistor according to Comparative Example 3, and FIG. 18 illustrates a drain current curve of gate-source voltage of a thin film transistor according to Example 1 of the present invention. It is a graph. In addition, the threshold voltage, slope, and charge mobility of the thin film transistors according to Comparative Example 1 and Example 1 were measured and shown in Table 2 below.
비교예 1Comparative Example 1 실시예 1Example 1
문턱전압(V)Threshold Voltage (V) 4.24.2 0.070.07
기울기(V/dec)Slope (V / dec) 0.210.21 0.110.11
전하 이동도(㎠/Vs)Charge mobility (㎠ / Vs) 4.44.4 1010
도 15를 참조하면, 중간층이 존재하지 않는 비교예 1은 게이트-소스 전압이 포지티브쪽으로 이동되었고, 문턱전압이 4.2V, 기울기가 0.21 및 전하 이동도가 4.4㎠/Vs로 나타났다. 또한, 도 16을 참조하면, 중간층이 In1 . 3Ga1Zn1Si0 . 4O5의 원자비로 30Å의 두께로 형성된 비교예 2는 게이트-소스 전압이 네거티브쪽으로 이동되었다. 또한 도 17을 참조하면, 중간층이 In0 . 9Ga1Zn1Si2 . 5O9의 원자비로 90Å의 두께로 형성된 비교예 3은 소자 구동 시 구동전압(Vds)이 0.1V와 10V 사이에 전류-전압 곡선이 교차되는 현상이 심하게 발생하며 소자의 채널층이 균일하지 않게 형성되었다는 것을 알 수 있다. 반면, 표 2와 도 18을 참조하면, 중간층이 In1 . 1Ga1Zn1Si0 . 9O7 .8의 원자비로 60Å의 두께로 형성된 실시예 1은 문턱전압이 -0.07V이고 전하 이동도도 10㎠/Vs이며, 기울기가 0.11으로 나타나, 박막트랜지스터의 특성이 현저히 향상되었다. Referring to FIG. 15, in Comparative Example 1 having no intermediate layer, the gate-source voltage was shifted to the positive side, and the threshold voltage was 4.2V, the slope was 0.21, and the charge mobility was 4.4 cm 2 / Vs. 16, the intermediate layer is In 1 . 3 Ga 1 Zn 1 Si 0 . In Comparative Example 2, which had a thickness of 30 mA with an atomic ratio of 4 O 5, the gate-source voltage was shifted toward the negative side. Referring also to Figure 17, the intermediate layer is In 0 . 9 Ga 1 Zn 1 Si 2 . In Comparative Example 3, which has a thickness of 90 로 with an atomic ratio of 5 O 9 , a phenomenon in which the driving voltage Vds crosses the current-voltage curve between 0.1 V and 10 V occurs when the device is driven, and the channel layer of the device is not uniform. It can be seen that it is not formed. On the other hand, referring to Table 2 and Figure 18, the intermediate layer is In 1 . 1 Ga 1 Zn 1 Si 0 . Embodiment 9 O 7 formed in an atomic ratio of 0.8 to a thickness of 60Å Example 1, the threshold voltage is -0.07V and the charge carrier mobility is also 10㎠ / Vs, the slope is indicated by 0.11, was improved remarkably the characteristics of the thin film transistor.
실험 2 : 에치 스토퍼 박막트랜지스터Experiment 2: etch stopper thin film transistor
<비교예 4><Comparative Example 4>
유리 기판 상에 몰리브덴으로 게이트 전극을 형성하고, SiO2의 게이트 절연막을 형성하였다. 그리고, In1Ga1Zn1O4의 원자비로 이루어진 액티브층을 형성하고, 액티브층 상에 SiO2의 에치 스토퍼를 형성하였다. 다음, 알루미늄으로 소스 전극과 드레인 전극을 형성하여 박막트랜지스터를 제조하였다.A gate electrode was formed of molybdenum on the glass substrate, and a gate insulating film of SiO 2 was formed. Then, an active layer composed of an atomic ratio of In 1 Ga 1 Zn 1 O 4 was formed, and an etch stopper of SiO 2 was formed on the active layer. Next, a thin film transistor was manufactured by forming a source electrode and a drain electrode from aluminum.
<실시예 2><Example 2>
전술한 비교예 4와 동일한 공정 조건 하에, 액티브층과 게이트 절연막 사이에 In1 . 1Ga1Zn1Si0 . 9O7 .8의 원자비로 이루어진 중간층을 60Å의 두께로 스퍼터링하여 형성한 것만을 달리하여 박막트랜지스터를 제조하였다. Under the same process conditions as those of Comparative Example 4 described above, In 1 . 1 Ga 1 Zn 1 Si 0 . 9 O by an intermediate layer consisting of an atomic ratio of 0.8 7 different only formed by sputtering to a thickness of 60Å to prepare a thin film transistor.
전술한 비교예 4 및 실시예 2에 따라 제조된 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류를 측정하여 도 19 및 도 20에 각각 나타내었다. 도 19는 비교예 4에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프이고, 도 20은 본 발명의 실시예 2에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프이다. 또한, 전술한 비교예 4과 실시예 2에 따른 박막트랜지스터의 문턱전압, 기울기 및 전하 이동도를 측정하여 하기 표 3에 나타내었다.Drain currents for the gate-source voltages of the thin film transistors manufactured according to Comparative Example 4 and Example 2 were measured and shown in FIGS. 19 and 20, respectively. FIG. 19 is a graph illustrating drain current curves of gate-source voltages of a thin film transistor according to Comparative Example 4, and FIG. 20 illustrates drain current curves of gate-source voltages of a thin film transistor according to Example 2 of the present invention. It is a graph. In addition, the threshold voltage, the slope and the charge mobility of the thin film transistors according to Comparative Example 4 and Example 2 were measured and shown in Table 3 below.
비교예 4Comparative Example 4 실시예 2Example 2
문턱전압(V)Threshold Voltage (V) 8.198.19 0.60.6
기울기(V/dec)Slope (V / dec) 0.390.39 0.30.3
전하 이동도(㎠/Vs)Charge mobility (㎠ / Vs) 8.18.1 10.110.1
도 19, 20 및 표 3을 참조하면, 중간층이 존재하지 않는 비교예 4는 문턱전압이 8.19V, 기울기가 0.39 및 전하 이동도가 8.1㎠/Vs로 나타났다. 반면, 중간층이 In1 . 1Ga1Zn1Si0 . 9O7 .8의 원자비로 60Å의 두께로 형성된 실시예 2는 문턱전압이 0.6V이고 전하 이동도도 10.1㎠/Vs이며, 기울기가 0.3으로 나타나, 박막트랜지스터의 특성이 현저히 향상되었다.Referring to FIGS. 19, 20 and Table 3, in Comparative Example 4 in which the intermediate layer does not exist, the threshold voltage was 8.19 V, the slope was 0.39, and the charge mobility was 8.1 cm 2 / Vs. In contrast, the middle layer is In 1 . 1 Ga 1 Zn 1 Si 0 . Embodiment 9 O 7 formed in an atomic ratio of 0.8 to a thickness of 60Å Example 2, the threshold voltage is 0.6V and the charge carrier mobility is also 10.1㎠ / Vs, the slope is indicated as 0.3, was improved remarkably the characteristics of the thin film transistor.
실험 3 : 2층 액티브층 코플라나 박막트랜지스터Experiment 3: 2-layer active layer coplanar thin film transistor
<비교예 5> Comparative Example 5
유리 기판 상에 SiO2의 버퍼층을 형성하고, 버퍼층 상에 In4Ga1Zn3O16 .5의 원자비로 이루어진 하부 액티브층을 240Å의 두께로 형성하고, 하부 액티브층 상에 Si10In5Ga1Zn1O35의 원자비로 이루어진 중간층을 40Å의 두께로 형성하여 액티브층을 형성하였다. 액티브층 상에 SiO2의 게이트 절연막을 형성하고 게이트 절연막 상에 몰리브덴으로 게이트 전극을 형성하고, SiO2의 층간 절연막을 형성한 다음, 알루미늄으로 소스 전극과 드레인 전극을 형성하여 박막트랜지스터를 제조하였다.A buffer layer of SiO 2 was formed on the glass substrate, a lower active layer having an atomic ratio of In 4 Ga 1 Zn 3 O 16 .5 was formed on the buffer layer to a thickness of 240 Å, and Si 10 In 5 was formed on the lower active layer. An intermediate layer consisting of an atomic ratio of Ga 1 Zn 1 O 35 was formed to a thickness of 40 GPa to form an active layer. A gate insulating film of SiO 2 was formed on the active layer, a gate electrode was formed of molybdenum on the gate insulating film, an interlayer insulating film of SiO 2 was formed, and a source electrode and a drain electrode were formed of aluminum to prepare a thin film transistor.
<비교예 6>Comparative Example 6
전술한 비교예 5와 동일한 공정 조건 하에, Si15In5Ga1Zn1O35의 원자비로 이루어진 중간층을 120Å의 두께로 형성하여 액티브층을 형성한 것만을 달리하여 박막트랜지스터를 제조하였다. Under the same process conditions as those of Comparative Example 5 described above, a thin film transistor was manufactured by only forming an intermediate layer having an atomic ratio of Si 15 In 5 Ga 1 Zn 1 O 35 to a thickness of 120 GPa to form an active layer.
<실시예 3><Example 3>
전술한 비교예 5와 동일한 공정 조건 하에, Si12 . 5In5Ga1Zn1O35의 원자비로 이루어진 중간층을 70Å의 두께로 형성하여 액티브층을 형성한 것만을 달리하여 박막트랜지스터를 제조하였다. Under the same process conditions as those of Comparative Example 5 described above, Si 12 . A thin film transistor was manufactured by forming an intermediate layer having an atomic ratio of 5 In 5 Ga 1 Zn 1 O 35 to a thickness of 70 kHz, except that only an active layer was formed.
전술한 비교예 5, 6 및 실시예 3에 따라 제조된 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류를 측정하여 도 21 내지 도 23에 각각 나타내었다. 도 21은 비교예 5에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프이고, 도 22는 비교예 6에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프이며, 도 23은 실시예 3에 따른 박막트랜지스터의 게이트-소스 전압에 대한 드레인 전류 곡선을 나타낸 그래프이다. 또한, 전술한 실시예 3에 따른 박막트랜지스터의 문턱전압, 전류 변화율, 전하 이동도, 포지티브 바이어스 템퍼라처 스트레스(positive bias temperature stress, PBTS), 커런트 스트레스(Current stress, CS) 및 네거티브 바이어스 템퍼라처 스트레스(negative bias temperature stress, NBTS)를 측정하여 하기 표 4에 나타내었고, 전류 변화율을 측정하여 도 24에 나타내었다.Drain currents for the gate-source voltages of the thin film transistors manufactured according to Comparative Examples 5, 6, and 3 described above were measured and shown in FIGS. 21 to 23, respectively. FIG. 21 is a graph illustrating drain current curves of a gate-source voltage of a thin film transistor according to Comparative Example 5, and FIG. 22 is a graph illustrating drain current curves of a gate-source voltage of a thin film transistor according to Comparative Example 6. FIG. 23 is a graph illustrating drain current curves of a gate-source voltage of a thin film transistor according to Example 3. FIG. In addition, the threshold voltage, current change rate, charge mobility, positive bias temperature stress (PBTS), current stress (CS), and negative bias temperature stress of the thin film transistor according to the third embodiment described above. (negative bias temperature stress, NBTS) was measured and shown in Table 4 below, and the rate of change of the current was measured and shown in FIG.
실시예 3Example 3
문턱전압(V)Threshold Voltage (V) -0.1-0.1
전류 변화율(@860nA)Current rate of change (@ 860nA) 0.13%0.13%
전하 이동도(㎠/Vs)Charge mobility (㎠ / Vs) 28.428.4
PBTS(△Vth)PBTS (△ Vth) 0.80.8
CS(△Vgs)CS (△ Vgs) 0.10.1
NBTS((△Vth)NBTS ((△ Vth) -0.04-0.04
도 21을 참조하면, 중간층이 Si10In5Ga1Zn1O35의 원자비로 40Å의 두께로 형성된 비교예 5는 게이트-소스 전압의 산포가 커져 소자의 불균일이 심한 것으로 나타났다. 또한, 도 22를 참조하면, 중간층이 Si15In5Ga1Zn1O35의 원자비로 120Å의 두께로 형성된 비교예 6은 캐리어가 너무 많이 게이트가 컨트롤하지 못하는 것으로 나타났다. 반면, 표 4, 도 23과 24를 참조하면, 중간층이 Si12 . 5In5Ga1Zn1O35의 원자비로 70Å의 두께로 형성된 실시예 3은 문턱전압이 -0.1V이고, 전류 변화율이 0.13%이며, 전하 이동도가 28.4㎠/Vs이고, PBTS가 0.8V이고 NBTS가 -.0.04V이며 CS가 0.1V로 나타나 박막트랜지스터의 특성이 우수한 것으로 나타났다.Referring to FIG. 21, Comparative Example 5 having an intermediate layer having a thickness of 40 μs with an atomic ratio of Si 10 In 5 Ga 1 Zn 1 O 35 showed that the dispersion of the gate-source voltage was large, resulting in severe nonuniformity of the device. In addition, referring to FIG. 22, Comparative Example 6 in which the intermediate layer was formed to a thickness of 120 μs at an atomic ratio of Si 15 In 5 Ga 1 Zn 1 O 35 showed that the gates did not control too many carriers. On the other hand, referring to Table 4, Figures 23 and 24, the intermediate layer is Si 12 . Example 3 formed with a thickness of 70 kW with an atomic ratio of 5 In 5 Ga 1 Zn 1 O 35 , has a threshold voltage of -0.1 V, a current variation rate of 0.13%, a charge mobility of 28.4 cm 2 / Vs, and a PBTS of 0.8 V, NBTS is -.0.04V and CS is 0.1V, which shows the excellent characteristics of the thin film transistor.
실험 4 : 중간층의 조성과 두께에 따른 코플라나 박막트랜지스터Experiment 4: Coplanar Thin Film Transistor According to Composition and Thickness of Interlayer
<실시예 4> <Example 4>
유리 기판 상에 SiO2의 버퍼층을 형성하고, 버퍼층 상에 In4Ga1Zn3O16 .5의 원자비로 이루어진 액티브층을 240Å의 두께로 형성하고, 액티브층 상에 중간층을 50Å의 두께로 형성하였다. 중간층 상에 SiO2의 게이트 절연막을 형성하고 게이트 절연막 상에 몰리브덴으로 게이트 전극을 형성하고, SiO2의 층간 절연막을 형성한 다음, 알루미늄으로 소스 전극과 드레인 전극을 형성하여 박막트랜지스터를 제조하였다.A buffer layer of SiO 2 was formed on the glass substrate, an active layer consisting of an atomic ratio of In 4 Ga 1 Zn 3 O 16 .5 was formed on the buffer layer to a thickness of 240 μs, and an intermediate layer was formed to a thickness of 50 μs on the active layer. Formed. A gate insulating film of SiO 2 was formed on the intermediate layer, a gate electrode was formed of molybdenum on the gate insulating film, an interlayer insulating film of SiO 2 was formed, and a source electrode and a drain electrode were formed of aluminum to prepare a thin film transistor.
<비교예 7>Comparative Example 7
전술한 실시예 4와 동일한 공정 조건 하에, 중간층을 제외하고 박막트랜지스터를 제조하였다. Under the same process conditions as in Example 4, except for the intermediate layer, a thin film transistor was prepared.
실시예 4에 따라 제조된 박막트랜지스터에서, 중간층의 실리콘 함량에 따른 중간층 내의 과잉 산소 양을 측정하여 도 25에 나타내었고, 중간층의 수소 함량에 따른 중간층 내의 과잉 산소 양을 측정하고 그에 따른 포지티브 바이어스 템퍼라처 스트레스를 측정하여 도 26에 나타내었고, 중간층의 두께를 각각 50Å, 100Å, 150Å으로 달리한 후 트랜스커브, 문턱전압, 전하이동도 및 DIBL(Drain-Induced Barrier Lowering)을 측정하여 도 27에 나타내었다. 또한, 전술한 실시예 4 및 비교예 7에 따라 제조된 박막트랜지스터의 포지티브 바이어스 템퍼라처 스트레스를 측정하여 도 28에 나타내었다.In the thin film transistor prepared according to Example 4, the amount of excess oxygen in the intermediate layer according to the silicon content of the intermediate layer was shown in FIG. 25, and the amount of excess oxygen in the intermediate layer according to the hydrogen content of the intermediate layer was measured and thus the positive bias temper. The Razer stress is measured and shown in FIG. 26, and the thickness of the intermediate layer is changed to 50 kV, 100 kPa and 150 kPa, respectively, and the transcurve, threshold voltage, charge mobility and drain-induced barrier lowering (DIBL) are measured and shown in FIG. 27. It was. In addition, the positive bias temperature stress of the thin film transistors prepared according to Example 4 and Comparative Example 7 was measured and shown in FIG. 28.
도 25를 참조하면, 중간층의 실리콘 원소의 함량이 2.9 내지 3.2×1022㎝-3인 경우, 중간층 내의 과잉 산소의 양을 약 100%에 인접하게 나타난다. 중간층의 실리콘 원소의 함량이 줄어들면 과잉 산소의 양이 늘어나 포지티브 바이어스 템퍼라처 스트레스 열화가 나타나고, 중간층의 실리콘 원소의 함량이 늘어나면 과잉 산소의 양이 줄어들어 소자가 도체화되는 것으로 나타났다. 이 결과를 통해, 중간층의 실리콘 원소의 함량을 2.9 내지 3.2×1022㎝- 3로 형성하여, 포지티브 바이어스 템퍼라처 스트레스 열화와 소자의 도체화를 방지할 수 있음을 알 수 있다.Referring to FIG. 25, when the content of the silicon element in the intermediate layer is 2.9 to 3.2 × 10 22 cm −3 , the amount of excess oxygen in the intermediate layer appears to be about 100%. When the content of the silicon element in the middle layer is reduced, the amount of excess oxygen increases, resulting in positive bias temperature stress degradation, and when the content of the silicon element in the middle layer is increased, the amount of excess oxygen is reduced, resulting in the conductor. With this result, the content of the silicon element of the intermediate layer 2.9 to 3.2 × 10 22 ㎝ - it can be seen that it is possible to form a three, preventing the conductor screen of the positive bias tempering racheo stress deteriorates the element.
도 26을 참조하면, 중간층에서 과잉 산소의 양의 비율이 100.24%이고 과잉 산소의 양이 2.4×1020㎝- 3로 나타나는 경우, 과잉 산소의 양에 대응하는 수소 2.5×1020㎝-3를 첨가하였다. 중간층 내의 과잉 산소의 양은 변함이 없으나, 포지티브 바이어스 템퍼라처 스트레스가 0.35V에서 0.21V로 약 0.14V 감소하는 것으로 나타났다. 이 결과를 통해, 중간층의 과잉 산소의 양에 대응하는 수소의 양을 첨가하면, 과잉 산소의 양은 변함이 없으나 포지티브 바이어스 템퍼라처 스트레스를 개선할 수 있음을 알 수 있다. Referring to Figure 26, the 100.24% Volume ratio of the excess oxygen in the intermediate layer and the amount of excess oxygen 2.4 × 10 20 ㎝ - if indicated by 3, hydrogen 2.5 × 10 20 ㎝ -3 corresponding to the amount of excess oxygen Added. The amount of excess oxygen in the interlayer remained unchanged, but the positive bias temperture stress was found to decrease by about 0.14V from 0.35V to 0.21V. From this result, it can be seen that by adding the amount of hydrogen corresponding to the amount of excess oxygen in the intermediate layer, the amount of excess oxygen remains unchanged but the positive bias temperture stress can be improved.
도 27을 참조하면, 중간층의 두께가 50Å인 경우, 문턱전압이 0.35V이고, 전하이동도가 9.97㎠/vs이며, DIBL이 0.11V로 나타났다. 중간층의 두께가 100Å인 경우, 문턱전압이 0.56V이고, 전하이동도가 10.95㎠/vs이며, DIBL이 -0.02V로 나타났다. 중간층의 두께가 150Å인 경우, 문턱전압이 1.6V이고, 전하이동도가 6.25㎠/vs이며, DIBL이 -1.75V로 나타났다. 이 결과를 통해, 중간층의 두께가 100Å를 초과하면, 문턱전압이 증가하고 전하이동도가 감소되며 DIBL도 감소되는 것을 알 수 있다.Referring to FIG. 27, when the thickness of the intermediate layer was 50 mA, the threshold voltage was 0.35V, the charge mobility was 9.97 cm 2 / vs, and the DIBL was 0.11V. When the thickness of the intermediate layer was 100 Hz, the threshold voltage was 0.56V, the charge mobility was 10.95 cm 2 / vs, and the DIBL was -0.02V. When the thickness of the intermediate layer was 150 kV, the threshold voltage was 1.6V, the charge mobility was 6.25 cm 2 / vs, and the DIBL was -1.75V. From this result, it can be seen that when the thickness of the intermediate layer exceeds 100 mW, the threshold voltage increases, the charge mobility decreases, and the DIBL decreases.
도 28을 참조하면, 비교예 7에 따른 박막트랜지스터는 스트레스 시간이 증가함에 따라 포지티브 바이어스 템퍼라처 스트레스도 크게 증가하나, 실시예4에 따른 박막트랜지스터는 스트레스 시간이 증가함에 따라 포지티브 바이어스 템퍼라처 스트레스의 증가 정도고 비교예 7에 비해 현저히 작게 나타났다. 이 결과를 통해, 본 발명의 중간층을 구비한 박막트랜지스터는 포지티브 바이어스 템퍼라처 스트레스 열화를 저감할 수 있어 소자의 신뢰성을 향상시킬 수 있음을 알 수 있다.Referring to FIG. 28, the thin film transistor according to Comparative Example 7 significantly increases the positive bias temperature stress as the stress time increases, but the thin film transistor according to the fourth embodiment has a positive bias temperture stress as the stress time increases. The degree of increase was significantly smaller than that of Comparative Example 7. As a result, it can be seen that the thin film transistor including the intermediate layer of the present invention can reduce the positive bias temperature stress deterioration, thereby improving the reliability of the device.
전술한 바와 같이, 본 발명은 게이트 절연막과 액티브층 사이에 4족 원소를 포함하는 중간층을 구비함으로써, 열처리 공정에 의해 게이트 절연막의 수소나 산소 원자가 액티브층으로 확산되는 것을 방지하여 소자가 열화되는 것을 방지할 수 있는 이점이 있다. As described above, the present invention provides an intermediate layer containing a Group 4 element between the gate insulating film and the active layer, thereby preventing the element from deteriorating by preventing diffusion of hydrogen or oxygen atoms of the gate insulating film into the active layer by a heat treatment process. There is an advantage that can be prevented.
또한, 본 발명은 액티브층과 게이트 절연막 사이에 실리콘 원소를 포함하는 중간층을 형성하여, 과잉 산소로 인한 포지티브 바이어스 템퍼라처 스트레스 열화를 방지할 수 있다. 또한, 중간층에 남아있는 과잉 산소의 양에 대응하는 만큼의 수소를 포함하여 과잉 산소가 전자를 포집하는 것을 막아 포지티브 바이어스 템퍼라처 스트레스 열화를 방지할 수 있다.In addition, the present invention can form an intermediate layer containing a silicon element between the active layer and the gate insulating film, thereby preventing the positive bias temperature stress degradation due to excess oxygen. In addition, it is possible to prevent excess oxygen from trapping electrons by including hydrogen corresponding to the amount of excess oxygen remaining in the intermediate layer, thereby preventing the positive bias temperture stress degradation.
이상 첨부된 도면을 참조하여 본 발명의 실시예를 설명하였지만, 상술한 본 발명의 기술적 구성은 본 발명이 속하는 기술 분야의 당업자가 본 발명의 그 기술적 사상이나 필수적 특징을 변경하지 않고서 다른 구체적인 형태로 실시될 수 있다는 것을 이해할 수 있을 것이다. 그러므로 이상에서 기술한 실시 예들은 모든 면에서 예시적인 것이며 한정적인 것이 아닌 것으로서 이해되어야 한다. 아울러, 본 발명의 범위는 상기 상세한 설명보다는 후술하는 특허청구범위에 의하여 나타내어진다. 또한, 특허청구범위의 의미 및 범위 그리고 그 등가 개념으로부터 도출되는 모든 변경 또는 변형된 형태가 본 발명의 범위에 포함되는 것으로 해석되어야 한다.Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above may be modified in other specific forms by those skilled in the art to which the present invention pertains without changing its technical spirit or essential features. It will be appreciated that it may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.
본 발명은 유기발광표시장치, 액정표시장치, 전기영동표시장치, 무기발광표시장치 등의 각종 표시장치에 적용될 수 있으며, TV, 모바일기기, 모니터, 스마트기기 등에 적용할 수 있다. 그러나, 본 발명은 이에 한정되지 않으며 영상을 표시할 수 있는 장치라면 어디에도 적용가능하다.The present invention can be applied to various display devices such as an organic light emitting display device, a liquid crystal display device, an electrophoretic display device, an inorganic light emitting display device, and can be applied to a TV, a mobile device, a monitor, a smart device, and the like. However, the present invention is not limited thereto and may be applied to any device capable of displaying an image.

Claims (16)

  1. 기판;Board;
    상기 기판 상에 위치하는 액티브층;An active layer on the substrate;
    상기 액티브층 상에 위치하는 게이트 절연막;A gate insulating layer on the active layer;
    상기 게이트 절연막 상에 위치하는 게이트 전극;A gate electrode on the gate insulating layer;
    상기 게이트 전극 상에 위치하는 층간 절연막; 및An interlayer insulating layer on the gate electrode; And
    상기 층간 절연막 상에 위치하며, 상기 액티브층에 각각 연결되는 소스 전극 및 드레인 전극을 포함하며,Located on the interlayer insulating film, and includes a source electrode and a drain electrode, respectively, connected to the active layer,
    상기 액티브층과 상기 게이트 절연막 사이에 위치하며, 4족 원소를 포함하는 산화물 반도체로 이루어진 중간층을 포함하는 박막트랜지스터 어레이 기판.A thin film transistor array substrate positioned between the active layer and the gate insulating film, the intermediate layer comprising an oxide semiconductor containing a Group 4 element.
  2. 제1 항에 있어서,According to claim 1,
    상기 중간층은 인듐, 갈륨 및 아연을 포함하며, 4족 원소를 더 포함하는 박막트랜지스터 어레이 기판. The intermediate layer includes indium, gallium, and zinc, and further comprising a Group 4 element.
  3. 제2 항에 있어서,The method of claim 2,
    상기 중간층은 In1 . 1Ga1Zn1Si(0.5~2)O(7.3~8.15)로의 원자 비율로 이루어지는 박막트랜지스터 어레이 기판. The intermediate layer was In 1 . A thin film transistor array substrate comprising an atomic ratio of 1 Ga 1 Zn 1 Si (0.5 to 2) O (7.3 to 8.15) .
  4. 제3 항에 있어서,The method of claim 3, wherein
    상기 중간층의 두께는 40 내지 70Å인 박막트랜지스터 어레이 기판.The thickness of the intermediate layer is a thin film transistor array substrate of 40 to 70Å.
  5. 제2 항에 있어서,The method of claim 2,
    상기 4족 원소는 실리콘인 것을 특징으로 하는 박막트랜지스터 어레이 기판.The Group 4 element is a thin film transistor array substrate, characterized in that the silicon.
  6. 제5 항에 있어서,The method of claim 5,
    상기 실리콘의 함량은 2.9 내지 3.2×1022㎝-3인 박막트랜지스터 어레이 기판.The silicon content is a thin film transistor array substrate of 2.9 to 3.2 × 10 22 cm -3 .
  7. 제5 항에 있어서,The method of claim 5,
    상기 중간층은 수소를 더 포함하며, 상기 수소의 함량은 1.2 내지 1.6×1021㎝-3인 박막트랜지스터 어레이 기판.The intermediate layer further comprises hydrogen, wherein the hydrogen content is 1.2 to 1.6 × 10 2 1cm -3 Thin film transistor array substrate.
  8. 제5 항에 있어서,The method of claim 5,
    상기 중간층의 두께는 50 내지 100Å인 박막트랜지스터 어레이 기판.The thickness of the intermediate layer is a thin film transistor array substrate 50 to 100Å.
  9. 기판;Board;
    상기 기판 상에 위치하는 게이트 전극;A gate electrode on the substrate;
    상기 게이트 전극 상에 위치하는 게이트 절연막;A gate insulating layer on the gate electrode;
    상기 게이트 절연막 상에 위치하는 액티브층;An active layer on the gate insulating layer;
    상기 액티브층 상에 위치하는 에치 스토퍼; 및An etch stopper located on the active layer; And
    상기 에치 스토퍼 상에 위치하며, 상기 액티브층에 각각 연결되는 소스 전극 및 드레인 전극을 포함하며,A source electrode and a drain electrode on the etch stopper and connected to the active layer, respectively;
    상기 액티브층과 상기 게이트 절연막 사이에 위치하며, 4족 원소를 포함하는 산화물 반도체로 이루어진 중간층을 포함하는 막트랜지스터 어레이 기판.A film transistor array substrate disposed between the active layer and the gate insulating film, the intermediate layer consisting of an oxide semiconductor containing a Group IV element.
  10. 제9 항에 있어서,The method of claim 9,
    상기 중간층은 인듐, 갈륨 및 아연을 포함하며, 4족 원소를 더 포함하는 막트랜지스터 어레이 기판. The intermediate layer includes indium, gallium and zinc, further comprising a Group 4 element.
  11. 제9 항에 있어서,The method of claim 9,
    상기 중간층은 In0 . 8Ga1Zn1Si0 .5O(4.2~4.7)의 원자 비율로 이루어지는 박막트랜지스터 어레이 기판. The middle layer was In 0 . 8 Ga 1 Zn 1 Si 0 .5 O thin film transistor array substrate of the atomic ratio of (4.2 ~ 4.7).
  12. 제9 항에 있어서,The method of claim 9,
    상기 중간층의 두께는 50 내지 100Å인 박막트랜지스터 어레이 기판. The thickness of the intermediate layer is a thin film transistor array substrate 50 to 100Å.
  13. 기판;Board;
    상기 기판 상에 위치하며, 하부 액티브층과 중간층을 포함하는 액티브층;An active layer on the substrate, the active layer including a lower active layer and an intermediate layer;
    상기 액티브층 상에 위치하는 게이트 절연막;A gate insulating layer on the active layer;
    상기 게이트 절연막 상에 위치하는 게이트 전극;A gate electrode on the gate insulating layer;
    상기 게이트 전극 상에 위치하는 층간 절연막; 및An interlayer insulating layer on the gate electrode; And
    상기 층간 절연막 상에 위치하며, 상기 액티브층에 각각 연결되는 소스 전극 및 드레인 전극을 포함하며,Located on the interlayer insulating film, and includes a source electrode and a drain electrode, respectively, connected to the active layer,
    상기 중간층은 4족 원소를 포함하는 산화물 반도체로 이루어진 박막트랜지스터 어레이 기판.The intermediate layer is a thin film transistor array substrate consisting of an oxide semiconductor containing a Group IV element.
  14. 제13 항에 있어서,The method of claim 13,
    상기 중간층은 인듐, 갈륨 및 아연을 포함하며, 4족 원소를 더 포함하는 박막트랜지스터 어레이 기판. The intermediate layer includes indium, gallium, and zinc, and further comprising a Group 4 element.
  15. 제14 항에 있어서,The method of claim 14,
    상기 중간층은 In5Ga1Zn1Si(12~13)O35로의 원자 비율로 이루어지는 박막트랜지스터 어레이 기판. The intermediate layer is a thin film transistor array substrate consisting of an atomic ratio of In 5 Ga 1 Zn 1 Si (12 ~ 13) O 35 .
  16. 제13 항에 있어서,The method of claim 13,
    상기 중간층의 두께는 50 내지 100Å인 박막트랜지스터 어레이 기판. The thickness of the intermediate layer is a thin film transistor array substrate 50 to 100Å.
PCT/KR2015/013802 2014-12-16 2015-12-16 Thin-film transistor array substrate WO2016099150A1 (en)

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