WO2016084343A1

WO2016084343A1 - Electronic device and manufacturing method for same

Info

Publication number: WO2016084343A1
Application number: PCT/JP2015/005755
Authority: WO
Inventors: Shinan Wang; Yutaka Setomoto
Original assignee: Canon Kabushiki Kaisha
Priority date: 2014-11-28
Filing date: 2015-11-18
Publication date: 2016-06-02
Also published as: JP2016103550A

Abstract

When an electronic device including through wirings and an element section in and on a semiconductor substrate is manufactured, a first insulating film is formed on each of first and second opposing surfaces of the substrate. Holes are formed in the substrate while at least parts of the first insulating film on the second surface are kept remained. A second insulating film is formed on an inner wall of each hole. The element section is formed on the first insulating film on the second surface such that electrodes of the element section are at least partly overlapped with bottoms of the holes. The first insulating film on the second surface is processed from the first surface side to make the element electrodes partly exposed toward the first surface side. A conductive material is filled in the holes by electrolytic plating with exposed portions of the electrodes used as seed layers.

Description

ELECTRONIC DEVICE AND MANUFACTURING METHOD FOR SAME

The present invention relates to an electronic device using through wirings, and a manufacturing method for the electronic device.

Higher speeds and more advanced functions are demanded in systems such as integrated circuits, typically LSIs. A chip mounting technique using a three-dimensional structure is required in order to realize the higher speeds and the more advanced functions in the systems such as the integrated circuits. For that reason, a through wiring (through line) capable of electrically interconnecting chips by the shortest distance has been used up to date. A typical material for the through wiring is Cu. The so-called via first method and via last method are known as techniques for manufacturing electronic devices that utilize the through wirings. In the via first method, a through wiring penetrating a substrate is formed prior to forming an element section. In that case, there is a possibility that a material of the through wiring may diffuse into the substrate or the element section during a heating step in a process of forming the element section, or that the through wiring may be deformed due to thermal expansion. Furthermore, the through wiring may be eroded by chemicals. On the other hand, in the via last method, a through wiring penetrating the substrate is formed after forming the element section. In that case, an insulating film around the through wiring is desirably formed at a temperature as low as possible to avoid damage of the element section. This causes a problem in ensuring required dielectric strength of the insulating film. Thus, due to a possibility of damage of the through wiring and deficient dielectric strength of the insulating film around the through wiring, the related-art techniques still has room for improvement in electrical reliability of electronic devices.

Patent Literature (PTL) 1 discloses a technique of forming an electronic device in the order of a through hole, an insulating film on an inner wall of the through hole, an element section, and finally a through wiring. According to the disclosed technique, a through hole (also called a penetrating hole) to receive the through wiring is first formed, and the insulating film is formed on the inner wall of the through hole. At that time, because the element section is not yet present on a substrate, the insulating film can be formed at a sufficiently high temperature, and good dielectric strength can be obtained. Thereafter, the element section is formed. At that time, because the through wiring is not yet formed, diffusion, deformation, erosion, etc. of the through wiring can be avoided which may be caused during the formation of the element section.

Japanese Patent Laid-Open No. 2012-195514

In the method disclosed in PTL 1, however, after removing the insulating film on a rear surface of the substrate once, an insulating film is needed to be formed again thereon for the reason that wiring electrodes are formed after forming the element section. When the insulating film is formed on the rear surface of the substrate again, the element section is present on the substrate. Therefore, the insulating film has to be formed just at a relatively low temperature to avoid damage of the element section. The film formation at such a low temperature may result in a risk that the dielectric strength of the insulating film on the rear surface of the substrate is insufficient and electrical reliability of the electric device cannot be assured.

In consideration of the problems described above, the present invention provides a manufacturing method for an electronic device including through wirings (through lines) and an element section in and on a substrate, the element section including electrodes, the manufacturing method including the steps of forming a first insulating film on each of a first surface and a second surface of the substrate, the first surface and the second surface being opposite to each other, forming holes in the substrate in a state not completely penetrating the first insulating film formed on the second surface, forming a second insulating film on an inner wall of each of the holes, forming the element section such that the electrodes are located on the first insulating film at the second surface side in positions above the holes, and filling a conductive material in the holes, the steps being executed successively in the order mentioned above.

In consideration of the problems described above, the present invention further provides another manufacturing method for an electronic device including through wirings and an element section in and on an insulating substrate, the manufacturing method including the steps of forming non-through holes not completely penetrating the insulating substrate, which has a first surface and a second surface opposite to each other, from the first surface side while a substrate material remains in the second surface, forming the element section such that, in the second surface, electrodes of the element section are at least partly overlapped with bottoms of the non-through holes, processing the substrate material remaining in the second surface from the first surface side to make the electrodes partly exposed at the bottoms of the non-through holes toward the first surface side such that the non-through holes become through holes, and filling a conductive material in the through holes by electrolytic plating with exposed portions of the electrodes used as seed layers, the steps being executed successively in the order mentioned above.

Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.

Fig. 1A is a sectional view referenced to explain an embodiment of a manufacturing method for an electronic device according to the present invention. Fig. 1B is a sectional view referenced to explain the embodiment of the manufacturing method for the electronic device according to the present invention. Fig. 1C is a sectional view referenced to explain the embodiment of the manufacturing method for the electronic device according to the present invention. Fig. 1D is a sectional view referenced to explain the embodiment of the manufacturing method for the electronic device according to the present invention. Fig. 1E is a sectional view referenced to explain the embodiment of the manufacturing method for the electronic device according to the present invention. Fig. 1F is a sectional view referenced to explain the embodiment of the manufacturing method for the electronic device according to the present invention. Fig. 1G is a sectional view referenced to explain the embodiment of the manufacturing method for the electronic device according to the present invention. Fig. 1H is a sectional view referenced to explain the embodiment of the manufacturing method for the electronic device according to the present invention. Fig. 2A is a sectional view referenced to explain EXAMPLE of the manufacturing method for the electronic device according to the present invention. Fig. 2B is a sectional view referenced to explain EXAMPLE of the manufacturing method for the electronic device according to the present invention. Fig. 2C is a sectional view referenced to explain EXAMPLE of the manufacturing method for the electronic device according to the present invention. Fig. 2D is a sectional view referenced to explain EXAMPLE of the manufacturing method for the electronic device according to the present invention. Fig. 2E is a sectional view referenced to explain EXAMPLE of the manufacturing method for the electronic device according to the present invention. Fig. 2F is a sectional view referenced to explain EXAMPLE of the manufacturing method for the electronic device according to the present invention. Fig. 2G is a sectional view referenced to explain EXAMPLE of the manufacturing method for the electronic device according to the present invention. Fig. 2H is a sectional view referenced to explain the relationship of the manufacturing method for the electronic device according to the present invention. Fig. 2I is a sectional view referenced to explain EXAMPLE of the manufacturing method for the electronic device according to the present invention. Fig. 2J is a sectional view referenced to explain EXAMPLE of the manufacturing method for the electronic device according to the present invention. Fig. 2K is a sectional view referenced to explain EXAMPLE of the manufacturing method for the electronic device according to the present invention. Fig. 2L is a sectional view referenced to explain EXAMPLE of the manufacturing method for the electronic device according to the present invention. Fig. 2M is a sectional view referenced to explain EXAMPLE of the manufacturing method for the electronic device according to the present invention. Fig. 3A is a sectional view referenced to explain another manufacturing method. Fig. 3B is a sectional view referenced to explain the other manufacturing method. Fig. 3C is a sectional view referenced to explain the other manufacturing method. Fig. 3D is a sectional view referenced to explain the other manufacturing method. Fig. 3E is a sectional view referenced to explain the other manufacturing method. Fig. 4A is an explanatory view of a sample information obtaining apparatus using a transducer according to the present invention. Fig. 4B is an explanatory view of a sample information obtaining apparatus using a transducer according to the present invention.

Description of Embodiment

A manufacturing method (fabrication method) for an electronic device according to an embodiment of the present invention is a manufacturing method for an electronic device including through wirings and an element section in and on a substrate, the element section including electrodes. More specifically, the manufacturing method is featured in successively performing the following steps (1) to (5) in the order mentioned below.
(1) A step of forming a first insulating film on each of a first surface and a second surface of the substrate, the first surface and the second surface being opposite to each other.
(2) A step of forming holes in the substrate in a state not completely penetrating the first insulating film formed on the second surface.
(3) A step of forming a second insulating film on an inner wall of each of the holes.
(4) A step of forming the element section such that the electrodes are located on the first insulating film at the second surface side in positions above the holes.
(5) A step of filling a conductive material in the holes.

Stated in another way, in a method of forming the electronic device according to the embodiment of the present invention, after forming holes in a substrate having a first surface and a second surface, a conductive material is filled in each of the holes by electrolytic plating while an element electrode exposed at the bottom of the hole is utilized as a seed layer. In the case of a semiconductor substrate, insulating films are formed on an inner wall of the hole and surfaces of the substrate. However, because those insulating films are formed prior to fabricating the element section, methods and conditions used in forming those insulating films are less restrictive. When the substrate is an insulating substrate such as a glass substrate, insulating films are not needed to be formed on the inner wall of the hole and the surfaces of the substrate. A conductive material is filled in each of the holes by electrolytic plating while an exposed portion of an element electrode, which is exposed by processing a substrate material at the second surface side of the substrate, is utilized as a seed layer.

The embodiment and EXAMPLES of the present invention will be described below with reference to the drawings. It is, however, to be noted that the present invention is not limited to the following embodiment and EXAMPLES, and that various modifications and alterations can be made within the scope not departing from the gist of the invention.

Embodiment

The embodiment of the manufacturing method for the electronic device according to the present invention is described with reference to Figs. 1A to 1H. Figs. 1A to 1H are each a sectional view referenced to explain the embodiment. For simplification of the drawing, only two through wirings and one element section are illustrated in each of Figs. 1A to 1H. First, a substrate 1 is prepared as illustrated in Fig. 1A. Here, the substrate 1 is a semiconductor substrate. The substrate 1 is, for example, a silicon substrate. The substrate 1 has a first surface 1a and a second surface 1b that are opposite to each other. The first surface 1a and the second surface 1b are desirably parallel to each other. The substrate 1 has a thickness of, e.g., 50 μm to 1000 μm. The manufacturing method will be described below in connection with the case where the substrate 1 is a silicon substrate. The silicon substrate is advantageous in that it can be more easily processed than substrates made of other materials.

Then, as illustrated in Fig. 1B, a first insulating film 2 is formed on each of the first surface 1a and the second surface 1b of the substrate 1. The first insulating film on the first surface 1a is denoted by 2a, and the first insulating film on the second surface 1b is denoted by 2b. The first insulating

films

2a and 2b may be formed at the same time or separately. Respective structures or thicknesses of the first insulating

films

2a and 2b may be the same or different from each other. The first insulating film 2 (including 2a and 2b; this is similarly applied to the following description) is constituted as, e.g., a single-layer film of silicon nitride or silicon oxide, or a multilayer film of silicon nitride and silicon oxide. The first insulating film 2 has a thickness of, e.g., 0.1 μm to 1.5 μm. A method of forming the silicon nitride may be CVD (Chemical Vapor Deposition). A method of forming the silicon oxide may be thermal oxidation or CVD.

Then, as illustrated in Fig. 1C, holes 3 are formed. Processing to form the holes 3 is performed on the substrate 1 from the side including the first surface 1a such that a portion 2d of the first insulating film 2b on the second surface 1b remains at the bottom of each of the holes 3. The shapes, number, layout, etc. of the holes 3 can be specified with a photoresist pattern depending on use. For example, the holes 3 have diameters of 20 μm to 100 μm and are arrayed at a period of 200 μm in the horizontal direction, and a period of 2 mm in the vertical direction. In the processing of the holes 3, the first insulating film 2a and the substrate 1 are successively processed, for example, with a photoresist pattern (not illustrated) used as an etching mask. The holes 3 are formed in the substrate 1 by employing RIE (Reactive Ion Etching), for example.

In Fig. 1C, an opening of the first insulating film 2a is denoted by 2c. An inner wall of each of the holes 3 is denoted by 3a, and an opening of the hole 3 is denoted by 3b. With the formation of the hole 3, a portion 2d of the first insulating film 2b is exposed at the bottom of the hole 3. There are no problems even when the portion 2d of the first insulating film 2b is slightly etched in the processing of the hole 3. However, a material and a thickness of the first insulating film 2b are determined in the step of Fig. 1B such that the portion 2d of the first insulating film 2b has mechanical strength at such an extent as not being broken in the step of processing the hole 3 and subsequent steps.

After processing the holes 3, the above-mentioned etching mask is removed by a suitable method. It is preferable that the inner wall 3a of each hole 3 is sufficiently smooth. For example, the surface roughness of the inner wall 3a of the hole 3 is preferably 50 nm or less at a maximum height Rmax. When the inner wall 3a of the hole 3 is not sufficiently smooth after the RIE, a process of smoothing the inner wall 3a is preferably performed. For example, a silicon oxide film is formed on the surface of the inner wall 3a through thermal oxidation, and the silicon oxide film is then removed by employing a chemical, e.g., fluoric acid or BHF (Buffered Hydrogen Fluoride). As a result, the inner wall 3a can be smoothed. Alternatively, heat treatment in a hydrogen atmosphere is also effective in smoothing the inner wall 3a. Because the portion 2d of the first insulating film 2b on the second surface 1b remains, the second surface 1b of the substrate 1 including the first insulating film 2b is kept flat.

Then, as illustrated in Fig. 1D, a second insulating film 4 is formed on the inner wall 3a (see Fig. 1C) of the hole 3. A material of the second insulating film 4 may be the same as or different from that of the first insulating film 2. When the materials of the second insulating film 4 and the first insulating film 2 are different from each other, the first insulating film 2 is a silicon nitride film and the second insulating film 4 is a silicon oxide film, for example. When the silicon oxide film is formed through thermal oxidation in the above-described combination, the second insulating film 4 is formed only on the inner wall 3a of the hole 3. One merit in the case where the materials of the second insulating film 4 and the first insulating film 2 are different from each other resides in that damage of the second insulating film 4 can be reduced in a step of forming an opening 2e-1 in the first insulating film 2b to make a part of an element electrode exposed as described later with reference to Fig. 1F. When the materials of the second insulating film 4 and the first insulating film 2 are the same, they are both silicon oxide films, for example, and the second insulating film 4 is formed through thermal oxidation of silicon. One merit in the case where the materials of the second insulating film 4 and the first insulating film 2 are the same resides in easiness in obtaining a state that stress is relatively low over the entire substrate.

A thickness of the second insulating film 4 is determined depending on the performance that is required for the second insulating film 4. The thickness of the second insulating film 4 is, e.g., 0.5 μm to 1.5 μm. A barrier film may be further disposed on the surface of the second insulating film 4 to prevent thermal diffusion of a material of the through wiring into the substrate 1. A material and a thickness of the barrier layer need to be designed depending on respective materials of a through electrode, the substrate, and the first insulating film, as well as a process temperature and time. In this embodiment, the barrier layer is suitably made of a silicon nitride with a thickness of about 100 nm, and is formed by LP-CVD (Low-Pressure-CVD), for example. When the inner wall 3a of the hole 3 is sufficiently smoothed in the step of Fig. 1C, the second insulating film 4 formed on the inner wall 3a is less susceptible to defects and is more resistant to stress caused during the thermal process, etc.

Then, as illustrated in Fig. 1E, an element section 5 is formed on the first insulating film 2b. Because the portion 2d of the first insulating film 2b on the second surface 1b remains at the bottom of the hole 3 in the step of processing the hole 3 as illustrated in Fig. 1C, the second surface 1b of the substrate 1 including the first insulating film 2b is flat. The element section 5 is formed on the flat second surface 1b of the substrate. Accordingly, the steps of filling the hole 3 with a temporary filling material and grinding the temporary filling material for planarization are not necessary. The element section 5 includes, for example, an electrode portion (including a lower electrode 6 and an upper electrode 7) and the other portion 8. The electrode portion is formed to be at least partly overlapped with a bottom of the hole 3, the bottom being defined by the portion 2d of the first insulating film 2b. For example, the lower electrode 6 is partly overlapped with a bottom 2d-2 of a hole 3-2, and the upper electrode 7 is partly overlapped with a bottom 2d-1 of a hole 3-1. Examples of the element section 5 are various types of MEMS (Micro Electro Mechanical System) elements. More specific examples are a CMUT (Capacitive Micromachined Ultrasonic Transducer) and a piezoelectric ultrasonic transducer. A method of forming the element section 5 is designed depending on specifications of a device to be formed.

Then, as illustrated in Fig. 1F, portions of the first insulating film 2b, the portions defining the bottoms 2d-1 and 2d-2 of the holes (see Fig. 1E), are processed to form openings 2e-1 and 2e-2 such that parts of the element electrodes are each exposed when viewed from the side including the opening 3b (see Fig. 1C) of the hole. In Fig. 1F, the opening 2e-1 is formed at the bottom of the hole 3-1, and a portion 7a of the upper electrode 7 is exposed. Similarly, the opening 2e-2 is formed at the bottom of the hole 3-2, and a portion 6a of the lower electrode 6 is exposed. The portion 2d of the first insulating film 2b is processed in a manner of not significantly damaging the second insulating film 4. For that purpose, processing to form the openings 2e (including 2e-1 and 2e-2) is made on the substrate 1 from the side including the first surface 1a (see Fig. 1A) by, e.g., dry etching with a dry film resist 9 used as a mask. Sizes of openings 9-1 and 9-2 in the dry film resist 9 are smaller than those of the opening 2c (see Fig. 1C) of the first insulating film 2a and the opening 3b (see Fig. 1C) of the hole 3. In other words, the opening 2c (see Fig. 1C) of the first insulating film 2a and the opening 3b of the hole 3 are not seen when viewed from a direction perpendicular to the first surface 1a of the substrate 1. In addition, RIE with high straight-forwardness is suitably used as a dry etching method. With the use of such a drying etching method, even when the first insulating film 2b and the second insulating film 4 are made of the same material, the second insulating film 4 on the inner wall 3a of the hole 3 is not significantly damaged during the processing of the portion 2d of the first insulating film 2b. When the materials of the first insulating film 2b and the second insulating film 4 are different from each other, damage of the second insulating film 4 can be further reduced by employing RIE gas with high selectivity. After processing the portion 2d of the first insulating film 2b, the dry film resist 9 is removed by an appropriate method.

Then, as illustrated in Fig. 1G, a conductive material 10 is filled in the holes 3 (including the holes 3-1 and 3-2, see Fig. 1F) by electrolytic plating while the exposed portion (including 6a and 7a) of the electrode of the element section 5 are utilized as seed layers. In order to protect the element section 5, all the electrodes (including the lower electrode 6 and the upper electrode 7) of the element section 5, those electrodes serving as the seed layers, are held at the same potential during the electrolytic plating. Moreover, during the plating, the conductive material 10 is filled in a state of completely filling the inside of each hole 3 up to the opening 2c (see Fig. 1C), and further projecting from the opening 2c (though not illustrated) with intent to assure reliable electrical connection to wiring electrodes that are formed later.

During the plating, a plating solution is circulated within the hole 3 from the opening 3b of the hole 3, and the conductive material 10 is grown starting from the exposed portion (including 6a and 7a) of the electrode of the element section 5. The conductive material 10 contains, e.g., Cu as a main component. In that case, the plating of the conductive material 10 is performed as electrolytic plating of Cu with, e.g., copper sulfate being a main solution. During the plating, respective surfaces of the lower electrode 6 and the upper electrode 7, which are positioned outside the holes 3, are kept from contacting the plating solution such that the plated conductive materials will not grow on those surfaces. For that purpose, the exposed portions in the second surface 1b of the substrate 1 are protected by an insulating material, for example. As a result, the plated conductive materials are allowed to grow only inside the holes 3, and good plating efficiency is obtained. After the plating, the substrate 1 is processed from the side including the first surface 1a (see Fig. 1A) such that end surfaces 10a and 10b of the conductive materials 10 are formed. For example, CMP (Chemical Mechanical Polishing) is used for the processing to form the end surfaces 10a and 10b. With the CMP, the end surfaces 10a and 10b are positioned substantially at the same height as the surface of the first insulating film 2a, and the substrate surface is planarized. The conductive materials 10 (including 10-1 and 10-2) having been subjected to the processing to form the end surfaces, as described above, become the through wirings.

Then, as illustrated in Fig. 1H,

electrode pads

11 and 12 are formed. The electrode pad 11 is formed to be connected to the end surface 10a of the through wiring 10-1. The electrode pad 12 is formed to be connected to the end surface 10b of the through wiring 10-2. As a result, the lower electrode 6 and the upper electrode 7 on the second surface 1b of the substrate 1 are led out to opposing positions at the first surface 1a of the substrate 1 via the through wirings 10-2 and 10-1, respectively. The

electrode pads

11 and 12 are each made of a metal as a main material.

In the above manufacturing steps of Figs. 1E to 1H, to enhance adhesion between adjacent films, to increase insulation performance, and/or to prevent inter-diffusion, a film being effective in realizing such an effect may be disposed between the adjacent films. Performing surface treatment of an underlying film before forming an overlying film is also effective in enhancing adhesion between those adjacent films. The surface of the underlying film is cleaned or activated by the surface treatment. An example of the surface treatment is plasma treatment or treatment using a chemical. An electronic device including the element section 5 and a through-wiring equipped substrate (including the substrate 1, the insulating

films

2 and 4, the through wirings 10, etc.) and having assured electrical reliability can be formed through the above manufacturing steps of Figs. 1A to 1H.

Then, though not illustrated, the electronic device (including the element section 5 and the through-wiring equipped substrate), which has been fabricated through the manufacturing steps of Figs. 1A to 1H, is connected to a control circuit. The connection to the control circuit is established via the

electrode pads

11 and 12. An example of a method for establishing the connection is metallic direct bonding, bump bonding, ACF (Anisotropic Conductive Film) bonding, or a wire bonding.

In the step of, in the manufacturing method of this embodiment, processing the first insulating film on the second surface from the side including the first surface such that a part of the element electrode is exposed at the bottom of the hole toward the first surface side, an inner diameter of the opening 2e formed in the first insulating film on the second surface is smaller than that of the hole. Such a structure of the inner diameter of the opening 2e being smaller than that of the hole is substantially an inevitable result of the above-described process. Thus, it is natural to set the inner diameter of the opening 2e to be smaller than that of the hole from the viewpoint of avoiding damage on the inner wall of the hole when the opening 2e is processed. However, a similar structure can also be fabricated by a process illustrated in Figs. 3A to 3E, which is different from the above-described process. More specifically, in the case of forming the through wirings 10 by, e.g., electrolytic plating and then connecting the

element electrodes

6 and 7 on the second surface to the through wirings 10 from the second surface side, when windows (corresponding to the openings 2e) are opened in the first insulating film 2b at positions above the through wirings 2b, sizes of the windows 2e-1 and 2e-2 can be each set smaller than the inner diameter of the hole 3. In that fabrication method, the element section 5 is formed thereafter. That fabrication method can also provide the insulating film with high dielectric strength through a high-temperature process while allowing the use of a process that hardly damages the element and the through wirings.

The structure that the inner diameter of each of the openings (including 2e-1 and 2e-2) in the first insulating film 2b is smaller than that of the hole 3 is effective in suppressing thermal deformation of the end surface of the through wiring at the side including the second surface 1b where the element section 5 is present. In other words, an edge portion of the opening in the first insulating film, the edge portion overlapping the end surface of the through wiring 10, can suppress the end surface of the through wiring from projecting toward the element section 5 with temperature variations. As a result, even with temperature variations, it is possible to reduce a risk of receiving stress from the end surfaces of the through wirings and causing permanent deformation or breakage of thin films (including the lower electrode 6, the upper electrode 7, and the other portion 8), which constitute the element. The projection of the end surface of each through wiring 10 toward the element section 5 with temperature variations is attributable to the fact that the through wiring 10 made of a metal has the larger thermal coefficient than the substrate 1 made of a semiconductor.

With the manufacturing method for the electronic device according to this embodiment, as described above, the electronic device is manufactured in the order of the insulating films on the surfaces of the substrate and on the inner walls of the holes, the element section, and finally the through wirings. Thus, since the insulating films are formed before the element section and the through wirings, the methods and the conditions used in forming the insulating films are less restrictive, and the insulating films having high dielectric strength can be formed easily. For example, a silicon oxide film having good dielectric strength can be formed at a high temperature of about 1000°C and used as the insulating film. Furthermore, since the first insulating film at the first surface side remains as it is and can be utilized as the insulating film at the first surface side, good dielectric strength is obtained. Moreover, the element section is hardly subjected to thermal degradation because there is no necessity of re-forming the insulating film at the first surface side after forming the element section, the re-formation needing heating (usually heating at 200°C or higher to obtain good dielectric strength). That point is remarkably effective when the element section includes a piezoelectric material (such as when the electronic device is a piezoelectric ultrasonic transducer). The reason is that the piezoelectric material exhibits a phenomenon of degrading piezoelectric characteristics under heating (particularly heating at 150°C or higher). In this embodiment, since the through wirings are formed after the element section, damage of the through wirings caused in the step of forming the element section is avoided. As a result, the electronic device having high electrical reliability can be obtained. In this embodiment, since there is no necessity of carrying out the steps of forming and removing a temporary filling material, grinding the substrate at the first surface side, and re-forming the insulating film at the first surface side, the manufacturing steps of the electronic device are simplified to a large extent.

Practical examples of the present invention will be described in more detail below.

Example 1

One practical example of the manufacturing method for the electronic device according to the present invention is described as EXAMPLE 1 with reference to Figs. 1A to 1H and Figs. 2A to 2M. The electronic device described here is the so-called CMUT. The CMUT is able to transmit and receive an ultrasonic wave by utilizing vibration of a vibration film. Particularly, good wide-band characteristics can be easily obtained in a liquid with the CMUT. In practice, the desired function and performance are realized by arranging, as one element, a plurality of vibration films in a two-dimensional array, and by arranging the plurality of elements side by side on a substrate, thus constituting one element section. Connection wirings corresponding to the individual elements need to be formed to control the elements independently. From the viewpoint of downsizing the CMUT and reducing parasitic capacity generated by the connection wirings, it is desirable to employ through wirings that penetrate a substrate. For simplicity of explanation, only one cell (one vibration film) of the CMUT is illustrated in Figs. 2A to 2M that are referenced to explain EXAMPLE 1. In EXAMPLE 1, the holes 3, the first insulating film 2, and the second insulating film 4 are first formed in and on the semiconductor substrate 1 as illustrated in Figs. 1A to 1D. Then, the element section 5 constituting the CMUT, the through wirings 10 (including 10-1 and 10-2) and so on are successively fabricated as illustrated in Figs. 2A to 2M.

Steps of forming the holes 3, the first insulating film 2, and the second insulating film 4 in and on the substrate 1 are described below with reference to Figs. 1A to 1D. The substrate 1 is first prepared as illustrated in Fig. 1A. The substrate 1 is a silicon substrate, and it has a diameter of 4" (inches) Φ, a thickness of 200 μm, and a resistivity of 0.1 Ω*cm. The first surface 1a and the second surface 1b of the substrate 1, which are opposed to each other, have specular glossiness at the same level as that of a silicon substrate generally commercialized. Then, as illustrated in Fig. 1B, the first insulating film 2 is formed on each of the first surface and the second surface of the substrate 1. The insulating film 2a on the first surface 1a and the insulating film 2b on the second surface 1b are each made of silicon oxide with a thickness of about 1 μm, and they are formed at the same time through thermal oxidation of silicon at a high temperature of about 1000°C.

Then, the holes 3 are formed as illustrated in Fig. 1C. Processing to form the holes 3 is made on the silicon substrate 1 from the side including the first surface 1a (see Fig. 1A) in such a manner that the portion 2d of the first insulating film 2b on the second surface remains at the bottom of each of the holes 3. The holes 3 are formed in a diameter of 50 μm and are arrayed at a period of 200 μm in the horizontal direction and a period of 2 mm in the vertical direction. In the processing to form the holes 3, RIE is performed on the first insulating film 2b made of silicon oxide and the silicon substrate 1 successively with a photoresist pattern (not illustrated) used as an etching mask. With the formation of the holes 3, the portion 2d of the first insulating film 2b is exposed at the bottom of each hole. The type of reactive gas and the processing conditions used in the RIE are different between the first insulating film 2b made of silicon oxide and the silicon substrate 1, and they are optimized to provide selectivity and an etching rate at a sufficient level for each of the first insulating film 2b and the silicon substrate 1. In particular, the RIE conditions for silicon are set such that the portion 2d of the first insulating film 2b is hardly damaged during the formation of the hole 3. After the processing to form the holes 3, the photoresist pattern used as the etching mask is removed by plasma ashing. A pattern of a Cr thin film is preferably used as the etching mask. In such a case, the pattern of the Cr thin film is first formed by employing a photoresist pattern.

Then, as illustrated in Fig. 1D, the second insulating film 4 is formed on the surface of the inner wall 3a (see Fig. 1C) of the hole 3. The second insulating film 4 is made of silicon oxide with a thickness of about 1 μm, and is formed through thermal oxidation of silicon at a high temperature of about 1000°C. In this EXAMPLE, since the second insulating film 4 and the first insulating film 2 are made of the same material, stress generated over the entire substrate is low. On the other hand, when the substrate is an insulating substrate such as a glass substrate, the steps of Figs. 1B and 1C are not necessary, and it is just needed, as illustrated in Fig. 1D, to form the holes 3 in the substrate illustrated in Fig. 1A. At that time, the holes 3 are each formed as a non-through hole while a material of the substrate 1 remains in an appropriate thickness at the bottom of the hole. In the above case, the first insulating film 2 (including 2a and 2b) and the second insulating film 4, illustrated in Fig. 1D, can be regarded as defining surfaces of the insulating substrate. In the case of the insulating substrate, although insulating films are not required to be formed at a high temperature on the substrate surfaces, the element section 5 and the through wirings 10 are desirably formed after forming the non-through holes. Generally, the insulating substrate is difficult to process, and a highly corrosive chemical or plasma needs to be used. If the non-through holes are formed after forming the element section 5 and the through wirings 10, there would be a risk that the element section 5 and the through wirings 10 are damaged. The reason why the holes 3 are formed as the non-through holes in Fig. 1D in the case of the insulating substrate resides in that the surface of the second surface 1b of the substrate is kept flat, and when the element section 5 is formed, the formation of the element section 5 is facilitated.

Steps of forming the CMUT-constituting element section 5 (see Fig. 2M) other than

connection wirings

6b and 7b on the second surface 1b (see Fig. 1A) of the substrate 1 will be described below with reference to Figs. 2A to 2I. Because, in the processing to form the holes 3 in Fig. 1C, the portion 2d of the first insulating film 2b on the second surface 1b remains at the bottom of each hole 3, the second surface 1b of the substrate 1 including the first insulating film 2b is flat. In other words, since the element section 5 (see Fig. 2M) is formed on the flat second surface 1b of the substrate, there is no necessity of filling the hole 3 with a temporary filling material, and then grinding the temporary filling material for planarization.

First, as illustrated in Fig. 2A, a first electrode 6 is formed on the second surface 1b (see Fig. 1A) of the substrate 1. The first electrode 6 is a lower electrode for driving a vibration film 20 (see Fig. 2M) of a CMUT cell. Because the first electrode 6 is formed on the first insulating film 2b, the first electrode 6 is insulated from the substrate 1. The first electrode 6 is positioned under a vibrating portion (i.e., a portion corresponding to a cavity 18 in Fig. 2M) of the vibration film 20 in the cell, and it extends toward a periphery beyond the vibrating portion of the vibration film 20. For individual cells in the same element, the associated first electrodes 6 are formed to be electrically conducted with each other. The first electrode 6 has a structure in which a Ti film with a thickness of about 10 nm and a W film with a thickness of about 50 nm are laminated. The first electrode 6 can be formed by a method including the steps of forming a metal film, forming an etching mask with photolithography, and etching the metal.

Then, as illustrated in Fig. 2B, an insulating film 13 is formed. The insulating film 13 covers an upper surface of the first electrode 6, and its one role is to function as an insulation protective film for the first electrode 6. The insulating film 13 is a film of silicon oxide with a thickness of 200 nm. The film of silicon oxide is formed by CVD at a substrate temperature of about 300°C. After forming the film of silicon oxide,

openings

13a, 13b and 13c are formed in the insulating film 13. The

openings

13a, 13b and 13c can be formed by a method including a step of forming an etching mask with photolithography, and a dry etching step with reactive ion etching.

Then, as illustrated in Fig. 2C, a sacrificial layer pattern 14 is formed. The sacrificial layer pattern 14 is used to form the cavity 18 (see Fig. 2M) in the cell and is made of Cr. The thickness of the Cr pattern 14 is determined depending on the height (thickness) of the cavity 18. When the height of the cavity 18 is 150 nm, for example, a Cr film with a thickness of 150 nm is first formed on the insulating film 13 by an electron-beam evaporation process. Thereafter, the Cr pattern 14 is formed by a method including photolithography and wet etching. In one example, the sacrificial layer pattern 14 has a columnar structure with a diameter of about 30 μm and a height of about 150 nm, and it is connected to an etched hole 17 (see Fig. 2G).

Then, as illustrated in Fig. 2D, an insulating film 15 is formed. The insulating film 15 covers a lower surface of the second electrode 7 formed in the next step, and its one role is to function as an insulation protective film for the second electrode 7 (see Fig. 2M). The insulating film 15 is made of silicon nitride with a thickness of 400 nm. The film of silicon nitride is formed by PE-CVD (Plasma Enhanced CVD) at a substrate temperature of about 300°C. During the film formation, a flow rate, etc. of film-forming gas is controlled such that a film of the silicon nitride becoming the insulating film 15 has tensile stress of about 0.1 GPa.

Then, as illustrated in Fig. 2E, the second electrode 7 is formed. The second electrode 7 is formed on the insulating film 15 as a part of the vibration film 20 (see Fig. 2M) in an opposite relation to the first electrode 6, and it serves as an upper electrode for driving the vibration film 20. In one example, the second electrode 7 is formed by successively laminating a Ti film of 10 nm and an AlNd alloy film of 100 nm. The second electrode 7 is formed by a method including the steps of forming a sputtered metal film, forming an etching mask with photolithography, and etching the metal. Film-forming conditions for the second electrode 7 are adjusted such that the second electrode 7 has tensile stress of 0.4 GPa or less at the time when manufacturing of the CMUT has completed. For the individual cells in the same element, the associated second electrodes 7 are formed to be electrically conducted with each other.

Then, as illustrated in Fig. 2F, an insulating film 16 is formed. The insulating film 16 covers an upper surface of the second electrode 7, and its one role is to function as an insulation protective film for the second electrode 7. The insulating film 16 has a similar structure to that of the insulating film 15 and may be formed in a similar manner to that used in forming the insulating film 15.

Then, as illustrated in Fig. 2G, an etched hole 17 is formed and the sacrificial layer pattern 14 (see Fig. 2F) is removed. More specifically, the etched hole 17 is first formed. The etched hole 17 is formed by a method including photolithography and reactive etching. Thereafter, an etchant is introduced via the etched hole 17 to remove the sacrificial layer pattern 14 made of Cr. As a result, the cavity 18 having the same shape as that of the sacrificial layer pattern 14 is formed.

Then, as illustrated in Fig. 2H, a thin film 19 is formed. The thin film 19 serves to not only seal off the etched hole 17 (see Fig. 2G), but also to constitute the vibration film 20 capable of vibrating above the cavity 18 in cooperation with the insulating film 15, the second electrode 7, and the insulating film 16. In one example, the thin film 19 is made of silicon nitride with a thickness of 500 nm. The thin film 19 is formed by PE-CVD at a substrate temperature of about 300°C similarly to the insulating film 15. The vibration film 20 formed as described above has a structure exhibiting tensile stress of about 0.7 GPa in its entirety, being free from sticking (phenomenon of a bottom surface of the vibration film 20 attaching to an inner surface of the cavity 18) or buckling, and being less susceptible to breakage. In the above manufacturing steps, before forming an upper layer film, plasma treatment may be performed on the surface of a lower layer film in order to increase adhesion between adjacent two of the insulating

films

15, 16 and 19. The surface of the under layer film is cleaned or activated with the plasma treatment.

Then, as illustrated in Fig. 2I, contact holes 21 (including 21a, 21b, 21c and 21d) for electrical connection are formed. The contact hole 21a is an opening where the surface of the first insulating film 2b in a region corresponding to the bottom 2d-1 of the hole 3-1 is partly exposed at the second surface 1b (see Fig. 1A) of the substrate 1. The contact hole 21b is an opening where the upper surface of the second electrode 7 is partly exposed. The contact hole 21c is an opening where the upper surface of the first electrode 6 is partly exposed. The contact hole 21d is an opening where the surface of the first insulating film 2b in a region corresponding to the bottom 2d-2 of the hole 3-2 is partly exposed at the second surface 1b (see Fig. 1A) of the substrate 1. The contact holes 21 can be formed by a method including a step of forming an etching mask with photolithography, and a step of reactive ion etching for the silicon nitride. The contact holes 21 are each a columnar hole with a diameter of about 10 μm, for example.

Then, as illustrated in Fig. 2J, a metal film 22 is formed on and above the second surface 1b (see Fig. 1A) of the substrate 1. The metal film 22 interconnects the second electrode 7 and the first electrode 6 via the contact holes 21b and 21c (see Fig. 2I) such that both the electrodes are kept at the same potential. Furthermore, the metal film 22 is formed on surfaces of the bottoms 2d (including 2d-1 and 2d-2) of the holes 3 (including 3-1 and 3-2) via the

contact holes

21a and 21d (see Fig. 2I), those surfaces being exposed at the second surface 1b (see Fig. 1A) of the substrate 1. The metal film 22 is formed, for example, by successively laminating a Ti film with a thickness of 10 nm and an Al film with a thickness of 500 nm. A method of forming the metal film 22 is, e.g., sputtering.

Then, as illustrated in Fig. 2K, the portions 2d-1 and 2d-2 (see Fig. 2J) of the first insulating film 2b are processed to make the metal film 22 partly exposed when viewed from the side including the openings 3b of the holes 3, thereby forming the openings 2e-1 and 2e-2. In Fig. 2K,

portions

7a and 6a of the metal film 22 are exposed. The second insulating film 4 needs to be not significantly damaged during the processing of the portions 2d (including 2d-1 and 2d-2) of the first insulating film 2b. For that purpose, the processing to form the openings 2e (including 2e-1 and 2e-2) is performed by dry etching under a condition that openings 9-1 and 9-2 of a dry film resist 9 used as an etching mask are set smaller than the opening 3b of the hole 3. In addition, RIE with high straight-forwardness is used as a dry etching method. At the same time as forming the openings 2e, an opening 2f is formed in the first insulating film 2a on the first surface 1a (see Fig. 1A) of the substrate 1, whereby the substrate 1 is exposed in the opening 2f. After forming the openings 2e-1, 2e-2 and 2f, the dry film resist 9 is removed by a suitable method.

A step of forming the through wirings 10 will be described below with reference to Fig. 2L. As illustrated in Fig. 2L, the conductive material 10 (including 10-1 and 10-2) is first filled in the hole 3 by electrolytic plating with the metal film 22 used as a seed layer. To assure reliability of electrical connection, the conductive material 10 is projected out from the opening 2c (see Fig. 1C) in the first insulating film 2a. During the electrolytic plating, a plating solution is circulated within the hole 3 from the opening 3b of the hole 3, and the conductive material 10 is grown starting from each of the exposed

portions

6a and 7a of the conductive metal film 22. The conductive material 10 contains, e.g., Cu as a main component. In that case, the plating of the conductive material 10 is performed as electrolytic plating of Cu with, e.g., copper sulfate being a main solution. During the plating, a surface of the conductive metal film 22, the surface being positioned outside the holes 3, is kept from contacting the plating solution such that the plated conductive material will not grow on the conductive metal film 22. In other words, the plated conductive materials are allowed to grow starting only from the exposed

portions

6a and 7a of the conductive metal film 22. During the plating, because the electrodes (including the first electrode 6 and the second electrode 7) of the CMUT- constituting element section are connected to each other via the metal film 22 and are held at the same potential, both the electrodes are not damaged by an electric field. After the plating growth, the substrate 1 is processed from the side including the first surface 1a such that end surfaces 10a and 10b of the conductive materials 10 are formed. For example, CMP is used for the processing to form the end surfaces 10a and 10b. With the CMP, the end surfaces 10a and 10b are positioned substantially at the same height as the surface of the first insulating film 2a, and the substrate surface is planarized. The conductive materials 10 having been subjected to the processing to form the end surfaces become the through wirings 10.

A step of forming the

connection wirings

6b and 7b and the

electrode pads

11, 12 and 23 will be described below with reference to Fig. 2M. As illustrated in Fig. 2M, the

electrode pads

11, 12 and 23 are first formed on the first surface 1a (see Fig. 1A) of the substrate 1. The

electrode pads

11 and 12 are formed to be connected to the through wirings 10-1 and 10-2, respectively. The electrode pad 23 is formed to be connected to the substrate 1 via the opening 2f (see Fig. 2L). The

electrode pads

11, 12 and 23 are each made of an Al film with a thickness of about 500 nm, and formed by a method including the steps of forming a sputtered Al film, forming an etching mask with photolithography, and etching Al. During the step of forming the

electrode pads

11, 12 and 23, the metal film 22 at the side including the second surface 1b (see Fig. 1A) of the substrate 1 is protected to avoid damage of the metal film 22. The metal film 22 is protected, for example, by employing a photoresist. After forming the

electrode pads

11, 12 and 23, the metal film 22 is processed to form patterns of the

connection wirings

6b and 7b. The metal film 22 is processed by a method including the steps of forming an etching mask with photolithography, and etching the metal.

During the processing of the metal film 22, the

electrode pads

11, 12 and 23 are protected by a photoresist. In the above-described steps, because the through wirings 10 are protected by the

electrode pads

11 and 12 and the

connection wirings

6b and 7b, they are not eroded by chemicals, etc. Furthermore, by forming the

connection wirings

6b and 7b and the

electrode pads

11, 12 and 23 at relatively low temperatures, the through wirings 10 are less susceptible to thermal deformation and thermal diffusion. As seen from Fig. 2M, the first electrode 6 positioned above the second surface 1b (see Fig. 1A) of the substrate 1 is connected to the through wiring 10-2 by the connection wiring 6b, and is led out to the electrode pad 12 that is positioned on the first surface 1a (see Fig. 1A) of the substrate 1. Similarly, the second electrode 7 positioned above the second surface 1b (see Fig. 1A) of the substrate 1 is connected to the through wiring 10-1 by the connection wiring 7b, and is led out to the electrode pad 11 that is positioned on the first surface 1a (see Fig. 1A) of the substrate 1.

Though not illustrated, the CMUT-constituting element section is then connected to a control circuit. The connection is established via the

electrode pads

11, 12 and 23. ACF bonding is used as a manner for the connection. In driving of the CMUT, a bias voltage is applied to the first electrode 6, and the second electrode 7 is used as an electrode for applying a signal or taking out a signal. Signal noise can be reduced by grounding the substrate 1 via the electrode pad 23.

The CMUT including the substrate equipped with the through wirings, the CMUT-constituting element section, and the control circuit is manufactured as described above. With the manufacturing method for the CMUT according to this embodiment, the CMUT is manufactured in the order of the first insulating films on the substrate surfaces and on the inner walls of the holes, the CMUT-constituting element section, and finally the through wirings. Thus, since the insulating films are formed before the CMUT-constituting element section and the through wirings, the methods and the conditions used in forming the insulating films are less restrictive, and the insulating films having high dielectric strength can be formed easily. For example, a silicon oxide film having good dielectric strength can be formed at a high temperature of about 1000°C and used as the insulating film. Furthermore, since the first insulating film at the first surface side remains as it is and utilized as the insulating film at the first surface side, good dielectric strength is obtained. Moreover, the CMUT-constituting element section is hardly subjected to thermal degradation because there is no necessity of heating up to 200°C or higher after forming the CMUT-constituting element section. In addition, since the through wirings are formed after the CMUT-constituting element section, degradation of the insulation and failures of the connection caused in the step of forming the CMUT-constituting element section are avoided. As a result, the CMUT having high electrical reliability can be obtained. Still further, since, when the holes are formed, the insulating film on the substrate surface at the side where the CMUT-constituting element section is to be formed is kept remained with the holes not completely penetrating the relevant insulating film, a step of planarizing the substrate surface at the side where the CMUT-constituting element section is to be formed is not needed, and the manufacturing steps of the CMUT are simplified to a large extent.

The above-described manufacturing method can be applied to or employed in manufacturing various electronic devices and systems including LSI chips and MEMS elements. As a result, it is possible to further reduce sizes, increase mounting densities, and realize more advanced functions of the electronic devices and the systems.

Example 2

Fig. 4A illustrates one example of a sample information obtaining apparatus utilizing a photo-acoustic effect. Pulsed light oscillated from a light source 2010 is applied to a sample 2014 via optical members 2012 including a lens, a mirror, and an optical fiber, for example. A light absorber 2016 present inside the sample 2014 absorbs energy of the pulsed light and generates a photo-acoustic wave 2018, i.e., an acoustic wave. A transducer 2020 according to the present invention, which is disposed in a probe 2022, receives the photo-acoustic wave 2018, converts the received photo-acoustic wave 2018 to an electrical signal, and outputs the electrical signal to a signal processing unit 2024. The signal processing unit 2024 executes signal processing, such as A/D conversion and amplification, on the input electrical signal, and outputs the processed electrical signal to a data processing unit 2026. The data processing unit 2026 obtains, as image data, sample information (i.e., characteristic information representing an optical characteristic value of the sample, such as a light absorption coefficient) from the input signal. Here, the signal processing unit 2024 and the data processing unit 2026 are collectively called a processor. A display unit 2028 displays an image on the basis of the image data input from the data processing unit 2026. Thus, the sample information obtaining apparatus of this example includes the transducer of the present invention, the light source, and the processor. The transducer receives the photo-acoustic wave generated from the sample that is irradiated with the light oscillated from the light source, and converts the received photo-acoustic wave to the electrical signal. The processor obtains the information of the sample from the electrical signal.

Fig. 4B illustrates another example of a sample information obtaining apparatus, e.g., an ultrasonic echo diagnosis apparatus, utilizing reflection of an acoustic wave. An acoustic wave transmitted to a sample 2114 from a transducer 2120 of the present invention, which is disposed in a probe 2122, is reflected by a reflector 2116. The transducer 2120 receives the reflected acoustic wave (reflected wave) 2118, converts the received acoustic wave 2118 to an electrical signal, and outputs the electrical signal to a signal processing unit 2124. The signal processing unit 2124 executes signal processing, such as A/D conversion and amplification, on the input electrical signal, and outputs the processed electrical signal to a data processing unit 2126. The data processing unit 2126 obtains, as image data, sample information (i.e., characteristic information representing a difference in acoustic impedance) from the input signal. Here, the signal processing unit 2124 and the data processing unit 2126 are collectively called a processor. A display unit 2128 displays an image on the basis of the image data input from the data processing unit 2126. Thus, the sample information obtaining apparatus of this example includes the transducer of the present invention, and the processor that obtains the information of the sample from the electrical signal output from the transducer. The transducer receives the acoustic wave generated from the sample, and outputs the electrical signal.

The probe may be of the type that is mechanically scanned or the type that is manually moved by a user, e.g., a doctor or an engineer, relative to the sample (i.e., the hand-held type). In the case of the apparatus utilizing the reflected wave as illustrated in Fig. 4B, a probe for transmitting the acoustic wave may be disposed separately from a probe for receiving the reflected acoustic wave. Furthermore, an apparatus may have the functions of both the apparatuses illustrated in Figs. 4A and 4B to be able to obtain both the sample information representing the optical characteristic value of the sample and the sample information representing the difference in acoustic impedance. In such a case, the transducer 2020 in Fig. 4A may be configured to transmit the acoustic wave and receive the reflected wave instead of just receiving the photo-acoustic wave.

The above-described transducer of the capacitive type, for example, can be further employed in a measuring apparatus that measures the magnitude of an external force. In such an application, the magnitude of an external force applied to the surface of the transducer is measured from an electrical signal generated by the transducer having received the external force.

According to the embodiment of the present invention, as described above, the element section is formed after forming the insulating films on the surfaces of the substrate, including the surfaces of the inner walls of the holes, and the through wirings are finally formed. Therefore, the methods and the conditions used in forming the insulating films on all the surfaces of the substrate are less restrictive, and the insulating films having high dielectric strength can be formed easily. According to another manufacturing method of the present invention, the electronic device is manufactured in the order of the holes (non-through holes) in an insulating substrate, the element section, and finally the through wirings. Hence the insulating substrate having sufficiently high dielectric strength can be used, and electrical reliability of the electronic device can be assured.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

This application claims the benefit of Japanese Patent Application No. 2014-240697, filed November 28, 2014, which is hereby incorporated by reference herein in its entirety.

Claims

A manufacturing method for an electronic device including through wirings and an element section in and on a substrate, the element section including electrodes, the manufacturing method comprising the steps of:
forming a first insulating film on each of a first surface and a second surface of the substrate, the first surface and the second surface being opposite to each other;
forming holes in the substrate in a state not completely penetrating the first insulating film formed on the second surface;
forming a second insulating film on an inner wall of each of the holes;
forming the element section such that the electrodes are located on the first insulating film at a second surface side in positions above the holes; and
filling a conductive material in the holes,
the steps being executed successively in order mentioned above.
The manufacturing method for the electronic device according to Claim 1, wherein the substrate is made of a semiconductor and is a silicon substrate.
The manufacturing method for the electronic device according to Claim 1 or 2, wherein the second insulating film is a silicon oxide film.
The manufacturing method for the electronic device according to any one of Claims 1 to 3, wherein materials of the first insulating film and the second insulating film are different from each other.
The manufacturing method for the electronic device according to any one of Claims 1 to 3, wherein materials of the first insulating film and the second insulating film are same.
The manufacturing method for the electronic device according to any one of Claims 1 to 5, wherein, in the step of processing the first insulating film on the second surface from a first surface side, an inner diameter of an opening formed in the first insulating film on the second surface is set smaller than an inner diameter of the hole such that the electrode is partly exposed at a bottom of the hole toward the first surface side.
A manufacturing method for an electronic device including through wirings and an element section in and on an insulating substrate, the manufacturing method including the steps of:
forming non-through holes not completely penetrating the substrate, which has a first surface and a second surface opposite to each other, from a first surface side while a substrate material is kept remained in the second surface;
forming the element section such that, in the second surface, electrodes of the element section are at least partly overlapped with bottoms of the non-through holes;
processing the substrate material remaining in the second surface from the first surface side to make the electrodes partly exposed at the bottoms of the non-through holes toward the first surface side such that the non-through holes become through holes; and
filling a conductive material in the through holes by electrolytic plating with exposed portions of the electrodes used as seed layers,
the steps being executed successively in order mentioned above.
The manufacturing method for the electronic device according to any one of Claims 1 to 7, wherein the element section is constituted as a capacitive ultrasonic transducer.
The manufacturing method for the electronic device according to any one of Claims 1 to 7, wherein the element section is constituted as a piezoelectric ultrasonic transducer.
An electronic device including electrodes electrically connected to through wirings that penetrate a substrate between a first surface and a second surface thereof opposite to each other, the electrodes being formed on the second surface,
wherein the electrodes are electrically connected to the through wirings via openings that have inner diameters smaller than diameters of the through wirings, and that are formed in an insulating film on the second surface or in an insulating portion in the second surface.
The electronic device according to Claim 10, wherein the electronic device is a capacitive ultrasonic transducer.
The electronic device according to Claim 10, wherein the electronic device is a piezoelectric ultrasonic transducer.
A sample information obtaining apparatus comprising the transducer according to Claim 11 or 12, and a processor configured to obtain information of a sample from an electrical signal output by the transducer,
wherein the transducer receives an acoustic wave from the sample and converts the received acoustic wave to an electrical signal.
The sample information obtaining apparatus according to Claim 13, further comprising a light source,
wherein the transducer receives a photo-acoustic wave generated upon the sample being irradiated with light emitted from the light source, and converts the received photo-acoustic wave to an electrical signal, and
the processor obtains the information of the sample from the electrical signal.
A sample information obtaining apparatus comprising the transducer according to Claim 11 or 12, a light source, and a processor configured to obtain information of a sample from an electrical signal output by the transducer,
wherein the transducer receives an acoustic wave generated upon the sample being irradiated with light oscillated from the light source, and converts the received acoustic wave to the electrical signal.
A measuring apparatus including the transducer according to Claim 11 or 12, the transducer undergoing an external force,
wherein the measuring apparatus measures a magnitude of the external force applied to a surface of the transducer by employing an electrical signal from the transducer.