WO2016050059A1

WO2016050059A1 - Shared storage concurrent access processing method and device, and storage medium

Info

Publication number: WO2016050059A1
Application number: PCT/CN2015/077552
Authority: WO
Inventors: 张丰举
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2014-09-30
Filing date: 2015-04-27
Publication date: 2016-04-07
Also published as: CN105446935A; CN105446935B

Abstract

Disclosed is a shared storage concurrent access processing method. The method comprises: for access queues on various access interfaces, randomly selecting unfinished storage accesses from one or more access queues, wherein there is no Bank conflict between the selected storage accesses; and conducting parallel decoding on the selected storage accesses, and transmitting same to respective corresponding Banks. Correspondingly, also disclosed are a shared storage concurrent access processing device, and a storage medium.

Description

Shared storage concurrent access processing method and device, storage medium

Technical field

The present invention relates to the field of digital chips, and in particular, to a shared storage concurrent access processing method and apparatus, and a storage medium.

Background technique

At present, most of the system-on-chip (SOC) systems have more than one processor and coprocessor, and the main data interaction between these processors is realized by shared storage. With the widespread application of multi-core SOC, access conflicts and bandwidth shortages of shared storage are increasingly becoming bottlenecks that constrain system performance.

The existing shared storage interface improvement method mainly solves the problem of reducing access delay, optimizing cross-boundary access, eliminating non-aligned access overhead, simple access collision avoidance, optimizing bandwidth and delay of continuous address access, etc., and is basically specific to Optimization of the scene.

As shown in Figure 1, it is a common shared storage concurrent access method. Among them, there is only one logically independent memory. When four interfaces have storage accesses, only one access can get a response (as shown by the solid line in the figure). Thus, even with four independent interfaces, there is only one interface with an effective bandwidth.

As shown in Figure 2, there is a logically independent logical block (Block) for a shared storage concurrent access mode with normal conflict avoidance. However, only the access of the queue head can be taken on the interface. When all four interfaces have storage accesses. When it occurs, only the access that does not have a block conflict can get a response (as shown by the solid line in the figure). Thus, even with four independent interfaces, the actual effective bandwidth is only 2.7 times that of a single interface due to the high probability of block collisions.

As shown in FIG. 3, it is a common shared storage concurrent access interface return mode, and from which interface the access is received, the data is returned from which interface. Obviously when there are multiple accesses coming in from the same interface, Although these accesses will be accepted by the interface, at the same time, because each interface can only return one data, only those accesses without interface conflicts get the actual response. As shown in Figure 3, access 0 and access1 enter from interface 0 (Interface 0), access 2 and access 3 enter from interface 1 (Interface 1), although these accesses are accepted by the corresponding interface, but at the same time because each interface Only one data can be returned, so only access0 and access2 get the actual response (the solid line indicates that it is accepted by the interface and gets the actual response), access1 and access3 do not get the actual response (the dotted line indicates that it is accepted by the interface but does not get the actual response) . Thus, even with four independent interfaces, the actual effective bandwidth is only 2.7 times that of a single interface because of the high probability of interface collisions.

Therefore, it is necessary to propose a new scheme to more effectively avoid access conflicts and make full use of interface bandwidth, solve the problem of access conflict and insufficient bandwidth of shared storage, and ensure that it is basically not affected by access methods.

Summary of the invention

In view of the above, the embodiment of the present invention provides a shared storage concurrent access processing method and apparatus, and a storage medium, which can more effectively avoid access conflicts and utilize interface bandwidth, and solve shared access conflicts and Insufficient bandwidth.

The technical solution of the embodiment of the present invention is implemented as follows:

In a first aspect, a shared storage concurrent access processing method is provided in the embodiment of the present invention, including:

For an access queue on each access interface, an unfinished storage access is arbitrarily selected from any one or more of the access queues, and there is no heap bank conflict between the selected storage accesses;

The selected memory accesses are decoded in parallel and transmitted to the respective banks.

In an embodiment of the invention, the method further includes:

Update the transmission status at any time according to the ID of the selected storage access;

Inform the corresponding access interface of the ID of the stored storage access, so that the access interface will The corresponding storage access is removed from the access queue.

In an embodiment of the present invention, each of the access interfaces corresponds to an access queue that includes multiple uncompleted transmissions, and the selected storage access is not greater than the total number of access interfaces.

In a second aspect, the embodiment of the present invention further provides a shared storage concurrent access processing device, including: a shared bus, multiple access interfaces, a shared storage access exchange management unit, and a shared memory, where

A shared bus configured to provide read and write channels for storage access from an access source, support for incomplete transfers, and support for out-of-order transmission;

An access interface configured to accept storage accesses sent over the shared bus and place the accepted storage accesses in an access queue;

The shared storage access switching management unit includes: an access selection module and a parallel decoding module, wherein

The access selection module is configured to arbitrarily select an unfinished storage access from any one or more of the access queues for the access queues on the respective access interfaces, and there is no bank conflict between the selected storage accesses;

The parallel decoding module is configured to decode the storage access selected by the access selection module in parallel and transmit to the corresponding heap bank;

The shared memory includes a plurality of logical blocks, and the logical blocks have no obvious correspondence with the access interface. Each logical block includes a plurality of banks, and the logical blocks refer to logical storage units that provide consecutive addresses, and the bank is used for performing A smaller physical storage unit interleaved with address rows and columns.

In an embodiment of the present invention, the shared storage access exchange management unit further includes a transmission status update module;

The access selection module is further configured to: after selecting the storage access, send the selected storage access ID to the transmission status update module;

The transmission status update module is configured to update the storage access ID according to the ID of the storage access Transmitting status; and notifying the corresponding access interface of the ID of the stored storage access;

The access interface is further configured to remove the corresponding storage access from the access queue according to the ID of the stored storage access.

In a third aspect, the embodiment of the present invention further provides a shared storage concurrent access processing method, including:

For each feedback data that needs to be returned, select any access interface as its pass interface;

The feedback data and its accompanying information are sent to an access interface, the accompanying information including an access ID and an identification of the pass-through interface.

In an embodiment of the present invention, selecting any one of the access interfaces as its pass interface includes:

Preferentially selecting an access interface corresponding to the feedback data as its pass interface;

If there is an access conflict in the access interface corresponding to the feedback data, any access interface that does not currently need to return data is selected as its pass interface.

In an embodiment of the invention, the method further includes:

The access interface receives the feedback data and its accompanying information, and returns the feedback data to the access source via the shared bus according to the accompanying information.

In a fourth aspect, the embodiment of the present invention further provides a shared storage concurrent access processing device, including: a shared bus, multiple access interfaces, a shared storage access exchange management unit, and a shared memory, where

An access interface configured to accept storage accesses sent over the shared bus and to accept The storage access is placed in the access queue; and configured to return the feedback data that needs to be returned to the access source through the shared bus according to the accompanying information of the feedback data;

The shared storage access exchange management unit includes: an interface selection module configured to select any one of the access interfaces as a pass-through interface for the feedback data of the storage access, and send the feedback data and its accompanying information to the access interface, The accompanying information includes an ID of the storage access corresponding to the feedback data and an identifier of the through interface;

The shared memory includes a plurality of logical blocks, each of which includes a plurality of banks, the logical blocks refer to logical storage units providing consecutive addresses, and the Bank is a smaller physical storage unit for performing address row and column interleaving.

In an embodiment of the present invention, the interface selection module is configured to select any one of the access interfaces as the pass-through interface for each feedback data that needs to be returned, including:

For each feedback data that needs to be returned, the access interface corresponding to the feedback data is preferentially selected as its pass interface; if there is an access conflict in the access interface corresponding to the feedback data, any access interface that does not currently need to return data is selected as the pass interface.

In a fifth aspect, an embodiment of the present invention provides a computer storage medium, where the computer storage medium stores computer executable instructions for performing the sharing provided by the first aspect or the third aspect of the present invention. Store concurrent access processing methods.

In the embodiment of the present invention, the storage access and the storage access are accepted regardless of the order, and any interface is selected as the through interface when the data is returned. Thus, multiple interfaces share the same on-chip memory, thereby improving the storage access bandwidth and being more effective. Avoid access violations and make full use of interface bandwidth, and are largely unaffected by access methods.

DRAWINGS

FIG. 1 is a schematic diagram of a common shared storage concurrent access method;

2 is a schematic diagram of a shared storage concurrent access mode with normal conflict avoidance;

FIG. 3 is a schematic diagram of a return mode of a common shared storage concurrent access interface;

4 is a schematic diagram of a shared storage concurrent access manner according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a return manner of a shared storage concurrent access interface according to an embodiment of the present invention; FIG.

FIG. 6 is a schematic structural diagram of a shared storage concurrent access processing apparatus according to an embodiment of the present invention; FIG.

7a-7b are schematic diagrams showing shared memory address encoding of a shared storage concurrent access processing device according to an embodiment of the present invention;

FIG. 8 is a flowchart of a shared storage concurrent access processing method according to an embodiment of the present invention.

detailed description

The present invention will be further described in detail below with reference to the accompanying drawings.

The shared storage concurrent access processing method and device provided by the embodiments of the present invention can improve the storage access bandwidth by sharing the memory in the same chip through multiple interfaces, can more effectively avoid the access conflict and fully utilize the interface bandwidth, and is basically not subject to The impact of access methods.

The specific implementation process of the embodiment of the present invention is described by taking four access interfaces, a memory including four logic blocks, and 16 independent banks as an example. It should be noted that the embodiments of the present invention are also applicable to and not limited to similar structures of eight interfaces, eight blocks, and 32 banks. The main feature of the similar structure is that there are multiple access interfaces, and Block and Bank are organized. Shared storage.

As shown in FIG. 4, there are four logically independent blocks and 16 independent banks in the memory. When four interfaces have storage accesses, each access interface corresponds to an access queue with multiple uncompleted transmissions. In the embodiment of the present invention, the out-of-order function can be used to access storage access from any access queue from the access queues access01 to access04, access11 to access14, access21 to access24, access31 to access34 of the four slave devices, and the selected storage access is selected. No more than the total number of access interfaces, parallel processing of the selected access storage, as long as there is no access to the Bank conflict will be responded, do not need to follow the order of the access queue or each access The queue takes an access rule to handle storage access. In this case, the probability of a bank collision is close to zero, and the actual effective bandwidth is about four times that of a single interface. For example, as shown in FIG. 4, access01, access03, access21, and access34 can be simultaneously taken for parallel processing.

In the embodiment of the present invention, the feedback data can be returned through any one of the access interfaces, and the data does not need to be returned according to the "from where to return the rules", as long as there is no data to be returned on the current interface, This interface can be used to return feedback data. With interfaces that do not have data to return to resolve access violations on the interface, all accesses can be actually responded at any time, so that the actual effective bandwidth is four times that of a single interface. As shown in Figure 5, access0 and access1 have access violations. When returning data, the feedback data for access1 does not use the original interface Interface0, but the interface Interface1, which has no data to return, returns its feedback data. When there is an access violation between access2 and access3, both access2 and access3 need to return data. The feedback data for access1 is returned by interface Interface2, and the feedback data for access3 is returned by interface Interface3.

As shown in FIG. 6, the shared storage concurrent access processing device structure of the four interfaces mainly includes: a shared bus, four access interfaces Slave0 to Slave3, a shared memory access switch unit, and a shared memory.

The shared bus provides read and write channels for storage access from the access source. It can be any topology but meets the following main features (see Figure 6 for a separate read and write channel, as well as a bus that supports both read and write channels): Master to slave (Slave) according to address routing; slave to Master according to ID routing; support for outstanding completion (outstanding); support out of order (out of order).

Four access interfaces Slave0~Slave3 are managed uniformly. The access queues of each access interface in Slave0~Slave3 have four locations (WID0&RID0~WID3&RID3) configured to accept storage accesses sent through the shared bus and will accept The storage access is placed in the access queue; in addition, the access interface can be configured to store the corresponding storage address based on the ID of the stored storage access. The store access is removed from the access queue. In addition, it may be configured to return the feedback data that needs to be returned to the access source through the shared bus according to the accompanying information of the feedback data.

The shared storage access switching management unit includes an access select module, a parallel decoding module, and a transaction state update module, where:

The access selection module is configured to arbitrarily select an unfinished storage access from any one or more access queues for the access queues on the respective access interfaces, and there is no bank conflict between the selected storage accesses;

The parallel decoding module is configured to decode the storage access selected by the access selection module in parallel and transmit to the corresponding bank; the access selection module is further configured to: after selecting the storage access, select the selected storage access The ID is sent to the transmission status update module;

The transmission status update module is configured to update its transmission status at any time according to the ID of the storage access; and notify the corresponding access interface of the ID of the stored storage access.

In addition, a date feedback & interface select module may be included, configured to select any one of the access interfaces as its pass interface for each feedback data, and send the feedback data and its accompanying information to the access And the accompanying information includes an ID of the storage access corresponding to the feedback data and an identifier of the pass interface.

As shown in FIG. 6, the shared memory includes four logical blocks Block0~Block3, each of which includes four banks (Bank0~Bank3), the logical block refers to a logical storage unit that provides consecutive addresses, and the Bank is used to A smaller physical storage unit that interleaves the address rows and columns. Each bank is responsible for multiple addresses, that is, multiple accessed addresses are located in the same bank. When the access arrives, the access is placed in the corresponding bank according to the accessed address. In practical applications, the shared memory can be organized in two levels, as shown in FIG. 7a, including four logical blocks (Blocks) encoded according to consecutive addresses, so as to facilitate the storage of data according to functions to avoid conflicts between concurrent accesses; Show that each block contains four banks encoded according to the horizontal address, which is convenient for storing data according to statistical characteristics. Avoid conflicts between concurrent accesses. In the above device, the word length is 128 bits; the first word is in Bank0, the second word is in Bank1, the third word is in Bank2, the fourth word is in Bank3, and so on. That is, the sequential addressing in the block, the horizontal addressing between the banks, the address in the bank is not continuous (the tolerance series of tolerance 4), and the address is interleaved between the banks.

The interface selection module is configured to select any one of the access interfaces as the pass-through interface for each feedback data that needs to be returned, including: for each feedback data that needs to be returned, preferentially selecting an access interface corresponding to the feedback data as its Through the interface; if the access interface corresponding to the feedback data has an access conflict, select any access interface that does not currently need to return data as its pass interface.

As shown in FIG. 8, the shared storage concurrent access processing method of the embodiment of the present invention may be implemented by using the apparatus shown in FIG. 6, and the method may specifically include the following steps:

Step 801: The access source sends the storage access to each access interface Slave0 to Slave3 through the shared bus, and judges whether the new storage access is accepted according to the total depth of the four access queues in Slave0~Slave3, and the accepted storage is accepted. Access is placed in the access queue;

Each access interface preferentially accepts its corresponding storage access. When the total space of the four access queues is insufficient, it can be selected according to any policy arbitration to accept or not accept new storage access according to the application characteristics.

Step 802: The access selection module of the shared storage access exchange management unit selects four storages without bank conflicts in a sequence of accepted but unfinished storage accesses from 32 locations corresponding to the four access queues of Slave0 to Slave3, respectively. Accessing, and sending the selected storage access ID to the transmission status update module of the shared storage access exchange management module;

Among them, the choice of storage access can be arbitrated according to any policy, the focus is on arbitrarily selecting one or more storage accesses from 32 locations of the four access queues for parallel processing, but the number of selected storage accesses is not greater than the logic of the shared memory. The number of blocks. In the embodiment of the present invention, the number of selected storage accesses may not exceed 4 (the total number of interfaces).

Step 803: The parallel decoding module of the shared storage access switching management unit decodes the selected conflict-free storage access in parallel and sends them to the corresponding banks;

Step 804: The transmission status update module updates its transmission status (transmission progress) based on the ID of each storage access, and notifies the access interface to remove the storage access from the access queue if the transmission is just completed.

Step 805: The interface selection module of the shared storage access exchange management unit selects an access interface for each feedback data that needs to be returned.

Here, for each feedback data that needs to be returned, any one of the access interfaces is selected as its pass interface. The access interface corresponding to the feedback data is preferentially selected as the pass-through interface. For other feedback data with interface conflicts, any access interface that does not need to return data can be selected as the pass-through interface. The interface selection policy can be flexibly set, which is not limited in the embodiment of the present invention.

Step 806: The interface selection module of the shared storage access switching management unit sends the feedback data and its accompanying information to the access interface.

The accompanying information mainly includes an ID of the storage access corresponding to the feedback data, and an identifier of the access interface through which the feedback data is to go.

Step 807: The access interface receives the feedback data and its accompanying information, and returns the feedback data to the access source through the shared bus according to the accompanying information.

Each of Slave0~Slave3 selects whether to accept the feedback data according to the accompanying information of the feedback data. If the identifier of the interface in the accompanying information is the same as the identifier of the interface, it is accepted, and the ID of the access is stored according to the accompanying information. The feedback data is returned to the corresponding access source through the shared bus; otherwise, the feedback data is not accepted, and subsequent data return processing is not performed.

For access that does not require returning data, such as a read access, the process can be terminated by step 804; for accesses that need to return feedback data, such as a write access, the flow ends at 807.

In the above steps,

steps

802 and 805 are the main reasons for improving the shared memory access bandwidth;

steps

801 and 807 are improvements to the existing on-chip data bus protocol. And flexible application is an auxiliary condition for the effective use of this method.

Compared with existing methods and devices for improving the bandwidth of shared storage interfaces, the method and apparatus of the present invention have the following features:

1) In the storage access arbitration of each interface, combined with the outstanding function, out of order scheduling and response, minimize the bank conflict in multi-port storage access, improve the entrance of static random access memory (SRAM, Static RAM) And export bandwidth.

2) When multiple concurrent accesses occur, each access interface does not work independently, but manages the queue resources uniformly, eliminating the fact that the access interface queue with access is full and the other access interfaces are free to accept new access. Bandwidth loss.

3) When multiple data returns, give up the way of going back and forth from where to go. The return data can be returned by any interface, and the return delay of each interface is controlled. The bus returns data according to ID, so it will not Any adverse effects that take advantage of the export bandwidth provided by the interface.

Suppose the SRAM has only one block and one access interface. Obviously, this method has nothing to do with the address patter at the time of access. Assuming that the bus bandwidth of a single interface is 1 (normalized unit), the shared storage access bandwidth of this scheme is just 1 .

1) Four independent bus interfaces and four independent blocks. If you use the normal method, the following four concurrent access sources will appear as follows:

The addresses of the four concurrent accesses fall on exactly four different blocks with a bandwidth of 4*1=4.

The addresses of the four concurrent accesses fall on three different blocks with a bandwidth of 3*1=3.

The addresses of the four concurrent accesses fall on two different blocks with a bandwidth of 2*1=2.

The addresses of 4 concurrent accesses fall in the same block with a bandwidth of 1.

Assume that the access addresses of each access source are independent of each other and the access addresses are evenly distributed, and the total number of access cases is:

N=4 ⁴ =256=N ₁ +N ₂ +N ₃ +N ₄

The probability that four concurrent access addresses fall on exactly four different blocks is: N4/N=9.38%.

The probability that four concurrent access addresses fall into three different blocks is: N3/N=56.25%.

The probability that four concurrent access addresses fall into two different blocks is: N2/N=32.81%.

The probability that four concurrent access addresses fall into the same block is: N1/N=1.56%.

Thus, the average bandwidth under this scheme is: B=B1*P1+B2*P2+B2*P2+B2*P2=4*9.38%+3*56.25%+2*32.81%+1*1.56%=2.73.

2) Using the apparatus and method provided by the embodiments of the present invention, it is assumed that the shared bus can support up to 16 outstanding unordered functions, that is, each access source supports an average of 4 outstanding unordered functions; the memory is divided into 4 logical independent functions. Block, each block is divided into 4 banks of address interleaving. Under this scheme, the following four situations will be generated from the four concurrent access sources selected from the 16 IDs:

The addresses of the four concurrent accesses fall in exactly four different banks with a bandwidth of 4*1G=4.

The addresses of the four concurrent accesses fall into three different banks with a bandwidth of 3*1=3.

The addresses of 4 concurrent accesses fall in two different banks with a bandwidth of 2*1=2.

The addresses of 4 concurrent accesses fall in the same bank with a bandwidth of 1.

N=N ₁ +N ₂ +N ₃ +N ₄ =16 ¹⁶ =18446744073709551616

N ₄ =NN ₁ -N ₂ -N ₃ =18446744049705622576

The probability that four concurrent access addresses fall on four different blocks is: N4/N=99.99%.

The probability that four concurrent access addresses fall into three different blocks is: N3/N=0.001%.

The probability that four concurrently accessed addresses fall into two different blocks is: N2/N=0.00%.

The probability that four concurrently accessed addresses fall on the same block is: N1/N=0.00.

Thus, the average bandwidth under this scheme is: B=B1*P1+B2*P2+B2*P2+B2*P2=4*99.99%+3*0.01%+2*0.00%+1*0.00%=4.

Therefore, compared with the conventional four independent bus interfaces, the advantages of the method and the device of the embodiment of the present invention are 46.5% higher than that of the conventional method.

The shared storage access exchange management unit in the shared storage concurrent access processing device provided by the embodiment of the present invention, and each module included in the shared storage access exchange management unit, such as an access selection module and a parallel decoding module, a transmission status update module, and an interface The selection module can be implemented by a computing device such as a processor in a computer; of course, the functions performed by the above processor can also be implemented by specific logic circuits; in the process of the specific embodiment, the processor can be a central processing unit (CPU) ), microprocessor (MPU), digital signal processor (DSP) or field programmable gate array (FPGA).

It should be noted that, in the embodiment of the present invention, if the shared storage concurrent access processing method is implemented in the form of a software function module, and is sold or used as a standalone product, it may also be stored in a computer readable storage medium. . Based on such understanding, the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions. A computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention. The foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the invention are not limited to any particular A combination of hardware and software.

Correspondingly, the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the shared storage concurrent access processing method in the embodiment of the present invention.

The above is a further detailed description of the present invention in connection with the specific embodiments, and the specific embodiments of the present invention are not limited to the description. It will be apparent to those skilled in the art that the present invention may be made without departing from the spirit and scope of the invention.

Industrial applicability

In the embodiment of the present invention, for an access queue on each access interface, an unfinished storage access is arbitrarily selected from any one or more of the access queues, and there is no bank conflict between the selected storage accesses; Parallel decoding is accessed and transmitted to the respective corresponding banks, so that access collisions can be more effectively avoided and the interface bandwidth can be fully utilized, and is basically not affected by the access mode.

Claims

A shared storage concurrent access processing method, the method comprising:

For an access queue on each access interface, an unfinished storage access is arbitrarily selected from any one or more of the access queues, and there is no heap bank conflict between the selected storage accesses;

The selected memory accesses are decoded in parallel and transmitted to the respective banks.
The method of claim 1 wherein the method further comprises:

Update the transmission status at any time according to the ID of the selected storage access;

The ID of the stored storage access is communicated to the corresponding access interface so that the access interface removes the corresponding storage access from the access queue.
The method according to claim 1 or 2, wherein each of the access interfaces corresponds to an access queue having a plurality of outstanding transmissions, and the selected storage access is not greater than the total number of access interfaces.
A shared storage concurrent access processing device, the device comprising: a shared bus, a plurality of access interfaces, a shared storage access exchange management unit, and a shared memory, wherein

A shared bus configured to provide read and write channels for storage access from an access source, support for incomplete transfers, and support for out-of-order transmission;

An access interface configured to accept storage accesses sent over the shared bus and place the accepted storage accesses in an access queue;

The shared storage access switching management unit includes: an access selection module and a parallel decoding module, wherein

The access selection module is configured to arbitrarily select an unfinished storage access from any one or more of the access queues for the access queues on the respective access interfaces, and there is no bank conflict between the selected storage accesses;

The parallel decoding module is configured to decode the storage access selected by the access selection module in parallel and transmit to the corresponding heap bank;

The shared memory includes a plurality of logical blocks, and the logical blocks have no obvious correspondence with the access interface. Each logical block includes a plurality of banks, and the logical blocks refer to logical storage units that provide consecutive addresses, and the bank is used for performing A smaller physical storage unit interleaved with address rows and columns.
The shared storage access exchange management unit according to claim 4, wherein the shared storage access exchange management unit further comprises a transmission status update module;

The access selection module is further configured to: after selecting the storage access, send the selected storage access ID to the transmission status update module;

The transmission status update module is configured to update its transmission status at any time according to the ID of the storage access; and notify the corresponding access interface of the ID of the processed storage access that has been processed;

The access interface is further configured to remove the corresponding storage access from the access queue according to the ID of the stored storage access.
The shared storage access switching management unit according to claim 4 or 5, wherein each of the access interfaces corresponds to an access queue having a plurality of outstanding transmissions, and the selected storage access is not greater than the total number of access interfaces.
A shared storage concurrent access processing method, the method comprising:

For each feedback data that needs to be returned, select any access interface as its pass interface;

The feedback data and its accompanying information are sent to an access interface, the accompanying information including an access ID and an identification of the pass-through interface.
The method of claim 7, wherein selecting any one of the access interfaces as its pass-through interface comprises:

Preferentially selecting an access interface corresponding to the feedback data as its pass interface;

If there is an access conflict in the access interface corresponding to the feedback data, any access interface that does not currently need to return data is selected as its pass interface.
The method of claim 7 wherein the method further comprises:

The access interface receives the feedback data and its accompanying information, and returns the feedback data to the access source via the shared bus according to the accompanying information.
A shared storage concurrent access processing device, the device comprising: a shared bus, a plurality of access interfaces, a shared storage access exchange management unit, and a shared memory, wherein

A shared bus configured to provide read and write channels for storage access from an access source, support for incomplete transfers, and support for out-of-order transmission;

An access interface configured to accept a storage access sent over the shared bus and place the accepted storage access in an access queue; and configured to pass the feedback data that needs to be returned through the shared bus based on the accompanying information of the feedback data Return to the access source;

The shared storage access exchange management unit includes: an interface selection module configured to select any one of the access interfaces as a pass-through interface for the feedback data of the storage access, and send the feedback data and its accompanying information to the access interface, The accompanying information includes an ID of the storage access corresponding to the feedback data and an identifier of the through interface;

The shared memory includes a plurality of logical blocks, each of which includes a plurality of banks, the logical blocks refer to logical storage units providing consecutive addresses, and the Bank is a smaller physical storage unit for performing address row and column interleaving.
The shared storage access exchange management unit according to claim 10, wherein the interface selection module is configured to select any one of the access interfaces as the pass-through interface for each feedback data that needs to be returned, including:

For each feedback data that needs to be returned, the access interface corresponding to the feedback data is preferentially selected as its pass interface; if there is an access conflict in the access interface corresponding to the feedback data, any access interface that does not currently need to return data is selected as the pass interface.
A computer storage medium storing computer executable instructions for performing the shared storage concurrent access processing method according to any one of claims 1 to 3; or

The computer executable instructions are for performing the shared storage concurrent access processing method of any one of claims 7 to 9.